CN105893895A - Communication method and circuit for security digital cards - Google Patents
Communication method and circuit for security digital cards Download PDFInfo
- Publication number
- CN105893895A CN105893895A CN201610195738.7A CN201610195738A CN105893895A CN 105893895 A CN105893895 A CN 105893895A CN 201610195738 A CN201610195738 A CN 201610195738A CN 105893895 A CN105893895 A CN 105893895A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- feedback signal
- signal
- safe digital
- type flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/0013—Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers
Landscapes
- Engineering & Computer Science (AREA)
- Artificial Intelligence (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
The embodiment of the invention relates to a communication method and circuit for security digital cards and belongs to the field of electronic data storage and processing. The communication method for the security digital cards comprises steps of: sampling and holding a feedback signal on the signal line of the security digital card by using an internal clock signal to generate an internal feedback signal; inverting an original clock signal to generate an inverted clock signal; triggering the reading of the internal feedback signal by using the inverted clock signal. The communication method and circuit for the security digital cards prevent incompatibility of the security digital cards.
Description
Technical field
The present embodiments relate to electronic data storage process field, the communication party of a kind of safe digital card
Method and circuit.
Background technology
Safe digital (Secure digital, SD) card is a kind of storage device based on quasiconductor fast-flash memory device.
SD card is developed with in August, 1999 joint development by the Shan Di company of PANASONIC, Toshiba and the U.S. the earliest.
2000, this three company initiated to have set up SD association (Secure digital association, SDA), battle array
Hold powerful, attracted the well-known manufacturer in the substantial amounts of world to participate in.Including IBM, Microsoft, Motorola,
NEC, Samsung etc..Under the promotion of these leading manufacturers, SD card has become as current consumer number
A kind of storage card being most widely used in equipment.
It will be understood by those skilled in the art that in order to and keep efficient communication, SD control between SD card
Device processed (SD host) needs to be connected with keeping in communication between SD card.And at actual printed circuit board (PCB) (Printed
Circuit board, PCB) on, it is exactly typically PCB trace that above-mentioned communication connects.And due to different PCB
The layout of upper components and parts is different, different from the length of the cabling of described SD card for connecting described SD controller.
This has resulted in signal and has been transmitted to SD card by SD controller, or when having the transmission of SD card to SD controller,
Certain Phase delay (Phase delay) can be produced.See the original clock signal of Fig. 1, SD card with outside
Phase delay t is there is between clock signal.The original clock signal of described SD card be SD card receive time
Clock signal.Described external timing signal is exactly the clock signal that described SD card controller sends.Due to this
The existence of Phase delay, can cause can accurately not reading the feedback letter on holding wire at SD controller end
Number.Once the described feedback signal of reading of mistake, will result between SD card and whole system incompatible
Problem.
Summary of the invention
For above-mentioned technical problem, embodiments provide communication means and the electricity of a kind of safe digital card
Road, effectively to avoid the generation of the incompatible situation of safe digital card.
On the one hand, embodiments providing the communication means of a kind of safe digital card, described method includes:
Use internal clock signal that the feedback signal on the holding wire of described safe digital card carries out sampling to keep,
To generate internal feedback signal；
Original clock signal is carried out anti-phase, to generate inverting clock signal；
Described inverting clock signal is used to trigger the reading to described internal feedback signal.
Optionally, described holding wire includes: command signal line.
Optionally, use internal clock signal that the feedback signal on the holding wire of described safe digital card is carried out
Sampling keeps, and includes generating internal feedback signal:
With described internal clock signal for the clock signal of input, utilize the first d type flip flop to described feedback letter
Number carry out sampling to keep, to generate described internal feedback signal.
Optionally, described first d type flip flop is hazard-free D flip-flop.
Optionally, use described inverting clock signal to trigger the reading to described internal feedback signal to include:
With described inverting clock signal for the clock signal of input, utilize the second d type flip flop anti-to described inside
Feedback signal is sampled.
Optionally, described second d type flip flop, when the rising edge of described inverting clock signal arrives, triggers institute
State the reading of internal feedback signal.
Optionally, described second d type flip flop is hazard-free D flip-flop.
Optionally, when described feedback signal is carried out individual data block read command or multiple data block read command
The feedback signal got.
On the other hand, the embodiment of the present invention additionally provides the telecommunication circuit of a kind of safe digital card, described circuit
Including:
First d type flip flop, for using anti-on the holding wire of described safe digital card of internal clock signal
Feedback signal carries out sampling and keeps, to generate internal feedback signal；
Phase inverter, for carrying out anti-phase to original clock signal, to generate inverting clock signal；
Second d type flip flop, for using described inverting clock signal to trigger the reading to described internal feedback signal
Take.
Optionally, described first d type flip flop and described second d type flip flop are all hazard-free D flip-flops.
Optionally, described holding wire includes: command signal line.
Optionally, described second d type flip flop, when the rising edge of described inverting clock signal arrives, triggers institute
State the reading of internal feedback signal.
Optionally, when described feedback signal is carried out individual data block read command or multiple data block read command
The feedback signal got.
The communication means of the safe digital card that the embodiment of the present invention provides and circuit, by using internal clocking to believe
Feedback signal on the holding wire of described safe digital card number carries out sampling keep, and use described anti-phase
Clock signal triggers the reading to described internal feedback signal, ensure that described feedback signal by sequencing contro
Accurate reading, effectively avoid the generation of the incompatible situation of safe digital card.
Accompanying drawing explanation
The detailed description that non-limiting example is made made with reference to the following drawings by reading, the present invention
Other features, objects and advantages will become more apparent upon:
Fig. 1 is the signal timing diagram communicated with SD card in prior art；
Fig. 2 is the flow chart of the communication means of the safe digital card that first embodiment of the invention provides；
Each letter when Fig. 3 is the communication means of the execution described safe digital card that first embodiment of the invention provides
Number signal timing diagram；
Fig. 4 is the structured flowchart of the telecommunication circuit of the safe digital card that second embodiment of the invention provides.
Detailed description of the invention
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that this
Specific embodiment described by place is used only for explaining the present invention, rather than limitation of the invention.The most also need
It is noted that for the ease of describing, accompanying drawing illustrate only part related to the present invention and not all knot
Structure.
First embodiment
Present embodiments provide a kind of technical scheme of the communication means of safe digital card.Described safe digital card
Communication means performed by SD controller.
Seeing Fig. 2, the communication means of described safe digital card includes:
S21, uses internal clock signal to sample the feedback signal on the holding wire of described safe digital card
Keep, to generate internal feedback signal.
When described internal clock signal is to communicate with described SD card, outside the reception of described SD controller
After clock signal, in the clock signal that described SD card is internally formed.In signal waveform, described inside
Clock signal is identical with the waveform of outside clock signal, is all rectangle square wave.In sequential relationship, described
Internal clock signal has the regular hour to postpone than outside clock signal.
Described holding wire refers to the order (Command, CMD) in described SD card controller with described SD card
The holding wire that line is connected.The definition of each pin according to SD card, described holding wire should be one
Individual two-way holding wire.It is to say, on the signal line, both can transmit by described SD card to institute
State the signal of SD card controller, it is also possible to transmit by described SD card controller to the signal of described SD card.
Owing to described holding wire is a two-way holding wire, it is to be understood that when described SD card control
Device is when described SD card sends various order, and described SD card can be got by described holding wire accordingly
Feedback signal.In the present embodiment, described feedback signal is carried out individual data block read command or many numbers
According to the feedback signal obtained after block read command, namely CMD17 or CMD18 order.
In the present embodiment, described SD card controller, after receiving above-mentioned feedback signal, utilizes a D
Trigger carries out sampling and keeps above-mentioned feedback signal.Further, the clock of input extremely described first d type flip flop
Signal is exactly previously described internal clock signal.Described first d type flip flop is hazard-free D flip-flop.
S22, carries out anti-phase to original clock signal, to generate inverting clock signal.
Described original clock signal is the clock signal received by SD card.
Under normal circumstances, described SD card controller uses a phase inverter to complete to believe described original clock
Number anti-phase process.And, it is further preferred that described phase inverter can be a not circuit.
S23, uses described inverting clock signal to trigger the reading to described internal feedback signal.
In the present embodiment, the second d type flip flop is used to trigger the reading to described internal feedback signal.Defeated
The described internal feedback signal of the signal of the signal input part entered to described second d type flip flop, and input to institute
The signal of the input end of clock stating the second d type flip flop is described inverting clock signal.Described second d type flip flop
It it is hazard-free D flip-flop.
Fig. 3 shows when performing the communication means of safe digital card that the present embodiment provides, each signal time
Order relation.See Fig. 3, t1For the Phase delay between the original clock signal of external timing signal and SD card,
t2For the Phase delay between the internal clock signal of external timing signal and SD card controller.Above-mentioned t1With t2
Sum is already close to the half period duration of clock signal.It is to say, the original clock signal of SD card with
Phase delay between the internal clock signal of SD card controller is close to half period.Therefore, if used
The clock signal of SD card triggers the reading to described internal feedback signal, can run into feedback time and set up the time
Not enough problem, still can not thoroughly solve the problem that SD card is incompatible.Accordingly, it would be desirable to use anti-phase
The clock signal of SD card triggers the reading to described internal feedback signal, to ensure that described internal feedback signal has
Enough sets up the time.
The present embodiment is by using the feedback signal on the internal clock signal holding wire to described safe digital card
Carry out sampling to keep, original clock signal is carried out anti-phase, to generate inverting clock signal, and use institute
State inverting clock signal and trigger the reading to described internal feedback signal, effectively avoid safe digital card not
The generation of compatible situation.
Second embodiment
Present embodiments provide a kind of technical scheme of the telecommunication circuit of safe digital card.In this technical scheme,
Described safe digital card is integrated in SD controller.
Seeing Fig. 4, the telecommunication circuit of described safe digital card includes: the first d type flip flop 41, phase inverter 42
And second d type flip flop 43.
The signal input part of described first d type flip flop 41 is connected with the feedback signal on holding wire, its clock
Input is connected with the internal clock signal of SD card controller, for generating the inside of described SD card controller
Feedback signal.It is to say, described first d type flip flop 41 is used for using internal clock signal to described peace
Feedback signal on the holding wire of full digital code card carries out sampling and keeps, to generate internal feedback signal.
Exemplary, described holding wire can be the cmd signal line of described SD card.
Described phase inverter 42 is for carrying out anti-phase to original clock signal.Through to described original clock signal
Anti-phase, described phase inverter 42 exports inverting clock signal.
Concrete, described phase inverter 42 can be a logic inverter circuit.
The signal input part of described second d type flip flop 43 with generated by described first d type flip flop 41 described in
Internal feedback signal connects, and its input end of clock is connected with described anti-phase external timing signal.It is so configured,
Described second d type flip flop 43 can trigger the reading to described internal feedback signal, and ensures to send out
The situation that raw SD card is incompatible.
Concrete, above-mentioned second d type flip flop 43 can be when the rising edge of described inverting clock signal arrives,
Trigger the reading of described internal feedback signal.
In the embodiment of the present invention, above-mentioned first d type flip flop 41 and described second d type flip flop 43 are all to maintain
Block d type flip flop.
The present embodiment passes through the first d type flip flop, being connected with each other between phase inverter and the second d type flip flop,
Carry out sampling by the feedback signal on first d type flip flop holding wire to described safe digital card to keep, logical
Cross phase inverter and described internal clock signal is carried out anti-phase, and triggered described inside by the second d type flip flop
The reading of feedback signal, effectively avoids the generation of the incompatible situation of SD card.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for this area skill
For art personnel, the present invention can have various change and change.All institutes within spirit and principles of the present invention
Any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (13)
1. the communication means of a safe digital card, it is characterised in that including:
Use internal clock signal that the feedback signal on the holding wire of described safe digital card carries out sampling to keep,
To generate internal feedback signal；
Original clock signal is carried out anti-phase, to generate inverting clock signal；
Described inverting clock signal is used to trigger the reading to described internal feedback signal.
The communication means of safe digital card the most according to claim 1, it is characterised in that described signal
Line includes: command signal line.
The communication means of safe digital card the most according to claim 1 and 2, it is characterised in that use
Internal clock signal carries out sampling and keeps the feedback signal on the holding wire of described safe digital card, to generate
Internal feedback signal includes:
With described internal clock signal for the clock signal of input, utilize the first d type flip flop to described feedback letter
Number carry out sampling to keep, to generate described internal feedback signal.
The communication means of safe digital card the most according to claim 3, it is characterised in that described first
D type flip flop is hazard-free D flip-flop.
The communication means of safe digital card the most according to claim 1 and 2, it is characterised in that use
Described inverting clock signal triggers the reading to described internal feedback signal and includes:
With described inverting clock signal for the clock signal of input, utilize the second d type flip flop anti-to described inside
Feedback signal is sampled.
The communication means of safe digital card the most according to claim 5, it is characterised in that described second
D type flip flop, when the rising edge of described inverting clock signal arrives, triggers the reading of described internal feedback signal.
The communication means of safe digital card the most according to claim 6, it is characterised in that described second
D type flip flop is hazard-free D flip-flop.
The communication means of secure data card the most according to claim 1 and 2, it is characterised in that described
Feedback signal is carried out the feedback signal got when individual data block read command or multiple data block read command.
9. the telecommunication circuit of a safe digital card, it is characterised in that including:
First d type flip flop, for using anti-on the holding wire of described safe digital card of internal clock signal
Feedback signal carries out sampling and keeps, to generate internal feedback signal；
Phase inverter, for carrying out anti-phase to original clock signal, to generate inverting clock signal；
Second d type flip flop, for using described inverting clock signal to trigger the reading to described internal feedback signal
Take.
The telecommunication circuit of safe digital card the most according to claim 9, it is characterised in that described
One d type flip flop and described second d type flip flop are all hazard-free D flip-flops.
The telecommunication circuit of 11. safe digital cards according to claim 9, it is characterised in that described letter
Number line includes: command signal line.
The telecommunication circuit of 12. safe digital cards according to claim 9, it is characterised in that described
2-D trigger, when the rising edge of described inverting clock signal arrives, triggers the reading of described internal feedback signal
Take.
The telecommunication circuit of 13. safe digital cards according to claim 9, it is characterised in that described instead
Feedback signal is carried out the feedback signal got when individual data block read command or multiple data block read command.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610195738.7A CN105893895A (en) | 2016-03-31 | 2016-03-31 | Communication method and circuit for security digital cards |
| PCT/CN2016/097025 WO2017166660A1 (en) | 2016-03-31 | 2016-08-26 | Secure digital card communication method and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610195738.7A CN105893895A (en) | 2016-03-31 | 2016-03-31 | Communication method and circuit for security digital cards |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105893895A true CN105893895A (en) | 2016-08-24 |
Family
ID=57014465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610195738.7A Pending CN105893895A (en) | 2016-03-31 | 2016-03-31 | Communication method and circuit for security digital cards |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105893895A (en) |
| WO (1) | WO2017166660A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017166660A1 (en) * | 2016-03-31 | 2017-10-05 | 乐视控股（北京）有限公司 | Secure digital card communication method and circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070023972A (en) * | 2005-08-25 | 2007-03-02 | 주식회사 엠픽사 | Complex memory card having function of communication and the method thereof |
| US20080191015A1 (en) * | 2005-07-19 | 2008-08-14 | Sony Corporation | Data Transfer System, Data Acquisition Device, Data Acquisition Method, Data Accumulation Device, Data Transmission Method, and Program for the Same |
| CN102361456A (en) * | 2011-10-26 | 2012-02-22 | 华亚微电子（上海）有限公司 | Clock phase alignment and adjustment circuit |
| CN102708074A (en) * | 2011-03-18 | 2012-10-03 | 飞思卡尔半导体公司 | Synchronous data processing system and method |
| CN104871247A (en) * | 2012-12-28 | 2015-08-26 | 桑迪士克科技股份有限公司 | Clock generation and delay architecture |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3552213B2 (en) * | 2001-08-31 | 2004-08-11 | 株式会社東芝 | SD memory card host controller and clock control method |
| CN103050144B (en) * | 2012-12-30 | 2016-05-25 | 深圳市凌启电子有限公司 | A kind of storage card power delivery circuit |
| CN105893895A (en) * | 2016-03-31 | 2016-08-24 | 乐视控股（北京）有限公司 | Communication method and circuit for security digital cards |
-
2016
- 2016-03-31 CN CN201610195738.7A patent/CN105893895A/en active Pending
- 2016-08-26 WO PCT/CN2016/097025 patent/WO2017166660A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080191015A1 (en) * | 2005-07-19 | 2008-08-14 | Sony Corporation | Data Transfer System, Data Acquisition Device, Data Acquisition Method, Data Accumulation Device, Data Transmission Method, and Program for the Same |
| KR20070023972A (en) * | 2005-08-25 | 2007-03-02 | 주식회사 엠픽사 | Complex memory card having function of communication and the method thereof |
| CN102708074A (en) * | 2011-03-18 | 2012-10-03 | 飞思卡尔半导体公司 | Synchronous data processing system and method |
| CN102361456A (en) * | 2011-10-26 | 2012-02-22 | 华亚微电子（上海）有限公司 | Clock phase alignment and adjustment circuit |
| CN104871247A (en) * | 2012-12-28 | 2015-08-26 | 桑迪士克科技股份有限公司 | Clock generation and delay architecture |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017166660A1 (en) * | 2016-03-31 | 2017-10-05 | 乐视控股（北京）有限公司 | Secure digital card communication method and circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2017166660A1 (en) | 2017-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2587385A1 (en) | Usb key device and method for realizing intelligent card communication using usb interface | |
| KR100845525B1 (en) | Memory card system, method transferring data thereof, and semiconductor memory device | |
| US8959268B2 (en) | Information processing apparatus, serial communication system, method of initialization of communication therefor and serial communication apparatus | |
| CN105468548B (en) | Communication of serial peripheral interface | |
| CN103714029A (en) | Novel two-line synchronous communication protocol and application | |
| CN101996262B (en) | General digital verification platform for non-contact intelligent card | |
| CN109270432B (en) | Test method and test system | |
| CN105068955B (en) | A kind of local bus architecture and data interactive method | |
| US9197394B2 (en) | Clock for serial communication device | |
| CN113946480A (en) | Detection device and method for I2C bus | |
| CN108694146B (en) | Asynchronous/synchronous interface circuit | |
| CN107392292B (en) | Electronic circuit and method for transmitting data | |
| US11023023B2 (en) | Start-and-stop detecting apparatus and method for I3C bus | |
| CN105893895A (en) | Communication method and circuit for security digital cards | |
| CN111143898A (en) | Data protection method for pluggable memory device | |
| US8510485B2 (en) | Low power digital interface | |
| Kapschitz et al. | Formal verification of synchronizers | |
| CN108614491B (en) | Communication system and method for programmable logic controller | |
| CN113570050B (en) | Bidirectional asynchronous synchronous first-in first-out adapter | |
| US20050086019A1 (en) | Method and apparatus for testing a bridge circuit | |
| CN103679257B (en) | A kind of contactless payment telecommunications integrated circuit card and implementation method | |
| CN102411556B (en) | Processing unit interface for intellectual property (IP) core and automatic generation method thereof | |
| CN208190652U (en) | A kind of mainboard of full duplex Universal Synchronous Asynchronous serial transceiver | |
| CN105446863A (en) | Electronic device with recording capability and circuit status recording method | |
| CN106055306B (en) | Memory device and operating method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160824 |
|
| WD01 | Invention patent application deemed withdrawn after publication |