WO2017160447A1 - System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices - Google Patents

System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices Download PDF

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Publication number
WO2017160447A1
WO2017160447A1 PCT/US2017/017895 US2017017895W WO2017160447A1 WO 2017160447 A1 WO2017160447 A1 WO 2017160447A1 US 2017017895 W US2017017895 W US 2017017895W WO 2017160447 A1 WO2017160447 A1 WO 2017160447A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
circuit
interconnect element
interconnect
common bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2017/017895
Other languages
English (en)
French (fr)
Inventor
Anil Kumar KANDALA
Srinivasa L. KURUMAJJI
Santosh Yachareni
Sandeep Vundavalli
Udaya Kumar BOBBILI
Golla V S R K PRASAD
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Priority to KR1020187029227A priority Critical patent/KR102648516B1/ko
Priority to CN201780011375.XA priority patent/CN109075793B/zh
Priority to JP2018548759A priority patent/JP6751442B2/ja
Priority to EP17710081.5A priority patent/EP3430725B1/en
Publication of WO2017160447A1 publication Critical patent/WO2017160447A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage

Definitions

  • Programmable logic devices exist as a well-known type of integrated circuit that may be programmed by a user to perform specified logic functions.
  • PLDs One type of PLDs is known as a field programmable gate array (FPGA).
  • FPGA field programmable gate array
  • the FPGA typically includes an array of programmable tiles. These programmable tiles comprise programmable logic, programmable interconnect, and an input/output (I/O) circuitry.
  • the programmable logic implements the logic of a user design using multiple programmable elements, known as logic elements (LEs) or combinational logic blocks (CLBs). Connectivity between programmable elements is achieved through the programmable interconnect.
  • the programmable interconnect may include a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIP).
  • PIP programmable interconnect points
  • the I/O circuitry provides incoming signals to the
  • the programmable logic, interconnect and I/O circuitry can be programmed/configured to support different signal-processing applications. Circuit technologies, such as SRAM, antifuse and flash, have been used for configuring an FPGA.
  • the selection circuit comprises a multiplexer.
  • the half-latch circuit further comprises an inverter coupled to a gate of a PMOS transistor.
  • the common bias circuit comprises a variable current source, the variable current source having an input for receiving data to tune the bias voltage.
  • a method of tuning a strength of a pull-up device in one of a plurality of interconnect elements includes: providing a common bias circuit; and transmitting a tunable bias voltage from the common bias circuit to the pull-up device to adjust the strength of the pull-up device.
  • FIG. 1 -2 illustrates an interconnect element of FIG. 1 -1 .
  • FPGAs may offer several types of interconnect depending on the distance between the logic elements that are to be connected.
  • multiplexer architectures may be used to implement programmable interconnect of FPGAs.
  • Such multiplexer architectures may include a half-latch circuit, also called a bus keeper, at the output of the multiplexer to retain the state of interconnect wires.
  • the half-latch circuit may maintain the output of the multiplexer at logic voltage levels to avoid high contention current in its driver when the multiplexer is unused.
  • the half-latch circuit has to be weak enough to pass on logic signals to logic elements or interconnect.
  • programmable logic device 100 may be other types of logic device that is programmable. In other cases, the device 100 does not need to be a
  • FIG. 3 illustrates another interconnect element having a half-latch circuit according to some embodiments. Similar to the half-latch circuit 126 of FIG. 1 -2, the half-latch circuit 326 of FIG. 3 comprises an inverter 136, a PMOS transistor 138 with its gate coupled to the inverter 136 at a node 137, and a driver 140 for providing outputs of the interconnect element 122. Each half-latch circuit 326 of FIG. 3 further comprises a pull-up device 310 (e.g., a PMOS transistor) with its source coupled to power source (VDD) and its drain coupled to the source of the transistor 138.
  • a pull-up device 310 e.g., a PMOS transistor
  • the current in the variable current source 324 may be adjusted by changing a digital code stored in the storage device (e.g., register, SRAM, e-fuse, etc.) which stores the digital code for controlling the common bias circuit 320 (e.g., the current source 324 therein).
  • the VGS voltage from gate to source
  • This reduction in current will be reflected in the current of the pull- up device 310 (as the gates of the pull-up device 310 and the transistor 322 are connected, and the source of these components is at the same supply level). So the reduction in variable current source leads to a reduction in the current of the pull-up device 310. Similarly, a increase in variable current source will lead to an increase in the current of the pull-up device 310. Thus, a similar technique may be employed to increase the strength of the pull-up device 310.
  • the inverter 136, the PMOS transistor 138, and the transistor 140 do not play a role in the tuning. However, after the tuning, the delay of the path of these components will depend on the current capability of the pull-up device 310, which is affected by the tuning.
  • each programmable tile includes a programmable interconnect element (INT) 51 1 as described above that has standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA.
  • the programmable interconnect element I NT 51 1 also includes the connections to and from the programmable logic element within the same tile.
  • a CLB 502 can include a configurable logic element CLE 512 that can be programmed to implement user logic plus a single programmable interconnect element INT 51 1 .
  • a BRAM 503 can include a BRAM logic element (BRL) 513 in addition to one or more programmable interconnect elements.
  • a DSP tile 506 can include a DSP logic element (DSPL) 514 in addition to an appropriate number of programmable interconnect elements.
  • An IOB 504 can include, for example, two instances of an input/output logic element (IOL) 515 in addition to one instance of the programmable interconnect element INT 51 1 .

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
PCT/US2017/017895 2016-03-17 2017-02-15 System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices Ceased WO2017160447A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020187029227A KR102648516B1 (ko) 2016-03-17 2017-02-15 프로그래머블 로직 디바이스에서 패브릭 멀티플렉서의 풋프린트를 감소시키고 수율을 향상시키는 시스템 및 방법
CN201780011375.XA CN109075793B (zh) 2016-03-17 2017-02-15 减小可编程逻辑器件空间并提高其良率的系统和方法
JP2018548759A JP6751442B2 (ja) 2016-03-17 2017-02-15 プログラマブルロジックデバイス内のフットプリントを削減し、ファブリック多重度を向上させるシステムおよび方法
EP17710081.5A EP3430725B1 (en) 2016-03-17 2017-02-15 System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/073,389 US9680474B1 (en) 2016-03-17 2016-03-17 System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices
US15/073,389 2016-03-17

Publications (1)

Publication Number Publication Date
WO2017160447A1 true WO2017160447A1 (en) 2017-09-21

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PCT/US2017/017895 Ceased WO2017160447A1 (en) 2016-03-17 2017-02-15 System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices

Country Status (6)

Country Link
US (1) US9680474B1 (https=)
EP (1) EP3430725B1 (https=)
JP (1) JP6751442B2 (https=)
KR (1) KR102648516B1 (https=)
CN (1) CN109075793B (https=)
WO (1) WO2017160447A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9830974B1 (en) * 2017-01-22 2017-11-28 Ambiq Micro, Inch SRAM with active substrate bias
US10353853B1 (en) * 2018-04-11 2019-07-16 Cypress Semiconductor Corporation USB type-C sideband signal interface circuit
US11423952B2 (en) 2019-12-16 2022-08-23 Xilinx, Inc. Multi-chip devices

Citations (3)

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US7116131B1 (en) * 2004-09-15 2006-10-03 Xilinx, Inc. High performance programmable logic devices utilizing dynamic circuitry
US7683664B1 (en) * 2009-01-21 2010-03-23 Xilinx, Inc. Selection circuit with programmable constant output
US20150002408A1 (en) * 2013-06-28 2015-01-01 Christopher P. Mozak I/o driver transmit swing control

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JP3467936B2 (ja) * 1995-11-06 2003-11-17 セイコーエプソン株式会社 半導体装置
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US7116131B1 (en) * 2004-09-15 2006-10-03 Xilinx, Inc. High performance programmable logic devices utilizing dynamic circuitry
US7683664B1 (en) * 2009-01-21 2010-03-23 Xilinx, Inc. Selection circuit with programmable constant output
US20150002408A1 (en) * 2013-06-28 2015-01-01 Christopher P. Mozak I/o driver transmit swing control

Also Published As

Publication number Publication date
US9680474B1 (en) 2017-06-13
CN109075793A (zh) 2018-12-21
KR102648516B1 (ko) 2024-03-15
EP3430725A1 (en) 2019-01-23
JP2019512957A (ja) 2019-05-16
KR20180122408A (ko) 2018-11-12
CN109075793B (zh) 2023-02-03
EP3430725B1 (en) 2020-07-29
JP6751442B2 (ja) 2020-09-02

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