KR102648516B1 - 프로그래머블 로직 디바이스에서 패브릭 멀티플렉서의 풋프린트를 감소시키고 수율을 향상시키는 시스템 및 방법 - Google Patents

프로그래머블 로직 디바이스에서 패브릭 멀티플렉서의 풋프린트를 감소시키고 수율을 향상시키는 시스템 및 방법 Download PDF

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KR102648516B1
KR102648516B1 KR1020187029227A KR20187029227A KR102648516B1 KR 102648516 B1 KR102648516 B1 KR 102648516B1 KR 1020187029227 A KR1020187029227 A KR 1020187029227A KR 20187029227 A KR20187029227 A KR 20187029227A KR 102648516 B1 KR102648516 B1 KR 102648516B1
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pull
circuit
interconnect
logic
bias voltage
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KR20180122408A (ko
Inventor
아닐 쿠마르 칸달라
스리니바사 엘. 쿠루마찌
산토쉬 야차레니
산딥 번다발리
우다야 쿠마르 보빌리
골라 브이 에스 알 케이 프라사드
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자일링크스 인코포레이티드
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
KR1020187029227A 2016-03-17 2017-02-15 프로그래머블 로직 디바이스에서 패브릭 멀티플렉서의 풋프린트를 감소시키고 수율을 향상시키는 시스템 및 방법 Active KR102648516B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/073,389 US9680474B1 (en) 2016-03-17 2016-03-17 System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices
US15/073,389 2016-03-17
PCT/US2017/017895 WO2017160447A1 (en) 2016-03-17 2017-02-15 System and method to reduce footprint and improve yield of fabric muxes in programmable logic devices

Publications (2)

Publication Number Publication Date
KR20180122408A KR20180122408A (ko) 2018-11-12
KR102648516B1 true KR102648516B1 (ko) 2024-03-15

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KR1020187029227A Active KR102648516B1 (ko) 2016-03-17 2017-02-15 프로그래머블 로직 디바이스에서 패브릭 멀티플렉서의 풋프린트를 감소시키고 수율을 향상시키는 시스템 및 방법

Country Status (6)

Country Link
US (1) US9680474B1 (https=)
EP (1) EP3430725B1 (https=)
JP (1) JP6751442B2 (https=)
KR (1) KR102648516B1 (https=)
CN (1) CN109075793B (https=)
WO (1) WO2017160447A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9830974B1 (en) * 2017-01-22 2017-11-28 Ambiq Micro, Inch SRAM with active substrate bias
US10353853B1 (en) * 2018-04-11 2019-07-16 Cypress Semiconductor Corporation USB type-C sideband signal interface circuit
US11423952B2 (en) 2019-12-16 2022-08-23 Xilinx, Inc. Multi-chip devices

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237221A (en) * 1991-11-25 1993-08-17 Hewlett-Packard Company On-chip pull-up circuit which may be selectively disabled
JP3467936B2 (ja) * 1995-11-06 2003-11-17 セイコーエプソン株式会社 半導体装置
US5706237A (en) * 1996-10-08 1998-01-06 International Business Machines Corporation Self-restore circuit with soft error protection for dynamic logic circuits
JPH11186881A (ja) * 1997-11-28 1999-07-09 Shijie Xianjin Jiti Electric Co Ltd ラッチ装置
US6768338B1 (en) * 2003-01-30 2004-07-27 Xilinx, Inc. PLD lookup table including transistors of more than one oxide thickness
JP4060236B2 (ja) * 2003-05-28 2008-03-12 三菱電機株式会社 デジタル／アナログ変換装置およびそれを備える表示装置
US7116131B1 (en) * 2004-09-15 2006-10-03 Xilinx, Inc. High performance programmable logic devices utilizing dynamic circuitry
US7355440B1 (en) * 2005-12-23 2008-04-08 Altera Corporation Method of reducing leakage current using sleep transistors in programmable logic device
US7477073B1 (en) * 2006-06-16 2009-01-13 Xilinx, Inc. Structures and methods for heterogeneous low power programmable logic device
JP2008032812A (ja) * 2006-07-26 2008-02-14 Matsushita Electric Ind Co Ltd 出力駆動装置および表示装置
US8958576B2 (en) * 2008-11-25 2015-02-17 Invensense, Inc. Dynamically biased amplifier
US7683664B1 (en) * 2009-01-21 2010-03-23 Xilinx, Inc. Selection circuit with programmable constant output
US8743630B2 (en) * 2011-05-23 2014-06-03 Infineon Technologies Ag Current sense amplifier with replica bias scheme
JP2013223189A (ja) * 2012-04-18 2013-10-28 Elpida Memory Inc 半導体装置
JP5806972B2 (ja) * 2012-04-27 2015-11-10 セイコーインスツル株式会社 出力ドライバ回路
CN203135843U (zh) * 2012-12-31 2013-08-14 意法半导体研发（上海）有限公司 传输门电路
CN103259519A (zh) * 2013-05-27 2013-08-21 苏州贝克微电子有限公司 漏极开路信号的有源上拉电路
US9374004B2 (en) * 2013-06-28 2016-06-21 Intel Corporation I/O driver transmit swing control
JP2015115654A (ja) * 2013-12-09 2015-06-22 株式会社東芝 単相差動変換回路およびアナログフロントエンド回路

Also Published As

Publication number Publication date
US9680474B1 (en) 2017-06-13
WO2017160447A1 (en) 2017-09-21
CN109075793A (zh) 2018-12-21
EP3430725A1 (en) 2019-01-23
JP2019512957A (ja) 2019-05-16
KR20180122408A (ko) 2018-11-12
CN109075793B (zh) 2023-02-03
EP3430725B1 (en) 2020-07-29
JP6751442B2 (ja) 2020-09-02

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