WO2017147947A1 - 一种无源极电阻的大功率场效应管互补输出电路 - Google Patents

一种无源极电阻的大功率场效应管互补输出电路 Download PDF

Info

Publication number
WO2017147947A1
WO2017147947A1 PCT/CN2016/076048 CN2016076048W WO2017147947A1 WO 2017147947 A1 WO2017147947 A1 WO 2017147947A1 CN 2016076048 W CN2016076048 W CN 2016076048W WO 2017147947 A1 WO2017147947 A1 WO 2017147947A1
Authority
WO
WIPO (PCT)
Prior art keywords
branch
output
fet
voltage
field effect
Prior art date
Application number
PCT/CN2016/076048
Other languages
English (en)
French (fr)
Inventor
刘广斌
Original Assignee
广州时艺音响科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广州时艺音响科技有限公司 filed Critical 广州时艺音响科技有限公司
Publication of WO2017147947A1 publication Critical patent/WO2017147947A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits

Definitions

  • the invention relates to the field of complementary output circuits based on semiconductor components, in particular to a high power FET complementary output circuit of a passive pole resistor, which adopts a passive pole resistance design to reduce the output impedance.
  • the complementary output circuit is a common output circuit, especially in the output stage of the audio power amplifier, which is usually designed in combination with semiconductor components such as field effect transistors, transistors, and the like.
  • the FET is a voltage control component, which is easier to drive than the triode, so it is favored by audio power amplifier designers in recent new products.
  • Large output power for example, a pure Class A output of 50 watts or more, or a Class A output of 70-700 watts or higher
  • Large output power usually requires a very large current output capability.
  • the pursuit of greater output current the following four problems are often encountered:
  • high-current FET tube withstand voltage is usually relatively low, according to the traditional complementary output design, and can not increase the supply voltage to the high-power output demand voltage.
  • the nominal impedance of the products on the market is deterministic, usually 4 ohms to 8 ohms. In the case of constant load, only large current output capability is not enough, and there is enough voltage to output high power, otherwise the surplus current output capability is not actually used.
  • High-current FETs, gate-source capacitance (Cgs), gate-drain capacitance (Cgd), and drain-source capacitance (Cds) are usually large. This reduces the response frequency of the output and also increases the requirements for the driver circuit as a signal input.
  • the present invention provides a high-power FET complementary output circuit of a passive pole resistor, which can realize a low output impedance, and has a large current output capability and a high-voltage complementary output with high withstand voltage.
  • the invention relates to a passive pole resistance high power FET complementary output circuit, comprising a FET complementary output branch, a first FET offset branch, a second FET offset branch, and a a partial pressure tube group branch, a second partial pressure tube group branch, a first partial pressure tube group bias branch, and a second partial pressure tube group offset branch; wherein the field effect tube complementary output branch includes complementary The first effect transistor output branch and the second FET output branch, and the source terminals of the two are directly connected as complementary output signal terminals;
  • the first FET bias branch is connected to the gate terminal of the first FET output branch to provide a bias voltage for the first FET output branch;
  • the second FET bias branch is connected to the second The gate terminal of the FET output branch provides a bias voltage for the second FET output branch;
  • the first FET bias branch and the second FET bias branch are connected as an input signal end;
  • the drain terminal of the first voltage dividing tube branch is connected to the positive power source, the source terminal of the first voltage dividing tube group branch is connected to the drain terminal of the first field effect transistor output branch, and the first field effect transistor output branch is connected
  • the drain-source voltage of the circuit is divided;
  • the biasing branch of the first voltage-dividing tube group is connected to the gate terminal of the branch of the first voltage-dividing tube group, and provides a bias voltage for the biasing branch of the first voltage-dividing tube group;
  • the drain terminal of the second voltage dividing tube group branch is connected to the negative power source, the source terminal of the second voltage dividing tube group branch is connected to the drain terminal of the second field effect transistor output branch, and the second field effect tube output branch is connected
  • the drain-source voltage of the circuit is divided; the biasing branch of the second voltage-dividing tube is connected to the gate terminal of the branch of the second voltage-dividing tube group to provide a bias voltage for the biasing branch of the second voltage-dividing tube group.
  • a clamp protection branch is further included, the clamp protection branch being coupled between the input signal terminal and the complementary output signal terminal.
  • the first constant current source and the second constant current source are further included; the output end of the first constant current source and the input end of the biasing branch of the first voltage dividing tube group Connecting; the input end of the second constant current source and the second partial pressure The output of the tube set bias branch is connected.
  • the third constant current source and the fourth constant current source are further included; the output end of the third constant current source is connected to the input end of the first FET bias branch The input end of the fourth constant current source is connected to the output end of the second FET bias branch.
  • the first FET output branch includes an N-type FET Q4 and a resistor R5 connected to the gate of the N-type FET Q4; a gate of the N-type FET Q4, The drain and source corresponding connection ends are respectively the gate terminal, the drain terminal and the source terminal of the first FET output branch; the second FET output branch includes a P-type field effect transistor Q5 and is connected to the P-type field The resistor R8 of the gate of the effect transistor Q5; the connection terminal corresponding to the gate, the drain and the source of the P-type field effect transistor Q5 is the gate terminal, the drain terminal and the source terminal of the output branch of the second FET, respectively.
  • the first FET bias branch includes a resistor R4, a resistor R6, a thermistor NTC1, and a coupling capacitor C2; the first end of the coupling capacitor C2 is connected to the input end of the resistor R5; The input end of R4 is connected to the first end of the coupling capacitor C2 and is used for connecting a positive current; the resistor R6 and the thermistor NTC1 are connected in parallel to form a first thermal branch, and the input end and the output end of the first thermal branch Connected to the output end of the resistor R4 and the second end of the coupling capacitor C2;
  • the second FET bias branch includes a resistor R9, a resistor R7, a thermistor NTC2, and a coupling capacitor C3; a second end of the coupling capacitor C3 is connected to an input terminal of the resistor R8; and an output terminal of the resistor R9 and the coupling capacitor C3
  • the two ends are connected and used for connecting a negative current;
  • the resistor R7 and the thermistor NTC2 are connected in parallel to form a second thermal branch, and the output end and the input end of the second thermal branch are respectively connected with the input end of the resistor R9 and the coupling capacitor
  • the first end of C3 is connected;
  • the input signal end includes a first signal input end; an output end of the first thermal branch and an input end of the second thermal branch are connected to each other as the first input signal end.
  • the first partial pressure tube group branch includes a plurality of sets of first partial pressure branches connected in parallel;
  • the second partial pressure tube group branch includes a plurality of sets of second partial pressure branches connected in parallel with each other road.
  • the first voltage dividing branch includes an N-type field effect transistor Q1 and a resistor R1 connected to the gate of the N-type field effect transistor Q1; a gate of the N-type field effect transistor Q1,
  • the connection terminals corresponding to the drain and the source are respectively a gate terminal, a drain terminal and a source terminal of the branch of the first voltage dividing tube group;
  • the second voltage dividing branch includes a P-type field effect transistor Q6 and a resistor R10 connected to the gate of the P-type field effect transistor Q6; the gate, the drain and the source corresponding to the P-type field effect transistor Q6 are respectively connected It is the gate terminal, the drain terminal and the source terminal of the second voltage divider group branch.
  • the first voltage dividing tube bias branch includes a parallel Zener diode D1 and a coupling capacitor C1; wherein the cathode of the Zener diode D1 is connected to the first end of the coupling capacitor C1, The anode of the Zener diode D1 is connected to the second end of the coupling capacitor C1;
  • the second voltage dividing tube bias branch includes a parallel voltage regulator D2 and a coupling capacitor C4; wherein the cathode of the Zener diode D2 is connected to the first end of the coupling capacitor C4, and the anode of the Zener diode D2 and the coupling capacitor C2 The second end of the connection.
  • the input signal terminal further includes a second signal input terminal; a parallel output terminal of the Zener diode D1 and the coupling capacitor C1 is connected between the parallel input terminal of the Zener diode D2 and the coupling capacitor C4. Interconnected as the second signal input.
  • the output tube (field effect tube) of the complementary output branch of the field effect tube consumes power at the time of large current output. It is not large and does not easily lead to positive temperature feedback. Therefore, the source resistance at the output of the FET complementary output branch can be removed, achieving low output impedance, and having a large current output capability and a high-voltage complementary output with high withstand voltage.
  • the large-span FET cannot be selected in the case of removing the source resistance in high-power applications, but the present invention can
  • the use of a large-span FET as an output tube further reduces the output impedance and the current is still stable (in one of the solutions with a thermal branch of the present invention, the quiescent current can be further stabilized).
  • the large current FET can be used as the output tube, and the voltage drop is relatively constant. During the dynamic working process, the parasitic capacitance does not need to be charged and discharged frequently, so the response frequency is not significantly reduced due to excessive parasitic capacitance.
  • FIG. 1 is a schematic diagram of a first circuit structure of a high power FET complementary output circuit of a passive pole resistor according to an embodiment.
  • FIG. 2 is a schematic diagram showing a second circuit structure of a high power FET complementary output circuit of a passive pole resistor according to an embodiment.
  • FIG. 3 is a schematic diagram of a third circuit structure of a high power FET complementary output circuit of a passive pole resistor according to an embodiment.
  • a high-power FET complementary output circuit for passive pole resistance which comprises a FET complementary output branch, a first FET bias branch, and a second FET bias branch Road, first partial pressure pipe group branch, second partial pressure pipe group branch, first partial pressure pipe group offset branch, second partial pressure pipe group offset branch; wherein, field effect tube complementary output branch
  • the path includes a complementary first FET output branch and a second FET output branch, the source terminals of which are directly connected as complementary output signal terminals.
  • the first FET output branch includes an N-type FET Q4 and a resistor R5 connected to the gate of the N-type FET Q4; the second FET output branch includes a P-type field effect.
  • the tube Q5 and the resistor R8 connected to the gate of the P-type field effect transistor Q5; the complementary output signal terminals of the first FET output branch and the second FET output branch are as shown in the OUT terminal of FIG.
  • the first FET bias branch includes a resistor R4, a resistor R6, a thermistor NTC1, and a coupling capacitor C2.
  • the second FET bias branch includes a resistor R9, a resistor R7, a thermistor NTC2, and a coupling capacitor C3.
  • the first voltage divider group branch includes an N-type field effect transistor Q1 and a resistor R1, an N-type field effect transistor Q2, and a resistor R2 and the like (the parallel data can be designed according to specific needs); the second voltage divider group branch Including P-type field effect transistor Q6 and resistor R10, P-type field effect transistor Q7 and resistor R11 and other related branches (the number of parallel can be designed according to specific needs); the first partial pressure tube set offset branch package
  • the parallel voltage regulator D1 and the coupling capacitor C1 are included;
  • the second voltage divider group bias branch includes a parallel voltage regulator D2 and a coupling capacitor C4.
  • FIG. 1 is only a specific circuit scheme designed to introduce the present invention, and does not mean that the present invention can only use the scheme of FIG. 1.
  • the circuit components in FIG. 1 can be as needed. Replacement with other equivalent components, circuit connections can also use other equivalent connections.
  • the first FET bias branch is connected to the gate terminal of the first FET output branch to provide a bias voltage for the first FET output branch; the second FET bias branch connection Providing a bias voltage for the second FET output branch at the gate terminal of the second FET output branch; the first FET bias branch and the second FET bias branch are interconnected As the input signal end, as shown in the IN terminal of Figure 1.
  • the drain terminal of the branch of the first voltage dividing tube group is connected to the positive power source (+VCC in Fig. 1), and the source terminal of the branch of the first voltage dividing tube group is opposite to the drain terminal of the output branch of the first field effect transistor Connecting, dividing the drain-source voltage of the first FET output branch; the first voltage-dividing tube bias branch is connected to the gate end of the first voltage-dividing tube branch, and is the first voltage-dividing tube group
  • the bias branch provides a bias voltage.
  • the drain terminal of the branch of the second voltage dividing tube group is connected to the negative power supply (-VCC in Fig. 1), the source terminal of the branch of the second voltage dividing tube group and the drain terminal of the output branch of the second field effect transistor Connecting, dividing the drain-source voltage of the output branch of the second field effect transistor; the biasing branch of the second voltage dividing tube is connected to the gate end of the branch of the second voltage dividing tube group, and is the second partial pressure tube group
  • the bias branch provides a bias voltage.
  • the gate terminal, the source terminal and the drain terminal are connection terminals corresponding to the gate, the source and the drain of the corresponding field effect transistor in each branch.
  • the drain-source voltage is the voltage drop of the corresponding FET, that is, the FET.
  • the N-type field effect transistor Q4 and the P-type field effect transistor Q5 are both large current field effect transistors, and there is no output resistance between the sources of the two, but directly communicated as the output terminal OUT.
  • the quiescent current does not rise significantly with the increase of temperature to form positive feedback.
  • the pressure drop of N-type FET Q4 and P-type FET Q5 can be controlled at a very low level, usually N-type.
  • the voltage drop of each of FET Q4 and P-type FET Q5 is within 10 volts. Thus, even if a large current is passed, neither the N-type field effect transistor Q4 nor the P-type field effect transistor Q5 will have much heat.
  • the first partial pressure branch group branch and the second partial pressure tube group branch During the whole work process, most of the voltage and dissipated power will be taken up by the first partial pressure branch group branch and the second partial pressure tube group branch, and the first partial pressure tube group branch and the second partial pressure tube group branch.
  • the number of parallels of the road can be increased or decreased as needed. Because, in general, the field effect transistor that also dissipates power, the high-voltage FET current is small, and the low-voltage FET current is large. This circuit combines the advantages of both.
  • the method may include, but is not limited to, the first FET output branch includes an N-type field effect transistor Q4 and a resistor R5 connected to the gate of the N-type FET Q4; the N-type field effect transistor
  • the gate, drain, and source corresponding terminals of Q4 are the gate terminal, the drain terminal, and the source terminal of the first FET output branch, respectively.
  • the second FET output branch includes a P-type field effect transistor Q5 and a resistor R8 connected to the gate of the P-type FET Q5; the gate, the drain and the source corresponding to the P-type field effect transistor Q5 are respectively connected The gate terminal, the drain terminal, and the source terminal of the branch of the second FET output branch.
  • the FET output branch in the present invention is not limited to two. According to specific needs, the connection scheme of the first FET output branch and the second FET output branch may be referred to, and Need to increase it.
  • the first field effect transistor bias branch includes a resistor R4, a resistor R6, a thermistor NTC1, and a coupling capacitor C2.
  • the first end of the coupling capacitor C2 is connected to the resistor R5.
  • the input end of the resistor R4 is connected to the first end of the coupling capacitor C2 and is used for connecting a positive current (which can be connected to the current source as shown in the output terminal of the constant current source I1 in FIG. 1); the resistor R6 and the heat sensitive
  • the resistor NTC1 is connected in parallel to form a first thermal branch, and the input end and the output end of the first thermal branch are respectively connected to the output end of the resistor R4 and the second end of the coupling capacitor C2.
  • the second FET bias branch includes a resistor R9, a resistor R7, a thermistor NTC2, and a coupling capacitor C3; a second end of the coupling capacitor C3 is connected to an input terminal of the resistor R8; and an output terminal of the resistor R9 and the coupling capacitor C3
  • the two ends are connected and used to connect a negative current (which can be connected to the current source as shown in the input terminal of the constant current source I2 in FIG. 1); the resistor R7 and the thermistor NTC2 are connected in parallel to form a second thermal branch, the second thermal The output and the input of the branch are respectively coupled to the input of the resistor R9
  • the first end of the capacitor C3 is connected.
  • the output end of the first thermal branch and the input end of the second thermal branch are connected to each other as an input signal terminal, i.e., an IN terminal.
  • the thermistor NTC1 and the thermistor NTC2 are both negative temperature coefficient thermistors, and the function is to reduce the temperature drift effect of the N-type field effect transistor Q4 and the P-type field effect transistor Q5.
  • the thermistor NTC1 and the N-type field effect transistor Q4 are closely mounted on the same heat sink, and a remarkable effect can be obtained.
  • the thermistor NTC2 is similar to the P-type field effect transistor Q5.
  • the first partial pressure tube group branch may include a plurality of sets of first partial pressure branches connected in parallel with each other; the second partial pressure tube group branch may include a plurality of sets of second partial pressure branches connected in parallel with each other.
  • the first voltage dividing branch includes an N-type field effect transistor Q1 and a resistor R1 connected to the gate of the N-type field effect transistor Q1; and the N-type field effect transistor Q1
  • the connection terminals corresponding to the gate, the drain and the source are respectively the gate terminal, the drain terminal and the source terminal of the branch of the first voltage dividing tube group.
  • the N-type field effect transistor Q2 and the gate resistance R2 and N type fields in Fig. 1 The effect transistor Q3 and the resistor R3 of the gate may each be referred to as a first voltage dividing branch.
  • the second voltage dividing branch includes a P-type field effect transistor Q6 and a resistor R10 connected to the gate of the P-type field effect transistor Q6; the connection terminals of the gate, the drain and the source of the P-type field effect transistor Q6 are respectively Dividing the gate, drain and source terminals of the branch group branch.
  • a P-type field effect transistor Q6 and a resistor R10 connected to the gate of the P-type field effect transistor Q6; the connection terminals of the gate, the drain and the source of the P-type field effect transistor Q6 are respectively Dividing the gate, drain and source terminals of the branch group branch.
  • the P-type field effect transistor Q7 and the gate resistor R11 and P field in Fig. 1 The effect transistor Q8 and the gate resistor R12 may each be referred to as a second voltage dividing branch.
  • the first voltage dividing tube group branch and the second voltage dividing tube group branch are not limited to the field effect tube, and the triode tube may be used instead.
  • the first voltage dividing tube group biasing branch includes a parallel voltage stabilizing tube D1 and a coupling capacitor C1.
  • the cathode of the Zener diode D1 and the coupling capacitor C1 are included.
  • the first end is connected, the anode of the Zener diode D1 Connected to the second end of the coupling capacitor C1.
  • the second voltage dividing tube bias branch includes a parallel voltage regulator D2 and a coupling capacitor C4; wherein the cathode of the Zener diode D2 is connected to the first end of the coupling capacitor C4, and the anode of the Zener diode D2 and the coupling capacitor C2 The second end of the connection.
  • the clamp protection branch is an added branch in the more optimized scheme of the embodiment, which is connected between the input signal end and the complementary output signal end, so as to prevent the input signal end, that is, the IN end and the complementary signal output end,
  • the voltage difference between the OUT terminals is too high to avoid the damage caused by the Vgs and Vds of the N-type FET Q4 and the P-type field Q5 exceeding the limit voltage of the component.
  • the clamp protection branch includes a Zener diode D3 and a Zener diode D4, and the connection directions of the two are opposite.
  • the anode of the Zener diode D3 is connected to the input signal terminal, that is, the IN terminal, and the cathode is connected to the cathode of the Zener diode D4; the anode of the Zener diode D4 is connected to the complementary output signal terminal, that is, the OUT terminal.
  • the Zener diode D3 and the Zener diode D4 can be exchanged.
  • the voltage at the input terminal of the resistor R4 is relatively stable with respect to the voltage at the IN terminal, and the resistor R5 has almost no voltage drop and can be ignored. Then the input terminal voltage of the resistor R4 is equal to the gate voltage of the N-type field effect transistor Q4, and the Vgs withstand voltage of the general field effect transistor is about 20V, so if the IN input signal is positive, and the OUT output load is too Heavy (such as in the case of a short circuit) may cause the pressure difference of the Vgs of the N-type field effect transistor Q4 to exceed the withstand voltage, thereby causing damage.
  • the clamp protection branch is added, and the voltage difference between the IN terminal and the OUT terminal is not greater than the total voltage difference between the Zener diode D3 and the Zener diode D4.
  • the input terminal voltage of the resistor R4 does not exceed the maximum withstand voltage of the gate voltage of the N-type field effect transistor Q4, that is, in theory, even if the circuit is short-circuited, it does not occur because the gate is broken down.
  • the N-type field effect transistor Q4 is burned off.
  • the above-mentioned clamp protection branch is similar to the protection of the P-type field effect transistor Q5.
  • the IN terminal there may be only one input signal end, such as the NI end in FIG. 1 or FIG. 2, or more than two, as shown in FIG. 3 including the IN 1 end and the IN 2 end.
  • the output ends of the first thermal branch (resistor R6 and thermistor NTC1) and the input ends of the second thermal branch (resistor R7 and thermistor NTC2) are mutually connected. Connection
  • the input signal terminal that is, the IN terminal, in FIG. 1 or FIG. 2
  • the IN terminal can be directly referred to as a signal input terminal, which is equivalent to the IN 1 terminal in FIG. 3, and is also convenient for description.
  • FIG. 3 is also referred to as a first signal input terminal, and the IN 2 terminal in FIG. 3 may be referred to as a second signal input terminal, which is connected to the parallel output terminal of the Zener diode D1 and the coupling capacitor C1 and the Zener diode. D2 and the parallel input terminals of the coupling capacitor C4 are connected to each other.
  • the IN 1 terminal and the IN 2 terminal can input two in-phase driving signals or the same driving signal, and even the two can directly connect the wires.
  • a constant current source can be used as the driving, and as shown in FIG. 1 or FIG. 2, the first constant current source I1 and the second constant current source I2 can be included; the output end of the first constant current source I1 and the first The input end of the biasing branch of the one-voltage tube group (the Zener diode D1 and the coupling capacitor C1) is connected; the input end of the second constant current source and the biasing branch of the second voltage dividing tube group (the Zener diode D2 and the coupling) The output of capacitor C4) is connected.
  • FIG. 3 may further include a third constant current source I3 and a fourth constant current source I4; an output end of the third constant current source I3 and an input end of the first field effect transistor bias branch (resistor R4) The input end of the fourth constant current source is connected to the output end of the second field effect transistor bias branch (resistor R9).
  • a third constant current source I3 and a fourth constant current source I4 an output end of the third constant current source I3 and an input end of the first field effect transistor bias branch (resistor R4)
  • the input end of the fourth constant current source is connected to the output end of the second field effect transistor bias branch (resistor R9).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)

Abstract

提供一种无源极电阻的大功率场效应管互补输出电路，其主要包括场效应管互补输出支路、第一场效应管偏置支路、第二场效应管偏置支路、第一分压管组支路、第二分压管组支路、第一分压管组偏置支路和第二分压管组偏置支路；其中第一分压管组支路及第二分压管组支路能够承受大部分的电压及耗散功率，从而可去除场效应管互补输出支路输出端的源极电阻，实现低输出阻抗，拥有大的电流输出能力和高耐压的大功率互补输出。

Description

一种无源极电阻的大功率场效应管互补输出电路 技术领域
本发明涉及基于半导体元件的互补输出电路领域，尤其涉一种无源极电阻的大功率场效应管互补输出电路，其采用无源极电阻设计以降低输出阻抗。
背景技术
互补输出电路是一种常见的输出电路，尤其是在音频功率放大器的输出级占据着主流地位，其通常结合半导体元件，例如场效应管、三极管等设计而成。
其中，场效应管为电压控制元件，比三极管更易于驱动，所以在近期的新产品中更受到音频功率放大器设计师们的青睐。大的输出功率(例如50瓦以上纯甲类输出，或70-700瓦甚至更高的甲乙类输出)通常需要非常大的电流输出能力。然而，在追求更大的输出电流的过程中，往往会碰到以下四个问题：
1、大电流的场效应管作为互补输出时，在栅极电压不变的情况下，电流会随场效应管的温度升高而增大，进而温度变得更高，形成正反馈，很容易烧毁作为功率输出的场效应管。所以一般会在两个互补的场效应管的源极之间增加电阻作为电流负反馈，以稳定其电流。然而这仅是妥协的方案，因为这样会提高输出阻抗，抑制最大电流输出，增加损耗。更好的设计应该是采用无源极电阻输出，同时能保证电流的稳定。
2、大电流的场效应管耐压通常比较低，按照传统的互补输出设计，并不能把供电电压提升到大功率输出的需求电压。尤其是音频功率放大器，作为负载的喇叭，市面上的产品的标称阻抗是确定的，通常为4欧姆到8欧姆。在负载不变的情况下，仅仅有大电流输出能力是不够，还要有足够的电压，才能输出大功率，否则富余的电流输出能力并没有被实际用上。
3、大电流的场效应管，栅-源电容(Cgs)、栅-漏电容(Cgd)和漏-源电容(Cds)通常都比较大。这就降低了输出的响应频率，也提高了对作为信号输入的驱动电路的要求。
4、为了增加输出功率，通常会采用多管并联的方式。一般的互补输出电路，为了获得 更佳的性能，会进行晶体管(场效应管)配对，但由于晶体管的离散性比较大，配对数量越大，配对精度要求越高，那么配对的难度就越大。需要从成千上万对晶体管里面，才能挑出几十对符号要求的，成本大大提高。
发明内容
基于以上问题，本发明提供一种无源极电阻的大功率场效应管互补输出电路，其可实现低输出阻抗，同时拥有大的电流输出能力和高耐压的大功率互补输出。
本发明提出的一种无源极电阻的大功率场效应管互补输出电路，包括场效应管互补输出支路、第一场效应管偏置支路、第二场效应管偏置支路、第一分压管组支路、第二分压管组支路、第一分压管组偏置支路、第二分压管组偏置支路；其中，场效应管互补输出支路包括互补的第一场效应管输出支路和第二场效应管输出支路，二者的源极端之间直接连接作为互补输出信号端；
第一场效应管偏置支路连接在第一场效应管输出支路的栅极端，为第一场效应管输出支路提供偏置电压；第二场效应管偏置支路连接在第二场效应管输出支路的栅极端，为第二场效应管输出支路提供偏置电压；第一场效应管偏置支路和第二场效应管偏置支路之间相互连接作为输入信号端；
第一分压管组支路的漏极端接入正电源，第一分压管组支路的源极端与第一场效应管输出支路的漏极端相连接，对第一场效应管输出支路的漏源电压进行分压；第一分压管组偏置支路连接在第一分压管组支路的栅极端，为第一分压管组偏置支路提供偏置电压；
第二分压管组支路的漏极端接入负电源，第二分压管组支路的源极端与第二场效应管输出支路的漏极端相连接，对第二场效应管输出支路的漏源电压进行分压；第二分压管组偏置支路连接在第二分压管组支路的栅极端，为第二分压管组偏置支路提供偏置电压。
在本发明的其中一优选方案中，还包括钳位保护支路，所述钳位保护支路连接在所述输入信号端和互补输出信号端之间。
在本发明的其中一优选方案中，还包括第一恒流源和第二恒流源；所述第一恒流源的输出端与所述第一分压管组偏置支路的输入端连接；所述第二恒流源的输入端与所述第二分压 管组偏置支路的输出端连接。
在本发明的其中一优选方案中，还包括第三恒流源和第四恒流源；所述第三恒流源的输出端与所述第一场效应管偏置支路的输入端连接；所述第四恒流源的输入端与所述第二场效应管偏置支路的输出端连接。
在本发明的其中一优选方案中，第一场效应管输出支路包括N型场效应管Q4以及连接在N型场效应管Q4栅极的电阻R5；N型场效应管Q4的栅极、漏极、源极对应的连接端分别为第一场效应管输出支路的栅极端、漏极端和源极端；第二场效应管输出支路包括P型场效应管Q5以及连接在P型场效应管Q5栅极的电阻R8；P型场效应管Q5的栅极、漏极、源极对应的连接端分别为第二场效应管输出支路的栅极端、漏极端和源极端。
在本发明的其中一优选方案中，第一场效应管偏置支路包括电阻R4、电阻R6、热敏电阻NTC1以及耦合电容C2；耦合电容C2的第一端连接电阻R5的输入端；电阻R4的输入端与耦合电容C2的第一端连接且用于连接正电流；所述电阻R6和热敏电阻NTC1并联成第一热敏支路，第一热敏支路的输入端与输出端分别与电阻R4的输出端、耦合电容C2的第二端连接；
第二场效应管偏置支路包括电阻R9、电阻R7、热敏电阻NTC2以及耦合电容C3；耦合电容C3的第二端连接电阻R8的输入端；电阻R9的输出端与耦合电容C3的第二端连接且用于连接负电流；所述电阻R7和热敏电阻NTC2并联成第二热敏支路，第二热敏支路的输出端与输入端分别与电阻R9的输入端、耦合电容C3的第一端连接；
所述输入信号端包括第一信号输入端；所述第一热敏支路的输出端与所述第二热敏支路的输入端之间相互连接作为所述第一输入信号端。
在本发明的其中一优选方案中，第一分压管组支路包括若干组相互并联的第一分压支路；第二分压管组支路包括若干组相互并联的第二分压支路。
在本发明的其中一优选方案中，所述第一分压支路包括N型场效应管Q1以及连接在N型场效应管Q1栅极的电阻R1；N型场效应管Q1的栅极、漏极、源极对应的连接端分别为第一分压管组支路的栅极端、漏极端和源极端；
所述第二分压支路包括P型场效应管Q6以及连接在P型场效应管Q6栅极的电阻R10；P型场效应管Q6的栅极、漏极、源极对应的连接端分别为第二分压管组支路的栅极端、漏极端和源极端。
在本发明的其中一优选方案中，第一分压管组偏置支路包括并联的稳压管D1和耦合电容C1；其中，稳压管D1的阴极与耦合电容C1的第一端连接，稳压管D1的阳极与耦合电容C1的第二端连接；
第二分压管组偏置支路包括并联的稳压管D2和耦合电容C4；其中，稳压管D2的阴极与耦合电容C4的第一端连接，稳压管D2的阳极与耦合电容C2的第二端连接。
在本发明的其中一优选方案中，所述输入信号端还包括第二信号输入端；稳压管D1和耦合电容C1的并联输出端与稳压管D2和耦合电容C4的并联输入端之间相互连接作为所述第二信号输入端。
本发明提出的一种无源极电阻的大功率场效应管互补输出电路至少具备以下有益效果：
1、由于第一分压管组支路、第二分压管组支路的存在，使得场效应管互补输出支路的输出管(场效应管)在大电流输出的时候，耗散功率并不大，不容易导致温度正反馈，因此可去除(场效应管互补输出支路)输出端的源极电阻，实现低输出阻抗，且拥有大的电流输出能力和高耐压的大功率互补输出。
2、由于大跨导的场效应管的温度特性更明显，如果没有稳定的电路设计，在大功率场合去除源极电阻的情况下是不能选用大跨导场效应管的，而本发明则可使用大跨导场效应管作为输出管，进一步降低输出阻抗，且电流依然稳定(在本发明其中一具有热敏支路的方案中，可使静态电流进一步稳定)。
3、可以采用大电流场效应管作为输出管，压降相对比较恒定，动态工作过程中不需要对寄生电容进行频繁的充电和放电，因而不会因寄生电容过大而显著降低响应频率。
4、只用少数的输出管(场效应管)即可输出大功率，一般情况下一至两对输出管就足够了使用，因而降低了输出管的配对难度。此外，由于第一分压管组支路和第二分压管组支路并不直接连接互补输出信号端，因此第一分压管组支路和第二分压管组支路(分压管)的 输出特性曲线的差异性并不影响互补输出信号端的信号输出特性，也不会导致互补输出信号端的输出信号失真，因此分压管不需要进行配对。
附图说明
图1是实施例提出的一种无源极电阻的大功率场效应管互补输出电路的第一种电路结构示意图。
图2中是实施例提出的一种无源极电阻的大功率场效应管互补输出电路的第二种电路结构示意图。
图3中是实施例提出的一种无源极电阻的大功率场效应管互补输出电路的第三种电路结构示意图。
具体实施方式
为了便于本领域技术人员理解，下面将结合附图以及实施例对本发明进行进一步描述。
整体实施例电路结构
本发明实施例提出的一种无源极电阻的大功率场效应管互补输出电路，其包括场效应管互补输出支路、第一场效应管偏置支路、第二场效应管偏置支路、第一分压管组支路、第二分压管组支路、第一分压管组偏置支路、第二分压管组偏置支路；其中，场效应管互补输出支路包括互补的第一场效应管输出支路和第二场效应管输出支路，二者的源极端之间直接连接作为互补输出信号端。
以图1为例，则第一场效应管输出支路包括N型场效应管Q4以及连接在N型场效应管Q4栅极的电阻R5；第二场效应管输出支路包括P型场效应管Q5以及连接在P型场效应管Q5栅极的电阻R8；第一场效应管输出支路和第二场效应管输出支路的互补输出信号端如图1中OUT端。第一场效应管偏置支路包括电阻R4、电阻R6、热敏电阻NTC1以及耦合电容C2；第二场效应管偏置支路包括电阻R9、电阻R7、热敏电阻NTC2以及耦合电容C3。第一分压管组支路包括N型场效应管Q1和电阻R1、N型场效应管Q2和电阻R2等关联支路(并联数据可根据具体需要设计)；第二分压管组支路包括P型场效应管Q6和电阻R10、P型场效应管Q7和电阻R11等关联支路(并联数量可根据具体需要设计)；第一分压管组偏置支路包 括并联的稳压管D1和耦合电容C1；第二分压管组偏置支路包括并联的稳压管D2和耦合电容C4。
当然，图1只是为了介绍本发明而设计出来的一种具体电路方案，并不代表本发明仅能使用图1的方案，在本发明的设计构思内，图1中的各电路元件可根据需要用其他等效元件代换，电路连接也可采用其他等效连接方式。
首先可参阅图1，本发明实施例的整体方案如下：
(1)第一场效应管偏置支路连接在第一场效应管输出支路的栅极端，为第一场效应管输出支路提供偏置电压；第二场效应管偏置支路连接在第二场效应管输出支路的栅极端，为第二场效应管输出支路提供偏置电压；第一场效应管偏置支路和第二场效应管偏置支路之间相互连接作为输入信号端，如图1中IN端。
(2)第一分压管组支路的漏极端接入正电源(图1中+VCC)，第一分压管组支路的源极端与第一场效应管输出支路的漏极端相连接，对第一场效应管输出支路的漏源电压进行分压；第一分压管组偏置支路连接在第一分压管组支路的栅极端，为第一分压管组偏置支路提供偏置电压。
(3)第二分压管组支路的漏极端接入负电源(图1中-VCC)，第二分压管组支路的源极端与第二场效应管输出支路的漏极端相连接，对第二场效应管输出支路的漏源电压进行分压；第二分压管组偏置支路连接在第二分压管组支路的栅极端，为第二分压管组偏置支路提供偏置电压。
其中，上述栅极端、源极端、漏极端为各支路中对应的场效应管的栅极、源极、漏极对应的连接端。漏源电压即为对应的场效应管的Vds也即场效应管的压降。
整体实施例效果分析
以图1为例，N型场效应管Q4与P型场效应管Q5均为大电流场效应管，且二者的源极之间没有输出电阻，而是直接连通作为输出端OUT。为了保证大电流输出的同时，静态电流不随温度升高而显著升高形成正反馈，N型场效应管Q4与P型场效应管Q5的压降可以控制在非常低的水平，通常是N型场效应管Q4与P型场效应管Q5各自的压降都在10伏以内。 这样，即使有大电流通过，N型场效应管Q4与P型场效应管Q5都不会有太大的发热。
整个工作过程中，大部分的电压及耗散功率将由第一分压管组支路及第二分压管组支路承受，并且第一分压管组支路及第二分压管组支路的并联数量可以按需增加或者减少。因为通常，同样耗散功率的场效应管，高耐压的场效应管电流小，低耐压的场效应管电流大。此电路可以将两者的优点结合起来。
支路电路结构
1、第一场效应管输出支路、第二场效应管输出支路
本实施例中，可以包括但不限于图1所示：第一场效应管输出支路包括N型场效应管Q4以及连接在N型场效应管Q4栅极的电阻R5；N型场效应管Q4的栅极、漏极、源极对应的连接端分别为第一场效应管输出支路的栅极端、漏极端和源极端。
第二场效应管输出支路包括P型场效应管Q5以及连接在P型场效应管Q5栅极的电阻R8；P型场效应管Q5的栅极、漏极、源极对应的连接端分别为第二场效应管输出支路的栅极端、漏极端和源极端。
需要说明的是，本发明中的场效应管输出支路并不仅限于两支，根据具体需要，可以参照第一场效应管输出支路和第二场效应管输出支路的连接方案，另外按需增加即可。
2、第一场效应管偏置支路、第二场效应管偏置支路
本实施例中，可以包括但不限于图1所示：第一场效应管偏置支路包括电阻R4、电阻R6、热敏电阻NTC1以及耦合电容C2；耦合电容C2的第一端连接电阻R5的输入端；电阻R4的输入端与耦合电容C2的第一端连接且用于连接正电流(可连接在电流源如图1中恒流源I1的输出端)；所述电阻R6和热敏电阻NTC1并联成第一热敏支路，第一热敏支路的输入端与输出端分别与电阻R4的输出端、耦合电容C2的第二端连接。
第二场效应管偏置支路包括电阻R9、电阻R7、热敏电阻NTC2以及耦合电容C3；耦合电容C3的第二端连接电阻R8的输入端；电阻R9的输出端与耦合电容C3的第二端连接且用于连接负电流(可连接在电流源如图1中恒流源I2的输入端)；所述电阻R7和热敏电阻NTC2并联成第二热敏支路，第二热敏支路的输出端与输入端分别与电阻R9的输入端、耦合 电容C3的第一端连接。
图1中第一热敏支路的输出端与第二热敏支路的输入端之间相互连接作为输入信号端即IN端。
本实施例中，热敏电阻NTC1和热敏电阻NTC2均为负温度系数热敏电阻，作用是减少N型场效应管Q4、P型场效应管Q5的温漂效应。优选将热敏电阻NTC1与N型场效应管Q4近距离安装在同一散热器上，能够获得显著的效果，热敏电阻NTC2与P型场效应管Q5亦是同理。
3、第一分压管组支路、第二分压管组支路
第一分压管组支路可以包括若干组相互并联的第一分压支路；第二分压管组支路可以包括若干组相互并联的第二分压支路。
本实施例中，可以包括但不限于图1所示：第一分压支路包括N型场效应管Q1以及连接在N型场效应管Q1栅极的电阻R1；N型场效应管Q1的栅极、漏极、源极对应的连接端分别为第一分压管组支路的栅极端、漏极端和源极端。当然，这里仅是取图1中第一分压管组支路的一分压支路为例进行介绍，同理，图1中N型场效应管Q2及栅极的电阻R2、N型场效应管Q3及栅极的电阻R3分别均可称为第一分压支路。
第二分压支路包括P型场效应管Q6以及连接在P型场效应管Q6栅极的电阻R10；P型场效应管Q6的栅极、漏极、源极对应的连接端分别为第二分压管组支路的栅极端、漏极端和源极端。当然，这里仅是取图1中第二分压管组支路的一分压支路为例进行介绍，同理，图1中P型场效应管Q7及栅极的电阻R11、P型场效应管Q8及栅极的电阻R12分别均可称为第二分压支路。
需要说明的是，本发明中第一分压管组支路和第二分压管组支路并不限于采用场效应管，也可采用三极管代替。
4、第一分压管组偏置支路、第二分压管组偏置支路
本实施例中，可以包括但不限于图1所示：第一分压管组偏置支路包括并联的稳压管D1和耦合电容C1；其中，稳压管D1的阴极与耦合电容C1的第一端连接，稳压管D1的阳极 与耦合电容C1的第二端连接。
第二分压管组偏置支路包括并联的稳压管D2和耦合电容C4；其中，稳压管D2的阴极与耦合电容C4的第一端连接，稳压管D2的阳极与耦合电容C2的第二端连接。
5、钳位保护支路
钳位保护支路是本实施例的更优化方案中增加的支路，其连接在所述输入信号端和互补输出信号端之间，目的可以防止输入信号端即IN端和互补信号输出端即OUT端之间的电压差过高，避免N型场效应管Q4、P型场Q5的Vgs和Vds超过元器件的极限电压造成的损坏问题。
请参阅图2，本实施例中，可以包括但不限于图2所示：钳位保护支路包括稳压管D3和稳压管D4，二者的连接方向相反。例如可以按图2中，稳压管D3的阳极与输入信号端即IN端连接，阴极与稳压管D4的阴极连接；稳压管D4的阳极与互补输出信号端即OUT端连接。当然，稳压管D3和稳压管D4可以调换。
假设没有该钳位保护支路，以图2为例，电阻R4的输入端电压相对于IN端的电压是相对稳定的，电阻R5几乎无压降，可以忽略。那么电阻R4的输入端电压也就等于N型场效应管Q4的栅极电压，而一般场效应管的Vgs耐压就在20V左右，所以，如果IN端输入信号为正，而OUT输出负载太重(比如接近短路的情况下)，便有可能导致N型场效应管Q4的Vgs的压差超过耐压，从而造成损坏。而本实施例增加了上述钳位保护支路，IN端与OUT端之间的电压差便不会大于稳压管D3和稳压管D4之间的总电压差，那么，只要稳压管选择合适，电阻R4的输入端电压就不会超过N型场效应管Q4栅极电压的最大承受值，也即是，在理论上，哪怕是电路出现短路，也不出现会由于栅极被击穿而烧掉N型场效应管Q4。上述钳位保护支路对于P型场效应管Q5的保护与此同理。
6、输入信号端
本实施例中，输入信号端可以仅有一个，如图1或图2中的NI端，也可以是2个以上，如图3中包括有IN 1端和IN 2端。若以图1或图2为例，第一热敏支路(电阻R6和热敏电阻NTC1)的输出端与第二热敏支路(电阻R7和热敏电阻NTC2)的输入端之间相互连接作 为输入信号端即IN端，在图1或图2中由于没有其他信号输入端，该IN端可直接称为信号输入端，其相当于图3中的IN 1端，为便于描述，也可与图3中的IN 1端同样称为第一信号输入端，图3中IN 2端可以称为第二信号输入端，其由稳压管D1和耦合电容C1的并联输出端及稳压管D2和耦合电容C4的并联输入端之间相互连接而成。
本实施例的图3中，IN 1端和IN 2端可以输入两个同相位驱动信号或者是同一个驱动信号，甚至二者可以直接连通导线。
7、恒流源
本实施例在使用时可采用恒流源作为驱动，以图1或图2为例，可包括第一恒流源I1和第二恒流源I2；第一恒流源I1的输出端与第一分压管组偏置支路(稳压管D1和耦合电容C1)的输入端连接；第二恒流源的输入端与第二分压管组偏置支路(稳压管D2和耦合电容C4)的输出端连接。
以图3为例，还可进一步包括第三恒流源I3和第四恒流源I4；第三恒流源I3的输出端与第一场效应管偏置支路(电阻R4)的输入端连接；所述第四恒流源的输入端与所述第二场效应管偏置支路(电阻R9)的输出端连接。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种无源极电阻的大功率场效应管互补输出电路，其特征在于，包括场效应管互补输出支路、第一场效应管偏置支路、第二场效应管偏置支路、第一分压管组支路、第二分压管组支路、第一分压管组偏置支路、第二分压管组偏置支路；其中，场效应管互补输出支路包括互补的第一场效应管输出支路和第二场效应管输出支路，二者的源极端之间直接连接作为互补输出信号端；
    第一场效应管偏置支路连接在第一场效应管输出支路的栅极端，为第一场效应管输出支路提供偏置电压；第二场效应管偏置支路连接在第二场效应管输出支路的栅极端，为第二场效应管输出支路提供偏置电压；第一场效应管偏置支路和第二场效应管偏置支路之间相互连接作为输入信号端；
    第一分压管组支路的漏极端接入正电源，第一分压管组支路的源极端与第一场效应管输出支路的漏极端相连接，对第一场效应管输出支路的漏源电压进行分压；第一分压管组偏置支路连接在第一分压管组支路的栅极端，为第一分压管组偏置支路提供偏置电压；
    第二分压管组支路的漏极端接入负电源，第二分压管组支路的源极端与第二场效应管输出支路的漏极端相连接，对第二场效应管输出支路的漏源电压进行分压；第二分压管组偏置支路连接在第二分压管组支路的栅极端，为第二分压管组偏置支路提供偏置电压。
  2. 根据权利要求1所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，还包括钳位保护支路，所述钳位保护支路连接在所述输入信号端和互补输出信号端之间。
  3. 根据权利要求1所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，还包括第一恒流源和第二恒流源；所述第一恒流源的输出端与所述第一分压管组偏置支路的输入端连接；所述第二恒流源的输入端与所述第二分压管组偏置支路的输出端连接。
  4. 根据权利要求3所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，还包括第三恒流源和第四恒流源；所述第三恒流源的输出端与所述第一场效应管偏置支路的输入端连接；所述第四恒流源的输入端与所述第二场效应管偏置支路的输出端连接。
  5. 根据权利要求1所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，第一场效应管输出支路包括N型场效应管Q4以及连接在N型场效应管Q4栅极的电阻R5；N型场效应管Q4的栅极、漏极、源极对应的连接端分别为第一场效应管输出支路的栅极端、漏极端和源极端；第二场效应管输出支路包括P型场效应管Q5以及连接在P型场效应管Q5栅极的电阻R8；P型场效应管Q5的栅极、漏极、源极对应的连接端分别为第二场效应管输出支路的栅极端、漏极端和源极端。
  6. 根据权利要求5所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，第一场效应管偏置支路包括电阻R4、电阻R6、热敏电阻NTC1以及耦合电容C2；耦合电容C2的第一端连接电阻R5的输入端；电阻R4的输入端与耦合电容C2的第一端连接且用于连接正电流；所述电阻R6和热敏电阻NTC1并联成第一热敏支路，第一热敏支路的输入端与输出端分别与电阻R4的输出端、耦合电容C2的第二端连接；
    第二场效应管偏置支路包括电阻R9、电阻R7、热敏电阻NTC2以及耦合电容C3；耦合电容C3的第二端连接电阻R8的输入端；电阻R9的输出端与耦合电容C3的第二端连接且用于连接负电流；所述电阻R7和热敏电阻NTC2并联成第二热敏支路，第二热敏支路的输出端与输入端分别与电阻R9的输入端、耦合电容C3的第一端连接；
    所述输入信号端包括第一信号输入端；所述第一热敏支路的输出端与所述第二热敏支路的输入端之间相互连接作为所述第一输入信号端。
  7. 根据权利要求6所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，第一分压管组支路包括若干组相互并联的第一分压支路；第二分压管组支路包括若干组相互并联的第二分压支路。
  8. 根据权利要求7所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，所述第一分压支路包括N型场效应管Q1以及连接在N型场效应管Q1栅极的电阻R1；N型场效应管Q1的栅极、漏极、源极对应的连接端分别为第一分压管组支路的栅极端、漏极端和源极端；
    所述第二分压支路包括P型场效应管Q6以及连接在P型场效应管Q6栅极的电阻R10；P型场效应管Q6的栅极、漏极、源极对应的连接端分别为第二分压管组支路的栅极端、漏极端和源极端。
  9. 根据权利要求8所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，第一分压管组偏置支路包括并联的稳压管D1和耦合电容C1；其中，稳压管D1的阴极与耦合电容C1的第一端连接，稳压管D1的阳极与耦合电容C1的第二端连接；
    第二分压管组偏置支路包括并联的稳压管D2和耦合电容C4；其中，稳压管D2的阴极与耦合电容C4的第一端连接，稳压管D2的阳极与耦合电容C2的第二端连接。
  10. 根据权利要求9所述的无源极电阻的大功率场效应管互补输出电路，其特征在于，
    所述输入信号端还包括第二信号输入端；稳压管D1和耦合电容C1的并联输出端与稳压管D2和耦合电容C4的并联输入端之间相互连接作为所述第二信号输入端。
PCT/CN2016/076048 2016-03-04 2016-03-10 一种无源极电阻的大功率场效应管互补输出电路 WO2017147947A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610128407.1 2016-03-04
CN201610128407.1A CN105811961B (zh) 2016-03-04 2016-03-04 一种无源极电阻的大功率场效应管互补输出电路

Publications (1)

Publication Number Publication Date
WO2017147947A1 true WO2017147947A1 (zh) 2017-09-08

Family

ID=56466834

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/076048 WO2017147947A1 (zh) 2016-03-04 2016-03-10 一种无源极电阻的大功率场效应管互补输出电路

Country Status (2)

Country Link
CN (1) CN105811961B (zh)
WO (1) WO2017147947A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112798149A (zh) * 2020-12-29 2021-05-14 杭州和利时自动化有限公司 一种多通道热电阻测量装置及冗余多通道热电阻测量装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101118780A (zh) * 2007-09-18 2008-02-06 钰创科技股份有限公司 一种具有感测放大器的闩锁器
CN102347757A (zh) * 2011-05-24 2012-02-08 北京空间机电研究所 一种低电平可调的高压脉冲转换器
US20130214838A1 (en) * 2012-02-21 2013-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. High speed level shifter for converting low input voltage into wide-range high output voltage
CN103430453A (zh) * 2011-01-27 2013-12-04 高通股份有限公司 耐高电压差动接收器
CN104423406A (zh) * 2013-08-30 2015-03-18 台湾积体电路制造股份有限公司 具有电压驱动器和电流驱动器的发送器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1066592C (zh) * 1997-08-18 2001-05-30 秦鲁生 基极电流偏置式准甲类电路
US6859074B2 (en) * 2001-01-09 2005-02-22 Broadcom Corporation I/O circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off
KR100585886B1 (ko) * 2004-01-27 2006-06-01 삼성전자주식회사 동적 문턱 전압을 가지는 반도체 회로
CN101930787A (zh) * 2009-06-24 2010-12-29 合肥力杰半导体科技有限公司 支持多内存标准的内存接口电路构架和在mos工艺上的实施
US9225303B1 (en) * 2014-07-11 2015-12-29 Nuvoton Technology Corporation Method and apparatus for Class AB audio amplifier output stage voltage protection

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101118780A (zh) * 2007-09-18 2008-02-06 钰创科技股份有限公司 一种具有感测放大器的闩锁器
CN103430453A (zh) * 2011-01-27 2013-12-04 高通股份有限公司 耐高电压差动接收器
CN102347757A (zh) * 2011-05-24 2012-02-08 北京空间机电研究所 一种低电平可调的高压脉冲转换器
US20130214838A1 (en) * 2012-02-21 2013-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. High speed level shifter for converting low input voltage into wide-range high output voltage
CN104423406A (zh) * 2013-08-30 2015-03-18 台湾积体电路制造股份有限公司 具有电压驱动器和电流驱动器的发送器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112798149A (zh) * 2020-12-29 2021-05-14 杭州和利时自动化有限公司 一种多通道热电阻测量装置及冗余多通道热电阻测量装置
CN112798149B (zh) * 2020-12-29 2024-02-02 杭州和利时自动化有限公司 一种多通道热电阻测量装置及冗余多通道热电阻测量装置

Also Published As

Publication number Publication date
CN105811961A (zh) 2016-07-27
CN105811961B (zh) 2019-01-22

Similar Documents

Publication Publication Date Title
CN102053645B (zh) 一种宽输入电压高电源抑制比基准电压源
US10038441B2 (en) Power switching cell with normally conducting field-effect transistors
US20100109779A1 (en) Hybrid class ab super follower
TW201820776A (zh) 運算放大器及其差分放大電路
CN109947172B (zh) 一种低压降高输出电阻镜像电流源电路
CN112564676B (zh) 一种比较器电路
TWI745608B (zh) 射頻功率放大器
US10141897B2 (en) Source follower
TWI654842B (zh) 反相器
WO2017147947A1 (zh) 一种无源极电阻的大功率场效应管互补输出电路
JP2019097165A (ja) リニアまたはｄ級トポロジーを用いた、高速、高電圧の増幅器出力ステージ
CN111193477B (zh) 一种复合放大器
CN106656067B (zh) 一种用普通运算放大器设计的高电压大功率放大电路
US8159304B1 (en) Apparatus and method for feed-forwarding in a current-feedback amplifier
KR101618971B1 (ko) 인버터 형태의 전력 증폭기
WO2023090064A1 (ja) リミッタ回路、整合回路及び電力増幅回路
TWI555329B (zh) 串疊開關裝置與穩壓保護方法
CN107395146B (zh) 一种恒定跨导放大器电路
CN203301430U (zh) 增强灌电流并驱动电容负载的cmos放大器
CN211151511U (zh) 一种带有温度补偿的欠压保护电路
CN109842389A (zh) 一种射频功率放大器及其功率控制电路
CN109474246B (zh) 电压箝位保护结构及运算放大器输入级结构
CN205622619U (zh) 一种低输出阻抗的大功率场效应管互补输出电路
CN113848368B (zh) 一种电压差值实时检测和动态调节电路
TW202023196A (zh) 通用序列匯流排控制電路

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16892138

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16892138

Country of ref document: EP

Kind code of ref document: A1