WO2017147908A1 - 一种像素矩阵的外围补偿系统及其方法、显示系统 - Google Patents

一种像素矩阵的外围补偿系统及其方法、显示系统 Download PDF

Info

Publication number
WO2017147908A1
WO2017147908A1 PCT/CN2016/075658 CN2016075658W WO2017147908A1 WO 2017147908 A1 WO2017147908 A1 WO 2017147908A1 CN 2016075658 W CN2016075658 W CN 2016075658W WO 2017147908 A1 WO2017147908 A1 WO 2017147908A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
row
pixel
pixel units
signal
Prior art date
Application number
PCT/CN2016/075658
Other languages
English (en)
French (fr)
Inventor
张盛东
王翠翠
林兴武
Original Assignee
北京大学深圳研究生院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京大学深圳研究生院 filed Critical 北京大学深圳研究生院
Priority to PCT/CN2016/075658 priority Critical patent/WO2017147908A1/zh
Publication of WO2017147908A1 publication Critical patent/WO2017147908A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present application relates to the field of display technologies, and in particular, to a peripheral compensation system for a pixel matrix, a method thereof, and a display system.
  • the conventional AMOLED pixel unit is a structure of two Thin Film Transistors (TFTs) and a storage capacitor, as shown in FIG. 1 , wherein the T1 tube is a driving transistor, T2 is a switching transistor, C S is a storage capacitor, and The OLED is a light emitting device.
  • the switching transistor T2 samples the signal from the data line in response to the signal from the scan control signal line.
  • the storage capacitor C S stores the sampled voltage after the switching transistor T2 is turned off, and the voltage signal stored by the driving transistor T1 according to the storage capacitor C S .
  • a current is supplied to the OLED that determines the brightness of the OLED.
  • the driving current I DS can be expressed as:
  • I DS is the drain-source current of the driving transistor T1
  • ⁇ n is the effective mobility of the thin film field effect transistor
  • C ox is the gate oxide capacitance per unit area of the thin film field effect transistor
  • W and L are respectively thin film field effect transistors.
  • the effective channel width and the effective channel length V G is the gate voltage of the thin film field effect transistor
  • V OLED is the voltage across the OLED, which is related to the threshold voltage of the OLED
  • V TH is the threshold voltage of the TFT.
  • the structure of the pixel circuit shown in FIG. 1 is simple, the components therein may deteriorate over time, and in particular, the driving transistor T1 and the organic light emitting diode OLED may age, and the threshold voltages of the driving transistor T1 and the OLED may drift. Moreover, the threshold voltage drift of the driving transistor T1 and the OLED of each pixel unit in the pixel matrix is also different; in addition, since the thin film field effect transistor is made of a polysilicon material, the driving transistor T1 of each pixel unit in the pixel matrix is caused.
  • the threshold voltage V TH has a non-uniform characteristic; in the above two cases, according to the formula (1), the driving current I DS changes at this time, which causes the display of the pixel matrix to be non-uniform.
  • the compensation in the pixel unit is to provide a constant driving current for the OLED through the complicated pixel unit circuit structure.
  • the circuit of this method is not only complicated, but also the circuit is complicated and further causes the aperture ratio and the yield of the pixel unit to decrease; the peripheral compensation phase A simpler pixel cell structure can be used, which is more suitable for industrial applications, but peripheral circuits require special design.
  • the peripheral compensation circuit first performs gamma correction on the digital original signal, and then adds the gamma corrected digital original signal and the digital compensation signal to the digital-to-analog conversion module to output a compensated output.
  • the analog display shows the signal to the pixel unit.
  • the present application provides a peripheral compensation system for a pixel matrix, the pixel matrix 100 including N rows and M columns of pixel units 101, N rows of scan lines, and M columns of data lines, pixel units 101 and respective The scan line and the data line are respectively connected, N and M are both positive integers, and the peripheral compensation system includes:
  • the gate scan driving module 200 is configured to send a scan signal to the pixel matrix 100 through the scan line to sequentially gate each row of pixel units 101 in one frame; the gate scan drive module 200 also passes N rows of feedback address lines and respectively The row pixel unit 101 is connected to send a detection control signal to the pixel matrix 100 through the feedback address line to sequentially strobe each row of pixel units 101 in one frame;
  • the column data driving module 300 is configured to send a first display signal to the pixel matrix 100 through the data line, the column data driving module 300 includes a first digital to analog conversion module 301, and the first digital to analog conversion module 301 receives the digital original signal. Outputting a gamma corrected first display signal that is an analog signal;
  • the compensation module 400 is connected to the M column pixel unit 101 through the M column feedback signal lines, and is configured to detect the electrical characteristic change of the pixel matrix 100 to transmit the second display signal to the pixel matrix 100 to compensate each pixel unit 101.
  • the compensation module 400 includes a second digital-to-analog conversion module 401, a detection module 402, and a storage module 403.
  • the detection module 402 is configured to detect a change in electrical characteristics of the pixel unit 101 through a feedback signal line, and The detected electrical characteristic change information is sent to the storage module 403.
  • the storage module 403 is configured to store the electrical characteristic change information sent by the detection module 402, and change to the second digital-to-analog conversion module according to the electrical characteristic change of each pixel unit 101.
  • the 401 sends a digital compensation signal; the second digital-to-analog conversion module 401 performs digital-to-analog conversion on the received digital compensation signal, and then outputs a second display signal to the pixel unit 101 through the feedback signal line, wherein the first display signal and the second display signal
  • the display signals collectively drive the pixel unit 101 to cause the pixel unit 101 to correctly display image or video information.
  • the pixel unit 101 includes a driving transistor T1, a first switching transistor T2, a second switching transistor T3, a storage capacitor Cs, and an organic light emitting diode OLED; a first pole of the first switching transistor T2 is coupled to The data line, the first switching transistor a second pole of T2 is coupled to a control electrode of the driving transistor T1, a control electrode of the first switching transistor T2 is coupled to the scan line; a first pole of the second switching transistor T3 is coupled to the feedback signal line, and a second a second pole of the switching transistor T3 is coupled to the second pole of the driving transistor T1, a control pole of the second switching transistor T3 is coupled to the feedback address line; a first pole of the driving transistor T1 is coupled to the power supply voltage VDD, a second pole of the driving transistor T1 is coupled to the anode of the organic light emitting diode OLED, and a cathode of the organic light emitting diode OLED is grounded; the storage capacitor Cs is coupled between the control electrode and
  • the gate scan driving module 200 is further connected to the N rows of pixel units 101 through N rows of off signal lines, respectively, for the pixel unit 101 to be written into the first display signal and the second display signal. And a cutoff signal is sent to the pixel unit 101 through the cutoff signal line, and the cutoff signal is used to prevent a current from flowing on the feedback signal line during the writing of the first display signal and the second display signal to the pixel unit 101.
  • the pixel unit 101 includes a driving transistor T1, a first switching transistor T2, a second switching transistor T3, a third switching transistor T4, a storage capacitor Cs, and an organic light emitting diode OLED;
  • a first pole of the first switching transistor T2 is coupled to the data line, a second pole of the first switching transistor T2 is coupled to a control pole of the driving transistor T1, and a control pole of the first switching transistor T2 is coupled to the a scan line; a first pole of the second switching transistor T3 is coupled to the feedback signal line, a second pole of the second switching transistor T3 is coupled to a positive pole of the organic light emitting diode OLED, and a second switching transistor T3 is controlled.
  • a first pole of the driving transistor T1 is coupled to the power supply voltage VDD, a second pole of the driving transistor T1 is coupled to the anode of the organic light emitting diode OLED, and a cathode of the organic light emitting diode OLED is grounded;
  • the storage capacitor Cs is coupled between the second pole of the first switching transistor T2 and the anode of the organic light emitting diode OLED for receiving the first display signal and the second display signal to couple the two signals by capacitive coupling After being added, it is finally loaded between the control electrode and the second pole of the driving transistor T1;
  • the second pole of the first switching transistor T2 is coupled to the control electrode of the driving transistor T1 through the third switching transistor T4, specifically, the first pole of the third switching transistor T4 and the first switching transistor T2.
  • a second pole is connected, a second pole of the third switching transistor T4 is connected to the control electrode of the driving transistor T1, and a control pole of the third switching transistor T4 is connected to the off signal line; or the driving transistor T1 is
  • One pole is coupled to the power supply voltage VDD through the third switching transistor T4, specifically, the first pole of the third switching transistor T4 is connected to the power supply voltage VDD, and the second pole of the third switching transistor T4 is coupled to the driving
  • the first pole of the transistor T1 is connected, the control electrode of the third switching transistor T4 is connected to the cut-off signal line; or the second pole of the driving transistor T1 is passed through the third switch crystal
  • the body tube T4 is coupled to the anode of the organic light emitting diode OLED.
  • the first pole of the third switching transistor T4 is coupled to the second pole of the driving transistor T1
  • the second pole of the third switching transistor T4 is The anode of the organic light emitting diode OLED is connected, and the gate of the third switching transistor T4 is connected to the off signal line.
  • the first display is a data image signal voltage
  • the second display signal is a sum of a threshold voltage and a compensation voltage of the driving transistor T1; or the first display signal is a threshold voltage of the driving transistor T1,
  • the second display signal is a sum of the data image signal voltage and the compensation voltage; or the first display signal is a sum of a threshold voltage of the driving transistor T1 and a data image signal voltage, and the second display signal is a compensation voltage.
  • the present application provides a method of a peripheral compensation system including the above-described pixel matrix, the pixel matrix 100 including N rows and M columns of pixel units 101, N rows of scan driving lines, and M columns of data lines, pixels
  • the unit 101 and the respective scan lines and data lines are respectively connected, and N and M are both positive integers.
  • the method includes the following operations: one frame time is composed of N equal line times t 1 to t N , and each row of pixel units 101 Do the following in order:
  • the gate scan driving module 200 validates the scan lines and the feedback address lines of the row of pixel units 101, and the column data driving module 300 and the compensation module The first display signal and the second display signal are written to the pixel unit 101 by the data line and the feedback signal line, wherein the first display signal and the second display signal jointly drive the pixel unit 101 to make the pixel unit 101 correct. Displaying image or video information; during t n+1 time, the gate scan driving module 200 invalidates the scan line of the row of pixel units 101 and continues to maintain the feedback address line, and the compensation module 400 detects the row of pixel units through the feedback signal line.
  • the electrical characteristic change of 101 is compensated when the row of pixel cells 101 is gated in the next frame; during t n+2 , the gate scan driving module 200 invalidates the scan line and the feedback address line of the row of pixel cells 101, The pixel unit 101 is driven by the first display signal and the second display signal to emit light.
  • the present application provides a method of a peripheral compensation system including the above-described pixel matrix, the pixel matrix 100 including N rows and M columns of pixel units 101, N rows of scan driving lines, and M columns of data lines, pixels
  • the unit 101 and the respective scan lines and data lines are respectively connected, N and M are positive integers
  • the method comprises a light-emitting operation frame and a detection compensation frame, wherein one frame time is composed of N equal line times t 1 to t N ;
  • any nth row of pixel units 101 is within t n time, where 1 ⁇ n ⁇ N: the gate scan driving module 200 makes the scan line and the feedback address line of the row of pixel units 101 valid.
  • the column data driving module 300 and the compensation module 400 respectively write the first display signal and the second display signal to the row of pixel units 101 through the data line and the feedback signal line, wherein the first display signal and the second display signal are driven together.
  • the pixel unit 101 causes the pixel unit 101 to correctly display image or video information; during t n+1 time, the gate scan driving module 200 invalidates the scan line and the feedback address line of the row of pixel units 101, and the pixel unit 101 is The first display signal and the second display signal are driven to emit light; in a detection compensation frame of one frame, each row of pixel units 101 or a plurality of rows of pixel units 101 in all of the pixel units 101 sequentially perform the following operations, when one frame In the detection compensation frame, when only a plurality of rows of pixel units 101 in all
  • the compensation module 400 detects the electrical characteristic change of the row of pixel units 101 through the feedback signal line, and refreshes and stores the electrical characteristic change information of the row of pixel units 101; the gate scan driving module 200 makes the row of pixels in the next row time.
  • the scan line and the feedback address line of the unit 101 are valid, and maintain one line time.
  • the column data driving module 300 and the compensation module 400 Do not write a low level signal to the row of pixel units 101 through the data line and the feedback signal line to cause the row of pixel units 101 to not emit light; wherein, before detecting the compensation frame, each row of pixel units 101 is sequentially written to a low level. The signal is not illuminated; wherein, the illuminating operation frame of several consecutive frames is followed by one frame detection compensation frame;
  • any nth row of pixel units 101 is within t n time, where 1 ⁇ n ⁇ N: the gate scan driving module 200 makes the scan line and the feedback address line of the row of pixel units 101 valid.
  • the column data driving module 300 and the compensation module 400 respectively write the first display signal and the second display signal to the row of pixel units 101 through the data line and the feedback signal line, wherein the first display signal and the second display signal are driven together.
  • the pixel unit 101 causes the pixel unit 101 to correctly display image or video information; during t n+1 , the gate scan driving module 200 invalidates the scan line and the feedback address line of the row of pixel units 101, and the pixel unit 101 is
  • the first display signal and the second display signal are driven to emit light; in the detection compensation frame of one frame, each row of pixel units 101 sequentially performs the following operations: when a specific row of pixel units 101 is turned on, the gate scan is driven.
  • the module 200 validates the scan line and the feedback address line of the row of pixel units 101 for one line time, during which the column data driving module 300 and the compensation module 400 respectively pass the data lines and
  • the feed signal line writes a fixed voltage signal to the row of pixel units 101 and the latest threshold voltage signal of the pixel unit 101 detected last time in the detection compensation frame; the gate scan driving module 200 makes the line in the next line time.
  • the scan line of the pixel unit 101 is invalid and the feedback address line is valid, maintaining one line time.
  • the compensation module 400 detects the change of the electrical characteristics of the row of pixel units 101 through the feedback signal line, and refreshes and stores the row of pixel units.
  • the electrical characteristic change information of 101 wherein the detection compensation frame is located when the pixel matrix is turned on and/or off.
  • the present application provides a method of a peripheral compensation system including the above-described pixel matrix, the pixel matrix 100 including N rows and M columns of pixel units 101, N rows of scan driving lines, and M columns of data lines.
  • the pixel unit 101 and the respective scan lines and data lines are respectively connected, N and M are positive integers, and the method includes a light-emitting operation frame and a detection compensation frame, wherein one frame time is composed of N equal line times t 1 to t N composition;
  • any nth row of pixel units 101 is within t n time, where 1 ⁇ n ⁇ N: the gate scan driving module 200 makes the scan line and the feedback address line of the row of pixel units 101 valid.
  • the column data driving module 300 and the compensation module 400 respectively write the first display signal and the second display signal to the row of pixel units 101 through the data line and the feedback signal line, wherein the first display signal and the second display signal are driven together.
  • the pixel unit 101 causes the pixel unit 101 to correctly display image or video information; during t n+1 , the gate scan driving module 200 invalidates the scan line and the feedback address line of the row of pixel units 101, and the pixel unit 101 is The first display signal and the second display signal are driven to emit light;
  • each row of pixel units 101 sequentially performs the following operations: any one of the nth rows of pixel units 101 is within t n time, when it is set to the row pixel unit 101 that needs to be detected for this frame
  • the gate scan driving module 200 invalidates the scan line of the row of pixel units 101 and validates the feedback address line, wherein the feedback address line effectively maintains a line time of a dry integer multiple, and during the valid period of the feedback address line, the compensation module 400 detects a change in electrical characteristics of the row of pixel units 101 through a feedback signal line, and refreshes and stores electrical characteristic change information of the row of pixel units 101; thereafter, the gate scan driving module 200 validates the scan lines of the row of pixel units 101 and The feedback address line is invalid, the scan line is effectively maintained for one line time, and the feedback address line is invalid until the next frame is maintained.
  • the column data driving module 300 writes a low level to the row of pixel units 101 through the data line to turn off the line of pixels. unit 101, so as not to emit light; T n in time, when the row pixel detecting means which is provided for the present frame 101 does not require any of a n-th row of pixel units 101
  • the gate scan driving module 200 disables the scan line of the row of pixel units 101 and the feedback address line, and maintains a row time.
  • the column data driving module 300 writes a low level to the row of pixel units 101 through the data line.
  • the present application provides a display system including a pixel matrix and a peripheral compensation system of the above-described pixel matrix.
  • the peripheral compensation system of the pixel matrix and the method and the display system thereof the addition of the first display signal and the second display signal in the pixel unit is realized, and the pixel can be compensated
  • the display is inaccurate due to changes in electrical characteristics, for example, compensating for threshold voltage shift of the driving transistor and the organic light emitting diode OLED, and solving display unevenness caused by different threshold voltages of driving transistors in each pixel unit in the display system It is also possible to improve display unevenness caused by degradation of luminous efficiency of the organic light emitting diode OLED.
  • the application has accurate gamma correction on the first display signal, and has a simple structure, and the number of bits of the first digital-to-analog conversion module and the second digital-to-analog conversion module is also low, if the analog domain is added, the original
  • the high voltage analog adder can be converted to a medium or low pressure adder.
  • FIG. 1 is a schematic diagram of a circuit structure of a conventional pixel unit
  • FIG. 2 is a schematic structural diagram of a display system in a first embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a pixel unit in an embodiment of the present application.
  • Figure 4 is a timing chart of the operation of the first embodiment of the present application.
  • FIG. 5 is a timing diagram of an operation of a light-emitting operation frame in a second embodiment of the present application.
  • FIG. 6 is a timing diagram of an operation of detecting a compensation frame in a second embodiment of the present application.
  • FIG. 7 is a timing diagram of an operation of detecting a compensation frame in a third embodiment of the present application.
  • FIG. 8 is a schematic diagram showing a first structure of a pixel unit in a fourth embodiment of the present application.
  • Figure 9 is a timing chart of the operation of the fourth embodiment of the present application.
  • FIG. 10 is a schematic diagram showing a second structure of a pixel unit in a fourth embodiment of the present application.
  • FIG. 11 is a schematic diagram showing a third structure of a pixel unit in a fourth embodiment of the present application.
  • Figure 12 is a timing chart showing the operation of the fifth embodiment of the present application.
  • the embodiment discloses a display system including a pixel matrix 100 and a peripheral compensation system of a pixel matrix (hereinafter referred to as a peripheral compensation system).
  • the pixel matrix 100 includes N rows and M columns of pixel cells 101, N rows of scan lines, and M columns of data lines.
  • the pixel cells 101 and the respective scan lines and data lines are respectively connected, and N and M are positive integers.
  • the peripheral compensation system includes a gate scan driving module 200, a column data driving module 300, and a compensation module 400, which are specifically described below.
  • the gate scan driving module 200 is configured to send a scan signal to the pixel matrix 100 through the scan line to sequentially strobe each row of pixel units 101 in one frame; the gate scan drive module 200 also passes through the N rows of feedback address lines and the N rows respectively.
  • the pixel unit 101 is connected to transmit a detection control signal to the pixel matrix 100 through the feedback address line to sequentially strobe each row of pixel units 101 in one frame.
  • the column data driving module 300 is configured to send the first display signal to the pixel matrix 100 through the data line.
  • the column data driving module 300 includes a first digital to analog conversion module 301, and the first digital to analog conversion module 301 receives the digital original. Signal, output is gamma corrected for simulation
  • the first display signal of the signal; specifically, the first digital-to-analog conversion module 301 may be M to correspond to the M-column pixel unit 101.
  • the column data driving module 300 may further include a first shift register 302, and the first shift register 302 is configured to receive the digital original signal and transmit the first digital to analog conversion. Module 301.
  • the compensation module 400 is connected to the M column pixel unit 101 through the M column feedback signal lines, and is used for detecting the electrical characteristic change of the pixel matrix 100 to transmit the second display signal to the pixel matrix 100 to compensate each pixel unit 101.
  • the “electrical characteristic change” herein may refer to a change in electrical characteristics of a transistor and/or an organic light emitting diode in the pixel unit 101, such as threshold change information of a transistor, and degradation information of an organic light emitting diode.
  • the compensation module 400 includes a second digital-to-analog conversion module 401, a detection module 402, and a storage module 403.
  • the detection module 402 is configured to detect a change in electrical characteristics of the pixel unit 101 through a feedback signal line, and detect the detected The electrical characteristic change information is sent to the storage module 403.
  • the storage module 403 is configured to store the electrical characteristic change information sent by the detection module 402, and send a digital compensation signal to the second digital-to-analog conversion module 401 according to the electrical characteristic change of each pixel unit 101.
  • the second digital-to-analog conversion module 401 performs digital-to-analog conversion on the received digital compensation signal, and then outputs a second display signal to the pixel unit 101 through the feedback signal line, wherein the second display signal and the first display signal jointly drive the pixel unit 101, so that The pixel unit 101 correctly displays image or video information to avoid the problem of inaccurate display of image or video information due to changes in electrical characteristics of the pixel unit 101.
  • the compensation module 400 may further include a second shift register 404 and a third shift register 405, and the second shift register 404 is configured to receive the digital compensation signal sent by the storage module 403.
  • the third digital-to-analog conversion module 405 is configured to detect the electrical characteristic change information sent by the module 402 and transmit the information to the storage module 403.
  • the pixel unit 101 includes a driving transistor T1, a first switching transistor T2, a second switching transistor T3, a storage capacitor Cs, and an organic light emitting diode OLED; a first pole of the first switching transistor T2 is coupled to the data line Data line, the second pole of the first switching transistor T2 is coupled to the control electrode of the driving transistor T1, the control electrode of the first switching transistor T2 is coupled to the scan line Scan[n]; the first pole of the second switching transistor T3 is coupled to The feedback signal line FD Line, the second pole of the second switching transistor T3 is coupled to the second pole of the driving transistor T1, the control pole of the second switching transistor T3 is coupled to the feedback address line Sen[n], and the driving transistor T1 One pole is coupled to the power supply voltage V DD , the second pole of the driving transistor T1 is coupled to the anode of the organic light emitting diode OLED, and the catho
  • the compensation module 400 can be used to detect changes in electrical characteristics of the driving transistor T1 and the organic light emitting diode OLED, for example, detecting threshold voltage offset information of the driving transistor T1 and the organic light emitting diode OLED, and detecting the light emission of the organic light emitting diode OLED. Efficiency degradation information, etc.
  • the transistor in the present application means that the transistor in the present application is a three-terminal transistor, the three terminals of which are the gate, the first pole and the second pole; when the transistor is a bipolar transistor, the control The pole refers to the base of the bipolar transistor, the first pole refers to the collector or emitter of the bipolar transistor, and the corresponding second pole refers to the emitter or collector of the bipolar transistor; when the transistor is a field effect
  • the gate refers to the gate of the field effect transistor, the first pole refers to the drain or source of the field effect transistor, and the corresponding second pole refers to the source or drain of the field effect transistor.
  • the transistor in the display system is usually a field effect transistor.
  • the circuit may be described by taking a transistor as an N-channel field effect transistor as an example.
  • the control electrode of the transistor is the gate, the first pole is the drain, and the second is the second.
  • the pole refers to the source; of course, in other embodiments the transistor can be other types of field effect transistors or bipolar transistors.
  • the transistor of the present application can be fabricated using amorphous silicon, polysilicon, an oxide semiconductor, an organic semiconductor, an NMOS/PMOS process, or a CMOS process.
  • This embodiment also discloses a method of a peripheral compensation system for a pixel matrix, the method comprising (1) a data write operation; (2) a feedback detection operation; and (3) a light-emitting operation. The details are described below.
  • One frame time is composed of N equal line times t 1 to t N , and each row of pixel units (101) sequentially performs (1) data writing operation: any one nth row of pixel units 101 in time t n , where 1 ⁇ n ⁇ N, the gate scan driving module 200 validates the scan line Scan[n] and the feedback address line Sen[n] of the row of pixel units 101, and the column data driving module 300 and the compensation module 400 respectively pass the data lines Data Line and The feedback signal line FD Line writes the first display signal and the second display signal to the row of pixel units 101, wherein the first display signal and the second display signal jointly drive the pixel unit 101 to cause the pixel unit 101 to correctly display image or video information.
  • FIG. 4 is a working sequence diagram of the embodiment.
  • the gating of the pixel matrix 100 is strobing the pixel unit 101 in units of rows, and the operation of the pixel unit 101 for each row, as described above, includes (1) a data write operation, (2) a feedback detection operation, and (3) Illumination operation.
  • the scan line Scan[n] of the nth row and the feedback address line Sen[n] are outputted to a high level, so that the first switching transistor T2 and the second switching transistor T3 are both turned on, and the first switch at this time
  • the transistor T2 transmits the data voltage V DATA from the data line Data Line to the first electrode of the storage capacitor C S
  • the second switching transistor T3 transmits the compensation voltage - (V TH0 + ⁇ V) signal from the feedback signal line FD Line to the signal a second electrode of the storage capacitor C S
  • V TH0 is an initial value or an intermediate value of a threshold voltage of the driving transistor T1 on the panel
  • ⁇ V is a threshold voltage drift amount or a difference between each pixel;
  • the storage capacitor C S is The voltage difference becomes V DATA +V TH0 + ⁇ V, that is, the voltage difference between the gate and source electrodes of the driving transistor T1 is V DATA +V TH + ⁇ V.
  • the line access detection module 402 starts to perform detection.
  • the organic light emitting diode OLED is not turned on, and no current flows through the OLED. Therefore, all the pixel currents I pixel will flow into the detection module 402, and the detection module 402 will further operate the compensation voltage according to the comparison of the detected pixel current I pixel and the current I data required for actual illumination, that is, the next time the write voltage needs to be written.
  • the feedback address line Sen[n] is outputted to a low level, the second switching transistor T3 is turned off, and the voltage difference on the storage capacitor CS is maintained as a voltage difference VDATA+VTH0+ ⁇ V in the data writing phase.
  • whether the second digital to analog conversion module 401 and the detection module 402 are connected to the feedback signal line FD Line may be selected by a switch.
  • the voltage on the feedback signal line FD Line may be set to Vref, which is not less than the turn-on voltage of the organic light emitting diode OLED, and therefore, the organic light emitting diode There is no current on the OLED, and all current flows into the detection module 402 via the second switching transistor T3.
  • the scan line Scan[n] and the feedback address line Sen[n] of the nth row are outputted to a low level, and the driving transistor T1 no longer receives the voltage signals from the data line Data Line and the feedback signal line FD Line, and is driven.
  • the transistor T1 drives the organic light emitting diode OLED to emit light according to a voltage difference across the storage capacitor C S .
  • the current flowing through the OLED at this time can be expressed as the formula (2)
  • the current of the diode OLED can be further simplified to
  • the current flowing through the organic light emitting diode OLED is independent of the threshold voltage drift of the driving transistor T1, the organic light emitting diode OLED or the unevenness between the pixel units 101, and thus the threshold voltage drift or the pixel unit of the driving transistor T1 and the organic light emitting diode OLED can be compensated.
  • ⁇ V ⁇ V TH + ⁇ ⁇
  • ⁇ V TH the threshold voltage of the driving transistor T1
  • the peripheral compensation system can further compensate for variations in the mobility of the driving transistor T1.
  • the operation of the scan line Scan[n] and the feedback address line Sen[n] is high, and the first display signal written is low.
  • the feedback signal line FD Line is connected to the detection module 402.
  • the driving transistor T1 is turned off, and the detecting module 402 applies a constant voltage to the positive electrode of the organic light emitting diode OLED to detect the current flowing through the OLED according to the control organic light.
  • the electrical characteristic curve of the diode can be used to know the degradation of the organic light emitting diode OLED at this time, and the relationship between V DATA and I DATA is modified to complete the degradation detection of the OLED luminous efficiency of the organic light emitting diode.
  • the degradation of the luminous efficiency of the organic light emitting diode OLED is relatively slow, the degradation of the luminous efficiency of the organic light emitting diode OLED can be detected once for a long time, or once every time the power is turned on or off.
  • the first display is a data image signal voltage
  • the second display signal is a sum of a threshold voltage and a compensation voltage of the driving transistor T1; or the first display signal is a threshold voltage of the driving transistor T1, and the second display signal The sum of the data image signal voltage and the compensation voltage; or, the first display signal is the sum of the threshold voltage of the driving transistor T1 and the data image signal voltage, and the second display signal is the compensation voltage.
  • the first switching transistor T2 is turned on, the first display signal written by the data line Data Line is V TH0 instead of V DATA , the second switching transistor T3 is turned on, and the feedback signal line FD Line is written.
  • the first switching transistor T2 is turned on, the first signal written by the data line Data Line is V DATA + ⁇ V instead of V DATA , and the second switching transistor T3 is turned on, and the feedback signal line FD Line is written as -V TH0 , then the voltage difference across the storage capacitor C S is still V DATA +V TH0 + ⁇ V.
  • the first switching transistor T2 is turned on, the first signal written by the data line Data Line is V DATA +V TH0 instead of V DATA , and the second switching transistor T3 is turned on, and the feedback signal line is turned on.
  • FD Line is written as - ⁇ V, the voltage difference across the storage capacitor C S is still V DATA +V TH0 + ⁇ V.
  • This embodiment discloses a method for a peripheral compensation system of a pixel matrix. In an embodiment, it can be implemented by the display system and the peripheral compensation system disclosed in Embodiment 1. The details are described below.
  • the method disclosed in this embodiment includes a lighting operation frame and a detection compensation frame.
  • the operation on the pixel unit 101 is also performed line by line, which includes (1) a data write operation and (2) a light-emitting operation.
  • (1) data writing operation in one frame of the light-emitting operation frame, any one of the n-th row of pixel units 101 is within t n time, wherein 1 ⁇ n ⁇ N, the gate scan driving module 200 makes the line The scan line Scan[n] of the pixel unit 101 and the feedback address line Sen[n] are valid, and the column data driving module 300 and the compensation module 400 write the same to the row pixel unit 101 through the data line Data Line and the feedback signal line FD Line, respectively.
  • a display signal and a second display signal wherein the first display signal and the second display signal collectively drive the pixel unit 101 to cause the pixel unit 101 to correctly display image or video information.
  • the gate scan driving module 200 invalidates the scan line Scan[n] and the feedback address line Sen[n] of the row of pixel units 101, and the pixel unit 101 is described.
  • the first display signal and the second display signal are driven to emit light.
  • each row of pixel units 101 includes (1) writing of a reference voltage, (2) feedback detection operation, and (3) writing low level data. Specifically, in the detection compensation frame of one frame, each row of pixel units 101 or a plurality of rows of pixel units 101 in all the pixel units 101 sequentially perform the following operations, and in the detection compensation frame of one frame, only all the pixel units 101 When a plurality of rows of pixel units 101 are sequentially subjected to the following operations, the row pixel unit 101 order of the following operations is arranged such that in the detection compensation frames of several frames, all the pixel units 101 perform the following operations one time: 1) Writing of reference voltage: When it is a specific row of pixel units 101, the gate scan driving module 200 makes the scan line Scan[n] and the feedback address line Sen[n] of the row of pixel units 101 valid and maintains a row time during which the column data driving module 300 and the compensation module 400 write a fixed voltage signal to the row of pixel units 101 through the data line Data Line and
  • the gate scan driving module 200 invalidates the scan line Scan[n] of the row of pixel units 101 and the feedback address line Sen[n], maintaining one line time, here During the line time, the compensation module 400 detects the change in the electrical characteristics of the row of pixel units 101 through the feedback signal line FD Line, and refreshes and stores the electrical characteristic change information of the row of pixel units 101.
  • the gate scan driving module 200 makes the scan line Scan[n] and the feedback address line Sen[n] of the row pixel unit 101 valid for one line time.
  • the column data driving module 300 and the compensation module 400 respectively write a low level signal to the row of pixel units 101 through the data line Data Line and the feedback signal line FD Line to make the row of pixel units 101 not emit light;
  • each row of pixel units 101 is first sequentially written with a low level signal to not emit light; wherein, a plurality of frames of the illumination operation frame are followed by a frame detection compensation frame.
  • FIG. 5 and FIG. 6 are respectively an operational timing diagram of the illumination operation frame and the detection compensation frame in the embodiment.
  • the driving speed of the circuit in the display system is fast, and the driving speed of the conventional 2T1C pixel is the same.
  • the detection compensation frame the display system can complete the detection of the electrical characteristic degradation of the pixel unit, and complete the refresh compensation information.
  • the display system can operate in a certain frame mode as a light-emitting operation frame, and insert a detection compensation frame of one frame or several frames for a period of time.
  • the illumination operation frame includes (1) a data write operation and (2) a light-emitting operation.
  • the scan line Scan[n] of the nth row and the feedback address line Sen[n] are outputted to a high level, so that the first switching transistor T2 and the second switching transistor T3 are both turned on, and the first switch at this time
  • the transistor T2 transmits the data voltage V DATA from the data line Data Line to the first electrode of the storage capacitor C S
  • the second switching transistor T3 transmits the compensation voltage - (V TH0 + ⁇ V) signal from the feedback signal line FD Line to the signal a second electrode of the storage capacitor C S
  • V TH0 is an initial value or an intermediate value of a threshold voltage of the driving transistor T1 on the panel
  • ⁇ V is a threshold voltage drift amount or a difference between each pixel;
  • the storage capacitor C S is The voltage difference becomes V DATA +V TH0 + ⁇ V, that is, the voltage difference between the gate and source electrodes of the driving transistor T1 is V DATA +V TH + ⁇ V.
  • the scan line Scan[n] and the feedback address line Sen[n] of the nth row are outputted to a low level, and the driving transistor T1 no longer receives the voltage signals from the data line Data Line and the feedback signal line FD Line, and is driven.
  • the transistor T1 drives the organic light emitting diode OLED to emit light according to a voltage difference across the storage capacitor C S .
  • the current flowing through the OLED at this time can be expressed as equation (5):
  • the current flowing through the organic light emitting diode OLED is independent of the threshold voltage drift of the driving transistor T1, the organic light emitting diode OLED or the unevenness between the pixel units 101, and thus the threshold voltage drift or pixel of the driving transistor T1 and the organic light emitting diode OLED can be compensated. A change caused by the unevenness between the units 101.
  • ⁇ V ⁇ V TH + ⁇ ⁇
  • ⁇ V TH the threshold voltage of the driving transistor T1
  • ⁇ is an amount related only to the amount of change in mobility
  • the current flowing through the organic light emitting diode OLED is approximately equal to the current I data required for light emission. Therefore, the peripheral compensation system can further compensate for variations in the mobility of the drive transistor.
  • V DATA , V TH0 and ⁇ V it is also possible to write V DATA , V TH0 and ⁇ V in other manners as shown in the embodiment, as long as the voltage difference across the storage capacitor C S is finally V DATA +V TH0 + ⁇ V.
  • the writing operation of the data starts to emit light.
  • the writing method is similar to that in the first embodiment, and details are not described herein again.
  • the compensation frame is detected, as described above, including (1) writing of a reference voltage, (2) feedback detection operation, and (3) writing low level data.
  • the driving transistor T1 is turned off, that is, the gate-source voltage V GS_T1 ⁇ 0 of the driving transistor T1, so that the organic light-emitting diode
  • the OLED does not emit light, that is, the positive electrode potential of the organic light emitting diode OLED is smaller than the turn-on voltage V TH — OLED , and this process may be referred to as writing of a black matrix.
  • the writing of the black matrix can also be performed row by row, such as writing a black matrix using a mode of illuminating the operation frame.
  • the scan control line Scan[n] and the feedback address line Sen[n] of the nth row are outputted to a high level, so that the first switching transistor T2 and the second switching transistor T3 are both turned on, at this time, the first The switching transistor T2 transmits a reference voltage V REF from the data line Data Line to the first electrode of the storage capacitor Cs, and the second switching transistor T3 transmits a compensation voltage -(V TH0 + ⁇ V) signal from the feedback signal line FD Line to the a second electrode of the storage capacitor Cs, wherein V TH0 is an initial value or an intermediate value of a threshold voltage of the driving transistor T1 in the display system, and ⁇ V is a threshold voltage drift amount or a difference between the respective pixel units 101; at this time, the storage capacitor Cs The voltage difference on the upper side becomes V REF +V TH0 + ⁇ V, that is, the voltage difference between the gate-source electrodes of the driving transistor T1 is V REF +V TH + ⁇ V.
  • the line access detection module 402 starts to perform detection.
  • the organic light emitting diode OLED is not turned on, and there is no current flowing through the light emitting diode OLED. Therefore, the current I pixel in the pixel unit will flow into the detecting module 402, and the detecting module 402 determines the further operation of the compensation voltage according to the comparison of the detected pixel current I pixel and the actual expected current I REF , that is, next time. Whether ⁇ V should be changed in the compensation voltage to be written, whether it is increased or decreased, ⁇ V can only operate one bit at a time.
  • the purpose of writing low-level data is to form the black matrix described above to avoid illumination of the organic light-emitting diode OLED during the detection process.
  • the voltage on the scan line Scan[n] of the nth row is at a high level, and the first switching transistor T2 is turned on, and the first switching transistor T2 transmits a low level voltage from the data line Data Line.
  • V R is sent to the first electrode of the storage capacitor Cs, the output of the feedback address line Sen[n] is still at a high level, the second switch transistor T3 is turned on, and the second switch transistor T3 transmits a low level from the feedback signal line FD Line
  • the signal is sent to the second electrode of the storage capacitor Cs such that the gate-to-source voltage difference of the driving transistor T1 is less than or equal to 0, so the driving transistor T1 is turned off; since the voltage of the second electrode of the Cs is low level, the level can make the organic light emitting The diode OLED does not emit light, and this level is held by the parasitic capacitance C OLED of the organic light emitting diode OLED itself.
  • the display system begins to perform the illumination operation frame.
  • only a portion of the pixel units 101 in the display system complete the detection compensation phase, and the display system begins to perform the illumination operation frame.
  • the 1-5 lines of the pixel unit 101 complete the threshold detection compensation
  • the 6-10 lines of the pixel unit 101 complete the threshold detection compensation operation, This type of push.
  • the first switching transistor T2 is turned on, the first signal written by the data line Data Line is V TH0 instead of V REF , the second switching transistor T3 is turned on, and the feedback signal line FD Line is written. - (V REF + ⁇ V), then the voltage difference across the storage capacitor Cs is still V REF + V TH0 + ⁇ V.
  • the first switching transistor T2 is turned on, the first signal written by the data line Data Line is V REF +V TH0 instead of V REF , the second switching transistor T3 is turned on, and the feedback signal line FD Line is written.
  • the value of - ⁇ V, then the voltage difference across the storage capacitor Cs is still V REF + V TH0 + ⁇ V.
  • the detection of the degradation of the luminous efficiency of the organic light emitting diode OLED can be similar to that described in the first embodiment, and details are not described herein again.
  • This embodiment discloses a method for a peripheral compensation system of a pixel matrix. In an embodiment, it can be implemented by the display system and the peripheral compensation system disclosed in Embodiment 1. Detailed description below
  • the difference from the second embodiment is that the operation of the illumination operation frame in the second embodiment is performed when the display system is powered on and/or off, but the embodiment does not need to write the black matrix.
  • the method disclosed in this embodiment also includes a lighting operation frame and a detection compensation frame.
  • the operation of the illuminating operation frame is the same as that in the second embodiment, and will not be described herein.
  • each row of pixel units (101) sequentially performs the following operations: (1) writing of reference voltage: when it is a specific row of pixel units 101, the gate scan driving module 200 makes The scan line Scan[n] and the feedback address line Sen[n] of the row of pixel units 101 Valid, maintaining a line time, during which the column data driving module 300 and the compensation module 400 write a fixed voltage signal to the row of pixel units 101 through the data line Data Line and the feedback signal line FD Line, respectively.
  • the gate scan driving module 200 invalidates the scan line Scan[n] of the row of pixel units 101 in the next line time
  • the feedback address line Sen[n] is valid, maintaining a line time, during which the compensation module 400 detects the change in the electrical characteristics of the row of pixel units 101 through the feedback signal line FD Line, and refreshes and stores the row of pixel units 101.
  • Electrical characteristic change information wherein the detection compensation frame is located when the pixel matrix is powered on and/or off.
  • FIG. 7 an operation timing diagram of detecting a compensation frame in this embodiment is shown.
  • the pixel circuit does not need to write the black matrix, and the working process of detecting the compensation frame can be started directly. After the detection and compensation operation is completed, the low level is not required to be written. So that the organic light emitting diode OLED does not emit light.
  • the scan line Scan[n] and the feedback address line Sen[n] of the nth row are outputted to a high level, so that the first switching transistor T2 and the second switching transistor T3 are both turned on, and the first switch at this time
  • the transistor T2 transmits a reference voltage V REF from the data line Data Line to the first electrode of the storage capacitor Cs, and the second switching transistor T3 transmits a compensation voltage -(V TH0 + ⁇ V) signal from the feedback signal line FD Line to the storage.
  • V TH0 is an initial value or an intermediate value of a threshold voltage of the driving transistor T1 on the panel
  • ⁇ V is a threshold voltage drift amount or a difference between respective pixels
  • the detection module 402 is started to perform detection. During the detection process, the organic light emitting diode OLED is not turned on, and no current flows through the organic light emitting diode OLED. Therefore, all pixel currents I pixel will flow into the detection module, and the detection module 402 compares the detected pixel current I pixel with the actual desired current I REF , and further determines the compensation voltage according to the size of the comparison, that is, the next time the write voltage needs to be written. Whether the ⁇ V of the incoming compensation voltage should change, whether it increases or decreases, ⁇ V can only operate one bit at a time.
  • the display system After the detection of all the rows on the panel is completed, the display system begins to enter the illumination operation frame, or if the detection process occurs during the shutdown process, the display system begins to enter the shutdown mode.
  • the written reference voltage may be V TH0 or V TH0 +V REF or the like as described in the second embodiment.
  • the gate scan driving module 200 in the display system of the present embodiment is further connected to the N rows of pixel units 101 through N rows of off signal lines, respectively, for use in the process of writing the first display signal and the second display signal by the pixel unit 101.
  • the cutoff signal is sent to the pixel unit 101 through the cutoff signal line, and the cutoff signal is used to prevent a current from flowing through the feedback signal line during the writing of the first display signal and the second display signal to the pixel unit 101.
  • the circuit structure of the pixel unit in the display system in this embodiment can be as shown in FIGS. 8, 10, and 11.
  • the pixel unit 101 includes a driving transistor T1, a first switching transistor T2, a second switching transistor T3, a third switching transistor T4, a storage capacitor Cs, and an organic light emitting diode OLED.
  • the first pole of the first switching transistor T2 is coupled to the data line Data Lin
  • the second pole of the first switching transistor T2 is coupled to the control pole of the driving transistor T1
  • the control pole of the first switching transistor T2 is coupled to the scan line Scan [n]
  • the first pole of the second switching transistor T3 is coupled to the feedback signal line FD Line
  • the second pole of the second switching transistor T3 is coupled to the anode of the organic light emitting diode OLED
  • the control pole of the second switching transistor T3 is coupled to the feedback The address line Sen[n]
  • the first pole of the driving transistor T1 is coupled to the power supply voltage V DD
  • the second pole of the driving transistor T1 is coupled to the anode of the organic light emitting diode OLED, and the cathode of the
  • the first pole of the driving transistor T1 is coupled to the power supply voltage V DD through the third switching transistor T4, specifically, the first pole of the third switching transistor T4
  • the power supply voltage V DD is connected
  • the second pole of the third switching transistor T4 is connected to the first pole of the driving transistor T1
  • the control pole of the third switching transistor T4 is connected to the cutoff signal line Sen[n].
  • the second pole of the driving transistor T1 is coupled to the anode of the organic light emitting diode OLED through the third switching transistor T4, specifically, the first pole of the third switching transistor T4.
  • the second pole of the third switching transistor T4 is connected to the anode of the organic light emitting diode OLED, and the gate of the third switching transistor T4 is connected to the off signal line Sen[n].
  • the second pole of the first switching transistor T2 is coupled to the control electrode of the driving transistor T1 through the third switching transistor T4, specifically, the first pole of the third switching transistor T4.
  • the second pole of the third switching transistor T4 is connected to the control pole of the driving transistor T1, and the third opening
  • the gate of the off transistor T4 is connected to the off signal line Sen[n].
  • the pixel unit 101 shown in Figs. 8, 10 and 11 can all operate using the timing chart shown in Fig. 9.
  • Em[n] is at a low level
  • the third switching transistor T4 is turned off, and Scan[n] and Sen[n] are at a high level.
  • the first display signal is written to one end of the storage capacitor Cs, and the second display signal is written to the other end of the storage capacitor Cs to complete data writing; in the subsequent threshold detection phase (2), Em[n] is at a high level.
  • the third switching transistor T4 is turned on, and the pixel unit 101 of the row is supplied with the power supply voltage.
  • the detecting module 402 can detect the current flowing through the pixel unit 101 and compare with a certain current through the feedback signal line FD Line. The result of the comparison determines the threshold change amount, and stores the change amount in the storage module 403. After the compensation detection is completed, both Sen[n] and Scan[n] are at a low level, and the pixel unit 101 emits light.
  • This embodiment discloses a method for a peripheral compensation system of a pixel matrix. In an embodiment, it can be implemented by the display system and the peripheral compensation system disclosed in Embodiment 1. The details are described below.
  • the method disclosed in the present implementation includes a illuminating operation frame and a detection compensation frame. Please refer to FIG. 12, which is a working sequence diagram of the embodiment.
  • any one of the nth rows of pixel units 101 is within t n time, where 1 ⁇ n ⁇ N: the gate scan driving module 200 causes the scan line Scan[n] of the row of pixel units 101 and The feedback address line Sen[n] is valid, and the column data driving module 300 and the compensation module 400 respectively write the first display signal and the second display signal to the row of pixel units 101 through the data line Data Line and the feedback signal line FD Line, wherein A display signal and a second display signal jointly drive the pixel unit 101 to cause the pixel unit 101 to correctly display image or video information; during t n+1 , the gate scan driving module 200 causes the scan line Scan of the row of pixel units 101 [ Both n] and the feedback address line Sen[n] are invalid, and the pixel unit 101 is driven by the first display signal and the second display signal to emit light.
  • each row of the pixel unit 101 sequentially performs the following operations: an arbitrary n-th row of pixel units 101 in a time T n, which is a row of pixels when the unit is provided for detecting a present frame requires 101
  • the gate scan driving module 200 invalidates the scan line Scan[n] of the row of pixel units 101 and the feedback address line Sen[n], wherein the feedback address line Sen[n] effectively maintains a line time of a dry integer multiple.
  • the compensation module 400 detects the change in the electrical characteristics of the row of pixel units 101 through the feedback signal line FD Line, and refreshes and stores the electrical characteristic change information of the row of pixel units 101;
  • the gate scan driving module 200 invalidates the scan line Scan[n] of the row of pixel units 101 and the feedback address line Sen[n], and the scan line Scan[n] effectively maintains one line time, and the feedback address line Sen[n] Invalid until the next frame, the column data driving module 300 writes a low level to the row of pixel units 101 through the data line Data Line to turn off the row of pixel units 101 so that they do not emit light; any nth row of pixels Unit 101 during t n time When the row pixel unit 101 is set to be a frame that does not need to be detected, the gate scan driving module 200 invalidates the scan line Scan[n] of the row of pixel units 101 and invalidates the feedback address line Sen[n].
  • the column data driving module 300 writes a low level to the row of pixel units 101 through the data line Data Line to turn off the row of pixel units 101 so that they do not emit light, thereby maintaining the consistency of the frame time.
  • the number and order of rows of the row pixel units 101 to be detected in the detection compensation frame of each frame are set so that all the pixel units 101 are detected in the detection compensation frames of several frames.
  • a plurality of consecutive frames of illumination operation frames are followed by a frame detection compensation frame to constitute an operation cycle.
  • the method disclosed in the present embodiment makes the detection time of the row pixel unit 101 adjustable. Due to the large-area high-resolution display system, the number of rows of pixel units included is a very large number. Therefore, the time per line is very small. If the detection time is limited to one line time, the detection accuracy of the external detection circuit is small. If the detection time of the pixel unit 101 is adjustable, the detection time of the detection unit can be increased to an integral multiple of the line time, thereby improving the detection precision of the external detection circuit and improving the display. Brightness uniformity. After several operation cycles, the electrical characteristic changes of all the pixel units 101 on the panel will be checked once, which will not affect the image or video display of the large-area resolution display system itself, and will only improve the uniformity. Thus, the method disclosed in the present application is particularly suitable for display systems of large area and high resolution.
  • the peripheral compensation system of the pixel matrix of the present application, the method thereof, and the display system realize the addition of the first display signal and the second display signal in the pixel unit, and can compensate for the problem of inaccurate display caused by the change of the electrical characteristics of the pixel unit.
  • the threshold voltage offset of the compensation driving transistor and the organic light emitting diode OLED is compensated for solving the display unevenness caused by the difference of the threshold voltages of the driving transistors in each pixel unit in the display system, and the luminous efficiency of the organic light emitting diode OLED can also be improved. Display unevenness caused by degradation.
  • the application has accurate gamma correction on the first display signal, and has a simple structure, and the number of bits of the first digital-to-analog conversion module and the second digital-to-analog conversion module is also low, if the analog domain is added, the original
  • the high voltage analog adder can be converted to a medium or low pressure adder.

Abstract

一种像素矩阵的外围补偿系统及其方法、显示系统。所述外围补偿系统包括栅极扫描驱动模块(200)、列数据驱动模块(300)和补偿模块(400)，其中补偿模块(400)通过M列反馈信号线分别与M列像素单元(101)相连，用于检测像素矩阵(100)的电特性变化以向像素矩阵(100)发送第二显示信号来对各像素单元(101)进行补偿。实现了第一显示信号和第二显示信号在像素单元(101)内的加法，对第一显示信号进行了精确的伽马校正的同时，结构简单，第一数模转换模块(301)和第二数模转换模块(401)的位数也低，如果采用模拟域相加的方式，原来的高压模拟加法器可以转换成中压或低压加法器。

Description

一种像素矩阵的外围补偿系统及其方法、显示系统 技术领域
本申请涉及显示器技术领域，尤其涉及一种像素矩阵的外围补偿系统及其方法、显示系统。
背景技术
有源矩阵驱动有机发光二极管(Active Matrix Organic Light-Emitting Diode，OLED)因具有高亮度、高发光效率、宽视角和低功耗等优点，近年来被人们广泛研究，并被迅速应用到新一代的显示系统当中。传统的AMOLED像素单元是两个薄膜场效应晶体管(Thin Film Transistor，TFT)和一个存储电容的结构，如图1所示，其中T1管为驱动晶体管、T2为开关晶体管、CS为存储电容和OLED为发光器件。开关晶体管T2响应来自扫描控制信号线上的信号，采样来自数据线的信号，存储电容CS在开关晶体管T2关断后保存所采样的电压，驱动晶体管T1根据存储电容CS所存储的电压信号为OLED提供电流，该电流决定了OLED的亮度。根据TFT的电压电流公式，驱动电流IDS可以表示为：
Figure PCTCN2016075658-appb-000001
其中，IDS为驱动晶体管T1的漏源电流，μn为薄膜场效应晶体管的有效迁移率，Cox为薄膜场效应晶体管单位面积的栅氧化层电容，W和L分别为薄膜场效应晶体管的有效沟道宽度和有效沟道长度，VG为薄膜场效应晶体管的栅极电压，VOLED为OLED两端的电压，与OLED的阈值电压相关，VTH为TFT的阈值电压。
虽然图1所示像素电路的结构简单，但随着时间的推移，其中的元件会老化，尤其是驱动晶体管T1和有机发光二极管OLED会老化，导致驱动晶体管T1和OLED的阈值电压都会产生漂移，且像素矩阵中各处像素单元的驱动晶体管T1和OLED的阈值电压漂移情况也是不一样的；另外，因薄膜场效应晶体管采用多晶硅材料制成，从而会导致像素矩阵中各个像素单元的驱动晶体管T1的阈值电压VTH具有不均匀的特性；以上两种情况，根据公式(1)可知，驱动电流IDS这时都会发生改变，这样就会造成像素矩阵显示的不均匀性。
针对驱动晶体管和OLED的阈值电压漂移和不均匀带来的像素矩阵显示不均匀的问题，目前有两类对阈值电压进行补偿的方法：像素单元内补偿和外围电路补偿。像素单元内补偿就是通过复杂的像素单元电路结构为OLED提供一个恒定的驱动电流，这种方法的电路不仅复杂，而且电路复杂又进一步会造成像素单元的开口率和良率下降；外围补偿相 比来说可以采用更简单的像素单元结构，因此更适合产业化应用，但外围电路需要特殊设计。
目前外围补偿的电路，都是将数字原始信号先进行伽马校正，再将经过伽马校正的数字原始信号与数字补偿信号相加后送入到一数模转换模块中，以输出一被补偿过的模拟显示信号给像素单元。这种做法的缺点在于，相加后信号的位数会很大，因此数模转换模块的结构会非常复杂；如果在模拟域将原始信号和补偿信号相加，则可能需要高压加法器，不仅会带来芯片面积的增大，还会增大功耗。
发明内容
根据本申请的第一方面，本申请提供一种像素矩阵的外围补偿系统，所述像素矩阵100包括N行M列像素单元101、N行扫描线和M列数据线，像素单元101和各自的扫描线和数据线分别连接，N和M均为正整数，所述外围补偿系统包括：
栅极扫描驱动模块200，用于通过扫描线向像素矩阵100发送扫描信号以在一帧内依次选通各行像素单元101；所述栅极扫描驱动模块200还通过N行反馈地址线分别与N行像素单元101连接，用于通过反馈地址线向像素矩阵100发送检测控制信号以在一帧内依次选通各行像素单元101；
列数据驱动模块300，用于通过数据线向像素矩阵100发送第一显示信号，所述列数据驱动模块300包括第一数模转换模块301，所述第一数模转换模块301接收数字原始信号，输出经过伽马校正的为模拟信号的第一显示信号；
补偿模块400，其通过M列反馈信号线分别与M列像素单元101相连，用于检测像素矩阵100的电特性变化以向像素矩阵100发送第二显示信号来对各像素单元101进行补偿。
在一实施例中，所述补偿模块400包括第二数模转换模块401、检测模块402和存储模块403；所述检测模块402用于通过反馈信号线检测像素单元101的电特性变化，并将检测得到的电特性变化信息发送给所述存储模块403；所述存储模块403用于存储检测模块402发送的电特性变化信息，并根据各像素单元101的电特性变化向第二数模转换模块401发送数字补偿信号；所述第二数模转换模块401对接收的数字补偿信号进行数模转换后通过反馈信号线向像素单元101输出第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息。
在一实施例中，所述像素单元101包括驱动晶体管T1、第一开关晶体管T2、第二开关晶体管T3、存储电容Cs和有机发光二极管OLED；所述第一开关晶体管T2的第一极耦合于所述数据线，第一开关晶体管 T2的第二极耦合于驱动晶体管T1的控制极，第一开关晶体管T2的控制极耦合于所述扫描线；所述第二开关晶体管T3的第一极耦合于所述反馈信号线，第二开关晶体管T3的第二极耦合于所述驱动晶体管T1的第二极，第二开关晶体管T3的控制极耦合于所述反馈地址线；所述驱动晶体管T1的第一极耦合于电源电压VDD，驱动晶体管T1的第二极耦合于所述有机发光二极管OLED的正极，有机发光二极管OLED的负极接地；所述存储电容Cs耦合于驱动晶体管T1的控制极和第二极之间，用于接收第一显示信号和第二显示信号，以通过电容耦合的方式将两种信号相加后加载到所述驱动晶体管T1的控制极和第二极之间。
在一实施例中，所述栅极扫描驱动模块200还通过N行截止信号线分别与N行像素单元101连接，用于当像素单元101被写入第一显示信号和第二显示信号过程中，通过所述截止信号线向像素单元101发送截止信号，所述截止信号用于防止第一显示信号和第二显示信号写入像素单元101过程中所述反馈信号线上有电流流过。
在一实施例中，所述像素单元101包括驱动晶体管T1、第一开关晶体管T2、第二开关晶体管T3、第三开关晶体管T4、存储电容Cs和有机发光二极管OLED；
具体地，所述第一开关晶体管T2的第一极耦合于所述数据线，第一开关晶体管T2的第二极耦合于驱动晶体管T1的控制极，第一开关晶体管T2的控制极耦合于所述扫描线；所述第二开关晶体管T3的第一极耦合于所述反馈信号线，第二开关晶体管T3的第二极耦合于所述有机发光二极管OLED的正极，第二开关晶体管T3的控制极耦合于所述反馈地址线；所述驱动晶体管T1的第一极耦合于电源电压VDD，驱动晶体管T1的第二极耦合于所述有机发光二极管OLED的正极，有机发光二极管OLED的负极接地；所述存储电容Cs耦合于第一开关晶体管T2的第二极和有机发光二极管OLED的阳极之间，用于接收第一显示信号和第二显示信号，以通过电容耦合的方式将两种信号相加后最终加载到所述驱动晶体管T1的控制极和第二极之间；
其中，第一开关晶体管T2的第二极是通过所述第三开关晶体管T4耦合于驱动晶体管T1的控制极，具体地，第三开关晶体管T4的第一极与所述第一开关晶体管T2的第二极连接，第三开关晶体管T4的第二极与所述驱动晶体管T1的控制极连接，第三开关晶体管T4的控制极连接于所述截止信号线；或者，所述驱动晶体管T1的第一极是通过所述第三开关晶体管T4耦合于电源电压VDD，具体地，第三开关晶体管T4的第一极与所述电源电压VDD连接，第三开关晶体管T4的第二极与所述驱动晶体管T1的第一极连接，第三开关晶体管T4的控制极连接于所述截止信号线；或者，驱动晶体管T1的第二极是通过所述第三开关晶 体管T4耦合于所述有机发光二极管OLED的正极，具体地，第三开关晶体管T4的第一极与所述驱动晶体管T1的第二极连接，第三开关晶体管T4的第二极与所述有机发光二极管OLED的正极连接，第三开关晶体管T4的控制极连接于所述截止信号线。
在一实施例中，所述第一显示为数据图像信号电压，第二显示信号为驱动晶体管T1的阈值电压和补偿电压之和；或者，所述第一显示信号为驱动晶体管T1的阈值电压，第二显示信号为数据图像信号电压和补偿电压之和；或者，所述第一显示信号为驱动晶体管T1的阈值电压和数据图像信号电压之和，第二显示信号为补偿电压。
根据本申请的第二方面，本申请提供一种包括上述像素矩阵的外围补偿系统的方法，所述像素矩阵100包括N行M列像素单元101、N行扫描驱动线和M列数据线，像素单元101和各自的扫描线和数据线分别连接，N和M均为正整数，所述方法包括以下操作：一帧时间由N个相等的行时间t1～tN组成，每行像素单元101依次进行下述操作：
任意一第n行像素单元101在tn时间内，其中1≤n≤N：栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线有效，列数据驱动模块300和补偿模块400分别通过数据线和反馈信号线向此行像素单元101写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块200使此行像素单元101的扫描线无效以及继续维持反馈地址线有效，补偿模块400通过反馈信号线检测此行像素单元101的电特性变化以在下帧该行像素单元101被选通时进行补偿；在tn+2时间内，栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线都无效，像素单元101被所述第一显示信号和第二显示信号驱动以发光。
根据本申请的第三方面，本申请提供一种包括上述像素矩阵的外围补偿系统的方法，所述像素矩阵100包括N行M列像素单元101、N行扫描驱动线和M列数据线，像素单元101和各自的扫描线和数据线分别连接，N和M均为正整数，所述方法包括发光操作帧和检测补偿帧，其中一帧时间由N个相等的行时间t1～tN组成；
在一帧的发光操作帧中，任意一第n行像素单元101在tn时间内，其中1≤n≤N：栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线有效，列数据驱动模块300和补偿模块400分别通过数据线和反馈信号线向此行像素单元101写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线都无效，像素单元101 被所述第一显示信号和第二显示信号驱动以发光；在一帧的检测补偿帧中，每行像素单元101或所有像素单元101中的若干行像素单元101依次进行下述操作，当在一帧的检测补偿帧中，只有所有像素单元101中的若干行像素单元101依次进行下述操作时，安排进行下述操作的行像素单元101次序，以使在若干帧的检测补偿帧中，所有像素单元101都进行了一遍下述操作：当轮到某一具体行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线有效，维持一个行时间，在此行时间内，列数据驱动模块300和补偿模块400分别通过数据线和反馈信号线向此行像素单元101写入一固定电压信号和上一次在检测补偿帧中检测到的像素单元101的最新阈值电压信号；下一个行时间内，栅极扫描驱动模块200使此行像素单元101的扫描线无效和反馈地址线有效，维持一个行时间，在此行时间内，补偿模块400通过反馈信号线检测此行像素单元101的电特性变化，并刷新和存储此行像素单元101的电特性变化信息；下一个行时间内，栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线有效，维持一个行时间，在此行时间内，列数据驱动模块300和补偿模块400分别通过数据线和反馈信号线向此行像素单元101写入低电平信号以使此行像素单元101不发光；其中，在检测补偿帧之前，各行像素单元101先被依次写入低电平信号以不发光；其中，连续若干帧的发光操作帧后面紧接着一帧检测补偿帧；
或者，
在一帧的发光操作帧中，任意一第n行像素单元101在tn时间内，其中1≤n≤N：栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线有效，列数据驱动模块300和补偿模块400分别通过数据线和反馈信号线向此行像素单元101写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线都无效，像素单元101被所述第一显示信号和第二显示信号驱动以发光；在一帧的检测补偿帧中，每行像素单元101依次进行下述操作：当轮到某一具体行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线有效，维持一个行时间，在此行时间内，列数据驱动模块300和补偿模块400分别通过数据线和反馈信号线向此行像素单元101写入一固定电压信号和上一次在检测补偿帧中检测到的像素单元101的最新阈值电压信号；下一个行时间内，栅极扫描驱动模块200使此行像素单元101的扫描线无效和反馈地址线有效，维持一个行时间，在此行时间内，补偿模块400通过反馈信号线检测此行像素单元101的电特性变化，并刷 新和存储此行像素单元101的电特性变化信息；其中，所述检测补偿帧位于像素矩阵开机和/或关机的时候。
根据本申请的第五方面，本申请提供一种包括上述的像素矩阵的外围补偿系统的方法，所述像素矩阵100包括N行M列像素单元101、N行扫描驱动线和M列数据线，像素单元101和各自的扫描线和数据线分别连接，N和M均为正整数，所述方法包括发光操作帧和检测补偿帧，其中一帧时间由N个相等的行时间t1～tN组成；
在一帧的发光操作帧中，任意一第n行像素单元101在tn时间内，其中1≤n≤N：栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线有效，列数据驱动模块300和补偿模块400分别通过数据线和反馈信号线向此行像素单元101写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块200使此行像素单元101的扫描线和反馈地址线都无效，像素单元101被所述第一显示信号和第二显示信号驱动以发光；
在一帧的检测帧中，每行像素单元101依次进行下述操作：任意一第n行像素单元101在tn时间内，当其为被设置为本帧需要进行检测的行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线无效以及反馈地址线有效，其中反馈地址线有效维持若个干整数倍的行时间，在所述反馈地址线有效期间内，补偿模块400通过反馈信号线检测此行像素单元101的电特性变化，并刷新和存储此行像素单元101的电特性变化信息；之后，栅极扫描驱动模块200使此行像素单元101的扫描线有效以及反馈地址线无效，扫描线有效维持一个行时间，反馈地址线无效维持到下一帧，列数据驱动模块300通过数据线向此行像素单元101写入一低电平，以关断此行像素单元101，使其不发光；任意一第n行像素单元101在tn时间内，当其为被设置为本帧不需要进行检测的行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线有效以及反馈地址线无效，都维持一个行时间，列数据驱动模块300通过数据线向此行像素单元101写入一低电平，以关断此行像素单元101，使其不发光；其中，设置在每一帧的检测补偿帧中需要进行检测的行像素单元101的行数以及次序，以使在若干帧的检测补偿帧中，所有像素单元101都被进行了检测；其中，连续若干帧的发光操作帧后面紧接着一帧检测补偿帧。
根据本申请的第五方面，本申请提供一种显示系统，包括一像素矩阵，以及上述的像素矩阵的外围补偿系统。
依上述实施的像素矩阵的外围补偿系统及其方法、显示系统，实现了将第一显示信号和第二显示信号在像素单元内的加法，可以补偿像素 单元因电特性变化导致的显示不准确的问题，例如，补偿驱动晶体管和有机发光二极管OLED的阈值电压偏移，解决显示系统中各像素单元内的驱动晶体管阈值电压不同而导致的显示不均匀问题，还可以改善因有机发光二极管OLED的发光效率退化造成的显示不均匀问题。本申请对第一显示信号进行了精确的伽马校正的同时，结构简单，第一数模转换模块和第二数模转换模块的位数也低，如果采用的模拟域相加的方式，原来的高压模拟加法器可以转换成中压或低压加法器。
附图说明
图1为传统像素单元的一种电路结构示意图；
图2为本申请的第一种实施例中显示系统的一种结构示意图；
图3为本申请一种实施例中像素单元的一种结构示意图；
图4为本申请的第一种实施例的一种工作时序图；
图5为本申请的第二种实施例中发光操作帧的一种工作时序图；
图6为本申请的第二种实施例中检测补偿帧的一种工作时序图；
图7为本申请的第三种实施例中检测补偿帧的一种工作时序图；
图8为本申请的第四种实施例中像素单元的第一种结构示意图；
图9为本申请的第四种实施例的一种工作时序图；
图10为本申请的第四种实施例中像素单元的第二种结构示意图；
图11为本申请的第四种实施例中像素单元的第三种结构示意图；
图12为本申请的第五种实施例的一种工作时序图。
具体实施方式
实施例1：
请参照图2，本实施例公开了一种显示系统，其包括像素矩阵100，以及像素矩阵的外围补偿系统(下面简称外围补偿系统)。
像素矩阵100包括N行M列像素单元101、N行扫描线和M列数据线，像素单元101和各自的扫描线和数据线分别连接，N和M均为正整数。
外围补偿系统包括栅极扫描驱动模块200、列数据驱动模块300和补偿模块400，下面具体说明。
栅极扫描驱动模块200用于通过扫描线向像素矩阵100发送扫描信号以在一帧内依次选通各行像素单元101；栅极扫描驱动模块200还通过N行反馈地址线分别与上述的N行像素单元101连接，用于通过反馈地址线向像素矩阵100发送检测控制信号以在一帧内依次选通各行像素单元101。
列数据驱动模块300用于通过数据线向像素矩阵100发送第一显示信号，在一实施例中，列数据驱动模块300包括第一数模转换模块301，第一数模转换模块301接收数字原始信号，输出经过伽马校正的为模拟 信号的第一显示信号；具体地，第一数模转换模块301可以为M个，以对应M列像素单元101。在一实施例中，列数据驱动模块300还可以包括第一移位暂存器302，第一移位暂存器302用于接收上述的数字原始信号，并传递给上述的第一数模转换模块301。
补偿模块400通过M列反馈信号线分别与M列像素单元101相连，用于检测像素矩阵100的电特性变化以向像素矩阵100发送第二显示信号来对各像素单元101进行补偿。需要说明的是，这里的“电特性变化”可以指的是像素单元101中晶体管和/或有机发光二极管的电特性变化，比如，晶体管的阈值变化信息，有机发光二极管的发光效率退化信息。在一具体实施例中，补偿模块400包括第二数模转换模块401、检测模块402和存储模块403；检测模块402用于通过反馈信号线检测像素单元101的电特性变化，并将检测得到的电特性变化信息发送给存储模块403；存储模块403用于存储检测模块402发送的电特性变化信息，并根据各像素单元101的电特性变化向第二数模转换模块401发送数字补偿信号；第二数模转换模块401对接收的数字补偿信号进行数模转换后通过反馈信号线向像素单元101输出第二显示信号，其中第二显示信号和上述的第一显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息，避免因像素单元101的电特性变化而导致的图像或视频信息显示不准确的问题。在一实施例中，补偿模块400还可以包括第二移位暂存器404和第三移位暂存器405，第二移位暂存器404用于接收存储模块403发出的数字补偿信号并传递给第二数模转换模块401；第三移位暂存器405用于检测模块402发出的电特性变化信息并将该信息传递给存储模块403。
请参照图3，为本实施例中像素单元101的一种具体电路结构。在一具体实施例中，像素单元101包括驱动晶体管T1、第一开关晶体管T2、第二开关晶体管T3、存储电容Cs和有机发光二极管OLED；第一开关晶体管T2的第一极耦合于上述数据线Data Line，第一开关晶体管T2的第二极耦合于驱动晶体管T1的控制极，第一开关晶体管T2的控制极耦合于上述扫描线Scan[n]；第二开关晶体管T3的第一极耦合于上述反馈信号线FD Line，第二开关晶体管T3的第二极耦合于驱动晶体管T1的第二极，第二开关晶体管T3的控制极耦合于上述反馈地址线Sen[n]；驱动晶体管T1的第一极耦合于电源电压VDD，驱动晶体管T1的第二极耦合于有机发光二极管OLED的正极，有机发光二极管OLED的负极接地；存储电容Cs耦合于驱动晶体管T1的控制极和第二极之间，用于接收第一显示信号和第二显示信号，以通过电容耦合的方式将两种信号相加后加载到所述驱动晶体管T1的控制极和第二极之间。对应本电路结构，补偿模块400可以用于检测驱动晶体管T1和有机发光二极 管OLED的电特性变化，例如，检测驱动晶体管T1和有机发光二极管OLED的阈值电压偏移信息，检测有机发光二极管OLED的发光效率退化信息等。
需要说明的是，本申请中的晶体管指的是，本申请中的晶体管为三端子晶体管，其三个端子为控制极、第一极和第二极；当晶体管为双极型晶体管时，控制极是指双极型晶体管的基极，第一极是指双极型晶体管的集电极或发射极，对应的第二极就是指双极型晶体管的发射极或集电极；当晶体管为场效应晶体管时，控制极是指场效应晶体管的栅极，第一极是指场效应晶体管的漏极或源极，对应的第二极就是指场效应晶体管的源极或漏极。显示系统中的晶体管通常为场效应晶体管，下面不妨以晶体管为N沟道场效应晶体管为例对电路进行说明，相应地，此时晶体管的控制极指栅极，第一极指漏极，第二极指源极；当然，在其他实施例中晶体管也可以是其他类型的场效应晶体管或双极型晶体管。本申请的晶体管，可以采用非晶硅、多晶硅、氧化物半导体、有机半导体、NMOS/PMOS工艺或者CMOS工艺来制造。
本实施例还公开了一种像素矩阵的外围补偿系统的方法，所述方法包括(1)数据写入操作；(2)反馈检测操作；(3)发光操作。下面具体说明。
一帧时间由N个相等的行时间t1～tN组成，每行像素单元(101)依次进行(1)数据写入操作：任意一第n行像素单元101在tn时间内，其中1≤n≤N，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]有效，列数据驱动模块300和补偿模块400分别通过数据线Data Line和反馈信号线FD Line向此行像素单元101写入第一显示信号和第二显示信号，其中第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息。(2)反馈检测操作：在tn+1时间内，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]无效以及继续维持反馈地址线Sen[n]有效，补偿模块400通过反馈信号线FD Line检测此行像素单元101的电特性变化以在下帧该行像素单元101被选通时进行补偿。(3)发光操作：在tn+2时间内，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]都无效，像素单元101被所述第一显示信号和第二显示信号驱动以发光。
下面再以一个实例进行说明。
请参照图4，为本实施例的一种工作时序图。对像素矩阵100的选通是以行为单位选通像素单元101，对每行的像素单元101的操作，如上所述，包括(1)数据写入操作、(2)反馈检测操作和(3)发光操作。
(1)数据写入操作
在tn时间，第n行的扫描线Scan[n]和反馈地址线Sen[n]输出为高电平，因此第一开关晶体管T2和第二开关晶体管T3都导通，此时第一开关晶体管T2传输来自数据线Data Line的数据电压VDATA发给存储电容CS的第一电极，第二开关晶体管T3传送来自反馈信号线FD Line的补偿电压-(VTH0+△V)信号发给存储电容CS的第二电极，其中VTH0为面板上驱动晶体管T1的阈值电压初始值或者中间值，△V为阈值电压漂移量或者各个像素间的差值；此时，存储电容CS上的电压差变为VDATA+VTH0+△V，也即为驱动晶体管T1的栅源电极之间的电压差为VDATA+VTH+△V。
(2)反馈检测操作
此阶段中，第n行的扫描线Scan[n]上的电压为低电平，则第一开关晶体管T2管关断，反馈地址线Sen[n]输出仍为高电平，反馈信号线FD Line接入检测模块402，开始进行检测，检测过程中有机发光二极管OLED不导通，OLED上不能有电流流过。因此所有像素电流Ipixel将流入检测模块402，检测模块402会根据比较检测到的像素电流Ipixel与实际发光所需的电流Idata的大小决定对补偿电压进行进一步的操作，即下次需要写入的补偿电压的ΔV是否应该发生变化，是增大还是减小，ΔV可以每次只发生一位的操作。完成检测以后反馈地址线Sen[n]输出为低电平，第二开关晶体管T3关断，存储电容CS上的电压差保持为数据写入阶段的电压差VDATA+VTH0+△V。在一实施例中，可以通过开关来选择第二数模转换模块401和检测模块402是否接入反馈信号线FD Line。在一实施例中，为了使所有像素电流Ipixel流入检测模块402，可以设置此时反馈信号线FD Line上的电压为Vref，该电压不小于有机发光二极管OLED的开启电压，因此，有机发光二极管OLED上没有电流，所有的电流都经第二开关晶体管T3流入检测模块402。
(3)发光操作
此阶段中，第n行的扫描线Scan[n]和反馈地址线Sen[n]输出为低电平，驱动晶体管T1不再接收来自数据线Data Line和反馈信号线FD Line的电压信号，驱动晶体管T1根据存储电容CS上的电压差驱动有机发光二极管OLED发光。此时流过OLED的电流可以表示为公式(2)
Figure PCTCN2016075658-appb-000002
其中驱动晶体管T1的迁移率μ和阈值电压VTH都可能发生变化，如果在一些像素单元101中只有驱动晶体管T1的阈值电压发生变化，则 VTH0+ΔV＝VTH，此时流过有机发光二极管OLED的电流可以进一步简化为
Figure PCTCN2016075658-appb-000003
可见流过有机发光二极管OLED的电流与驱动晶体管T1、有机发光二极管OLED的阈值电压漂移或像素单元101间的不均匀无关，因此可以补偿驱动晶体管T1和有机发光二极管OLED的阈值电压漂移或像素单元101间的不均匀而产生的变化。
如果驱动晶体管T1的迁移率也发生了变化，即μ＝μ0+Δμ，则ΔV也应该包含一部分迁移率变化的信息，即ΔV＝ΔVTH+αΔμ，其中ΔVTH为驱动晶体管T1的阈值电压变化量，此时流过有机发光二极管OLED的电流可以表示为
Figure PCTCN2016075658-appb-000004
其α是只与迁移率变化量相关的量，最后流过有机发光二极管OLED的电流近似等于发光所需的电流Idata。因此该外围补偿系统可以进一步补偿驱动晶体管T1迁移率的变化。
了进一步校正有机发光二极管OLED的发光效率退化，还可以进一步完成如下操作，扫描线Scan[n]和反馈地址线Sen[n]的电压为高电平，写入的第一显示信号为低电平，反馈信号线FD Line接入检测模块402，此时驱动管晶体管T1关断，检测模块402在有机发光二极管OLED的正极施加某一恒定电压，检测流过OLED的电流大小，根据对照有机发光二极管的电特性曲线，就可以知道此时有机发光二极管OLED的退化情况，修改VDATA和IDATA之间的关系，完成有机发光二极管OLED发光效率退化检测。另外，由于有机发光二极管OLED发光效率的退化相对缓慢，因此，有机发光二极管OLED发光效率的退化可以很长时间检测一次，或者在每次开机或关机的时候检测一次。
在一实施例中，第一显示为数据图像信号电压，第二显示信号为驱动晶体管T1的阈值电压和补偿电压之和；或者，第一显示信号为驱动晶体管T1的阈值电压，第二显示信号为数据图像信号电压和补偿电压之和；或者，第一显示信号为驱动晶体管T1的阈值电压和数据图像信号电压之和，第二显示信号为补偿电压。
例如，在数据写入操作阶段，第一开关晶体管T2导通，数据线Data  Line写入的第一显示信号为VTH0而不是VDATA，第二开关晶体管T3导通，反馈信号线FD Line写入的为-(VDATA+ΔV)，则此时存储电容CS两端的电压差仍为VTH0-(-(VDATA+ΔV))＝VDATA+VTH0+ΔV。
又例如，在数据写入操作阶段，第一开关晶体管T2导通，数据线Data Line写入的第一信号为VTH0+ΔV而不是VDATA，第二开关晶体管T3导通，反馈信号线FD Line写入的为-VDATA，则此时存储电容CS两端的电压差仍为VTH0+ΔV-(-VDATA)＝VDATA+VTH0+ΔV。
又例如，在数据写入操作阶段，第一开关晶体管T2导通，数据线Data Line写入的第一信号为VDATA+ΔV而不是VDATA，第二开关晶体管T3导通，反馈信号线FD Line写入的为-VTH0，则此时存储电容CS两端的电压差仍为VDATA+VTH0+ΔV。
又例如，在数据写入操作阶段，第一开关晶体管T2导通，数据线Data Line写入的第一信号为VDATA+VTH0而不是VDATA，第二开关晶体管T3导通，反馈信号线FD Line写入的为-ΔV，则此时存储电容CS两端的电压差仍为VDATA+VTH0+ΔV。
实施例2：
本实施例公开了一种像素矩阵的外围补偿系统的方法，在一实施例中，其可通过实施例一中公开的显示系统和外围补偿系统进行实施。下面具体说明。
本实施例公开的方法包括发光操作帧和检测补偿帧。
在发光操作帧中，对像素单元101的操作也是逐行进行的，其包括(1)数据写入操作和(2)发光操作。具体地，(1)数据写入操作：在一帧的发光操作帧中，任意一第n行像素单元101在tn时间内，其中1≤n≤N，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]有效，列数据驱动模块300和补偿模块400分别通过数据线Data Line和反馈信号线FD Line向此行像素单元101写入第一显示信号和第二显示信号，其中第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息。(2)发光操 作：在tn+1时间内，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]都无效，像素单元101被所述第一显示信号和第二显示信号驱动以发光。
在检测补偿帧中，对每行像素单元101的操作包括(1)参考电压的写入、(2)反馈检测操作和(3)写入低电平数据。具体地，在一帧的检测补偿帧中，每行像素单元101或所有像素单元101中的若干行像素单元101依次进行下述操作，当在一帧的检测补偿帧中，只有所有像素单元101中的若干行像素单元101依次进行下述操作时，安排进行下述操作的行像素单元101次序，以使在若干帧的检测补偿帧中，所有像素单元101都进行了一遍下述操作：(1)参考电压的写入：当轮到某一具体行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]有效，维持一个行时间，在此行时间内，列数据驱动模块300和补偿模块400分别通过数据线Data Line和反馈信号线FD Line向此行像素单元101写入一固定电压信号和上一次在检测补偿帧中检测到的像素单元101的最新阈值电压信号。(2)反馈检测操作：下一个行时间内，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]无效和反馈地址线Sen[n]有效，维持一个行时间，在此行时间内，补偿模块400通过反馈信号线FD Line检测此行像素单元101的电特性变化，并刷新和存储此行像素单元101的电特性变化信息。(3)写入低电平数据：下一个行时间内，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]有效，维持一个行时间，在此行时间内，列数据驱动模块300和补偿模块400分别通过数据线Data Line和反馈信号线FD Line向此行像素单元101写入低电平信号以使此行像素单元101不发光；其中，在检测补偿帧之前，各行像素单元101先被依次写入低电平信号以不发光；其中，连续若干帧的发光操作帧后面紧接着一帧检测补偿帧。
下面再以一个实例进行说明。
请参照图5和图6，分别为本实施例中发光操作帧和检测补偿帧的一种工作时序图。在发光操作帧中，显示系统中的电路的驱动速度很快，与传统的2T1C像素的驱动速度一样，在检测补偿帧中，显示系统可完成像素单元的电特性退化检测，并完成刷新补偿信息的功能。显示系统可以在某些帧工作模式为发光操作帧，一段时间入插入一帧或几帧时间的检测补偿帧。
发光操作帧，如上所述，包括(1)数据写入操作和(2)发光操作。
(1)数据写入操作
在tn时间，第n行的扫描线Scan[n]和反馈地址线Sen[n]输出为高电平，因此第一开关晶体管T2和第二开关晶体管T3都导通，此时第一开 关晶体管T2传输来自数据线Data Line的数据电压VDATA发给存储电容CS的第一电极，第二开关晶体管T3传送来自反馈信号线FD Line的补偿电压-(VTH0+△V)信号发给存储电容CS的第二电极，其中VTH0为面板上驱动晶体管T1的阈值电压初始值或者中间值，△V为阈值电压漂移量或者各个像素间的差值；此时，存储电容CS上的电压差变为VDATA+VTH0+△V，也即为驱动晶体管T1的栅源电极之间的电压差为VDATA+VTH+△V。
(2)发光操作
此阶段中，第n行的扫描线Scan[n]和反馈地址线Sen[n]输出为低电平，驱动晶体管T1不再接收来自数据线Data Line和反馈信号线FD Line的电压信号，驱动晶体管T1根据存储电容CS上的电压差驱动有机发光二极管OLED发光。此时流过OLED的电流可以表示为公式(5)：
Figure PCTCN2016075658-appb-000005
其中驱动晶体管T1的迁移率μ和阈值电压VTH都可能发生变化，如果在一些像素单元101中只有驱动晶体管T1的阈值电压发生变化，则ΔV＝ΔVTH，其中ΔVTH为驱动晶体管T1的阈值电压变化量，即VTH0+ΔV＝VTH，此时流过有机发光二极管OLED的电流可以进一步简化为：
Figure PCTCN2016075658-appb-000006
可见，流过有机发光二极管OLED的电流与驱动晶体管T1、有机发光二极管OLED的阈值电压漂移或像素单元101间的不均匀无关，因此可以补偿驱动晶体管T1和有机发光二极管OLED的阈值电压漂移或像素单元101间的不均匀而产生的变化。
如果驱动晶体管T1的迁移率也发生了变化，即μ＝μ0+Δμ，则ΔV也应该包含一部分迁移率变化的信息，即ΔV＝ΔVTH+αΔμ，其中ΔVTH为驱动晶体管T1的阈值电压变化量，此时流过有机发光二极管OLED的电流可以表示为：
Figure PCTCN2016075658-appb-000007
其中，α是只与迁移率变化量相关的量，最后流过有机发光二极管OLED的电流近似等于发光所需的电流Idata。因此该外围补偿系统可以进一步补偿驱动晶体管的迁移率的变化。当然，还可以如实施例一种所示还可以采用其他的方式写入VDATA，VTH0和ΔV，只要最后使得存储电容CS两端的电压差为VDATA+VTH0+△V即可完成数据的写入操作，进而开始发光。写入方法与实施例一中相似，这里不再赘述。
检测补偿帧，如上所述，包括(1)参考电压的写入、(2)反馈检测操作和(3)写入低电平数据。
在进行检测补偿帧之前，显示系统中所有的像素单元101需要被写入某一电平，使得驱动晶体管T1被关断，即驱动晶体管T1的栅源极电压VGS_T1≤0，使得有机发光二极管OLED不发光，即有机发光二极管OLED的正极电位小于其开启电压VTH_OLED，此过程可以称之为黑矩阵的写入。黑矩阵的写入也可以是逐行进行的，如采用发光操作帧的模式写入黑矩阵。
(1)参考电压的写入
在某一时间，第n行的扫描控制线Scan[n]和反馈地址线Sen[n]输出为高电平，因此第一开关晶体管T2和第二开关晶体管T3都导通，此时第一开关晶体管T2传输来自数据线Data Line的参考电压VREF发给存储电容Cs的第一电极，第二开关晶体管T3传送来自反馈信号线FD Line的补偿电压-(VTH0+△V)信号发给存储电容Cs的第二电极，其中VTH0为显示系统中驱动晶体管T1的阈值电压初始值或者中间值，△V为阈值电压漂移量或者各个像素单元101间的差值；此时，存储电容Cs上的电压差变为VREF+VTH0+△V，也即为驱动晶体管T1的栅源电极之间的电压差为VREF+VTH+△V。
(2)反馈检测操作
此阶段中，第n行的扫描线Scan[n]上的电压为低电平，则第一开关晶体管T2管关断，反馈地址线Sen[n]输出仍为高电平，反馈信号线FD Line接入检测模块402，开始进行检测，检测过程中有机发光二极管OLED不导通，有要发光二极管OLED上不能有电流流过。因此像素单元中的电流Ipixel将流入检测模块402，检测模块402会根据比较检测到的像素电流Ipixel与实际期望的电流IREF，比较的大小决定对补偿电压进行进一步的操作，即下次需要写入的补偿电压中ΔV是否应该发生变化，是增大还是减小，ΔV可以每次只发生一位的操作。
(3)写入低电平数据
写入低电平数据的目的是形成上述的黑矩阵，避免探测过程中有机发光二极管OLED发光。完成探测以后，第n行的扫描线Scan[n]上的 电压为高电平，则第一开关晶体管T2管导通，此时第一开关晶体管T2传输来自数据线Data Line的低电平电压VR发给存储电容Cs的第一电极，反馈地址线Sen[n]输出仍为高电平，第二开关管T3导通，第二开关晶体管T3传送来自反馈信号线FD Line的低电平信号发给存储电容Cs的第二电极，使得驱动晶体管T1的栅源电压差小于等于0，因此驱动晶体管T1关断；由于Cs第二电极的电压为低电平，该电平可以使有机发光二极管OLED不发光，且该电平被有机发光二极管OLED自身的寄生电容COLED保存。
在一实施例中，显示系统中所有像素单元101完成探测补偿之后，显示系统开始进行发光操作帧。
在一实施例中，显示系统中只有一部分像素单元101完成探测补偿阶段，显示系统就开始进行发光操作帧。例如，第一次的检测补偿帧中，像素单元101的1-5行完成了阈值探测补偿，则第二次的检测补偿帧中，像素单元101的6-10行完成阈值探测补偿操作，以此类推。
在一实施例中，，第一开关晶体管T2导通，数据线Data Line写入的第一信号为VTH0而不是VREF，第二开关晶体管T3导通，反馈信号线FD Line写入的为-(VREF+ΔV)，则此时存储电容Cs两端的电压差仍为VREF+VTH0+ΔV。
在一实施例中，第一开关晶体管T2导通，数据线Data Line写入的第一信号为VREF+VTH0而不是VREF，第二开关晶体管T3导通，反馈信号线FD Line写入的为-ΔV，则此时存储电容Cs两端的电压差仍为VREF+VTH0+ΔV。
另外，对于有机发光二极管OLED发光效率退化的检测可以类似实施例一中所述，这里不再赘述。
实施例3
本实施例公开了一种像素矩阵的外围补偿系统的方法，在一实施例中，其可通过实施例一中公开的显示系统和外围补偿系统进行实施。下面具体说明
与实施例二的一个不同为，实施例二中的发光操作帧的操作，本实施例放在显示系统开机和/或关机的时候进行，但是本实施例不需要写入黑矩阵。
本实施例公开的方法也包括发光操作帧和检测补偿帧。
发光操作帧的操作与实施例二中一样，在这里不再赘述。
在一帧的检测补偿帧中，每行像素单元(101)依次进行下述操作：(1)参考电压的写入：当轮到某一具体行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n] 有效，维持一个行时间，在此行时间内，列数据驱动模块300和补偿模块400分别通过数据线Data Line和反馈信号线FD Line向此行像素单元101写入一固定电压信号和上一次在检测补偿帧中检测到的像素单元101的最新阈值电压信号；(2)反馈检测操作：下一个行时间内，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]无效和反馈地址线Sen[n]有效，维持一个行时间，在此行时间内，补偿模块400通过反馈信号线FD Line检测此行像素单元101的电特性变化，并刷新和存储此行像素单元101的电特性变化信息；其中，所述检测补偿帧位于像素矩阵开机和/或关机的时候。
下面再以一个实例进行说明。
请参照图7，为本实施例中检测补偿帧的一种工作时序图。如上所述，与实施例二不同，在进行检测补偿帧前，像素电路不需要写入黑矩阵，可以直接开始检测补偿帧的工作过程，探测补偿操作完成以后，也不需要写入低电平以使有机发光二极管OLED不发光。
(1)参考电压的写入
在某一时间，第n行的扫描线Scan[n]和反馈地址线Sen[n]输出为高电平，因此第一开关晶体管T2和第二开关晶体管T3都导通，此时第一开关晶体管T2传输来自数据线Data Line的参考电压VREF发给存储电容Cs的第一电极，第二开关晶体管T3传送来自反馈信号线FD Line的补偿电压-(VTH0+△V)信号发给存储电容Cs的第二电极，其中VTH0为面板上驱动晶体管T1的阈值电压初始值或者中间值，△V为阈值电压漂移量或者各个像素间的差值；此时，存储电容Cs上的电压差变为VREF+VTH0+△V，也即为驱动晶体管T1的栅源电极之间的电压差为VREF+VTH0+△V。
(2)反馈检测操作
此时第n行的扫描线Scan[n]上的电压为低电平，则第一开关晶体管T2管关断，反馈地址线Sen[n]输出仍为高电平，反馈信号线FD Line接入检测模块402，开始进行检测，检测过程中有机发光二极管OLED不导通，有机发光二极管OLED上不能有电流流过。因此所有像素电流Ipixel将流入检测模块，检测模块402会比较检测到的像素电流Ipixel与实际期望的电流IREF，并根据比较的大小决定对补偿电压进行进一步的操作，即下次需要写入的补偿电压中ΔV是否应该发生变化，是增大还是减小，ΔV可以每次只发生一位的操作。
完成面板上所有行的探测以后，显示系统开始进入发光操作帧，或者如果该探测过程发生在关机的过程中，则显示系统开始进入关机模式。
在其他一些实施例中，在写入参考电压阶段，写入的参考电压如实施例二中所述可以为VTH0或者VTH0+VREF等。
实施例4
为了防止上述实施例中的数据写入操作阶段中，反馈信号线FD Line上有电流流过。下面分别说明。
本实施例的显示系统中的栅极扫描驱动模块200还通过N行截止信号线分别与N行像素单元101连接，用于当像素单元101被写入第一显示信号和第二显示信号过程中，通过截止信号线向像素单元101发送截止信号，截止信号用于防止第一显示信号和第二显示信号写入像素单元101过程中反馈信号线上有电流流过。
本实施例中的显示系统中的像素单元的电路结构可以如图8、10、11所示。
像素单元101包括驱动晶体管T1、第一开关晶体管T2、第二开关晶体管T3、第三开关晶体管T4、存储电容Cs和有机发光二极管OLED。具体地，第一开关晶体管T2的第一极耦合于数据线Data Lin，第一开关晶体管T2的第二极耦合于驱动晶体管T1的控制极，第一开关晶体管T2的控制极耦合于扫描线Scan[n]；第二开关晶体管T3的第一极耦合于反馈信号线FD Line，第二开关晶体管T3的第二极耦合于有机发光二极管OLED的正极，第二开关晶体管T3的控制极耦合于反馈地址线Sen[n]；驱动晶体管T1的第一极耦合于电源电压VDD，驱动晶体管T1的第二极耦合于所述有机发光二极管OLED的正极，有机发光二极管OLED的负极接地；存储电容Cs耦合于第一开关晶体管T2的第二极和有机发光二极管OLED的阳极之间，用于接收第一显示信号和第二显示信号，以通过电容耦合的方式将两种信号相加后最终加载到所述驱动晶体管T1的控制极和第二极之间。
如图8所示，像素单元101中，所述驱动晶体管T1的第一极是通过所述第三开关晶体管T4耦合于电源电压VDD，具体地，第三开关晶体管T4的第一极与所述电源电压VDD连接，第三开关晶体管T4的第二极与所述驱动晶体管T1的第一极连接，第三开关晶体管T4的控制极连接于截止信号线Sen[n]。
如图10所示，像素单元101中，驱动晶体管T1的第二极是通过所述第三开关晶体管T4耦合于所述有机发光二极管OLED的正极，具体地，第三开关晶体管T4的第一极与所述驱动晶体管T1的第二极连接，第三开关晶体管T4的第二极与所述有机发光二极管OLED的正极连接，第三开关晶体管T4的控制极连接于截止信号线Sen[n]。
如图11所示，像素单元101中，第一开关晶体管T2的第二极是通过所述第三开关晶体管T4耦合于驱动晶体管T1的控制极，具体地，第三开关晶体管T4的第一极与所述第一开关晶体管T2的第二极连接，第三开关晶体管T4的第二极与所述驱动晶体管T1的控制极连接，第三开 关晶体管T4的控制极连接于截止信号线Sen[n]。
图8、10和11中所示的像素单元101，都可以采用图9所示的时序图进行工作。在第n行的像素单元101的数据写入操作阶段(1)中，Em[n]为低电平，第三开关晶体管T4关断，Scan[n]和Sen[n]为高电平，第一显示信号写入存储电容Cs的一端，第二显示信号写入存储电容Cs的另一端即可完成数据写入；在之后的阈值检测阶段(2)中，Em[n]为高电平，第三开关晶体管T4导通，为此行的像素单元101提供电源电压，则此时检测模块402通过反馈信号线FD Line可以检测此时流过像素单元101的电流并与某一电流进行比较，比较的结果决定阈值变化量，并将该变化量存储在存储模块403；完成补偿检测以后，Sen[n]和Scan[n]都为低电平，像素单元101进行发光。
实施例5
本实施例公开了一种像素矩阵的外围补偿系统的方法，在一实施例中，其可通过实施例一中公开的显示系统和外围补偿系统进行实施。下面具体说明。
本实施公开的方法包括发光操作帧和检测补偿帧。请参照图12，为本实施例的一种工作时序图。
在一帧的发光操作帧中，任意一第n行像素单元101在tn时间内，其中1≤n≤N：栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]有效，列数据驱动模块300和补偿模块400分别通过数据线Data Line和反馈信号线FD Line向此行像素单元101写入第一显示信号和第二显示信号，其中第一显示信号和第二显示信号共同驱动像素单元101，使像素单元101正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]和反馈地址线Sen[n]都无效，像素单元101被第一显示信号和第二显示信号驱动以发光。
在一帧的检测补偿帧中，每行像素单元101依次进行下述操作：任意一第n行像素单元101在tn时间内，当其为被设置为本帧需要进行检测的行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]无效以及反馈地址线Sen[n]有效，其中反馈地址线Sen[n]有效维持若个干整数倍的行时间，在此反馈地址线Sen[n]有效期间内，补偿模块400通过反馈信号线FD Line检测此行像素单元101的电特性变化，并刷新和存储此行像素单元101的电特性变化信息；之后，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]有效以及反馈地址线Sen[n]无效，扫描线Scan[n]有效维持一个行时间，反馈地址线Sen[n]无效维持至下一帧，列数据驱动模块300通过数据线Data Line向此行像 素单元101写入一低电平，以关断此行像素单元101，使其不发光；任意一第n行像素单元101在tn时间内，当其为被设置为本帧不需要进行检测的行像素单元101时，栅极扫描驱动模块200使此行像素单元101的扫描线Scan[n]有效以及反馈地址线Sen[n]无效，都维持一个行时间，列数据驱动模块300通过数据线Data Line向此行像素单元101写入一低电平，以关断此行像素单元101，使其不发光，从而保持帧时间的一致性。其中，设置在每一帧的检测补偿帧中需要进行检测的行像素单元101的行数以及次序，以使在若干帧的检测补偿帧中，所有像素单元101都被进行了检测。另外连续若干帧的发光操作帧后面紧接着一帧检测补偿帧，构成一个操作周期。
本实施公开的方法，其使得行像素单元101的检测时间是可调节的。由于大面积高分辨率的显示系统，其包括的像素单元的行数是非常大数目的，因此，每行的时间非常小，如果把检测的时间局限于一行时间内，外部检测电路的检测精度比较低，会降低补偿效果；当像素单元101的检测时间是可调节的时，此时检测单元的检测时间可以增大为整数倍的行时间，从而提高外部检测电路的检测精度，提高显示器的亮度均匀度。经过若干操作周期后，面板上所有像素单元101的电特性变化都将被检查一遍，不会对大面积分辨率的显示系统本身的图像或视频显示造成影响，只会提高均匀度。因而，本实施公开的方法，尤其适合大面积高分辨率的显示系统。
本申请的像素矩阵的外围补偿系统及其方法、显示系统，实现了将第一显示信号和第二显示信号在像素单元内的加法，可以补偿像素单元因电特性变化导致的显示不准确的问题，例如，补偿驱动晶体管和有机发光二极管OLED的阈值电压偏移，解决显示系统中各像素单元内的驱动晶体管阈值电压不同而导致的显示不均匀问题，还可以改善因有机发光二极管OLED的发光效率退化造成的显示不均匀问题。本申请对第一显示信号进行了精确的伽马校正的同时，结构简单，第一数模转换模块和第二数模转换模块的位数也低，如果采用的模拟域相加的方式，原来的高压模拟加法器可以转换成中压或低压加法器。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请发明构思的前提下，还可以做出若干简单推演或替换。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (10)

  1. 一种像素矩阵的外围补偿系统，所述像素矩阵(100)包括N行M列像素单元(101)、N行扫描线和M列数据线，像素单元(101)和各自的扫描线和数据线分别连接，N和M均为正整数，其特征在于，包括：
    栅极扫描驱动模块(200)，用于通过扫描线向像素矩阵(100)发送扫描信号以在一帧内依次选通各行像素单元(101)；所述栅极扫描驱动模块(200)还通过N行反馈地址线分别与N行像素单元(101)连接，用于通过反馈地址线向像素矩阵(100)发送检测控制信号以在一帧内依次选通各行像素单元(101)；
    列数据驱动模块(300)，用于通过数据线向像素矩阵(100)发送第一显示信号，所述列数据驱动模块(300)包括第一数模转换模块(301)，所述第一数模转换模块(301)接收数字原始信号，输出经过伽马校正的为模拟信号的第一显示信号；
    补偿模块(400)，其通过M列反馈信号线分别与M列像素单元(101)相连，用于检测像素矩阵(100)的电特性变化以向像素矩阵(100)发送第二显示信号来对各像素单元(101)进行补偿。
  2. 如权利要求1所述的像素矩阵的外围补偿系统，其特征在于，所述补偿模块(400)包括第二数模转换模块(401)、检测模块(402)和存储模块(403)；所述检测模块(402)用于通过反馈信号线检测像素单元(101)的电特性变化，并将检测得到的电特性变化信息发送给所述存储模块(403)；所述存储模块(403)用于存储检测模块(402)发送的电特性变化信息，并根据各像素单元(101)的电特性变化向第二数模转换模块(401)发送数字补偿信号；所述第二数模转换模块(401)对接收的数字补偿信号进行数模转换后通过反馈信号线向像素单元(101)输出第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元(101)，使像素单元(101)正确显示图像或视频信息。
  3. 如权利要求1或2所述的像素矩阵的外围补偿系统，其特征在于，所述像素单元(101)包括驱动晶体管T1、第一开关晶体管T2、第二开关晶体管T3、存储电容Cs和有机发光二极管OLED；所述第一开关晶体管T2的第一极耦合于所述数据线，第一开关晶体管T2的第二极耦合于驱动晶体管T1的控制极，第一开关晶体管T2的控制极耦合于所述扫描线；所述第二开关晶体管T3的第一极耦合于所述反馈信号线，第二开关晶体管T3的第二极耦合于所述驱动晶体管T1的第二极，第二开关晶体管T3的控制极耦合于所述反馈地址线；所述驱动晶体管T1的第一极耦合于电源电压VDD，驱动晶体管T1的第二极耦合于所述有机发光二极管OLED的正极，有机发光二极管OLED的负极接地；所述存储电容 Cs耦合于驱动晶体管T1的控制极和第二极之间，用于接收第一显示信号和第二显示信号，以通过电容耦合的方式将两种信号相加后加载到所述驱动晶体管T1的控制极和第二极之间。
  4. 如权利要求1或2所述的像素矩阵的外围补偿系统，其特征在于，所述栅极扫描驱动模块(200)还通过N行截止信号线分别与N行像素单元(101)连接，用于当像素单元(101)被写入第一显示信号和第二显示信号过程中，通过所述截止信号线向像素单元(101)发送截止信号，所述截止信号用于防止第一显示信号和第二显示信号写入像素单元(101)过程中所述反馈信号线上有电流流过。
  5. 如权利要求4所述的像素矩阵的外围补偿系统，其特征在于，所述像素单元(101)包括驱动晶体管T1、第一开关晶体管T2、第二开关晶体管T3、第三开关晶体管T4、存储电容Cs和有机发光二极管OLED；
    具体地，所述第一开关晶体管T2的第一极耦合于所述数据线，第一开关晶体管T2的第二极耦合于驱动晶体管T1的控制极，第一开关晶体管T2的控制极耦合于所述扫描线；所述第二开关晶体管T3的第一极耦合于所述反馈信号线，第二开关晶体管T3的第二极耦合于所述有机发光二极管OLED的正极，第二开关晶体管T3的控制极耦合于所述反馈地址线；所述驱动晶体管T1的第一极耦合于电源电压VDD，驱动晶体管T1的第二极耦合于所述有机发光二极管OLED的正极，有机发光二极管OLED的负极接地；所述存储电容Cs耦合于第一开关晶体管T2的第二极和有机发光二极管OLED的阳极之间，用于接收第一显示信号和第二显示信号，以通过电容耦合的方式将两种信号相加后最终加载到所述驱动晶体管T1的控制极和第二极之间；
    其中，第一开关晶体管T2的第二极是通过所述第三开关晶体管T4耦合于驱动晶体管T1的控制极，具体地，第三开关晶体管T4的第一极与所述第一开关晶体管T2的第二极连接，第三开关晶体管T4的第二极与所述驱动晶体管T1的控制极连接，第三开关晶体管T4的控制极连接于所述截止信号线；或者，所述驱动晶体管T1的第一极是通过所述第三开关晶体管T4耦合于电源电压VDD，具体地，第三开关晶体管T4的第一极与所述电源电压VDD连接，第三开关晶体管T4的第二极与所述驱动晶体管T1的第一极连接，第三开关晶体管T4的控制极连接于所述截止信号线；或者，驱动晶体管T1的第二极是通过所述第三开关晶体管T4耦合于所述有机发光二极管OLED的正极，具体地，第三开关晶体管T4的第一极与所述驱动晶体管T1的第二极连接，第三开关晶体管T4的第二极与所述有机发光二极管OLED的正极连接，第三开关晶体管T4的控制极连接于所述截止信号线。
  6. 如权利要求3或5所述的像素矩阵的外围补偿系统，其特征在于：
    所述第一显示为数据图像信号电压，第二显示信号为驱动晶体管T1的阈值电压和补偿电压之和；或者，
    所述第一显示信号为驱动晶体管T1的阈值电压，第二显示信号为数据图像信号电压和补偿电压之和；或者，
    所述第一显示信号为驱动晶体管T1的阈值电压和数据图像信号电压之和，第二显示信号为补偿电压。
  7. 一种包括如权利要求1至6中任一项所述的像素矩阵的外围补偿系统的方法，所述像素矩阵(100)包括N行M列像素单元(101)、N行扫描驱动线和M列数据线，像素单元(101)和各自的扫描线和数据线分别连接，N和M均为正整数，其特征在于，所述方法包括以下操作：一帧时间由N个相等的行时间t1～tN组成，每行像素单元(101)依次进行下述操作：
    任意一第n行像素单元(101)在tn时间内，其中1≤n≤N：栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线有效，列数据驱动模块(300)和补偿模块(400)分别通过数据线和反馈信号线向此行像素单元(101)写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元(101)，使像素单元(101)正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线无效以及继续维持反馈地址线有效，补偿模块(400)通过反馈信号线检测此行像素单元(101)的电特性变化以在下帧该行像素单元(101)被选通时进行补偿；在tn+2时间内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线都无效，像素单元(101)被所述第一显示信号和第二显示信号驱动以发光。
  8. 一种包括如权利要求1至6中任一项所述的像素矩阵的外围补偿系统的方法，所述像素矩阵(100)包括N行M列像素单元(101)、N行扫描驱动线和M列数据线，像素单元(101)和各自的扫描线和数据线分别连接，N和M均为正整数，其特征在于，所述方法包括发光操作帧和检测补偿帧，其中一帧时间由N个相等的行时间t1～tN组成；
    在一帧的发光操作帧中，任意一第n行像素单元(101)在tn时间内，其中1≤n≤N：栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线有效，列数据驱动模块(300)和补偿模块(400)分别通过数据线和反馈信号线向此行像素单元(101)写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元(101)，使像素单元(101)正确显示图像或视频信息；在tn+1时间 内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线都无效，像素单元(101)被所述第一显示信号和第二显示信号驱动以发光；在一帧的检测补偿帧中，每行像素单元(101)或所有像素单元(101)中的若干行像素单元(101)依次进行下述操作，当在一帧的检测补偿帧中，只有所有像素单元(101)中的若干行像素单元(101)依次进行下述操作时，安排进行下述操作的行像素单元(101)次序，以使在若干帧的检测补偿帧中，所有像素单元(101)都进行了一遍下述操作：当轮到某一具体行像素单元(101)时，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线有效，维持一个行时间，在此行时间内，列数据驱动模块(300)和补偿模块(400)分别通过数据线和反馈信号线向此行像素单元(101)写入一固定电压信号和上一次在检测补偿帧中检测到的像素单元(101)的最新阈值电压信号；下一个行时间内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线无效和反馈地址线有效，维持一个行时间，在此行时间内，补偿模块(400)通过反馈信号线检测此行像素单元(101)的电特性变化，并刷新和存储此行像素单元(101)的电特性变化信息；下一个行时间内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线有效，维持一个行时间，在此行时间内，列数据驱动模块(300)和补偿模块(400)分别通过数据线和反馈信号线向此行像素单元(101)写入低电平信号以使此行像素单元(101)不发光；其中，在检测补偿帧之前，各行像素单元(101)先被依次写入低电平信号以不发光；其中，连续若干帧的发光操作帧后面紧接着一帧检测补偿帧；
    或者，
    在一帧的发光操作帧中，任意一第n行像素单元(101)在tn时间内，其中1≤n≤N：栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线有效，列数据驱动模块(300)和补偿模块(400)分别通过数据线和反馈信号线向此行像素单元(101)写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元(101)，使像素单元(101)正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线都无效，像素单元(101)被所述第一显示信号和第二显示信号驱动以发光；在一帧的检测补偿帧中，每行像素单元(101)依次进行下述操作：当轮到某一具体行像素单元(101)时，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线有效，维持一个行时间，在此行时间内，列数据驱动模块(300)和补偿模块(400)分别通过数据线和反馈信号线向此行像素单元(101)写入一固定电压信号和上一次在检测补偿帧中检测到的像素单元(101)的最新阈值电压信号；下一个 行时间内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线无效和反馈地址线有效，维持一个行时间，在此行时间内，补偿模块(400)通过反馈信号线检测此行像素单元(101)的电特性变化，并刷新和存储此行像素单元(101)的电特性变化信息；其中，所述检测补偿帧位于像素矩阵开机和/或关机的时候。
  9. 一种包括如权利要求1至6中任一项所述的像素矩阵的外围补偿系统的方法，所述像素矩阵(100)包括N行M列像素单元(101)、N行扫描驱动线和M列数据线，像素单元(101)和各自的扫描线和数据线分别连接，N和M均为正整数，其特征在于，所述方法包括发光帧和检测帧，其中一帧时间由N个相等的行时间t1～tN组成；
    在一帧的发光帧中，任意一第n行像素单元(101)在tn时间内，其中1≤n≤N：栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线有效，列数据驱动模块(300)和补偿模块(400)分别通过数据线和反馈信号线向此行像素单元(101)写入第一显示信号和第二显示信号，其中所述第一显示信号和第二显示信号共同驱动像素单元(101)，使像素单元(101)正确显示图像或视频信息；在tn+1时间内，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线和反馈地址线都无效，像素单元(101)被所述第一显示信号和第二显示信号驱动以发光；
    在一帧的检测帧中，每行像素单元(101)依次进行下述操作：任意一第n行像素单元(101)在tn时间内，当其为被设置为本帧需要进行检测的行像素单元(101)时，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线无效以及反馈地址线有效，其中反馈地址线有效维持若个干整数倍的行时间，在所述反馈地址线有效期间内，补偿模块(400)通过反馈信号线检测此行像素单元(101)的电特性变化，并刷新和存储此行像素单元(101)的电特性变化信息；之后，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线有效以及反馈地址线无效，扫描线有效维持一个行时间，反馈地址线无效维持到下一帧，列数据驱动模块(300)通过数据线向此行像素单元(101)写入一低电平，以关断此行像素单元(101)，使其不发光；任意一第n行像素单元(101)在tn时间内，当其为被设置为本帧不需要进行检测的行像素单元(101)时，栅极扫描驱动模块(200)使此行像素单元(101)的扫描线有效以及反馈地址线无效，都维持一个行时间，列数据驱动模块(300)通过数据线向此行像素单元(101)写入一低电平，以关断此行像素单元(101)，使其不发光；其中，设置在每一帧的检测补偿帧中需要进行检测的行像素单元(101)的行数以及次序，以使在若干帧的检测补偿帧中，所有像素单元(101) 都被进行了检测；其中，连续若干帧的发光操作帧后面紧接着一帧检测补偿帧。
  10. 一种显示系统，包括一像素矩阵，以及如权利要求1至6中任一项所述的像素矩阵的外围补偿系统。
PCT/CN2016/075658 2016-03-04 2016-03-04 一种像素矩阵的外围补偿系统及其方法、显示系统 WO2017147908A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/075658 WO2017147908A1 (zh) 2016-03-04 2016-03-04 一种像素矩阵的外围补偿系统及其方法、显示系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/075658 WO2017147908A1 (zh) 2016-03-04 2016-03-04 一种像素矩阵的外围补偿系统及其方法、显示系统

Publications (1)

Publication Number Publication Date
WO2017147908A1 true WO2017147908A1 (zh) 2017-09-08

Family

ID=59743387

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/075658 WO2017147908A1 (zh) 2016-03-04 2016-03-04 一种像素矩阵的外围补偿系统及其方法、显示系统

Country Status (1)

Country Link
WO (1) WO2017147908A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110264931A (zh) * 2019-07-10 2019-09-20 京东方科技集团股份有限公司 像素电路中晶体管的阈值电压漂移的检测方法及检测装置
CN111799291A (zh) * 2019-04-01 2020-10-20 美科米尚技术有限公司 发光元件显示器
CN113168812A (zh) * 2018-12-14 2021-07-23 深圳市柔宇科技股份有限公司 显示组件和电子装置
CN114333698A (zh) * 2021-12-30 2022-04-12 武汉天马微电子有限公司 显示面板和显示装置
CN114822406A (zh) * 2022-05-20 2022-07-29 昆山国显光电有限公司 显示装置及其驱动方法
CN114842804A (zh) * 2022-05-09 2022-08-02 北京奕斯伟计算技术有限公司 像素驱动电路、显示面板和电子设备
CN115206260A (zh) * 2022-07-28 2022-10-18 福州京东方光电科技有限公司 驱动电路、显示装置和充电补偿方法
CN115206260B (zh) * 2022-07-28 2024-04-16 福州京东方光电科技有限公司 驱动电路、显示装置和充电补偿方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578411A (zh) * 2012-07-19 2014-02-12 乐金显示有限公司 用于感测像素电流的显示装置及其像素电流感测方法
CN103854603A (zh) * 2012-12-03 2014-06-11 乐金显示有限公司 有机发光显示装置及其操作方法
US20140347332A1 (en) * 2013-05-22 2014-11-27 Samsung Display Co., Ltd. Organic light emitting display and method for driving the same
US20140362124A1 (en) * 2013-06-07 2014-12-11 Samsung Display Co., Ltd. Organic light emitting display device
CN105023539A (zh) * 2015-07-10 2015-11-04 北京大学深圳研究生院 一种像素矩阵的外围补偿系统、方法和显示系统
CN105206224A (zh) * 2015-09-24 2015-12-30 北京大学深圳研究生院 一种具有反馈通道的显示系统
CN105702206A (zh) * 2016-03-04 2016-06-22 北京大学深圳研究生院 一种像素矩阵的外围补偿系统及其方法、显示系统

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578411A (zh) * 2012-07-19 2014-02-12 乐金显示有限公司 用于感测像素电流的显示装置及其像素电流感测方法
CN103854603A (zh) * 2012-12-03 2014-06-11 乐金显示有限公司 有机发光显示装置及其操作方法
US20140347332A1 (en) * 2013-05-22 2014-11-27 Samsung Display Co., Ltd. Organic light emitting display and method for driving the same
US20140362124A1 (en) * 2013-06-07 2014-12-11 Samsung Display Co., Ltd. Organic light emitting display device
CN105023539A (zh) * 2015-07-10 2015-11-04 北京大学深圳研究生院 一种像素矩阵的外围补偿系统、方法和显示系统
CN105206224A (zh) * 2015-09-24 2015-12-30 北京大学深圳研究生院 一种具有反馈通道的显示系统
CN105702206A (zh) * 2016-03-04 2016-06-22 北京大学深圳研究生院 一种像素矩阵的外围补偿系统及其方法、显示系统

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113168812A (zh) * 2018-12-14 2021-07-23 深圳市柔宇科技股份有限公司 显示组件和电子装置
CN111799291A (zh) * 2019-04-01 2020-10-20 美科米尚技术有限公司 发光元件显示器
CN111799291B (zh) * 2019-04-01 2023-11-10 美科米尚技术有限公司 发光元件显示器
CN110264931A (zh) * 2019-07-10 2019-09-20 京东方科技集团股份有限公司 像素电路中晶体管的阈值电压漂移的检测方法及检测装置
CN110264931B (zh) * 2019-07-10 2023-07-18 京东方科技集团股份有限公司 像素电路中晶体管的阈值电压漂移的检测方法及检测装置
CN114333698B (zh) * 2021-12-30 2023-02-28 武汉天马微电子有限公司 显示面板和显示装置
CN114333698A (zh) * 2021-12-30 2022-04-12 武汉天马微电子有限公司 显示面板和显示装置
CN114842804B (zh) * 2022-05-09 2023-09-12 北京奕斯伟计算技术股份有限公司 像素驱动电路、显示面板和电子设备
CN114842804A (zh) * 2022-05-09 2022-08-02 北京奕斯伟计算技术有限公司 像素驱动电路、显示面板和电子设备
CN114822406A (zh) * 2022-05-20 2022-07-29 昆山国显光电有限公司 显示装置及其驱动方法
CN114822406B (zh) * 2022-05-20 2023-12-05 昆山国显光电有限公司 显示装置及其驱动方法
CN115206260A (zh) * 2022-07-28 2022-10-18 福州京东方光电科技有限公司 驱动电路、显示装置和充电补偿方法
CN115206260B (zh) * 2022-07-28 2024-04-16 福州京东方光电科技有限公司 驱动电路、显示装置和充电补偿方法

Similar Documents

Publication Publication Date Title
US10692434B2 (en) Pixel circuit, display panel, display device and driving method
US11881164B2 (en) Pixel circuit and driving method thereof, and display panel
CN105702206B (zh) 一种像素矩阵的外围补偿系统及其方法、显示系统
US10140923B2 (en) Pixel driving system of AMOLED having initialization signal of alternating high and low levels and method for driving pixel of AMOLED having initialization signal of alternating high and low levels
US10679554B2 (en) Pixel circuit with compensation for drift of threshold voltage of OLED, driving method thereof, and display device
WO2017147908A1 (zh) 一种像素矩阵的外围补偿系统及其方法、显示系统
US11024229B2 (en) Display panel and detection method thereof, and display device
US9430968B2 (en) Display device and drive method for same
US11468835B2 (en) Pixel circuit and driving method thereof, and display device
US10504436B2 (en) Pixel driving circuits, pixel driving methods and display devices
JP4915195B2 (ja) 表示装置
US10535299B2 (en) Pixel circuit, array substrate, display device and pixel driving method
WO2019037300A1 (zh) Amoled像素驱动电路
WO2015180419A1 (zh) 像素电路及其驱动方法和一种显示装置
US11348526B2 (en) Pixel mixed compensation circuit and pixel mixed compensation method
WO2016150372A1 (zh) 像素电路及其驱动方法和一种显示装置
US11348518B2 (en) Method for driving display panel and display device
US10650740B2 (en) Pixel driving circuit and display device
CN108777131B (zh) Amoled像素驱动电路及驱动方法
US10748489B2 (en) Pixel driving circuit and driving method thereof, and display apparatus
CN107424564B (zh) 像素装置、用于像素装置的驱动方法和显示设备
JP6175718B2 (ja) 駆動方法および表示装置
US20200234652A1 (en) Pixel circuit and driving method thereof, and display apparatus
US10726771B2 (en) Pixel circuit, driving method and display device
JP4590831B2 (ja) 表示装置、および画素回路の駆動方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16892099

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16892099

Country of ref document: EP

Kind code of ref document: A1