WO2017140138A1

WO2017140138A1 - Ultrathin embedded packaging method for chip and package

Info

Publication number: WO2017140138A1
Application number: PCT/CN2016/106615
Authority: WO
Inventors: 高洪涛; 陆美华; 刘玉宝; 汤正兴; 栾旭峰
Original assignee: 上海伊诺尔信息技术有限公司
Priority date: 2016-02-17
Filing date: 2016-11-21
Publication date: 2017-08-24
Also published as: CN105632943B; CN105632943A

Abstract

Provided are an ultrathin embedded packaging method for a chip and a package. The packaging method comprises the following steps: providing a substrate; forming on the front side of the substrate at least one chip mounting window and at least one pin connection window running through the substrate; affixing an electrically-conductive carrier tape to a rear side of the substrate, where a carrier tape functional solder pad is provided on the surface of the electrically-conductive carrier tape facing the substrate, and a carrier tape solder pad electrically conducted with the carrier tape functional solder pad is provided on another surface of the electrically-conductive carrier tape, and the carrier tape functional solder pad is exposed through the pin connection window; affixing a chip into the chip mounting window; electrically connecting a solder point on the surface of the chip to the carrier tape functional solder pad through the pin connection window; and employing a cover plate to cover the surface of the substrate having the chip, thus forming a package. The advantages of the present invention are the implementation of ultrathin packaging, increased product reliability, a simplified process, and improved protection provided for the chip.

Description

Chip ultra-thin embedded packaging method and package

Technical field

The present invention relates to the field of chip packaging, and in particular to an ultra-thin embedded packaging method and a package of a chip.

Background technique

With the continuous advancement of integrated circuit packaging technology, the integration of integrated circuits is increasing, the functions are becoming more and more abundant, and the requirements for product application fields are becoming more and more demanding. This requires integrated circuit packaging enterprises to develop new types. Package form to match new needs.

For example, in the field of smart card packaging, the demand for smart cards in domestic and foreign markets is very large. At present, the smart card industry is developing towards a technological innovation route, new technologies are emerging, new manufacturing technologies are also increasing, and many old manufacturing Technology is also constantly being improved and enhanced, so that the requirements for the function and performance of smart cards are inevitable.

The traditional smart card packaging method (ie, the manufacturing method) is: first, the chip is mounted on the carrier tape of the smart card by using a chip mounting device, and then the function pad of the chip and the pad of the carrier tape are used by using a wire bonding device. After the electrical connection is made, the smart card module with the wire bonding is glued or molded, and then the packaged smart card module is punched. Finally, the smart card module is formed into a card form by using a card making device. However, this packaging method has many disadvantages: high production cost, high material cost, complicated production process, poor product reliability, low production efficiency, and chip damage.

With the development of the Internet of Things, there is an increasing need for smart card packaging modules to be surface mountable. One solution is to use traditional semiconductor packages, such as flat four-sided leadless packages, or chip size packages; but this type of package It is difficult to implement plug-in or current card-making methods. How to develop a package that can adapt to current plug-in applications or card-making applications, as well as surface mount, has become a technical problem that needs to be solved in the technical field.

Summary of the invention

The technical problem to be solved by the present invention is to provide an ultra-thin embedded packaging method and a package body of the chip, which can realize ultra-thin packaging, improve product reliability, simple process and provide better protection for the chip, and The packaging method and package can be adapted to current plug-in applications or card-making applications, as well as surface mount.

In order to solve the above problems, the present invention provides an ultra-thin embedded packaging method for a chip, comprising the steps of: providing a substrate; forming at least one chip mounting window and at least one pin extending through the substrate on a front surface of the substrate; a connection window; a conductive carrier tape is mounted on a back surface of the substrate, the conductive carrier tape is provided with a carrier function pad toward a surface of the substrate, and the other surface of the conductive carrier tape is provided with a Carrying a carrier pad with a functional pad electrically conductive, the carrier function pad being exposed from the pin connection window; mounting a chip in the chip mounting window; connecting through the pin The window electrically connects the solder joint of the surface of the chip with the carrier function pad; covering the substrate with a cover plate to form a package body.

Further, a chip mounting window and the pin connection window are formed by a mechanical physical method or a chemical etching method.

Further, the material of the base body and the cover plate is a dielectric material.

Further, the conductive carrier tape is attached to the back side of the substrate by a press-fitting method.

Further, the chip mounting window extends through the substrate.

Further, the chip is bonded to the surface of the substrate by the conductive or non-conductive glue on the conductive carrier tape.

Further, solder joints and carrier tape functional pads on the surface of the chip are electrically connected through the pin connection window by electroplating or electroless plating.

Further, the chip is electrically connected through the pin connection window by a method of printing a conductive paste Surface solder joints and carrier tape functional pads.

Further, the chip is mounted in the chip mounting window by using a conductive adhesive or a non-conductive adhesive, and is dried, and the drying temperature is less than 200 degrees Celsius.

Further, the cover plate is pressed against the surface of the substrate, and the pressing temperature is less than 200 degrees Celsius.

Further, in the step of providing the substrate, the substrate is placed in a roll shape and gradually spreads as the subsequent steps proceed.

The present invention also provides a package packaged by the above package method, comprising: a substrate; the front surface of the substrate is formed with at least one chip mounting window and at least one pin connection window penetrating the substrate; a conductive carrier tape The conductive carrier tape is mounted on the back surface of the substrate, and the conductive carrier tape is provided with a carrier function pad toward a surface of the substrate, and the other surface of the conductive carrier tape is disposed with the carrier a carrier tape with a functional pad electrically conductive, the carrier tape function pad being exposed from the pin connection window; a chip mounted in the chip mounting window, a solder joint on the chip surface Electrically connecting to the carrier function pad; a cover plate covering the substrate having a surface of the chip to form a package.

Further, the chip mounting window extends through the substrate, and the chip is mounted on a surface of the conductive carrier tape facing the substrate.

The invention has the advantages that the ultra-thin package is realized by a simple process, the package thickness is less than 300 micrometers, the product reliability is improved, and the package structure can better protect the chip and avoid damage of the chip, and the package method and package The body can be adapted to current plug-in applications or card-making applications, as well as surface mount.

DRAWINGS

1 is a schematic diagram showing the steps of an ultra-thin embedded packaging method of a chip of the present invention;

2A-2L are process flow diagrams of an ultra-thin embedded packaging method of the chip of the present invention.

Figure 3 is an initial state of the substrate of the present invention.

detailed description

The ultra-thin embedded packaging method and the specific implementation manner of the package provided by the present invention will be described in detail below with reference to the accompanying drawings.

1 is a schematic diagram of the steps of the ultra-thin embedded packaging method of the chip of the present invention. Referring to FIG. 1, the packaging method of the present invention includes the following steps: Step S10, providing a substrate; Step S11, forming at least one chip mounting window on the substrate And at least one pin connection window penetrating the substrate; in step S12, a conductive carrier tape is mounted on a surface of the substrate, and the conductive carrier tape is provided with a carrier function pad toward a surface of the substrate. The other surface of the conductive carrier tape is provided with a carrier tape electrically conductively connected to the carrier tape, and the carrier function pad is exposed from the pin connection window; step S13; a chip is mounted in the chip mounting window; in step S14, a solder joint and a carrier function pad are electrically connected to the surface of the chip through the pin connection window; and step S15, covering the substrate with a cover plate and having a chip The surface forms a package.

Referring to step S10, FIG. 2A and FIG. 2B, a substrate 200 is provided. The substrate 200 can be made of a dielectric material such as FR4. Referring to FIG. 3, the base body 200 is placed in a roll shape, for example, wound on a reel 300, and gradually unfolds and performs subsequent operations as the subsequent steps are performed. The area indicated by the dotted line in the figure is the area that has been subjected to subsequent operations. .

Referring to step S11, FIG. 2C and FIG. 2D, at least one chip mounting window 210 and at least one pin connection window 220 extending through the substrate are formed on the front surface of the base 200. In the embodiment, a chip mounting window 210 and six pin connection windows 220 extending through the substrate 200 are formed on the substrate 200. Further, the chip mounting window 210 may penetrate the base body 200 or may not penetrate the base body 200. In the specific embodiment, the chip mounting window 210 is The base body 200 is worn.

The ultra-thin embedded packaging method of the chip of the present invention forms a chip mounting window 210 and the pin connection window 220 by a physical method or a chemical etching method, and the physical method includes mechanical drilling, laser drilling, etc. No restrictions are imposed.

Referring to step S12, FIG. 2E and FIG. 2F, a conductive carrier tape 230 is mounted on the back surface of the substrate 200. The conductive carrier tape 230 is provided with a carrier function pad 240 toward a surface of the substrate. The other surface of the carrier tape 230 is provided with a carrier tape pad 250 that is electrically conductive to the carrier tape function pad 240, and the carrier tape function pad 240 is exposed from the pin connection window 220.

The carrier tape function pad 240 is electrically connected to a solder joint on the surface of the chip 260 in a subsequent process. After the package body is formed, the carrier tape pad 250 is electrically connected as a contact surface to an external component. In this embodiment, the conductive carrier tape 230 is attached to the back side of the substrate 200 by a press-fit method. The conductive carrier tape 230 may be made of a metal material such as copper, nickel, or gold.

Referring to step S13, FIG. 2G and FIG. 2H, the chip 260 is mounted in the chip mounting window 210. If the chip mounting window 210 does not penetrate the substrate 200, the chip 260 is mounted on the bottom of the chip mounting window 210. If the chip mounting window 210 penetrates the substrate 200, the chip 260 is mounted on the surface of the conductive carrier tape 230 facing the substrate 200.

The chip 260 is bonded to the bottom of the chip mounting window 210 or the conductive carrier tape 230 toward the surface of the substrate 200 by a conductive or non-conductive glue. The non-conductive glue may be a mixture of an epoxy resin or the like and a filler such as silica; the conductive paste is a mixture of a metal such as tin-lead or the like and a flux. Applying a conductive or non-conductive paste to the bottom of the chip mounting window 210 or the conductive carrier tape 230 toward the surface of the substrate 200, placing the chip 260 on a conductive or non-conductive paste, below 200 The Celsius is dried so that the chip 260 is fixed to the bottom of the chip mounting window 210 or the conductive carrier tape 230 toward the surface of the substrate 200 by a conductive or non-conductive glue.

Referring to step S14, FIG. 2I and FIG. 2J, solder joints (not shown in the drawing) electrically connecting the surface of the chip 260 and the carrier function pad 240 are electrically connected through the pin connection window 220, for example, to form a conductive Article 290. The electrical connection may be performed by electroplating or electroless plating, and the solder joints and the carrier function pads 240 on the surface of the chip 260 are electrically connected through the pin connection window 220, and the connection material is copper or nickel or Gold or the like; or a method of printing a conductive paste, the solder joints on the surface of the chip 260 and the carrier tape function pads 240 are electrically connected through the pin connection window 220, and the connection material is silver or gold.

Referring to step S15, FIG. 2K and FIG. 2L, the substrate 200 is covered with a cover plate 270 to have a surface of the chip 260 to form a package 280. The material of the cover plate 270 is a dielectric material such as FR4. The cover plate 270 can be pressed against the surface of the base body 200 at a press temperature of less than 200 degrees Celsius.

The substrate 200 and the cover plate 270 are both made of a dielectric material, which can protect the chip well, block electrical short circuit, and have a high glass transition temperature, and can withstand the surface mount process. .

After the package body 280 is formed, the package body 280 is cut as needed to form a final product.

Referring to FIG. 2K and FIG. 2L, the package packaged by the above packaging method comprises: a substrate 200 having a front surface formed with at least one chip mounting window 210 and at least one pin connection window extending through the substrate 220. a conductive carrier tape 230 is mounted on the back surface of the substrate 200. The conductive carrier tape 230 is provided with a carrier function pad 240 toward a surface of the substrate 200. The conductive carrier tape The other surface of the 230 is provided with a carrier pad 250 that is electrically conductive to the carrier function pad 240, and the carrier function pad 240 is exposed from the pin connection window 220. A chip 260 is mounted in the chip mounting window 210. The solder joint on the surface of the chip 260 and the carrier function pad 240 can be electrically connected through a conductive strip 290. A cover plate 270 covers the surface of the substrate 200 having the chip 260 to form a package 280. Further, the chip mounting window The chip 260 is inserted through the substrate 200, and the chip 260 is mounted on the surface of the conductive carrier tape 230 facing the substrate 200.

The above description is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. These improvements and retouchings should also be considered. It is the scope of protection of the present invention.

Claims

An ultra-thin embedded packaging method for a chip, comprising the following steps:

Providing a substrate, the substrate being placed in a roll shape, and gradually expanding as the subsequent steps are performed;

Forming at least one chip mounting window and at least one pin connection window penetrating the substrate on a front surface of the substrate, the chip mounting window penetrating the substrate;

Mounting a conductive carrier tape on a back surface of the substrate, the conductive carrier tape is mounted on the back surface of the substrate by pressing, and the conductive carrier tape is provided with a carrier tape functional soldering on a surface of the substrate. The other surface of the conductive carrier tape is provided with a carrier tape pad electrically connected to the carrier tape function pad, and the tape carrier function pad is exposed from the pin connection window;

Mounting a chip in the chip mounting window, the chip is mounted in the chip mounting window by using a conductive adhesive or a non-conductive adhesive, and drying, the drying temperature is less than 200 degrees Celsius;

Electroplating or electroless plating or printing of a conductive paste, electrically connecting the solder joints of the chip surface and the carrier function pads through the pin connection window;

Covering the substrate with a cover plate to form a package body, the cover plate is pressed against the surface of the substrate, and the pressing temperature is less than 200 degrees Celsius;
An ultra-thin embedded packaging method for a chip, comprising the following steps:

Providing a substrate,

Forming at least one chip mounting window and at least one pin connection window penetrating the substrate on a front surface of the substrate;

Mounting a conductive carrier tape on a back surface of the substrate, the conductive carrier tape is provided with a carrier function pad toward a surface of the substrate, and another surface of the conductive carrier tape is disposed with the carrier tape a carrier pad electrically conductively conductive, the carrier function pad being exposed from the pin connection window;

Mounting a chip in the chip mounting window;

Electrically connecting the solder joints of the surface of the chip and the carrier function pads through the pin connection window;

Covering the substrate with a cover has a surface of the chip to form a package.
The ultra-thin embedded packaging method of a chip according to claim 2, wherein the chip mounting window and the pin connection window are formed by a physical method or a chemical etching method.
The ultra-thin embedded packaging method of the chip according to claim 2, wherein the material of the substrate and the cover is a dielectric material.
The ultra-thin embedded packaging method of a chip according to claim 2, wherein the conductive carrier tape is attached to the back surface of the substrate by a press-fitting method.
The ultra-thin embedded packaging method of a chip according to claim 2, wherein the chip mounting window extends through the substrate.
The ultra-thin embedded packaging method of a chip according to claim 6, wherein the chip is bonded to the surface of the substrate by the conductive or non-conductive glue.
The ultra-thin embedded packaging method of a chip according to claim 2, wherein the solder joints of the chip surface and the carrier tape functional pads are electrically connected through the pin connection window by electroplating or electroless plating.
The ultra-thin embedded packaging method of a chip according to claim 2, wherein a solder joint and a carrier function pad of the surface of the chip are electrically connected through the pin connection window by a method of printing a conductive paste.
The ultra-thin embedded packaging method of the chip according to claim 2, wherein the chip is mounted in the chip mounting window by using a conductive adhesive or a non-conductive adhesive, and the drying temperature is less than 200 degrees Celsius.
The ultra-thin embedded packaging method of a chip according to claim 2, wherein the cover plate is pressed against the surface of the substrate, and the pressing temperature is less than 200 degrees Celsius.
The ultra-thin embedded packaging method of the chip according to claim 2, wherein the substrate step is provided In the step, the substrate is placed in a roll shape and gradually spreads as the subsequent steps proceed.
A package, comprising:

a substrate having a front surface formed with at least one chip mounting window and at least one pin connection window extending through the substrate;

a conductive carrier tape, the conductive carrier tape is mounted on a back surface of the substrate, the conductive carrier tape is provided with a carrier function pad toward a surface of the substrate, and the other surface of the conductive carrier tape is disposed a carrier pad electrically conductive to the carrier function pad, the carrier function pad being exposed from the pin connection window;

a chip mounted in the chip mounting window, the solder joint on the surface of the chip is electrically connected to the carrier function pad;

A cover plate covering the substrate has a surface of the chip to form a package.
The package of claim 13 wherein said chip mounting window extends through said substrate, said chip being mounted on said conductive carrier tape toward a surface of said substrate.