WO2017140005A1 - 阵列基板、液晶显示装置及液晶显示装置的驱动方法 - Google Patents

阵列基板、液晶显示装置及液晶显示装置的驱动方法 Download PDF

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WO2017140005A1
WO2017140005A1 PCT/CN2016/075477 CN2016075477W WO2017140005A1 WO 2017140005 A1 WO2017140005 A1 WO 2017140005A1 CN 2016075477 W CN2016075477 W CN 2016075477W WO 2017140005 A1 WO2017140005 A1 WO 2017140005A1
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Prior art keywords
thin film
film transistor
line
common electrode
scan
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English (en)
French (fr)
Inventor
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/033,639 priority Critical patent/US20180046000A1/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal vertical alignment agent, a liquid crystal display element, and a method for preparing a liquid crystal display element.
  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate, a liquid crystal display device having the array substrate, and a driving method of the liquid crystal display device.
  • the liquid crystal display device of the In-Plane Switching (IPS) mode is a liquid crystal display device in which liquid crystal molecules are responsive in the in-plane direction of the array substrate by an electric field substantially parallel to the surface of the array substrate. Due to its excellent viewing angle characteristics, it is used in display applications in various fields.
  • a parallel electric field generated by the edge of the pixel electrode or the common electrode and a longitudinal electric field generated between the pixel electrode and the common electrode form a multi-dimensional electric field, so that the pixel electrode or the common electrode in the liquid crystal cell and the pixel electrode Or all of the aligned liquid crystal molecules directly above the common electrode can generate a rotation conversion, thereby improving the working efficiency of the plane-oriented liquid crystal and increasing the light transmission efficiency.
  • the pixel electrode or the common electrode is usually disposed on the array substrate, and therefore, the quality of the array substrate is the key to the product yield of the liquid crystal display device.
  • a plurality of scan lines and a plurality of data lines are generally disposed on the array substrate, and the plurality of scan lines intersect the plurality of data lines vertically and horizontally to form a plurality of pixel units, and each of the pixel units is provided with a thin film transistor.
  • the gate of the thin film transistor is connected to the scan line, the source is connected to the data line, and the drain and the image are The electrodes are connected.
  • the technical problem to be solved by the present invention is to provide an array substrate which can make the change of the voltage of the common electrode coincide with the change of the voltage of the pixel electrode when the gate is closed, thereby preventing the liquid crystal display device from being displayed during the display process.
  • There are undesirable phenomena such as afterimages and flickering.
  • the present invention also provides a liquid crystal display device and a method of driving the liquid crystal display device.
  • the present invention provides an array substrate including a substrate and two scan lines, data lines, and common electrode lines disposed on the substrate, the scan lines and the data lines, and the The common electrode lines are disposed in an insulated manner and form a pixel unit, and the pixel unit includes a pixel electrode, a common electrode, a first thin film transistor, and a second thin film transistor, a gate of the first thin film transistor and the second a gate of the thin film transistor is connected to the scan line, a source of the first thin film transistor is connected to the data line, a drain of the first thin film transistor is connected to the pixel electrode, and the second film A source of the transistor is connected to the common electrode line, a drain of the second thin film transistor is connected to the common electrode, and the second thin film transistor is the same as the first thin film transistor.
  • the gates of the first thin film transistors and the gates of the second thin film transistors in the pixel unit are connected to different and adjacent two scan lines.
  • the gate of the first thin film transistor and the gate of the second thin film transistor in the pixel unit are connected to the same scan line.
  • the array substrate further includes at least one scan line, and the data line and the common electrode line enclosing the pixel unit with the at least one scan line.
  • the data line and the common electrode line are parallel and spaced apart from each other, and the scan lines are parallel to each other, and each of the pixel units is formed by two adjacent scan lines and one of the data lines and one of the The common electrode lines are formed by crossing each other in an insulated manner.
  • the present invention also provides a liquid crystal display device including data The drive substrate, the scan driver, and the array substrate according to any one of the preceding claims, wherein the data driver is connected to the data line of the array substrate, the scan driver is connected to the scan line, and the data driver is used for
  • the pixel electrode provides a gray scale voltage
  • the scan driver is configured to provide a scan signal to turn on or off a gate of the first thin film transistor and a gate of the second thin film transistor.
  • the liquid crystal display device further includes a common voltage generating circuit for supplying a common voltage to the common electrode.
  • the present invention provides a driving method of a liquid crystal display device, including:
  • the gray scale voltage charging a corresponding pixel electrode via a source and a drain of the first thin film transistor
  • the scan signal activating a gate of the second thin film transistor; providing a common voltage to a common corresponding to the scan line of the row
  • An electrode line that charges a corresponding common electrode via a source and a drain of the second thin film transistor; the second thin film transistor is the same as the first thin film transistor.
  • the present invention provides a driving method of another liquid crystal display device, including the steps of:
  • the gray scale voltage charging a corresponding pixel electrode via a source and a drain of the first thin film transistor
  • a common voltage is supplied to the common electrode line corresponding to the row of scan lines, and the common voltage is charged to the corresponding common electrode via the source and the drain of the second thin film transistor.
  • a gate of the first thin film transistor and a gate of the second thin film transistor are connected to a scan line, a source of the first thin film transistor is connected to the data line, a drain of the first thin film transistor is connected to the pixel electrode, and a source of the second thin film transistor is connected to the a common electrode line, a drain of the second thin film transistor is connected to the common electrode, and therefore, the pixel electrode is charged via the first thin film transistor, and the common electrode is charged via a second thin film transistor;
  • the second thin film transistor is the same as the first thin film transistor, a parasitic capacitance existing between a drain and a gate of the second thin film transistor connected to the common electrode and the pixel electrode
  • the parasitic capacitance existing between the drain and the gate of the connected first thin film transistor is identical, so that the change of the common voltage of the common electrode coincides with the change of the gray scale voltage of the pixel electrode at the moment when the gate is closed, thereby preventing
  • the liquid crystal display device has a defect such as afterimage or flickering during display.
  • FIG. 1 is a schematic structural view of an array substrate in an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of the array substrate in the first embodiment of the present invention corresponding to the portion I in FIG. 1;
  • FIG. 3 is a schematic structural view of an array substrate in accordance with a portion I of FIG. 1 in a second embodiment of the present invention.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined.
  • the ground connection, or the integral connection may be a mechanical connection; it may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • the array substrate includes a substrate and two scan lines, data lines and common electrode lines disposed on the substrate, the scan lines and the data lines and the common electrode lines are An insulating manner is disposed in a cross manner, and a pixel unit is formed.
  • the pixel unit includes a pixel electrode, a common electrode, a first thin film transistor, and a second thin film transistor, and a gate of the first thin film transistor and a gate of the second thin film transistor a pole is connected to the scan line, a source of the first thin film transistor is connected to the data line, a drain of the first thin film transistor is connected to the pixel electrode, and a source of the second thin film transistor Connected to the common electrode line, a drain of the second thin film transistor is connected to the common electrode, and the second thin film transistor is the same as the first thin film transistor.
  • the array substrate further includes at least one scan line, and the data line and the common electrode line enclosing the pixel unit with the at least one scan line, that is, the array substrate includes a substrate and a setting a plurality of scan lines, a plurality of data lines, and a plurality of common electrode lines on the substrate, wherein the scan lines are interdigitated with the data lines and the common electrode lines in an insulating manner to form a plurality of pixels unit.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • 2 is a schematic structural view of the array substrate in the first embodiment of the present invention corresponding to the portion I in FIG.
  • the array substrate includes a substrate 100 and a plurality of scan lines 200, a plurality of data lines 300, and a plurality of common electrode lines 400 disposed on the substrate 100.
  • the plurality of scan lines 200 are parallel to each other, and the data lines 300 are disposed in the same direction as the common electrode line 400.
  • the data lines 300 and the common electrode line 400 are mutually parallel.
  • the scanning line 200 and the data line 300 and the common electrode line 400 are vertically and horizontally intersected to form a plurality of pixel units 700.
  • each of the pixel units 700 is surrounded by two adjacent scan lines 200 and one of the data lines 300 and one of the common electrode lines 400 in an insulating manner, that is, adjacent two
  • the scan line 200 spans one of the data lines 300 and one of the common electrode lines 400, and the closed quadrilateral formed is the pixel unit 700.
  • a pixel electrode 500, a common electrode 600, a first thin film transistor 710, and a second thin film transistor 720 are disposed in each of the pixel units 700.
  • the first thin film transistor 710 includes a gate 711, a source 712 and a drain 713.
  • the second thin film transistor 720 includes a gate 721, a source 722 and a drain 723.
  • the gate 711 of the first thin film transistor 710 and the gate 721 of the second thin film transistor 720 are both connected to the scan line 200 in the same pixel unit 700.
  • the source 712 of the first thin film transistor 710 is connected to the data line 300, and the drain 713 of the first thin film transistor 710 is connected to the pixel electrode 500.
  • the source 722 of the second thin film transistor 720 is connected to the common electrode line 400, and the drain 723 of the second thin film transistor 720 is connected to the common electrode 600.
  • the second thin film transistor 720 is the same as the first thin film transistor 710. Specifically, the second thin film transistor 720 has the same structure as the first thin film transistor 710.
  • the common electrode 600 includes a plurality of common sub-electrodes (not numbered in the figure), and the pixel electrode 500 includes a plurality of pixel sub-electrodes (not numbered in the drawing), and each of the common sub-electrodes corresponds to one pixel sub-electrode, that is, The correspondence between the common sub-electrode and the pixel sub-electrode is one-to-one.
  • the extending direction of the common sub-electrode may be parallel to the extending direction of the pixel sub-electrode.
  • An electric field is formed between the common electrode 600 and the pixel electrode 500. .
  • the gate 711 of the first thin film transistor 710 and the gate 721 of the second thin film transistor 720 in each of the pixel units 700 are connected to different and adjacent two Scan line 200.
  • the pixel unit 700 is formed in one pixel unit 700 formed by the intersection of the nth scanning line 200, the n+1th scanning line 200, the nth data line 300, and the nth common electrode line 400.
  • the gate 711 of the first thin film transistor 710 is connected to the nth scan line 200
  • the gate 721 of the second thin film transistor 720 is connected to the n+1th scan line 200
  • the source 712 of the first thin film transistor 710 Connected to the nth data line 300
  • the source 722 of the second thin film transistor 720 is connected to the nth common electrode line 400, where n is a natural number.
  • a scan driver (not shown) of the liquid crystal display device outputs a scan signal, and when the scan signal is transmitted to the gate 711 of the first thin film transistor 710 via the nth scan line 200, the nth The gate 711 of the first thin film transistor 710 connected to the scan line 200 is turned on. At this time, the nth data line 300 transmits the gray scale voltage outputted by the data driver (not shown) of the liquid crystal display device. Going to the source 712 of the first thin film transistor 710, and transmitting the gray scale voltage to the pixel electrode 500 connected to the drain 713 via the source 712 and the drain 713 of the first thin film transistor 710, The pixel electrode 500 is charged.
  • the scan driver of the liquid crystal display device outputs a scan signal for the n+1th scan line 200, and the scan signal is connected to the n+1th scan line 200 via the n+1th scan line 200.
  • the gate 721 of the second thin film transistor 720 is turned on.
  • the common electrode line 400 connected to the source of the second thin film transistor 720 passes the common voltage via the source 722 and the drain 723 of the second thin film transistor 720. It is transmitted to the common electrode 600 to charge the common electrode 600.
  • a voltage on the pixel electrode 500 forms a difference from a voltage on the common electrode 600, thereby forming an electric field that causes the liquid crystal to respond, so that the liquid crystal display device displays a picture.
  • the gate 711 of the first thin film transistor 710 When the gate 711 of the first thin film transistor 710 is turned off, the pixel connected to the drain 713 is present due to the parasitic capacitance Cst1 existing between the gate 711 and the drain 713 of the first thin film transistor 710.
  • the voltage on electrode 500 is pulled down by ⁇ Vp1.
  • the gate 721 of the second thin film transistor 720 is turned off, and the common electrode connected to the drain 723 is connected due to the parasitic capacitance Cst2 existing between the gate 721 and the drain 723 of the second thin film transistor 720.
  • the voltage on electrode 600 is pulled down by ⁇ Vp2.
  • the parasitic capacitance between the gate 711 and the drain 713 of the first thin film transistor 710 is Cst1 is equal to the parasitic capacitance Cst2 between the gate 721 and the drain 723 of the second thin film transistor 720, so that the voltage pull-down value ⁇ Vp2 on the common electrode 600 is equal to the voltage pull-down value on the pixel electrode 500.
  • ⁇ Vp1 thereby avoiding the afterimage caused by the voltage pull-down value ⁇ Vp2 on the common electrode 600 being different from the voltage pull-down value ⁇ Vp1 on the pixel electrode 500 Bad phenomenon such as flickering.
  • FIG. 3 is a schematic structural view of the array substrate in the second embodiment of the present invention corresponding to the portion I in FIG.
  • the structure of the array substrate in the second embodiment of the invention is substantially the same as that of the array substrate in the first embodiment, except that each pixel unit of the array substrate in the present embodiment (second embodiment)
  • the gate 711 of the first thin film transistor 710 and the gate 721 of the second thin film transistor 720 in 700 are connected to the same scan line 200.
  • the scan driver of the liquid crystal display device When the scan driver of the liquid crystal display device outputs a scan signal for the nth scan line 200, the scan signal connects the first thin film transistor connected to the nth scan line 200 via the nth scan line 200.
  • the gate 711 of the 710 and the gate 721 of the second thin film transistor 720 are simultaneously turned on.
  • the data line 300 of the nth section transmits a gray scale voltage to the source 712 of the first thin film transistor 710, and the gray is passed through the source 712 and the drain 713 of the first thin film transistor 710.
  • the step voltage is transmitted to the pixel electrode 500 connected to the drain 713 to charge the pixel electrode 500; the common electrode line 400 connected to the source of the second thin film transistor 720 passes a common voltage via the second film A source 722 and a drain 723 of the transistor 720 are transferred to the common electrode 600 to charge the common electrode 600.
  • a voltage on the pixel electrode 500 forms a difference from a voltage on the common electrode 600, thereby forming an electric field that causes the liquid crystal to respond, so that the liquid crystal display device displays a picture.
  • the gate 711 of the first thin film transistor 710 When the gate 711 of the first thin film transistor 710 is turned off, the pixel connected to the drain 713 is present due to the parasitic capacitance Cst1 existing between the gate 711 and the drain 713 of the first thin film transistor 710.
  • the voltage on electrode 500 is pulled down by ⁇ Vp1.
  • the gate 721 of the second thin film transistor 720 is turned off, and the common electrode connected to the drain 723 is connected due to the parasitic capacitance Cst2 existing between the gate 721 and the drain 723 of the second thin film transistor 720.
  • the voltage on electrode 600 is pulled down by ⁇ Vp2.
  • the parasitic capacitance between the gate 711 and the drain 713 of the first thin film transistor 710 is Cst1 is equal to the parasitic capacitance Cst2 between the gate 721 and the drain 723 of the second thin film transistor 720, so that the voltage pull-down value ⁇ Vp2 on the common electrode 600 is equal to the voltage pull-down value on the pixel electrode 500.
  • ⁇ Vp1 thereby avoiding the afterimage caused by the voltage pull-down value ⁇ Vp2 on the common electrode 600 being different from the voltage pull-down value ⁇ Vp1 on the pixel electrode 500 Bad phenomenon such as flickering.
  • the embodiment of the present invention further provides a liquid crystal display device including a data driver, a scan driver, and the array substrate according to any of the above embodiments or embodiments.
  • the data driver is connected to the data line on the array substrate
  • the scan driver is connected to the scan line
  • the data driver is configured to provide a gray scale voltage for the pixel electrode
  • the scan driver is used for A scan signal is issued to turn on or off the gate of the first thin film transistor and the gate of the second thin film transistor.
  • the liquid crystal display device further includes a common voltage generating circuit for supplying a common voltage to the common electrode.
  • Another embodiment of the present invention provides a driving method of another liquid crystal display device, and the driving method of the liquid crystal display device includes the following steps:
  • the gray scale voltage charging a corresponding pixel electrode via a source and a drain of the first thin film transistor
  • the scan signal activating a gate of the second thin film transistor; providing a common voltage to a common corresponding to the scan line of the row
  • An electrode line that charges a corresponding common electrode via a source and a drain of the second thin film transistor; the second thin film transistor is the same as the first thin film transistor.
  • a gray scale voltage of the pixel electrode forms a difference with a common voltage of the common electrode to form an electric field that causes a liquid crystal of the liquid crystal display device to respond, thereby causing the liquid crystal display device to display a picture.
  • the gate of the first thin film transistor When the gate of the first thin film transistor is turned off, a parasitic capacitance exists between a gate of the first thin film transistor and a drain of the first thin film transistor, and is connected to a drain of the first thin film transistor The voltage on the pixel electrode is pulled low. At the same time, the gate of the second thin film transistor is turned off, and the common electrode connected to the drain is present due to a parasitic capacitance between the gate of the second thin film transistor and the drain of the second thin film transistor. The voltage on it is also pulled low.
  • Parasitic capacitance is equal to a parasitic capacitance between a gate of the second thin film transistor and a drain of the second thin film transistor, such that a voltage pull-down value on the common electrode is equal to a voltage pull-down value on the pixel electrode, thereby avoiding The phenomenon that the voltage pull-down value on the common electrode is different from the residual value of the voltage on the pixel electrode, such as afterimage and picture flicker.
  • Another embodiment of the present invention provides a driving method of another liquid crystal display device, and the driving method of the liquid crystal display device includes the following steps:
  • the gray scale voltage charging a corresponding pixel electrode via a source and a drain of the first thin film transistor
  • a common voltage is supplied to the common electrode line corresponding to the row of scan lines, and the common voltage is charged to the corresponding common electrode via the source and the drain of the second thin film transistor.
  • the gray scale voltage of the pixel electrode forms a difference with the common voltage of the common electrode to form an electric field that responds to the liquid crystal, thereby causing the liquid crystal display device to display a picture.
  • the gate of the first thin film transistor When the gate of the first thin film transistor is turned off, a parasitic capacitance exists between a gate of the first thin film transistor and a drain of the first thin film transistor, and is connected to a drain of the first thin film transistor The voltage on the pixel electrode is pulled low. At the same time, the gate of the second thin film transistor is turned off, and the common electrode connected to the drain is present due to a parasitic capacitance between the gate of the second thin film transistor and the drain of the second thin film transistor. The voltage on it is also pulled low.
  • the structure of the first thin film transistor is the same as the structure of the second thin film transistor, between the gate of the first thin film transistor and the drain of the first thin film transistor a parasitic capacitance equal to a parasitic capacitance between a gate of the second thin film transistor and a drain of the second thin film transistor, such that a voltage pull-down value on the common electrode is equal to a voltage lower on the pixel electrode
  • the value is such as to avoid an undesirable phenomenon such as afterimage or picture flicker caused by a voltage pull-down value on the common electrode being different from a voltage pull-down value on the pixel electrode.

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Abstract

一种液晶显示装置及液晶显示装置的驱动方法，液晶显示装置包括阵列面板，阵列面板包括基板（100）以及设置于基板（100）上的两条扫描线（200）、数据线（300）及公共电极线（400），扫描线（200）与数据线（300）及公共电极线（400）以绝缘的方式交叉设置，并形成像素单元（700），像素单元（700）包括像素电极（500）、公共电极（600）、第一薄膜晶体管（710）及第二薄膜晶体管（720），第一薄膜晶体管（710）的栅极（711）及第二薄膜晶体管（720）的栅极（721）均连接于扫描线（200），第一薄膜晶体管（710）的源极（712）连接于数据线（300），漏极（713）连接于像素电极（500），第二薄膜晶体管（720）的源极（722）连接于公共电极线（400），漏极（723）连接公共电极（600）。阵列基板可以在栅极（711、721）关闭时，使公共电极（600）的电压的变化与像素电极（500）的电压的变化一致，从而防止液晶显示装置在显示过程中出现残像、画面闪烁等不良现象。

Description

阵列基板、液晶显示装置及液晶显示装置的驱动方法
本申请要求于2015年02月18日提交中国专利局、申请号为201610091227.0、发明名称为“阵列基板、液晶显示装置及液晶显示装置的驱动方法”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种液晶垂直取向剂、液晶显示元件以及液晶显示元件的制备方法。
技术领域
本发明涉及液晶显示领域，尤其涉及一种阵列基板、具有该阵列基板的液晶显示装置及液晶显示装置的驱动方法。
背景技术
面内切换(In-Plane Switching，IPS)模式的液晶显示装置，是利用包含与阵列基板的表面大致平行的电场使液晶分子沿阵列基板面内方向响应的液晶显示装置。由于具有优异的视角特性，所以被用于各个领域的显示用途当中。在IPS模式的液晶显示装置中，通过像素电极或公共电极边缘所产生的平行电场以及像素电极与公共电极间产生的纵向电场形成多维电场，使液晶盒内像素电极或公共电极之间、像素电极或公共电极正上方所有取向液晶分子都能够产生旋转转换，从而可提高平面取向系液晶的工作效率并增大透光效率。在IPS模式中，像素电极或公共电极通常设置于阵列基板上，因此，阵列基板的品质是液晶显示装置的产品良率的关键。
在现有技术中，阵列基板上通常设置有多条扫描线及多条数据线，多条扫描线与多条数据线纵横相交，形成多个像素单元，每个像素单元内设置有一个薄膜晶体管，薄膜晶体管的栅极与扫描线连接，源极与数据线连接，漏极与像 素电极连接。然而，在该技术中，由于与像素电极相连的漏极与栅极之间存在寄生电容，因此，在栅极关闭的瞬间，栅极电压的变化会将像素电极的电压拉低，进而使得公共电极上的公共电压和像素电极的灰阶电压均发生变化，从而会导致液晶显示装置在显示过程中出现残像、画面闪烁等不良现象。
发明内容
本发明所要解决的技术问题在于，提供一种阵列基板，所述阵列基板可以在栅极关闭时，使公共电极的电压的变化与像素电极的电压的变化一致，从而防止液晶显示装置在显示过程中出现残像、画面闪烁等不良现象。
本发明还提供液晶显示装置及液晶显示装置的驱动方法。
为了解决上述技术问题，本发明采用以下技术方案：
第一方面，本发明提供一种阵列基板，所述阵列基板包括基板以及设置于所述基板上的两条扫描线、数据线及公共电极线，所述扫描线与所述数据线及所述公共电极线以绝缘的方式交叉设置，并形成像素单元，所述像素单元包括像素电极、公共电极、第一薄膜晶体管及第二薄膜晶体管，所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极均连接于所述扫描线，所述第一薄膜晶体管的源极连接于所述数据线，所述第一薄膜晶体管的漏极连接于所述像素电极，所述第二薄膜晶体管的源极连接于所述公共电极线，所述第二薄膜晶体管的漏极连接所述公共电极，所述第二薄膜晶体管与所述第一薄膜晶体管相同。
其中，所述像素单元内的所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极连接于不同的且相邻的两条所述扫描线。
其中，所述像素单元内的所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极连接于同一条所述扫描线。
其中，所述阵列基板还包括至少一条扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线。
其中，所述数据线与所述公共电极线相互平行且间隔设置，所述扫描线相互平行，每个所述像素单元由相邻两条所述扫描线与一条所述数据线及一条所述公共电极线以绝缘的方式相互交叉而围成。
第二方面，本发明还提供一种液晶显示装置，所述液晶显示装置包括数据 驱动器、扫描驱动器及以上任一项所述的阵列基板，所述数据驱动器与所述阵列基板的所述数据线连接，所述扫描驱动器与所述扫描线连接，所述数据驱动器用于为所述像素电极提供灰阶电压，所述扫描驱动器用于提供扫描信号以开启或关闭所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极。
其中，所述液晶显示装置还包括公共电压产生电路，所述公共电压产生电路用于为所述公共电极提供公共电压。
第三方面，本发明提供一种液晶显示装置的驱动方法，包括：
提供一扫描信号到一行连接有第一薄膜晶体管的扫描线，该行所述扫描线启动所述第一薄膜晶体管的栅极；
提供一灰阶电压到该行所述扫描线对应的一列数据线，所述灰阶电压经由所述第一薄膜晶体管的源极和漏极为对应的像素电极充电；
提供扫描信号到下一行扫描线，该行所述扫描线连接有第二薄膜晶体管，所述扫描信号启动所述第二薄膜晶体管的栅极；提供一公共电压到与该行扫描线对应的公共电极线，所述公共电极线经由所述第二薄膜晶体管的源极和漏极为对应的公共电极充电；所述第二薄膜晶体管与所述第一薄膜晶体管相同。
第四方面，本发明提供另一种液晶显示装置的驱动方法，包括步骤：
提供一扫描信号到一行扫描线，启动连接于该行所述扫描线的第一薄膜晶体管的栅极和第二薄膜晶体管的栅极，其中，所述第二薄膜晶体管与所述第一薄膜晶体管相同；
提供一灰阶电压到该行所述扫描线对应的一列数据线，所述灰阶电压经由所述第一薄膜晶体管的源极和漏极为对应的像素电极充电；
提供一公共电压到与该行扫描线对应的公共电极线，所述公共电压经由所述第二薄膜晶体管的源极和漏极为对应的公共电极充电。
与现有技术相比，本发明的技术方案至少具有以下有益效果：
在本发明的技术方案中，由于每个像素单元内设置有一第一薄膜晶体管和一第二薄膜晶体管，所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极均连接于所述扫描线，所述第一薄膜晶体管的源极连接于所述数据线，所述第一薄膜晶体管的漏极连接所述像素电极，所述第二薄膜晶体管的源极连接于所 述公共电极线，所述第二薄膜晶体管的漏极连接所述公共电极，因此，所述像素电极经由所述第一薄膜晶体管充电，而所述公共电极经由第二薄膜晶体管充电；
又由于所述第二薄膜晶体管与所述第一薄膜晶体管相同，因此，与所述公共电极连接的所述第二薄膜晶体管的漏极与栅极间所存在的寄生电容和与所述像素电极连接的所述第一薄膜晶体管的漏极与栅极间存在的寄生电容一致，从而使得在栅极关闭的瞬间，公共电极的公共电压的变化与像素电极的灰阶电压的变化一致，从而防止液晶显示装置在显示过程中出现残像、画面闪烁等不良现象。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的变形形式。
图1是本发明实施例中阵列基板的结构示意图；
图2是本发明第一实施例中的阵列基板对应图1中I部分的结构示意图；及
图3是本发明第二实施例中的阵列基板对应图1中I部分的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而 不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现该工序所预期的作用则也包括在本用语中。另外，本说明书中用“-”表示的数值范围是指将“-”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
在本发明的实施例中，所述阵列基板包括基板以及设置于所述基板上的两条扫描线、数据线及公共电极线，所述扫描线与所述数据线及所述公共电极线以绝缘的方式交叉设置，并形成像素单元，所述像素单元包括像素电极、公共电极、第一薄膜晶体管及第二薄膜晶体管，所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极均连接于所述扫描线，所述第一薄膜晶体管的源极连接于所述数据线，所述第一薄膜晶体管的漏极连接于所述像素电极，所述第二薄膜晶体管的源极连接于所述公共电极线，所述第二薄膜晶体管的漏极连接所述公共电极，所述第二薄膜晶体管与所述第一薄膜晶体管相同。
在本发明的实施例中，所述阵列基板还包括至少一条扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线，即：所述阵列基板包括基板以及设置于所述基板上的多条扫描线、多条数据线及多条公共电极线，其中，所述扫描线与所述数据线及所述公共电极线以绝缘的方式交叉设置，形成多个像素单元。
请一并参阅图1和图2，图1是本发明实施例中阵列基板的结构示意图， 图2是本发明第一实施例中的阵列基板对应图1中I部分的结构示意图。在本发明的第一实施例中，所述阵列基板包括基板100以及设置于基板100上的多条扫描线200、多条数据线300、多条公共电极线400。在本实施例中，多条所述扫描线200之间相互平行，所述数据线300与所述公共电极线400同向设置，优选地，所述数据线300与所述公共电极线400相互平行。所述扫描线200与所述数据线300及所述公共电极线400以绝缘的方式纵横交叉，形成多个像素单元700。具体地，每个所述像素单元700由相邻两条扫描线200与一条所述数据线300及一条所述公共电极线400以绝缘的方式相互交叉而围成，亦即：相邻两条扫描线200横跨一条所述数据线300及一条所述公共电极线400，所形成的闭合四边形即为所述像素单元700。
每个像素单元700内设置有像素电极500、公共电极600、第一薄膜晶体管710及第二薄膜晶体管720。所述第一薄膜晶体管710包括栅极711、源极712及漏极713，所述第二薄膜晶体管720包括栅极721、源极722及漏极723。所述第一薄膜晶体管710的栅极711及所述第二薄膜晶体管720的栅极721均连接于同一像素单元700内的扫描线200。所述第一薄膜晶体管710的源极712连接于所述数据线300，所述第一薄膜晶体管710的漏极713连接所述像素电极500。所述第二薄膜晶体管720的源极722连接于所述公共电极线400，所述第二薄膜晶体管720的漏极723连接所述公共电极600。所述第二薄膜晶体管720与所述第一薄膜晶体管710相同，具体地，所述第二薄膜晶体管720与所述第一薄膜晶体管710的结构相同。
所述公共电极600包括多个公共子电极(图中未编号)，所述像素电极500包括多个像素子电极(图中未编号)，每一个所述公共子电极对应一个像素子电极，即所述公共子电极与所述像素子电极的对应关系为一对一。所述公共子电极的延伸方向可以与所述像素子电极的延伸方向平行。所述公共电极600与像素电极500之间形成电场。。
在本实施例中，每个所述像素单元700内的所述第一薄膜晶体管710的栅极711及所述第二薄膜晶体管720的栅极721连接于不同的且相邻的两条所述扫描线200。例如，在由第n条扫描线200、第n+1条扫描线200、第n条数据线300及第n条公共电极线400绝缘而相交形成的一个像素单元700中，所 述第一薄膜晶体管710的栅极711连接于第n条扫描线200，所述第二薄膜晶体管720的栅极721连接于第n+1条扫描线200，第一薄膜晶体管710的源极712连接于第n条数据线300，第二薄膜晶体管720的源极722连接于第n条公共电极线400，其中，n为自然数。
液晶显示装置的扫描驱动器(图未示出)输出扫描信号，当所述扫描信号经由第n条所述扫描线200传输至所述第一薄膜晶体管710的栅极711时，第n条所述扫描线200所连接的所述第一薄膜晶体管710的栅极711被打开，此时，第n条所述数据线300将由液晶显示装置的数据驱动器(图未示出)输出的灰阶电压传输到所述第一薄膜晶体管710的源极712，并经由所述第一薄膜晶体管710的源极712和漏极713将所述灰阶电压传输到与所述漏极713连接的像素电极500，为所述像素电极500充电。
同时，液晶显示装置的扫描驱动器为第n+1条扫描线200输出扫描信号，所述扫描信号经由所述第n+1条扫描线200将与所述第n+1条扫描线200连接的第二薄膜晶体管720的栅极721打开，此时，与所述第二薄膜晶体管720的源极连接的公共电极线400将公共电压经由所述第二薄膜晶体管720的源极722和漏极723传输给所述公共电极600，为所述公共电极600充电。
所述像素电极500上的电压与所述公共电极600上的电压形成一差值，从而形成使液晶响应的电场，使液晶显示装置显示画面。
当所述第一薄膜晶体管710的栅极711关闭时，由于所述第一薄膜晶体管710的栅极711与漏极713之间存在的寄生电容Cst1，与所述漏极713连接的所述像素电极500上的电压被拉低ΔVp1。同时，所述第二薄膜晶体管720的栅极721关闭，由于所述第二薄膜晶体管720的栅极721与漏极723之间存在的寄生电容Cst2，与所述漏极723连接的所述公共电极600上的电压被拉低ΔVp2。在本实施例中，由于所述第一薄膜晶体管710的结构与所述第二薄膜晶体管720的结构相同，因此，所述第一薄膜晶体管710的栅极711与漏极713之间的寄生电容Cst1等于所述第二薄膜晶体管720的栅极721与漏极723之间的寄生电容Cst2，从而使所述公共电极600上的电压拉低值ΔVp2等于所述像素电极500上的电压拉低值ΔVp1，从而避免由公共电极600上的电压拉低值ΔVp2不同于所述像素电极500上的电压拉低值ΔVp1所引起的残像、画 面闪烁等不良现象。
请参阅图3，图3是本发明第二实施例中的阵列基板对应图1中I部分的结构示意图。在发明的第二实施例中的阵列基板的结构与第一实施例中的阵列基板的结构基本相同，不同之处在于：本实施例(第二实施例)中的阵列基板的每个像素单元700内的所述第一薄膜晶体管710的栅极711及所述第二薄膜晶体管720的栅极721连接于同一条所述扫描线200上。
当液晶显示装置的扫描驱动器为第n条扫描线200输出扫描信号时，所述扫描信号经由所述第n条扫描线200将连接于所述第n条扫描线200的所述第一薄膜晶体管710的栅极711及所述第二薄膜晶体管720的栅极721同时打开。此时，第n条所述数据线300将灰阶电压传输到所述第一薄膜晶体管710的源极712，并经由所述第一薄膜晶体管710的源极712和漏极713将所述灰阶电压传输到与所述漏极713连接的像素电极500，为所述像素电极500充电；与所述第二薄膜晶体管720的源极连接的公共电极线400将公共电压经由所述第二薄膜晶体管720的源极722和漏极723传输给所述公共电极600，为所述公共电极600充电。
所述像素电极500上的电压与所述公共电极600上的电压形成一差值，从而形成使液晶响应的电场，使液晶显示装置显示画面。
当所述第一薄膜晶体管710的栅极711关闭时，由于所述第一薄膜晶体管710的栅极711与漏极713之间存在的寄生电容Cst1，与所述漏极713连接的所述像素电极500上的电压被拉低ΔVp1。同时，所述第二薄膜晶体管720的栅极721关闭，由于所述第二薄膜晶体管720的栅极721与漏极723之间存在的寄生电容Cst2，与所述漏极723连接的所述公共电极600上的电压被拉低ΔVp2。在本实施例中，由于所述第一薄膜晶体管710的结构与所述第二薄膜晶体管720的结构相同，因此，所述第一薄膜晶体管710的栅极711与漏极713之间的寄生电容Cst1等于所述第二薄膜晶体管720的栅极721与漏极723之间的寄生电容Cst2，从而使所述公共电极600上的电压拉低值ΔVp2等于所述像素电极500上的电压拉低值ΔVp1，从而避免由公共电极600上的电压拉低值ΔVp2不同于所述像素电极500上的电压拉低值ΔVp1所引起的残像、画 面闪烁等不良现象。
本发明的实施例还提供了一种液晶显示装置，所述液晶显示装置包括数据驱动器、扫描驱动器及以上任一实施例或实施方式所述的阵列基板。所述数据驱动器与所述阵列基板上的所述数据线连接，所述扫描驱动器与所述扫描线连接，所述数据驱动器用于为所述像素电极提供灰阶电压，所述扫描驱动器用于发出扫描信号以开启或关闭所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极。所述液晶显示装置还包括公共电压产生电路，所述公共电压产生电路用于为所述公共电极提供公共电压。
本发明的实施例还提供另一种液晶显示装置的驱动方法，所述液晶显示装置的驱动方法包括以下步骤：
提供一扫描信号到一行连接有第一薄膜晶体管的扫描线，该行所述扫描线启动所述第一薄膜晶体管的栅极；
提供一灰阶电压到该行所述扫描线对应的一列数据线，所述灰阶电压经由所述第一薄膜晶体管的源极和漏极为对应的像素电极充电；
提供扫描信号到下一行扫描线，该行所述扫描线连接有第二薄膜晶体管，所述扫描信号启动所述第二薄膜晶体管的栅极；提供一公共电压到与该行扫描线对应的公共电极线，所述公共电极线经由所述第二薄膜晶体管的源极和漏极为对应的公共电极充电；所述第二薄膜晶体管与所述第一薄膜晶体管相同。
所述像素电极的灰阶电压与所述公共电极的公共电压形成一差值，从而形成使液晶显示装置的液晶响应的电场，进而使液晶显示装置显示画面。
当所述第一薄膜晶体管的栅极关闭时，由于所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的漏极之间存在寄生电容，与所述第一薄膜晶体管的漏极连接的所述像素电极上的电压被拉低。同时，所述第二薄膜晶体管的栅极关闭，由于所述第二薄膜晶体管的栅极与所述第二薄膜晶体管的漏极之间存在寄生电容，与所述漏极连接的所述公共电极上的电压也被拉低。在本实施例中，由于所述第一薄膜晶体管的结构与所述第二薄膜晶体管的结构相同，因此，所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的漏极之间的寄生电容等于所 述第二薄膜晶体管的栅极与所述第二薄膜晶体管的漏极之间的寄生电容，从而使所述公共电极上的电压拉低值等于所述像素电极上的电压拉低值，从而避免由公共电极上的电压拉低值不同于所述像素电极上的电压拉低值所引起的残像、画面闪烁等不良现象。
本发明的实施例还提供另一种液晶显示装置的驱动方法，所述液晶显示装置的驱动方法包括以下步骤：
提供一扫描信号到一行扫描线，启动连接于该行所述扫描线的第一薄膜晶体管的栅极和第二薄膜晶体管的栅极，所述第二薄膜晶体管与所述第一薄膜晶体管相同；
提供一灰阶电压到该行所述扫描线对应的一列数据线，所述灰阶电压经由所述第一薄膜晶体管的源极和漏极为对应的像素电极充电；
提供一公共电压到与该行扫描线对应的公共电极线，所述公共电压经由所述第二薄膜晶体管的源极和漏极为对应的公共电极充电。
所述像素电极的灰阶电压与所述公共电极的公共电压形成一差值，从而形成使液晶响应的电场，进而使液晶显示装置显示画面。
当所述第一薄膜晶体管的栅极关闭时，由于所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的漏极之间存在寄生电容，与所述第一薄膜晶体管的漏极连接的所述像素电极上的电压被拉低。同时，所述第二薄膜晶体管的栅极关闭，由于所述第二薄膜晶体管的栅极与所述第二薄膜晶体管的漏极之间存在寄生电容，与所述漏极连接的所述公共电极上的电压也被拉低。在本实施例中，由于所述第一薄膜晶体管的结构与所述第二薄膜晶体管的结构相同，因此，所述第一薄膜晶体管的栅极与所述第一薄膜晶体管的漏极之间的寄生电容等于所述第二薄膜晶体管的栅极与所述第二薄膜晶体管的漏极之间的寄生电容，从而使所述公共电极上的电压拉低值等于所述像素电极上的电压拉低值，从而避免由公共电极上的电压拉低值不同于所述像素电极上的电压拉低值所引起的残像、画面闪烁等不良现象。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、 “具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (20)

  1. 一种阵列基板，所述阵列基板包括基板以及设置于所述基板上的两条扫描线、数据线及公共电极线，其中，所述扫描线与所述数据线及所述公共电极线以绝缘的方式交叉设置，并形成像素单元，所述像素单元包括像素电极、公共电极、第一薄膜晶体管及第二薄膜晶体管，所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极均连接于所述扫描线，所述第一薄膜晶体管的源极连接于所述数据线，所述第一薄膜晶体管的漏极连接于所述像素电极，所述第二薄膜晶体管的源极连接于所述公共电极线，所述第二薄膜晶体管的漏极连接所述公共电极，所述第二薄膜晶体管与所述第一薄膜晶体管相同。
  2. 如权利要求1所述的阵列基板，其中，所述像素单元内的所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极连接于不同的且相邻的两条所述扫描线。
  3. 如权利要求1所述的阵列基板，其中，所述像素单元内的所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极连接于同一条所述扫描线。
  4. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括至少一条扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线。
  5. 如权利要求2所述的阵列基板，其中，所述阵列基板还包括至少一条扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线。
  6. 如权利要求3所述的阵列基板，其中，所述阵列基板还包括至少一条扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线。
  7. 如权利要求4所述的阵列基板，其中，所述数据线与所述公共电极线相互平行且间隔设置，所述扫描线相互平行，每个所述像素单元由相邻两条所述扫描线与一条所述数据线及一条所述公共电极线以绝缘的方式相互交叉而围成。
  8. 如权利要求5所述的阵列基板，其中，所述数据线与所述公共电极线相互平行且间隔设置，所述扫描线相互平行，每个所述像素单元由相邻两条所述扫描线与一条所述数据线及一条所述公共电极线以绝缘的方式相互交叉而围成。
  9. 如权利要求6所述的阵列基板，其中，所述数据线与所述公共电极线相互平行且间隔设置，所述扫描线相互平行，每个所述像素单元由相邻两条所述扫描线与一条所述数据线及一条所述公共电极线以绝缘的方式相互交叉而围成。
  10. 一种液晶显示装置，其中，所述液晶显示装置包括数据驱动器、扫描驱动器及阵列基板，所述阵列基板包括基板以及设置于所述基板上的两条扫描线、数据线及公共电极线，所述扫描线与所述数据线及所述公共电极线以绝缘的方式交叉设置，并形成像素单元，所述像素单元包括像素电极、公共电极、第一薄膜晶体管及第二薄膜晶体管，所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极均连接于所述扫描线，所述第一薄膜晶体管的源极连接于所述数据线，所述第一薄膜晶体管的漏极连接于所述像素电极，所述第二薄膜晶体管的源极连接于所述公共电极线，所述第二薄膜晶体管的漏极连接所述公共电极，所述第二薄膜晶体管与所述第一薄膜晶体管相同；所述数据驱动器与所述阵列基板的所述数据线连接，所述扫描驱动器与所述扫描线连接，所述数据驱动器用于为所述像素电极提供灰阶电压，所述扫描驱动器用于提供扫描信号以开启或关闭所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极。
  11. 如权利要求10所述的液晶显示装置，其中，所述像素单元内的所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极连接于不同的且相邻的两条所述扫描线。
  12. 如权利要求10所述的液晶显示装置，其中，所述像素单元内的所述第一薄膜晶体管的栅极及所述第二薄膜晶体管的栅极连接于同一条所述扫描线。
  13. 如权利要求10所述的液晶显示装置，其中，所述阵列基板还包括至少一条扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线。
  14. 如权利要求11所述的液晶显示装置，其中，所述阵列基板还包括至少一条扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线。
  15. 如权利要求12所述的液晶显示装置，所述阵列基板还包括至少一条 扫描线、与所述至少一条扫描线围成所述像素单元的数据线及公共电极线。
  16. 如权利要求13所述的液晶显示装置，其中，所述数据线与所述公共电极线相互平行且间隔设置，所述扫描线相互平行，每个所述像素单元由相邻两条所述扫描线与一条所述数据线及一条所述公共电极线以绝缘的方式相互交叉而围成。
  17. 如权利要求10所述的液晶显示装置，其中，所述液晶显示装置还包括公共电压产生电路，所述公共电压产生电路用于为所述公共电极提供公共电压。
  18. 如权利要求16所述的液晶显示装置，其中，所述液晶显示装置还包括公共电压产生电路，所述公共电压产生电路用于为所述公共电极提供公共电压。
  19. 一种液晶显示装置的驱动方法，其中，包括步骤：
    提供一扫描信号到一行连接有第一薄膜晶体管的扫描线，该行所述扫描线启动所述第一薄膜晶体管的栅极；
    提供一灰阶电压到该行所述扫描线对应的一列数据线，所述灰阶电压经由所述第一薄膜晶体管的源极和漏极为对应的像素电极充电；
    提供扫描信号到下一行扫描线，该行所述扫描线连接有第二薄膜晶体管，所述扫描信号启动所述第二薄膜晶体管的栅极；提供一公共电压到与该行扫描线对应的公共电极线，所述公共电极线经由所述第二薄膜晶体管的源极和漏极为对应的公共电极充电；所述第二薄膜晶体管与所述第一薄膜晶体管相同。
  20. 一种液晶显示装置的驱动方法，其中，包括步骤：
    提供一扫描信号到一行扫描线，启动连接于该行所述扫描线的第一薄膜晶体管的栅极和第二薄膜晶体管的栅极，其中，所述第二薄膜晶体管与所述第一薄膜晶体管相同；
    提供一灰阶电压到该行所述扫描线对应的一列数据线，所述灰阶电压经由所述第一薄膜晶体管的源极和漏极为对应的像素电极充电；
    提供一公共电压到与该行扫描线对应的公共电极线，所述公共电压经由所述第二薄膜晶体管的源极和漏极为对应的公共电极充电。
PCT/CN2016/075477 2016-02-18 2016-03-03 阵列基板、液晶显示装置及液晶显示装置的驱动方法 Ceased WO2017140005A1 (zh)

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