WO2017133185A1 - 数据采集芯片的测试系统、装置及其控制方法 - Google Patents

数据采集芯片的测试系统、装置及其控制方法 Download PDF

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Publication number
WO2017133185A1
WO2017133185A1 PCT/CN2016/089414 CN2016089414W WO2017133185A1 WO 2017133185 A1 WO2017133185 A1 WO 2017133185A1 CN 2016089414 W CN2016089414 W CN 2016089414W WO 2017133185 A1 WO2017133185 A1 WO 2017133185A1
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Prior art keywords
data
module
data acquisition
acquisition chip
noise
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PCT/CN2016/089414
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English (en)
French (fr)
Inventor
覃伟和
管洲
宋海宏
杨炼
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深圳市汇顶科技股份有限公司
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Priority to KR1020177011071A priority Critical patent/KR101953332B1/ko
Priority to EP16863197.6A priority patent/EP3226138B1/en
Priority to US15/594,552 priority patent/US20170248650A1/en
Publication of WO2017133185A1 publication Critical patent/WO2017133185A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2646—Testing of individual semiconductor devices for measuring noise
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

Definitions

  • the invention relates to the technical field of fingerprint recognition, in particular to a test system, a device and a control method thereof for a data acquisition chip.
  • the test system for the fingerprint identification chip generally tests a plurality of chips at the same time, thereby improving test efficiency.
  • ATE Automatic Test Equipment
  • ATE first collects test data of multiple DUTs (Device Under Test), and then tests multiple DUTs. The data is uploaded to the PC to complete the noise calculation of each DUT on the PC side.
  • the noise calculation is generally to find the variance of the same pixel point position data in the multi-frame data.
  • the present invention aims to solve at least one of the technical problems in the related art to some extent.
  • an object of the present invention is to provide a test device for a data acquisition chip, which can improve the efficiency of chip testing and reduce the cost of chip testing.
  • Another object of the present invention is to provide a test system for a data acquisition chip.
  • Still another object of the present invention is to provide a method of controlling a test apparatus for a data acquisition chip.
  • an embodiment of the present invention provides a test apparatus for a data acquisition chip, where the data acquisition chip includes a plurality of data sampling points, and the testing apparatus includes: a data acquisition module, the data acquisition module and The data acquisition chip is connected to receive the multi-frame sampling data collected by the data acquisition chip; the storage module is configured to store the multi-frame sampling data; and the processing module is configured to perform sampling according to the multi-frame Data is used to calculate noise of the plurality of data sampling points to obtain a noise test result; a data transceiver module, the data transceiver module is configured to upload the noise test result to a host computer; and a control module, where the control module is configured to: Controlling the data collection module, the storage module, the processing module, and the data transceiver module.
  • the testing device of the data acquisition chip of the embodiment of the invention calculates the noise of the plurality of data sampling points according to the multi-frame sampling data, and obtains the noise test result by calculating the noise of the plurality of data sampling points, and uploads the noise test result to the upper computer. Improve the efficiency of chip testing, reduce the cost of chip testing, and better ensure the reliability of testing.
  • test apparatus of the data acquisition chip according to the above embodiment of the present invention may further have the following additional technical features:
  • the data acquisition chip is a fingerprint identification chip.
  • the storage module includes: a memory module for storing the multi-frame sampling data; a memory control module, the memory control module and the memory module and the control respectively The modules are connected to control the memory module to read and write multi-frame sampled data under the control of the control module.
  • each frame sample data of the multi-frame sample data includes sample values of a plurality of data sample points
  • the processing module includes: a calculation unit module, and the calculation unit module and The control module is connected to calculate a variance of a plurality of sample values of each data sample point in the multi-frame sample data, and a fall value of the plurality of sample values of each data sample point in the multi-frame sample data; the noise judgment module
  • the noise judging module is connected to the computing unit module, and is configured to determine whether a variance corresponding to each data sampling point is less than a predetermined variance and whether a counter value corresponding to each data sampling point is less than a predetermined counter value, so as to determine The noise test of each data sampling point is passed, and the noise test result is obtained.
  • the data collection module has a buffer for buffering the multi-frame sample data.
  • the testing device further includes a switch module, the switch module includes one or more switches, and the data acquisition chip includes one or more, one Or the plurality of data acquisition chips are connected to the one or more switches one by one; the data acquisition module receives the multi-frame sampling data collected by the data acquisition chip after the switch module is closed.
  • another embodiment of the present invention provides a test system for a data acquisition chip, comprising: a test device for a data acquisition chip as described above; an automatic test device ATE, the ATE and the data acquisition
  • the test device of the chip is connected to the PC; the PC is connected to the ATE, and the PC obtains the noise test result uploaded by the test device of the data acquisition chip by using the ATE, and then according to the noise test result
  • the data acquisition chip performs corresponding operations.
  • the testing device calculates the noise of the plurality of data sampling points according to the multi-frame sampling data, so as to obtain the noise test result by calculating the noise of the plurality of data sampling points, thereby obtaining the noise test result, and further It is judged whether the data acquisition chip is qualified, and the noise test result is uploaded to the PC, which improves the efficiency of the chip test, reduces the cost of the chip test, and better ensures the reliability of the test.
  • a further embodiment of the present invention provides a method for controlling a test apparatus for a data acquisition chip, comprising the steps of: receiving multi-frame sample data collected by a data acquisition chip, and storing the multi-frame sample data; Calculating noise of the plurality of data sampling points according to the multi-frame sampling data to obtain a noise test result; and uploading the noise test result to a host computer.
  • the control method of the data acquisition chip of the embodiment of the present invention calculates the noise of the plurality of data sampling points according to the multi-frame sampling data, so as to obtain the noise test result by calculating the noise of the plurality of data sampling points, and uploading the noise test result to
  • the upper computer improves the efficiency of the chip test, reduces the cost of the chip test, and better guarantees the reliability of the test.
  • control method of the test apparatus of the data acquisition chip according to the above embodiment of the present invention may further have the following additional technical features:
  • each frame sample data of the multi-frame sample data includes sample values of a plurality of data sample points, and the plurality of data sample points are calculated according to the multi-frame sample data.
  • Noise to obtain a noise test result, further comprising: calculating a variance of a plurality of sample values of each data sample point in the multi-frame sample data, and a value of a plurality of sample values of each of the data sample points in the multi-frame sample data Determining whether the variance corresponding to each data sampling point is less than a predetermined variance and whether the data value corresponding to each data sampling point is less than a predetermined value, to determine whether the noise test of each data sampling point passes, thereby obtaining noise Test Results.
  • the method further includes: buffering the multi-frame sampling data.
  • FIG. 1 is a schematic structural diagram of a test system for a fingerprint recognition type chip in the related art
  • FIG. 3 is a schematic diagram of a pixel matrix in a fingerprint identification chip in the related art
  • FIG. 5 is a schematic structural diagram of a testing apparatus of a data acquisition chip according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a test apparatus for a data acquisition chip according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method of controlling a test apparatus of a data acquisition chip according to an embodiment of the present invention.
  • FIG. 8 is a flow chart of a method of controlling a test apparatus of a data acquisition chip according to an embodiment of the present invention.
  • the stability of the fingerprint recognition chip will affect the quality of the captured fingerprint image and the accuracy of the final fingerprint recognition.
  • the surface of the fingerprint identification chip has m*n pixels. Due to the difference of components in the circuit and the influence of the system design, different noises exist at each pixel point, as shown in FIG.
  • the picture shows the data collected at the same pixel at different times in the no-load state. Due to the noise, the amplitude of the collected data will fluctuate, and the noise is larger. The larger the motion is, the more the data collected by the pixel will not be recognized once the noise exceeds a certain range, and the fingerprint recognition will fail when the number of unrecognizable pixels in the pixel matrix of m x n exceeds a certain number. . This shows the importance of chip testing.
  • the invention is based on the above problems, and proposes a test system, a device and a control method thereof for a data acquisition chip.
  • test system an apparatus, and a control method thereof for a data acquisition chip according to an embodiment of the present invention are described below with reference to the accompanying drawings.
  • test apparatus for a data acquisition chip according to an embodiment of the present invention will be described with reference to the accompanying drawings.
  • FIG. 5 is a schematic structural diagram of a test apparatus of a data acquisition chip according to an embodiment of the present invention.
  • the test device 10 of the data acquisition chip includes a switch module 100, a data acquisition module 200, a storage module 300, a processing module 400, a data transceiver module 500, and a control module 600.
  • the data acquisition chip includes a plurality of data sampling points.
  • the data collection module 200 is connected to the data acquisition chip through the switch module 100, so that after the switch module 100 is closed, the data acquisition module 200 receives the multi-frame sample data collected by the data acquisition chip.
  • the storage module 300 is configured to store multi-frame sampling data.
  • the processing module 400 is configured to calculate noise of the plurality of data sampling points according to the multi-frame sampling data to obtain a noise test result.
  • the data transceiver module 500 is configured to upload the noise test result to the host computer.
  • the control module 600 is configured to control the switch module 100, the data collection module 200, the storage module 300, the processing module 400, and the data transceiver module 500.
  • the testing device 10 of the embodiment of the invention has the noise computing capability of the PC, and only uploads the noise test result to the upper computer according to the sampling data operation, thereby reducing the data transmission amount between the data acquisition chip and the upper computer, thereby improving the chip.
  • the efficiency and accuracy of the test reduces the cost of the chip test and better guarantees the reliability of the test.
  • the data acquisition chip may be a fingerprint identification chip, which reduces the testing cost of a plurality of fingerprint identification chips, ensures the stability of the fingerprint identification chip, and further improves the accuracy of fingerprint recognition.
  • the bit machine includes: ATE 20 and PC 30.
  • the ATE 20 is connected to the test device, and the PC 30 is connected to the ATE 20.
  • the data acquisition chip ie, the chip under test
  • the ATE ATE
  • the test device 10 of the embodiment of the present invention can communicate independently two or two, but the device under test is isolated from the device of the present invention by the switch module 100 (corresponding to an analog switch). Therefore, the test apparatus 10 of the embodiment of the present invention is prevented from having an influence on other test items of the ATE test DUT; after the switch module is closed, the data is collected, converted, and cached in the local large-capacity memory by using the test apparatus 10 of the embodiment of the present invention. To ensure the stability of the test.
  • the storage module 300 includes a memory module 301 and a memory control module 302.
  • the memory module 301 is configured to store multi-frame sampling data.
  • the memory control module 302 is connected to the memory module 301 and the control module 600, respectively, to control the memory module 301 to read and write multi-frame sampled data under the control of the control module 600.
  • the data collection module 200 has a cache (not specifically identified in the figure) for buffering multi-frame sample data.
  • the switch module 100 includes one or more switches (shown as switch 101, switch 102, ..., switch 10N in FIG. 6), data acquisition chip. Including one or more (DUT 0, DUT1, ..., DUT n), one or more data acquisition chips are associated with one or more switches in a one-to-one correspondence.
  • the processing module 400 includes a computing unit module 401 and a noise determining module 402.
  • the sampling data of each frame in the multi-frame sampling data includes sampling values of a plurality of data sampling points.
  • the calculation unit module 401 is connected to the control module 600 to calculate a variance of a plurality of sample values of each data sample point in the multi-frame sample data, and a plurality of sample values of each data sample point in the multi-frame sample data. A point value.
  • the noise judging module 402 is connected to the computing unit module 401. The noise judging module 402 is configured to determine whether the variance corresponding to each data sampling point is less than a predetermined variance and whether the counter value corresponding to each data sampling point is less than a predetermined counter value, so as to determine The noise test of each data sampling point is passed, and the noise test result of the data acquisition chip is obtained.
  • the number of data sampling points whose recording variance is greater than the predetermined variance, or the counter value is greater than the predetermined counter value, or the variance is greater than the predetermined variance and the counter value is greater than the predetermined counter value if the number is greater than the predetermined number, the corresponding data
  • the noise test of the acquisition chip passes, otherwise it does not pass.
  • predetermined variance, the predetermined risk value and the predetermined number can be entered according to the actual situation. Line adjustment.
  • the testing apparatus 10 of the embodiment of the present invention performs noise testing by calculating the variance of the sampling values of a plurality of different moments of the same pixel and the value of the counter point, and only performs the noise test result as the data after the calculation is completed.
  • the noise test of the acquisition chip is passed or not uploaded to the host computer such as ATE 20.
  • the data acquisition module 200, the storage module 300, the processing module 400, the data transceiver module 500, and the control module 600 can be field-programmable through an FPGA (Field-Programmable Gate Array). Gate array) implementation.
  • the switch module 100 is responsible for controlling whether the data transmission bus between the DUT and the FPGA is turned on. When the switch module 100 is disconnected, the DUT can communicate with the ATE 20; when the switch module 100 is closed, the DUT communicates with the FPGA.
  • the data acquisition module 200 is mainly responsible for collecting the data of the DUT, that is, receiving the multi-frame sampling data collected by the data acquisition chip, and secondly, the multi-frame sampling data is correspondingly converted and sent to the buffer, and the request signal output is generated when the buffered data reaches a certain number. Go to the subordinate module.
  • the control module 600 is mainly responsible for the control of the entire system, such as triggering the data acquisition module 200 to collect data and receiving the read cache request signal, triggering the memory control module 302 to start the memory module 301 to read and write data, and the like.
  • the memory control module 302 is primarily responsible for the control of the memory module 301 and the arbitration of the read and write data.
  • the memory module 301 is primarily responsible for storing a large amount of data of the DUT.
  • the calculation unit module 401 is mainly responsible for completing the implementation of the noise test algorithm and outputting the calculation result.
  • the noise judging module 402 is mainly responsible for judging the calculation result output by the calculation unit module 401, and judging whether the test passes.
  • the data transceiver module 500 is mainly responsible for receiving data sent by the ATE 20 to the FPGA and transmitting noise test results to the ATE 20.
  • the switch in the switch module 100 is closed, and the data enters the data acquisition module 200 via the switch module 100, and the data is collated in the data acquisition module 200, including serial-to-parallel conversion, buffering.
  • the control module 600 is triggered, and the control module 600 starts the memory control module 302.
  • the memory control module 302 sequentially writes the data buffered by the upper module to the memory module 301.
  • the control module 600 starts the memory control module. 302, the data is taken out from the memory module 301 and sent to the calculation unit module 401.
  • the calculation of the noise is completed in the calculation unit module 401 and the calculation result is sent to the noise determination module 402, and the noise calculation result and the setting according to the noise are implemented in the noise determination module 40.
  • the threshold is compared to determine whether the test of the data sampling point is passed, and then the noise test result is sent to the data transceiver module 500, and after being parsed, sent to the PC through the ATE 20, and the PC according to the received noise test result, such as If the DUT0 noise test fails or passes, the DUT is classified, and the DUT whose noise test result does not pass will be discarded.
  • the noise of the plurality of data sampling points is calculated according to the multi-frame sampling data, so that the noise test result is obtained by calculating the noise of the plurality of data sampling points, and the noise is obtained.
  • the test results are uploaded to the host computer, which reduces the test time, improves the efficiency of the chip test, and completes the noise calculation by calculating the variance and the calculation of the counter point, improves the chip test accuracy, reduces the cost of the chip test, and better guarantees the test. Reliability.
  • Embodiments of the present invention also provide a test system for a data acquisition chip, which includes the test device of the above data acquisition chip, an ATE, and a PC.
  • the ATE is connected to the test device of the data acquisition chip, and the PC is connected with the ATE.
  • the PC obtains the noise test result uploaded by the test device of the data acquisition chip through the ATE, and then performs corresponding operations on the data acquisition chip according to the noise test result.
  • test system of the data acquisition chip may be the same as that described in the test device of the data acquisition chip of the embodiment of the present invention, and will not be described in detail herein.
  • the test device calculates the noise of the plurality of data sampling points according to the multi-frame sampling data, to determine whether the data acquisition chip is qualified by calculating the noise of the plurality of data sampling points, and then the noise test
  • the result is uploaded to the PC through ATE, which reduces the test time, improves the efficiency of the chip test, and completes the noise calculation by calculating the variance and the calculation of the counter point, improves the chip test accuracy, reduces the cost of the chip test, and better guarantees The reliability of the test.
  • FIG. 7 is a flow chart of a method of controlling a test apparatus of a data acquisition chip according to an embodiment of the present invention.
  • control method of the test device of the data acquisition chip includes the following steps:
  • control method of the embodiment of the present invention after receiving the multi-frame sampling data collected by the data acquisition chip, the control method of the embodiment of the present invention further includes: buffering the multi-frame sampling data.
  • each frame of sample data in the multi-frame sample data includes sample values of a plurality of data sample points, and noise of the plurality of data sample points is calculated according to the multi-frame sample data to obtain a noise test result. And further comprising: calculating a variance of the plurality of sample values of each data sample point in the multi-frame sample data, and a value of the plurality of sample values of each of the data sample points in the multi-frame sample data; determining each data sample point Whether the corresponding variance is less than the predetermined variance and whether the data value corresponding to each data sampling point is less than a predetermined value, to determine whether the noise test of each data sampling point passes, thereby obtaining a noise test result.
  • test device embodiment of the data acquisition chip is also applicable to the control method of the test device of the data acquisition chip of the embodiment, and details are not described herein again.
  • control method of the embodiment of the present invention includes the following steps:
  • ATE first disconnects the switch in the switch module, and controls the DUT and the FPGA to work in a specific mode by issuing configuration parameters.
  • the configuration of the DUT includes setting the scan mode, the amplitude of the ADC, the number of integrations, etc., so that the DUT enters the waiting for scanning state;
  • the configuration of the FPGA includes setting the pixel specification (m*n matrix) of the current DUT, and collecting the data bit width. , collecting the number of data frames, etc., and finally entering the waiting for acquisition state.
  • the data bus connected between the DUT and the FPGA is usually a serial bus, such as SPI, I 2 C bus, etc., so the collected data first needs to be serial-to-parallel after entering the FPGA, and then stored in the cache according to a specific format, and the cache is usually used.
  • FIFO implementation According to the parameters configured by the ATE, when the cached data reaches the configured number, a request signal can be sent to request the lower module to read the data in the cache.
  • the memory control module when the control module receives the request signal, the memory control module is triggered to read the buffer data in the acquisition data module, and then write into the memory module, where the memory is usually an external memory, such as SDRAM, SRAM, or the like. Since data acquisition is acquired in parallel for multiple DUTs, it is necessary to arbitrate data in the memory control module, which will be used for each DUT. The data is written into the memory module one by one until the N (the value of N is set according to design requirements, N is greater than or equal to 2) frame data.
  • the control module triggers the memory control module to send the data to the computing unit module in a prescribed format, and secondly, the noise calculation of each pixel is completed in the computing unit module.
  • the noise calculation includes two parts. The first part is to calculate the variance S 2 of the data of the same pixel in the multi-frame data, which can be expressed as:
  • x1, x2, ..., xn are respectively the first frame, the second frame, ... the nth frame data corresponding to the pixel point, and M is the mean value of the N frame data of the pixel point;
  • the second part is to find the counter value V of the same pixel data in the multi-frame data, which can be expressed as:
  • V max(x1, x2, ..., xn)-min(x1, x2, ..., xn).
  • the second is whether the number of pixels in the pixel matrix in which the noise test fails is greater than the threshold LimNum. If it is less than the threshold LimNum, it is determined that the DUT noise test corresponding to the pixel matrix passes, otherwise fail.
  • the noise judging module sends the noise test result to the data transceiver module, and the second data transceiver module uploads the result to the ATE according to the interface protocol.
  • the noise of the plurality of data sampling points is calculated according to the multi-frame sampling data, so that the noise test result is obtained by calculating the noise of the plurality of data sampling points, thereby the noise test result Uploading to the host computer reduces the test time, improves the efficiency of the chip test, and improves the core by calculating the variance and the calculation of the noise.
  • the accuracy of the test is reduced, the cost of the chip test is reduced, and the reliability of the test is better ensured.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated and defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

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Abstract

一种数据采集芯片的测试装置（10）及其控制方法，该测试装置（10）包括：接收数据采集芯片采集的多帧采样数据的数据采集模块（200）；存储模块（300）；计算多个数据采样点的噪声，以得到噪声测试结果的处理模块（400）；将所述噪声测试结果上传的数据收发模块（500）；控制模块（600）。该测试装置（10），通过计算多个数据采样点的噪声，从而只需上传噪声测试结果，提高了芯片测试的效率，降低了芯片测试的成本，更好地保证测试的可靠性。

Description

数据采集芯片的测试系统、装置及其控制方法
本申请要求于2016年2月2日提交中国专利局、申请号为201610074545.6、发明名称为“数据采集芯片的测试系统、装置及其控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及指纹识别技术领域，特别涉及一种数据采集芯片的测试系统、装置及其控制方法。
背景技术
相关技术中，如图1所示，对指纹识别芯片的测试系统一般会同时测试多颗芯片，从而提高测试效率。其中，由于ATE(Automatic Test Equipment，自动测试设备)并不具备计算功能，所以在测试时，ATE先采集多片DUT(Device Under Test，被测器件)的测试数据，然后将多片DUT的测试数据上传到PC端，以在PC端完成每片DUT的噪声计算。噪声计算一般为求多帧数据中同一个像素点位置数据的方差。
然而，在上述系统中，由于ATE与PC之间的数据传输方式为串行传输，一旦采集数据量很大时，数据传输需耗费大量时间，尤其是在进行芯片的量产测试时，提高了大量的测试成本，并且单纯采用求方差的计算方式进行噪声计算，一旦噪声表现为冒点，如图2所示，则数据的方差并不能准确反应出该像素点的噪声大小，从而影响指纹识别芯片的稳定性，进而降低指纹识别的准确率。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。
为此，本发明的一个目的在于提出一种数据采集芯片的测试装置，该装置可以提高芯片测试的效率，降低芯片测试的成本。
本发明的另一个目的在于提出一种数据采集芯片的测试系统。
本发明的再一个目的在于提出一种数据采集芯片的测试装置的控制方法。
为达到上述目的，本发明一方面实施例提出了一种数据采集芯片的测试装置，所述数据采集芯片包括多个数据采样点，所述测试装置包括：数据采集模块，所述数据采集模块与数据采集芯片相连，接收所述数据采集芯片采集的多帧采样数据；存储模块，所述存储模块用于存储所述多帧采样数据；处理模块，所述处理模块用于根据所述多帧采样数据计算所述多个数据采样点的噪声，以得到噪声测试结果；数据收发模块，所述数据收发模块用于将所述噪声测试结果上传至上位机；以及控制模块，所述控制模块用于对所述数据采集模块、所述存储模块、所述处理模块和所述数据收发模块进行控制。
本发明实施例的数据采集芯片的测试装置，根据多帧采样数据计算多个数据采样点的噪声，以通过计算多个数据采样点的噪声得到噪声测试结果，将噪声测试结果上传至上位机，提高了芯片测试的效率，降低了芯片测试的成本，更好地保证测试的可靠性。
另外，根据本发明上述实施例的数据采集芯片的测试装置还可以具有以下附加的技术特征：
可选地，在本发明的一个实施例中，所述数据采集芯片为指纹识别芯片。
进一步地，在本发明的一个实施例中，所述存储模块包括：存储器模块，用于存储所述多帧采样数据；存储器控制模块，所述存储器控制模块分别与所述存储器模块和所述控制模块相连，以在所述控制模块的控制下控制所述存储器模块进行多帧采样数据的读写。
进一步地，在本发明的一个实施例中，所述多帧采样数据中每一帧采样数据包括多个数据采样点的采样值，所述处理模块包括：计算单元模块，所述计算单元模块与所述控制模块相连，以计算多帧采样数据中每个数据采样点的多个采样值的方差，以及多帧采样数据中每个数据采样点的多个采样值的冒点值；噪声判断模块，所述噪声判断模块与所述计算单元模块相连，用于判断每个数据采样点对应的方差是否小于预定方差以及每个数据采样点对应的冒点值是否小于预定冒点值，以判断所述每个数据采样点的噪声测试是否通过，进而得到噪声测试结果。
进一步地，在本发明的一个实施例中，所述数据采集模块具有缓存，用于缓存所述多帧采样数据。
可选地，在本发明的一个实施例中，所述测试装置还包括开关模块，所述开关模块包括一个或多个开关，所述数据采集芯片包括一个或多个，一个 或多个数据采集芯片一一对应地与一个或多个开关相连；所述数据采集模块在所述开关模块闭合后，接收所述数据采集芯片采集的多帧采样数据。
为达到上述目的，本发明另一方面实施例提出了一种数据采集芯片的测试系统，包括：如上述所述的数据采集芯片的测试装置；自动测试设备ATE，所述ATE与所述数据采集芯片的测试装置相连；PC机，所述PC机与所述ATE相连，所述PC机通过所述ATE得到所述数据采集芯片的测试装置上传的噪声测试结果，进而根据所述噪声测试结果对所述数据采集芯片进行相应的操作。
本发明实施例的数据采集芯片的测试系统，测试装置根据多帧采样数据计算多个数据采样点的噪声，以通过计算多个数据采样点的噪声得到噪声测试结果，从而得到噪声测试结果，进而判断数据采集芯片是否合格，并且将噪声测试结果上传至PC机，提高了芯片测试的效率，降低了芯片测试的成本，更好地保证测试的可靠性。
为达到上述目的，本发明再一方面实施例提出了一种数据采集芯片的测试装置的控制方法，包括以下步骤：接收数据采集芯片采集的多帧采样数据，并存储所述多帧采样数据；根据所述多帧采样数据计算所述多个数据采样点的噪声，以得到噪声测试结果；以及将所述噪声测试结果上传至上位机。
本发明实施例的数据采集芯片的测试装置的控制方法，根据多帧采样数据计算多个数据采样点的噪声，以通过计算多个数据采样点的噪声得到噪声测试结果，将噪声测试结果上传至上位机，提高了芯片测试的效率，降低了芯片测试的成本，更好地保证测试的可靠性。
另外，根据本发明上述实施例的数据采集芯片的测试装置的控制方法还可以具有以下附加的技术特征：
进一步地，在本发明的一个实施例中，所述多帧采样数据中每一帧采样数据包括多个数据采样点的采样值，所述根据所述多帧采样数据计算多个数据采样点的噪声，以得到噪声测试结果，进一步包括：计算多帧采样数据中每个数据采样点的多个采样值的方差，以及多帧采样数据中每个数据采样点的多个采样值的冒点值；判断每个数据采样点对应的方差是否小于预定方差以及每个数据采样点对应的冒点值是否小于预定冒点值，以判断所述每个数据采样点的噪声测试是否通过，进而得到噪声测试结果。
进一步地，在本发明的一个实施例中，在所述接收数据采集芯片采集的 多帧采样数据之后，上述方法还包括：对所述多帧采样数据进行缓存。
本发明附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为相关技术中对指纹识别类芯片的测试系统的结构示意图；
图2为相关技术中冒点噪声示意图；
图3为相关技术中指纹识别芯片中像素矩阵示意图；
图4为相关技术中像素点噪声示意图；
图5为根据本发明实施例的数据采集芯片的测试装置的结构示意图；
图6为根据本发明一个具体实施例的数据采集芯片的测试装置的结构示意图；
图7为根据本发明实施例的数据采集芯片的测试装置的控制方法的流程图；以及
图8为根据本发明一个具体实施例的数据采集芯片的测试装置的控制方法的流程图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
下面在描述根据本发明实施例提出的数据采集芯片的测试系统、装置及其控制方法之前，先来简单描述一下芯片测试的重要性。
以指纹识别芯片为例，指纹识别芯片的稳定性将影响采集指纹图像的质量以及最终指纹识别的准确率。如图3所示，指纹识别芯片的表面有m*n个像素点，由于电路中元器件的差异性以及系统设计的影响，导致每个像素点存在不同的噪声，如图4所示，该图为空载状态下不同时刻对同一个像素点采集到的数据，受噪声的影响，采集到的数据幅度会波动，且噪声越大波 动越大，一旦噪声超过一定范围时，则该像素点采集到的数据将无法被识别，而当m x n的像素矩阵中无法被识别的像素点的数目超过一定数量时，指纹识别将失败。由此可知芯片测试的重要性。
然而，在相关技术中，一旦采集数据量很大时，ATE与PC之间的数据传输(串行传输)需耗费大量时间，提高了大量的测试成本，并且由于数据的方差并不能准确反应出该像素点的噪声大小，从而影响指纹识别芯片的稳定性，进而降低指纹识别的准确率。
本发明中正是基于上述问题，而提出了一种数据采集芯片的测试系统、装置及其控制方法。
下面参照附图描述根据本发明实施例提出的数据采集芯片的测试系统、装置及其控制方法，首先将参照附图描述根据本发明实施例提出的数据采集芯片的测试装置。
图5为根据本发明实施例的数据采集芯片的测试装置的结构示意图。
如图5所示，该数据采集芯片的测试装置10包括：开关模块100、数据采集模块200、存储模块300、处理模块400、数据收发模块500和控制模块600。
其中，数据采集芯片包括多个数据采样点。具体地，数据采集模块200通过开关模块100与数据采集芯片相连，以在开关模块100闭合后，数据采集模块200接收数据采集芯片采集的多帧采样数据。存储模块300用于存储多帧采样数据。处理模块400用于根据多帧采样数据计算多个数据采样点的噪声，以得到噪声测试结果。数据收发模块500用于将噪声测试结果上传至上位机。控制模块600用于对开关模块100、数据采集模块200、存储模块300、处理模块400和数据收发模块500进行控制。本发明实施例的测试装置10具备PC机的噪声计算能力，根据采样数据运算后仅将噪声测试结果上传至上位机，减少了数据采集芯片与上位机之间的数据传输量，如此可以提高芯片测试的效率和准确率，降低芯片测试的成本，更好地保证测试的可靠性。
可选地，在本发明的一个实施例中，数据采集芯片可以为指纹识别芯片，降低了大量指纹识别芯片的测试成本，保证指纹识别芯片的稳定性，进而提高指纹识别的准确率。
进一步地，在本发明的一个实施例中，如图6所示，本发明实施例的上 位机包括：ATE 20与PC机30。其中，ATE 20与测试装置相连，PC机30与ATE 20相连。
数据采集芯片(即被测芯片)、ATE和本发明实施例的测试装置10之间可两两独立通信，但被测芯片与本发明装置之间用开关模块100(相当于模拟开关)隔离，从而避免本发明实施例的测试装置10在ATE测试DUT其他测试项时产生影响；在开关模块闭合后，使用本发明实施例的测试装置10将数据采集、转换，并且缓存于本地大容量存储器中，保证测试的稳定性。
进一步地，在本发明的一个实施例中，如图6所示，存储模块300包括：存储器模块301和存储器控制模块302。
其中，存储器模块301用于存储多帧采样数据。存储器控制模块302分别与存储器模块301和控制模块600相连，以在控制模块600的控制下控制存储器模块301进行多帧采样数据的读写。
进一步地，在本发明的一个实施例中，数据采集模块200具有缓存(图中未具体标识)，用于缓存多帧采样数据。
可选地，在本发明的一个实施例中，如图6所示，开关模块100包括一个或多个开关(如图6中开关101、开关102、…、开关10N所示)，数据采集芯片包括一个或多个(DUT 0、DUT1、…、DUT n)，一个或多个数据采集芯片一一对应地与一个或多个开关相连。
进一步地，在本发明的一个实施例中，如图6所示，处理模块400包括：计算单元模块401和噪声判断模块402。
其中，多帧采样数据中每一帧采样数据包括多个数据采样点的采样值。具体地，计算单元模块401与控制模块600相连，以计算多帧采样数据中每个数据采样点的多个采样值的方差，以及多帧采样数据中每个数据采样点的多个采样值的冒点值。噪声判断模块402与计算单元模块401相连，噪声判断模块402用于判断每个数据采样点对应的方差是否小于预定方差以及每个数据采样点对应的冒点值是否小于预定冒点值，以判断每个数据采样点的噪声测试是否通过，进而得到数据采集芯片的噪声测试结果。例如，记录方差大于预定方差、或冒点值大于预定冒点值、或方差大于预定方差和冒点值大于预定冒点值的数据采样点的数量，若该数量大于预定数量，则对应的数据采集芯片的噪声测试通过，否则为不通过。
需要说明的是，预定方差、预定冒点值和预定数量可以根据实际情况进 行调整。
在本发明的实施例中，本发明实施例的测试装置10通过求同一像素点的多个不同时刻的采样值的方差以及冒点值进行噪声测试，并且完成运算后只将噪声测试结果如数据采集芯片的噪声测试为通过或者不通过上传到上位机如ATE 20。
在本发明的一个具体实施例中，如图6所示，数据采集模块200、存储模块300、处理模块400、数据收发模块500和控制模块600可以通过FPGA(Field－Programmable Gate Array，现场可编程门阵列)实现。其中，开关模块100负责控制DUT与FPGA之间的数据传输总线是否导通，当开关模块100断开时，DUT可以与ATE 20通信；当开关模块100闭合时，DUT与FPGA通信。数据采集模块200主要负责采集DUT的数据，即接收数据采集芯片采集的多帧采样数据，其次将多帧采样数据做相应的转换后送入缓存，并且当缓存数据到达一定数目时产生请求信号输出到下级模块。控制模块600主要负责整个系统的控制，如触发数据采集模块200采集数据并且接收读缓存请求信号、触发存储器控制模块302启动存储器模块301读写数据等等。存储器控制模块302主要负责存储器模块301的控制以及读写数据的仲裁。存储器模块301主要负责存储DUT的大量数据。计算单元模块401主要负责完成噪声测试算法的实现，并且把计算结果输出。噪声判断模块402主要负责对计算单元模块401输出的计算结果进行判断，判断测试是否通过。数据收发模块500主要负责接收ATE 20下发到FPGA的数据和发送噪声测试结果到ATE 20。
举例而言，ATE 20对DUT和FPGA配置后，闭合开关模块100中的开关，数据经开关模块100进入数据采集模块200，在该数据采集模块200内完成数据的整理，包括串并转换，缓存等处理后触发控制模块600，控制模块600启动存储器控制模块302，存储器控制模块302有序地将上级模块缓存的数据写入存储器模块301，存储完N帧数据后，控制模块600启动存储器控制模块302将数据从存储器模块301中取出送往计算单元模块401，在计算单元模块401中完成噪声的计算并且把计算结果送至噪声判断模块402，在噪声判断模块40实现根据噪声计算结果与设定的阈值作比较，判定该数据采样点的测试是否通过，然后将噪声测试结果送往数据收发模块500，经解析后通过ATE 20送往PC机，PC机根据接收到的噪声测试结果，如 DUT0的噪声测试不通过或者通过，对DUT进行分类，噪声测试结果不通过的DUT将被丢弃。
需要说明的是，具体如何采用求方差以及冒点计算将在下面的数据采集芯片的测试装置的控制方法的实施例中进行详细赘述。
根据本发明实施例的数据采集芯片的测试装置，在开关模块闭合后，根据多帧采样数据计算多个数据采样点的噪声，以通过计算多个数据采样点的噪声得到噪声测试结果，将噪声测试结果上传至上位机，减少了测试时间，提高了芯片测试的效率，并且通过求方差以及冒点计算完成噪声计算，提高了芯片测试准确率，降低了芯片测试的成本，更好地保证测试的可靠性。
本发明的实施例还提出了一种数据采集芯片的测试系统，该系统包括上述数据采集芯片的测试装置、ATE和PC机。其中，ATE与数据采集芯片的测试装置相连，PC机与ATE相连，PC机通过ATE得到数据采集芯片的测试装置上传的噪声测试结果，进而根据噪声测试结果对数据采集芯片进行相应的操作。
应理解，根据本发明实施例的数据采集芯片的测试系统的具体实现过程可与本发明实施例的数据采集芯片的测试装置中描述的相同，此处不再详细描述。
根据本发明实施例的数据采集芯片的测试系统，测试装置根据多帧采样数据计算多个数据采样点的噪声，以通过计算多个数据采样点的噪声判断数据采集芯片是否合格，然后将噪声测试结果通过ATE上传至PC机，减少了测试时间，提高了芯片测试的效率，并且通过求方差以及冒点计算完成噪声计算，提高了芯片测试准确率，降低了芯片测试的成本，更好地保证测试的可靠性。
图7为根据本发明实施例的数据采集芯片的测试装置的控制方法的流程图。
如图7所示，该数据采集芯片(包括多个数据采样点)的测试装置的控制方法包括以下步骤：
S701，接收数据采集芯片采集的多帧采样数据，并存储多帧采样数据。
其中，在本发明的一个实施例中，在接收数据采集芯片采集的多帧采样数据之后，本发明实施例的控制方法还包括：对多帧采样数据进行缓存。
S702，根据多帧采样数据计算多个数据采样点的噪声，以得到噪声测试 结果。
其中，在本发明的一个实施例中，多帧采样数据中每一帧采样数据包括多个数据采样点的采样值，根据多帧采样数据计算多个数据采样点的噪声，以得到噪声测试结果，进一步包括：计算多帧采样数据中每个数据采样点的多个采样值的方差，以及多帧采样数据中每个数据采样点的多个采样值的冒点值；判断每个数据采样点对应的方差是否小于预定方差以及每个数据采样点对应的冒点值是否小于预定冒点值，以判断每个数据采样点的噪声测试是否通过，进而得到噪声测试结果。
S703，将噪声测试结果上传至上位机。
需要说明的是，前述对数据采集芯片的测试装置实施例的解释说明也适用于该实施例的数据采集芯片的测试装置的控制方法，此处不再赘述。
在本发明的一个具体实施例，其中将对如何采用求方差以及冒点计算进行详细描述，如图8所示，本发明实施例的控制方法包括以下步骤：
S801，配置参数。
可以理解为，ATE先断开开关模块中的开关，通过下发配置参数的形式控制DUT和FPGA工作于特定的模式下。
其中，对DUT的配置包括设定扫描模式、ADC幅度、积分次数等等，让DUT进入等待扫描状态；对FPGA的配置包括设定当前DUT的像素规格(m*n矩阵)、采集数据位宽、采集数据帧数等等，最后进入等待采集状态。
S802，采集数据。
也就是说，在ATE完成对DUT和FPGA的参数配置之后，闭合开关模块中的开关，并且触发DUT和FPGA进入数据采集模式。DUT与FPGA之间连接的数据总线通常为串行总线，如SPI，I2C总线等，因此采集的数据进入FPGA后首先需要进行串并转换，然后按照特定的格式存入缓存，缓存通常使用FIFO实现。根据ATE配置的参数，当缓存数据达到配置数量时便可发出请求信号，请求下级模块读取缓存中的数据。
S803，存储数据。
进一步地，当控制模块接收到请求信号时，便触发存储器控制模块将采集数据模块中的缓存数据读出，然后写入存储器模块内，此处的存储器通常为外部存储器，比如SDRAM、SRAM等。由于数据采集是对多个DUT并行采集的，因此在存储器控制模块中需要对数据进行仲裁，将每个DUT的 数据逐一写入存储器模块直到存完N(根据设计需求设定N的值，N大于等于2)帧数据。
S804，计算噪声。
举例而言，当采集完N帧数据后，控制模块触发存储器控制模块将数据按规定格式取出送往计算单元模块，其次在此计算单元模块中完成每个像素点的噪声计算。噪声计算包括两部分，第一部分为计算多帧数据中同一个像素点的数据的方差S2，可以表示为：
S2＝((x1-M)2+(x2-M)2+…(xn-M)2)/n，
其中，x1、x2、…、xn分别为对应该像素点的第1帧，第2帧，…第n帧数据，M为该像素点N帧数据的均值；
第二部分为求多帧数据中同一个像素点数据的冒点值V，可以表示为：
V＝max(x1，x2，…，xn)-min(x1，x2，…，xn)。
S805，噪声判断。
其中，噪声的判断可以分为两项：
其一为判断每个像素点的方差S2和冒点V是否小于阈值LimVar和LimJit，如果两者均小于对应的阈值，则判定该像素点的噪声测试通过(pass)；否则失败(fail)，并且计数器FailNum加1：
S2≥LimVar or V≥LimJit：fail；FailNum++；
S2<LimVar and V<LimJit：pass；
其二为一个像素矩阵中噪声测试失败的像素点的数目是否大于阈值LimNum，如果小于阈值LimNum，则判定该像素矩阵对应的DUT噪声测试通过(pass)，否则失败(fail)。
FailNum≥LimNum：fail；
FailNum<LimNum：pass。
S806，输出结果。
也就是说，噪声判断模块将噪声测试结果送入数据收发模块，其次数据收发模块按照接口协议将结果上传到ATE。
根据本发明实施例的数据采集芯片的测试装置的控制方法，根据多帧采样数据计算多个数据采样点的噪声，以通过计算多个数据采样点的噪声得到噪声测试结果，从而将噪声测试结果上传至上位机，减少了测试时间，提高了芯片测试的效率，并且通过求方差以及冒点计算完成噪声计算，提高了芯 片测试准确率，降低了芯片测试的成本，更好地保证测试的可靠性。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征 进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (10)

  1. 一种数据采集芯片的测试装置，其特征在于，所述数据采集芯片包括多个数据采样点，所述测试装置包括：
    数据采集模块，所述数据采集模块与数据采集芯片相连，接收所述数据采集芯片采集的多帧采样数据；
    存储模块，所述存储模块用于存储所述多帧采样数据；
    处理模块，所述处理模块用于根据所述多帧采样数据计算所述多个数据采样点的噪声，以得到噪声测试结果；
    数据收发模块，所述数据收发模块用于将所述噪声测试结果上传至上位机；以及
    控制模块，所述控制模块用于对所述数据采集模块、所述存储模块、所述处理模块和所述数据收发模块进行控制。
  2. 根据权利要求1所述的数据采集芯片的测试装置，其特征在于，所述数据采集芯片为指纹识别芯片。
  3. 根据权利要求1所述的数据采集芯片的测试装置，其特征在于，所述存储模块包括：
    存储器模块，用于存储所述多帧采样数据；
    存储器控制模块，所述存储器控制模块分别与所述存储器模块和所述控制模块相连，以在所述控制模块的控制下控制所述存储器模块进行多帧采样数据的读写。
  4. 根据权利要求1所述的数据采集芯片的测试装置，其特征在于，所述多帧采样数据中每一帧采样数据包括多个数据采样点的采样值，
    所述处理模块包括：
    计算单元模块，所述计算单元模块与所述控制模块相连，以计算多帧采样数据中每个数据采样点的多个采样值的方差，以及多帧采样数据中每个数据采样点的多个采样值的冒点值；
    噪声判断模块，所述噪声判断模块与所述计算单元模块相连，用于判断每个数据采样点对应的方差是否小于预定方差以及每个数据采样点对应的冒点值是否小于预定冒点值，以判断所述每个数据采样点的噪声测试是否通过，进而得到噪声测试结果。
  5. 根据权利要求1所述的数据采集芯片的测试装置，其特征在于，所 述数据采集模块具有缓存，用于缓存所述多帧采样数据。
  6. 根据权利要求1所述的数据采集芯片的测试装置，其特征在于，所述测试装置还包括开关模块，所述开关模块包括一个或多个开关，所述数据采集芯片包括一个或多个，一个或多个数据采集芯片一一对应地与一个或多个开关相连；
    所述数据采集模块在所述开关模块闭合后，接收所述数据采集芯片采集的多帧采样数据。
  7. 一种数据采集芯片的测试系统，其特征在于，包括：
    如权利要求1-6任一项所述的数据采集芯片的测试装置；
    自动测试设备ATE，所述ATE与所述数据采集芯片的测试装置相连；
    PC机，所述PC机与所述ATE相连，所述PC机通过所述ATE得到所述数据采集芯片的测试装置上传的噪声测试结果，进而根据所述噪声测试结果对所述数据采集芯片进行相应的操作。
  8. 一种数据采集芯片的测试装置的控制方法，其特征在于，所述数据采集芯片包括多个数据采样点，包括以下步骤：
    接收数据采集芯片采集的多帧采样数据，并存储所述多帧采样数据；
    根据所述多帧采样数据计算多个数据采样点的噪声，以得到噪声测试结果；以及
    将所述噪声测试结果上传至上位机。
  9. 根据权利要求8所述的数据采集芯片的测试装置的控制方法，其特征在于，所述多帧采样数据中每一帧采样数据包括多个数据采样点的采样值，所述根据所述多帧采样数据计算多个数据采样点的噪声，以得到噪声测试结果，进一步包括：
    计算多帧采样数据中每个数据采样点的多个采样值的方差，以及多帧采样数据中每个数据采样点的多个采样值的冒点值；
    判断每个数据采样点对应的方差是否小于预定方差以及每个数据采样点对应的冒点值是否小于预定冒点值，以判断所述每个数据采样点的噪声测试是否通过，进而得到噪声测试结果。
  10. 根据权利要求8所述的数据采集芯片的测试装置的控制方法，其特征在于，在所述接收数据采集芯片采集的多帧采样数据之后，还包括：
    对所述多帧采样数据进行缓存。
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