WO2017124576A1 - 一种基于自偏置共源共栅结构的跨导放大器 - Google Patents

一种基于自偏置共源共栅结构的跨导放大器 Download PDF

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WO2017124576A1
WO2017124576A1 PCT/CN2016/072178 CN2016072178W WO2017124576A1 WO 2017124576 A1 WO2017124576 A1 WO 2017124576A1 CN 2016072178 W CN2016072178 W CN 2016072178W WO 2017124576 A1 WO2017124576 A1 WO 2017124576A1
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transistor
pmos
nmos
drain
input
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PCT/CN2016/072178
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English (en)
French (fr)
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徐代果
胡刚毅
李儒章
王健安
陈光炳
王育新
刘涛
刘璐
邓民明
石寒夫
王旭
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中国电子科技集团公司第二十四研究所
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Priority to US16/625,671 priority Critical patent/US11121677B1/en
Publication of WO2017124576A1 publication Critical patent/WO2017124576A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
    • H03F3/45488—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by using feedback means
    • H03F3/45493—Measuring at the loading circuit of the differential amplifier
    • H03F3/45497—Controlling the input circuit of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0035—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
    • H03G1/007—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using FET type devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification

Definitions

  • the invention belongs to the field of analog or digital-analog hybrid integrated circuit technology, and in particular relates to a transconductance amplifier based on a self-biased cascode structure.
  • the method used includes using a low threshold tube or providing an additional bias voltage for the MOS tube, but this increases the complexity of the process or circuit design; on the other hand, the conventional compensation In this way, it is difficult to increase the unity gain bandwidth while the amplifier achieves high gain. Therefore, several conventional structures are difficult to meet the requirements of high performance transconductance amplifiers.
  • FIG. 1 shows a schematic diagram of a conventional two-stage transconductance amplifier. Since the PMOS tube is used as the input tube, it has the advantages of excellent matching and low noise, so it is not high speed and low. For noise applications, a PMOS transistor is typically used as the input transistor for the transconductance amplifier.
  • the input signals VIP and VIN are input from the gates of the PMOS input transistors M1 and M2, and the PMOS transistors M1 and M2 and the NMOS transistors M3 and M4 both operate in a saturation region, thereby enabling the first stage amplifier to provide a large DC.
  • the gain, second-stage common-source amplifier consists of an NMOS transistor M5 and a PMOS transistor M6. This structure provides a large output swing while maintaining a certain gain.
  • Capacitor C C and resistor R C form an RC compensation structure that allows the amplifier to achieve a certain unity gain bandwidth while remaining stable.
  • the amplifier gain expression is:
  • Fig. 1 The advantage of the structure of Fig. 1 is that the circuit structure is simple.
  • the inventors of the present application have found that, due to the use of RC compensation, a large compensation phase RC is required to obtain a low frequency left half plane zero point; meanwhile, due to the standard process, the resistance The resistance of the resistance is poor, and it is difficult to obtain a relatively fixed left half plane zero.
  • FIG. 2 shows a schematic diagram of a self-biased cascode transconductance amplifier.
  • PMOS input transistors M1, M2, M3 and M4 form a self-offset.
  • the source common gate input stage structure at the same time, the PMOS transistors M0, M8, M9 and M10 form a constant current source structure.
  • the structure is characterized in that the threshold voltage is changed by specifically setting the substrate voltages of the PMOS transistors M3 and M4 and the PMOS transistors M8 and M10, thereby achieving the purpose of increasing the output impedance thereof.
  • the working principle of the PMOS tube M1 and M3 is designed to be the same as the width of the PMOS tube M1 in FIG.
  • the sum of the lengths is designed to be the same as the length of the PMOS tube M1 in Fig. 1, so that the input tube M1 in Fig. 1 and the input tubes M1 and M3 in Fig. 2 occupy the same layout area.
  • the PMOS tube M2 and M4, M8 and M9 and other self-biased cascode MOS tube sizes adopt the same design method, and the PMOS tube is made by the method mentioned above.
  • the threshold voltages of M3 and M4 are less than the threshold voltages of M1 and M2, and the half-circuit circuit is analyzed under a certain input voltage VIN/VIP:
  • Vthp3 and Vthp1 are the threshold voltages of the PMOS transistors M3 and M1, respectively, and V S3 is the source voltage of the PMOS transistor M3. If the appropriate threshold voltage and the input voltage are set so that the equation (2) is satisfied, then the PMOS transistor M1 and M3 can work in the saturation zone.
  • Gain [2] g m1,2 ⁇ ((g m3 ⁇ r o3 ⁇ r o1 )
  • the amplifier shown in Fig. 2 has a certain improvement in DC gain compared to the amplifier shown in Fig. 1.
  • the inventors of the present application have found that the circuit structure shown in FIG. 2 requires the use of a low threshold tube exclusively, or provides a bias voltage VCM, which increases the process or circuit complexity; on the other hand, the amplifier structure shown in FIG. The RC compensation method is still adopted, and the compensation effect is limited.
  • the present invention provides a transconductance amplifier based on a self-biased cascode structure, which further improves the DC gain of the amplifier without increasing the process or circuit complexity. Achieving a larger unity gain bandwidth to achieve a higher quality factor can effectively solve the problems of traditional structures.
  • a transconductance amplifier based on a self-biased cascode structure comprising a self-biased cascode input stage structure composed of PMOS input transistors M1, M2, M3 and M4, and NMOS tubes M5, M6, M7 and M8 Self-biased cascode first-stage load structure, second-stage common-source amplifier structure composed of NMOS transistor M9 and PMOS transistor M10, bias circuit structure composed of NMOS transistors M11, M12 and PMOS transistor M13, amplifier compensation capacitor C C , an amplifier load capacitance C L , a reference current source Iref, and a PMOS transistor M0 providing a constant current source function;
  • the sources of the PMOS input transistors M1 and M2 are connected to the drain of the PMOS transistor M0, the gates of the PMOS input transistors M1 and M3 are connected to the input signal VIN, and the gates of the PMOS input transistors M2 and M4 are connected to the input signal VIP, and the PMOS input transistor
  • the drain of M1 is connected to the source of the PMOS input transistor M3, the drain of the PMOS input transistor M2 is connected to the source of the PMOS input transistor M4, and the substrate of the PMOS input transistors M3 and M4 is connected to the bias voltage Vp, and the bias voltage Vp is The gate voltage of the PMOS transistor M13 connected to the gate and drain in the amplifier bias circuit is provided;
  • the gate and the drain of the NMOS transistor M5 are connected to the gates of the NMOS transistors M6, M7, M8 and the drain of the PMOS input transistor M3, and the drain of the NMOS transistor M6 is connected to the drain of the PMOS input transistor M4, the NMOS transistor
  • the source of M5 is connected to the drain of NMOS transistor M7
  • the source of NMOS transistor M6 is connected to the drain of NMOS transistor M8, the source of NMOS transistors M7 and M8 is grounded
  • the substrate of NMOS transistors M5 and M6 is connected to bias voltage Vn.
  • the bias voltage Vn is provided by the gate voltage of the NMOS transistor M11 connected to the gate drain in the amplifier bias circuit;
  • the sources of the PMOS transistors M10, M0, and M13 are connected to the power supply voltage vdd, the gates of the PMOS transistors M10 are connected to the gates of the PMOS transistors M0 and M13, the drain of the PMOS transistor M10, the end of the compensation capacitor Cc, and the NMOS transistor M9.
  • connection node is the output terminal Vout of the transconductance amplifier
  • the other end of the compensation capacitor Cc is connected to the drain of the PMOS input transistor M2
  • the load capacitance C L The other end is connected to the source of the NMOS transistor M9, and the gate of the NMOS transistor M9 is connected to the drain of the PMOS input transistor M4;
  • the drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M12, the gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and the gate and drain of the NMOS transistor M11.
  • the source of the NMOS transistors M11 and M12 is grounded, and the other end of the reference current source Iref is connected to the power supply voltage vdd.
  • the input tube and the load tube of the first-stage amplifier adopt a self-biased cascode structure, which is obviously improved compared with the conventional structure.
  • the output impedance of the primary amplifier increases the DC gain of the first stage amplifier; the PMOS transistors M3 and M4 of the first stage amplifier and the substrate voltages of the NMOS transistors M5 and M6 are provided by the amplifier bias circuit, and no external bias voltage is required.
  • the compensation capacitor Cc is connected in such a way that the transfer function of the amplifier generates a zero point in the left half plane, and the zero point of the left half plane can be used to compensate the first non-primary pole of the transfer function, thus maintaining a large phase At the same time, the unity gain bandwidth of the amplifier is greatly increased, thereby achieving a higher quality factor.
  • the ratio of the channel lengths of the PMOS input transistors M1 and M3 is 1:4, and the ratio of the channel lengths of the NMOS transistors M5 and M7 is 1:4.
  • the capacitance of the compensation capacitor Cc is 2 to 4 pF.
  • the invention also discloses a transimpedance amplifier based on a self-biased cascode structure using an NMOS transistor as an input tube, comprising a self-biased cascode input stage structure composed of NMOS input transistors M1, M2, M3 and M4.
  • PMOS tube M5, M6, M7 and M8 form a self-biased cascode first stage load structure
  • NMOS tube M9 and PMOS tube M10 constitute a second stage common source amplifier structure
  • NMOS tube M11, M12 and PMOS tube M13 constitutes a bias circuit structure, an amplifier compensation capacitor C C , an amplifier load capacitor C L , a reference current source Iref, and a PMOS transistor M0 that provides a constant current source function;
  • the sources of the NMOS input transistors M1 and M2 are grounded, the gates of the NMOS input transistors M1 and M3 are connected to the input signal VIN, the gates of the NMOS input transistors M2 and M4 are connected to the input signal VIP, and the drain of the NMOS input transistor M1 is connected to the NMOS.
  • the source of the input transistor M3, the drain of the NMOS input transistor M2 is connected to the source of the NMOS input transistor M4, and the substrate of the NMOS input transistors M3 and M4 is connected to the bias voltage Vn, and the bias voltage Vn is biased by the amplifier.
  • the gate voltage of the NMOS transistor M11 connected to the gate drain is provided;
  • the gate and the drain of the PMOS transistor M5 are connected to the gates of the PMOS transistors M6, M7, M8 and the drain of the NMOS input transistor M3, and the drain of the PMOS transistor M6 is connected to the drain of the NMOS input transistor M4, the PMOS transistor
  • the source of M5 is connected to the drain of PMOS transistor M7
  • the source of PMOS transistor M6 is connected to the drain of PMOS transistor M8,
  • the source of PMOS transistors M7 and M8 is connected to the drain of PMOS transistor M0, and the substrate of PMOS transistor M5 and M6.
  • a bias voltage Vp which is provided by the gate voltage of the PMOS transistor M13 connected to the gate drain in the amplifier bias circuit;
  • the PMOS transistor M10 source electrode connected to the power supply voltage vdd, L of the PMOS transistor M10 drain end, one end of the compensation capacitance Cc, the drain of the NMOS transistor M9 and the load capacitance C connected to form a connection node, and the connecting node
  • the gate of the PMOS transistor M10 is connected to the drain of the NMOS input transistor M4
  • the other end of the compensation capacitor Cc is connected to the drain of the PMOS input transistor M2
  • the source of the tube M9 is grounded, and the gate of the NMOS transistor M9 is connected to the gate of the NMOS input tube M12;
  • the sources of the PMOS transistors M0 and M13 are connected to the power supply voltage vdd, the gate of the PMOS transistor M0 is connected to the gate and the drain of the PMOS transistor M13, the drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M12, and the drain of the NMOS transistor M12 is The gate is connected to one end of the reference current source Iref and the gate and drain of the NMOS transistor M11, the sources of the NMOS transistors M11 and M12 are grounded, and the other end of the reference current source Iref is connected to the power supply voltage vdd.
  • the ratio of the channel lengths of the NMOS input transistors M1 and M3 is 1:4, and the ratio of the channel lengths of the PMOS transistors M5 and M7 is 1:4.
  • the capacitance of the compensation capacitor Cc is 2 to 4 pF.
  • Figure 1 is a schematic diagram of a conventional two-stage transconductance amplifier.
  • Figure 2 is a schematic diagram of a conventional self-biased cascode transconductance amplifier.
  • FIG. 3 is a schematic diagram of a small signal equivalent circuit of the self-biased cascode structure of FIG.
  • FIG. 4 is a schematic diagram of a transconductance amplifier based on a self-biased cascode structure provided by the present invention.
  • FIG. 5 is a small signal equivalent circuit of the transconductance amplifier based on the self-biased cascode structure of FIG.
  • FIG. 6 is a schematic diagram of the variation of the AC characteristic of the self-biased cascode transconductance amplifier with the compensation capacitor Cc according to FIG.
  • FIG. 7 is a schematic diagram of comparison of simulation results of three structural AC characteristics of FIG. 1, FIG. 2 and FIG.
  • FIG. 8 is a schematic diagram of another transconductance amplifier based on a self-biased cascode structure provided by the present invention.
  • the present invention provides a self-biased cascode input stage structure composed of a PMOS input transistor M1, M2, M3, and M4, which is based on a self-biased cascode structure.
  • NMOS tube M5, M6, M7 and M8 form a self-biased cascode first stage load structure
  • NMOS tube M9 and PMOS tube M10 form a second stage common source amplifier structure
  • NMOS tube M11, M12 and PMOS tube M13 a bias circuit structure
  • an amplifier compensation capacitor C C an amplifier load capacitor C L
  • a reference current source Iref a PMOS transistor M0 that provides a constant current source function
  • the PMOS input transistors M1, M2, M3 and M4 form a self-biased cascode structure, which provides a higher output impedance while maintaining a large transconductance, the PMOS transistors M1 and M3 are connected in series, and the PMOS transistors M2 and M4 are connected in series.
  • the sources of the PMOS input transistors M1 and M2 are connected to the drain of the PMOS transistor M0, and the gates of the PMOS input transistors M1 and M3 are connected to the input signal VIN.
  • the gates of the PMOS input transistors M2 and M4 are connected to the input signal VIP, the drain of the PMOS input transistor M1 is connected to the source of the PMOS input transistor M3, the drain of the PMOS input transistor M2 is connected to the source of the PMOS input transistor M4, and the PMOS input transistor M3 And the substrate of M4 is connected to a bias voltage Vp, which is provided by the gate voltage of the PMOS transistor M13 connected to the gate drain in the amplifier bias circuit;
  • the NMOS transistors M5, M6, M7 and M8 form a self-biased cascode structure to provide high output impedance, the NMOS transistors M5 and M7 are connected in series, the NMOS transistors M6 and M8 are connected in series, and the gate and the drain of the NMOS transistor M5 are both Connected to the gates of the NMOS transistors M6, M7, M8 and the drain of the PMOS input transistor M3, the drain of the NMOS transistor M6 is connected to the drain of the PMOS input transistor M4, and the source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M7.
  • the source of the NMOS transistor M6 is connected to the drain of the NMOS transistor M8, the source of the NMOS transistors M7 and M8 is grounded, and the substrate of the NMOS transistors M5 and M6 is connected to the bias voltage Vn, which is biased by the amplifier bias circuit.
  • the gate voltage of the NMOS transistor M11 connected to the drain is provided;
  • the sources of the PMOS transistors M10, M0, and M13 are connected to the power supply voltage vdd, the gates of the PMOS transistors M10 are connected to the gates of the PMOS transistors M0 and M13, the drain of the PMOS transistor M10, the end of the compensation capacitor Cc, and the NMOS transistor M9.
  • connection node is the output terminal Vout of the transconductance amplifier
  • the other end of the compensation capacitor Cc is connected to the drain of the PMOS input transistor M2
  • the load capacitance C L The other end is connected to the source of the NMOS transistor M9, and the gate of the NMOS transistor M9 is connected to the drain of the PMOS input transistor M4;
  • the drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M12, the gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and the gate and drain of the NMOS transistor M11, and the sources of the NMOS transistors M11 and M12 are grounded.
  • the other end of the reference current source Iref is connected to the power supply voltage vdd.
  • the invention provides a self-biased cascode structure based transconductance amplifier, and the input tube and the load tube of the first stage amplifier adopt a self-biased cascode structure, and the traditional structure phase
  • the output impedance of the first-stage amplifier is significantly increased, and the DC gain of the first-stage amplifier is increased; the substrate voltages of the PMOS transistors M3 and M4 of the first-stage amplifier and the NMOS transistors M5 and M6 are provided by the amplifier bias circuit.
  • the compensation capacitor Cc is connected in such a way that the transfer function of the amplifier produces a zero point in the left half plane, and the zero point of the left half plane can be used to compensate for the first non-primary pole of the transfer function. Therefore, while maintaining a large phase margin, the unity gain bandwidth of the amplifier is greatly increased, thereby achieving a higher quality factor.
  • the half-side circuit is analyzed, and the channel widths of the PMOS transistors M1 and M3 in FIG. 4 are both designed to be the same as the width of the PMOS transistor M1 in FIG. 1, and the sum of the channel lengths of the PMOS transistors M1 and M3 in FIG. 4 is designed as The lengths of the PMOS transistors M1 in FIG. 1 are the same; on the other hand, the channel widths of the NMOS transistors M5 and M7 in FIG. 4 are both designed to be the same as the width of the NMOS transistor M3 in FIG. 1, and the NMOS transistor M5 of FIG. The sum of the channel lengths of M7 is designed to be the same as the length of the NMOS transistor M3 in Fig.
  • the input pipe M1 and the load pipe M3 in Fig. 1 and the input pipes M1 and M3 in Fig. 4 and the load pipes M5 and M7 are The area of the layout is the same.
  • the DC gain of the amplifier in FIG. 4 can be expressed as:
  • Gain [proposed] g m1,2 ⁇ ((g m3 ⁇ r o1 ⁇ r o3)
  • the DC gain of the transconductance amplifier structure based on the self-biased cascode structure shown in FIG. 4 is significantly larger than that shown in FIG.
  • the ratio of the channel lengths of the PMOS input transistors M1 and M3 is 1:4
  • the NMOS The ratio of the channel lengths of the tubes M5 and M7 is also 1:4.
  • gm 5 ⁇ r o5 ⁇ r o7 is the small-signal equivalent output impedance of the NMOS transistors M5 and M7 of the series structure shown in Fig. 4, which can be obtained by solving the equation (7).
  • the small signal equivalent circuit transfer function has a left half plane zero point, and its expression is:
  • k is a constant, and it is known from the equation (8) that in the transfer function of the circuit structure of the present invention, there is a left half plane zero point, and the left half plane zero point increases with the compensation capacitor Cc. It will move to the low frequency, and its specific change trend is shown in Figure 6. It can be seen from FIG. 6 that as the compensation capacitor Cc increases, the amplitude-frequency characteristic and the phase-frequency characteristic of the circuit structure shown in the present invention are upwardly lifted, which indicates that the simulation result is consistent with the previous theoretical derivation. This left half-plane zero can therefore be used to compensate for the first non-primary pole of the transfer function, such that the circuit structure of the present invention can achieve a larger unity gain bandwidth.
  • the above three structures are carefully designed in a 0.18 ⁇ m CMOS process, and the same input/output tube and load tube size are used, and the compensation capacitor Cc is taken as 2 pF, and the load is taken. The capacitance is taken at 15pF.
  • the comparison results of the simulation results of the AC characteristics of the three structures are shown in Fig. 7.
  • the solid line represents the simulation result of the AC characteristic of the present invention
  • the broken line represents the simulation result of the AC characteristic of the structure of Fig. 2
  • the centerline represents the simulation results of the AC characteristics of the structure of Figure 1.
  • the present invention has a significantly higher DC gain than the conventional structures 1 and 2, since the input and load tubes of the first stage both employ a self-biased cascode structure.
  • the compensation method used due to the compensation method used, a left half-plane zero is generated, the unity-gain bandwidth is significantly increased, and a larger phase margin can be obtained. (Phase margin);
  • the compensation capacitor Cc to be used in the present invention has a smaller area and saves area.
  • the basic parameters of the three structures are shown in Table 1.
  • the low self-biased transconductance amplifier structure proposed by the present invention is compared with the conventional two structures. With the same power consumption, the DC gain is increased by at least 26%, the unity-gain bandwidth is increased by at least 140%, and the quality factor (FOM) is increased by at least 210%.
  • Parameter Structure 1 Structure 2 this invention Power supply(V) 1.8 1.8 1.8 Technology( ⁇ m) 0.18 0.18 0.18 Capacitive load(pF) 15 15 15 15 Unity-gain bandwidth(MHz) 56 60 146 Phase margin (°) 60 63 71 DC gain (dB) 71 76 96 Power consumption ( ⁇ W) 720 720 720 FOM (dB.MHz/ ⁇ W) 5.5 6.3 19.5
  • the capacitance of the compensation capacitor Cc is 2 to 4 pF, so that a better compensation effect can be achieved without occupying too large a chip area.
  • the structure shown in FIG. 4 is a structure in which a PMOS transistor is used as an input tube. It is also known that all the analysis of the present invention is equally applicable to the case where an NMOS transistor is used as an input tube, and the principle diagram thereof is as shown in FIG. Accordingly, the present invention also discloses a self-biased cascode-based transconductance amplifier using an NMOS transistor as an input transistor, including a self-biased cascode composed of NMOS input transistors M1, M2, M3, and M4.
  • Input stage structure self-biased cascode first stage load structure composed of PMOS tubes M5, M6, M7 and M8, second stage common source amplifier structure composed of NMOS tube M9 and PMOS tube M10, NMOS tubes M11, M12 a bias circuit structure formed by the PMOS transistor M13, an amplifier compensation capacitor C C , an amplifier load capacitor C L , a reference current source Iref, and a PMOS transistor M0 providing a constant current source function;
  • the sources of the NMOS input transistors M1 and M2 are grounded, the gates of the NMOS input transistors M1 and M3 are connected to the input signal VIN, the gates of the NMOS input transistors M2 and M4 are connected to the input signal VIP, and the drain of the NMOS input transistor M1 is connected to the NMOS.
  • the source of the input transistor M3, the drain of the NMOS input transistor M2 is connected to the source of the NMOS input transistor M4, and the substrate of the NMOS input transistors M3 and M4 is connected to the bias voltage Vn, which is biased by the amplifier bias circuit
  • the gate voltage of the NMOS transistor M11 connected to the drain is provided;
  • the gate and the drain of the PMOS transistor M5 are connected to the gates of the PMOS transistors M6, M7, M8 and the drain of the NMOS input transistor M3, and the drain of the PMOS transistor M6 is connected to the drain of the NMOS input transistor M4, the PMOS transistor
  • the source of M5 is connected to the drain of PMOS transistor M7
  • the source of PMOS transistor M6 is connected to the drain of PMOS transistor M8,
  • the source of PMOS transistors M7 and M8 is connected to the drain of PMOS transistor M0, and the substrate of PMOS transistor M5 and M6.
  • a bias voltage Vp which is provided by the gate voltage of the PMOS transistor M13 connected to the gate drain in the amplifier bias circuit;
  • the PMOS transistor M10 source electrode connected to the power supply voltage vdd, L of the PMOS transistor M10 drain end, one end of the compensation capacitance Cc, the drain of the NMOS transistor M9 and the load capacitance C connected to form a connection node, and the connecting node
  • the gate of the PMOS transistor M10 is connected to the drain of the NMOS input transistor M4
  • the other end of the compensation capacitor Cc is connected to the drain of the PMOS input transistor M2
  • the source of the tube M9 is grounded, and the gate of the NMOS transistor M9 is connected to the gate of the NMOS input tube M12;
  • the sources of the PMOS transistors M0 and M13 are connected to the power supply voltage vdd, the gate of the PMOS transistor M0 is connected to the gate and the drain of the PMOS transistor M13, the drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M12, and the drain of the NMOS transistor M12 is The gate is connected to one end of the reference current source Iref and The gate and the drain of the NMOS transistor M11, the sources of the NMOS transistors M11 and M12 are grounded, and the other end of the reference current source Iref is connected to the power supply voltage vdd.
  • the structure shown in FIG. 8 is similar to the structure shown in FIG. 4 except that the NMOS transistor is used as the input tube, and details are not described herein again.
  • the channel length ratio of the PMOS input transistors M1 and M3 is 1:4.
  • the channel length ratio of the NMOS transistors M5 and M7 is 1:4.
  • the capacitance of the compensation capacitor Cc is 2 to 4 pF, so that a better compensation effect can be achieved without occupying too large a chip area.

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Abstract

一种基于自偏置共源共栅结构的跨导放大器，包括PMOS输入管M1、M2、M3和M4构成的自偏置共源共栅输入级结构，NMOS管M5、M6、M7和M8构成的自偏置共源共栅第一级负载结构，NMOS管M9和PMOS管M10构成的第二级共源放大器结构，NMOS管M11、M12和PMOS管M13构成的偏置电路结构，放大器补偿电容C C，放大器负载电容C L，基准电流源Iref和提供恒流源功能的PMOS管M0。上述技术方案的第一级放大器的输入管和负载管均采用了自偏置共源共栅结构，提高了第一级放大器的输出阻抗，增加了第一级放大器的直流增益；补偿电容Cc的连接方式，实现了更高的质量因数。

Description

一种基于自偏置共源共栅结构的跨导放大器 技术领域
本发明属于模拟或数模混合集成电路技术领域，具体涉及一种基于自偏置共源共栅结构的跨导放大器。
背景技术
近年来，随着集成电路制造技术的不断发展，对低功耗模拟集成电路的需要逐渐增加，为了适应低功耗的要求，电源电压进一步降低。针对这一趋势，为了保证放大器的工作性能，发展出来一些提高跨导放大器增益的结构，其中，自偏置共源共栅结构就是一种。在这种结构下，通过调节MOS管的衬底电压，改变MOS管的阈值电压，从而改变MOS管的跨导和输出阻抗，这样，跨导放大器就可以获得比常规结构更高的增益。传统结构下，如果需要改变MOS管的阈值电压，采用的方法包括使用低阈值管或为MOS管提供额外偏置电压，但这会增加工艺或者电路设计的复杂度；另一方面，传统的补偿方式，很难在放大器实现高增益的同时，提高单位增益带宽。因此，传统的几种结构，很难满足高性能跨导放大器的要求。
为了更详细的描述上述技术问题，本申请先来分析两种传统结构跨导放大器的工作原理和优缺点。请参考图1所示的结构1，其给出了一种传统两级跨导放大器原理图，由于当采用PMOS管作为输入管时，具有匹配性优良和低噪声等优点，所以在非高速低噪声应用的场合通常采用PMOS管作为跨导放大器的输入管。结构1中，输入信号VIP和VIN从PMOS输入管M1和M2的栅极输入，PMOS管M1和M2和NMOS管M3和M4都工作在饱和区，从而使得第一级 放大器能提供较大的直流增益，第二级共源放大器由NMOS管M5和PMOS管M6构成，这种结构在保持一定增益的同时，能够提供较大的输出摆幅。电容CC和电阻RC构成一个RC补偿结构，使得放大器在保持稳定的情况下，能够获得一定的单位增益带宽。在图1所示的结构下，放大器增益表达式为：
Gain[1]＝gm1,2·(ro2||ro4)·gm5·(ro5||ro6)  (1)
图1结构的优点是电路结构简单，但是，本申请的发明人研究发现，由于采用RC补偿，要获得一个低频的左半平面零点需要很大的补偿电阻RC；同时，由于标准工艺下，电阻的阻值一致性较差，很难获得相对固定的左半平面零点。
请参考图2所示的结构2，其给出了一种自偏置共源共栅跨导放大器原理图，在结构2中，PMOS输入管M1、M2、M3和M4构成了自偏置共源共栅输入级结构，同时，由PMOS管M0、M8、M9和M10构成恒流源结构。该结构的特点在于，通过专门设置PMOS管M3和M4以及PMOS管M8和M10的衬底电压来改变其阈值电压，从而实现提高其输出阻抗的目的。下面分析其工作原理，以图2中输入级PMOS管为例，将PMOS管M1和M3的沟道宽度设计成和图1中PMOS管M1的宽度相同，同时将PMOS管M1和M3的沟道长度之和设计成和图1中PMOS管M1的长度相同，这样，图1中的输入管M1与图2中的输入管M1和M3所占版图面积相同。在图2所示的结构中，PMOS管M2和M4、M8和M9等其他几处自偏置共源共栅结构MOS管尺寸采用同样的设计方法，通过前面所提到的方法，使得PMOS管M3和M4的阈值电压小于M1和M2的阈值电压，分析半边电路，在一定的输入电压VIN/VIP之下：
VIN+|Vthp3|<VS3<VIN+|Vthp1|  (2)
其中，Vthp3和Vthp1分别为PMOS管M3和M1的阈值电压， VS3为PMOS管M3的源极电压，如果设置合适的阈值电压和输入电压，使得式(2)得到满足，那么PMOS管M1和M3都可以工作在饱和区。
下面分析在式(2)得到满足的情况下，自偏置共源共栅结构的输出阻抗，其小信号等效电路图如图3所示，对其列节点KCL方程如下：
Figure PCTCN2016072178-appb-000001
解上述方程可得：
Req＝gm3·ro1·ro3+ro1+ro3≈gm3·ro1·ro3  (4)
因此，图2所示结构的增益表达式为：
Gain[2]＝gm1,2·((gm3·ro3·ro1)||ro5)·gm7·((gm8·ro8·ro9)||ro7)  (5)
由(5)式可知，图2所示放大器相比于图1所示放大器，其直流增益有一定程度的提高。但是，本申请的发明人研究发现，图2所示电路结构需要专门使用低阈值管，或者提供一个偏置电压VCM，这会增加工艺或者电路复杂度；另一方面，图2所示放大器结构仍然采用RC补偿方式，其补偿效果有限。
发明内容
针对现有技术存在的技术问题，本发明提供一种基于自偏置共源共栅结构的跨导放大器，该结构在不增加工艺或者电路复杂度的情况下，进一步提高放大器直流增益，同时可以获得更大的单位增益带宽，从而实现更高的质量因数，可以有效解决传统结构存在的问题。
为了实现上述目的，本发明采用如下技术方案：
一种基于自偏置共源共栅结构的跨导放大器，包括PMOS输入管M1、M2、M3和M4构成的自偏置共源共栅输入级结构，NMOS管M5、M6、M7和M8构成的自偏置共源共栅第一级负载结构，NMOS 管M9和PMOS管M10构成的第二级共源放大器结构，NMOS管M11、M12和PMOS管M13构成的偏置电路结构，放大器补偿电容CC，放大器负载电容CL，基准电流源Iref和提供恒流源功能的PMOS管M0；其中，
所述PMOS输入管M1和M2的源极接PMOS管M0的漏极，PMOS输入管M1和M3的栅极接输入信号VIN，PMOS输入管M2和M4的栅极接输入信号VIP，PMOS输入管M1的漏极接PMOS输入管M3的源极，PMOS输入管M2的漏极接PMOS输入管M4的源极，PMOS输入管M3和M4的衬底接偏置电压Vp，该偏置电压Vp由放大器偏置电路中栅漏相连的PMOS管M13的栅压提供；
所述NMOS管M5的栅极和漏极均与NMOS管M6、M7、M8的栅极以及PMOS输入管M3的漏极连接，NMOS管M6的漏极接PMOS输入管M4的漏极，NMOS管M5的源极接NMOS管M7的漏极，NMOS管M6的源极接NMOS管M8的漏极，NMOS管M7和M8的源极接地，NMOS管M5和M6的衬底接偏置电压Vn，该偏置电压Vn由放大器偏置电路中栅漏相连的NMOS管M11的栅压提供；
所述PMOS管M10、M0、M13的源极接电源电压vdd，PMOS管M10的栅极接PMOS管M0和M13的栅极，PMOS管M10的漏极、补偿电容Cc的一端、NMOS管M9的漏极和负载电容CL的一端相互连接形成一个连接节点，且该连接节点为所述跨导放大器的输出端Vout，补偿电容Cc的另一端接PMOS输入管M2的漏极，负载电容CL的另一端和NMOS管M9的源极接地，NMOS管M9的栅极接PMOS输入管M4的漏极；
所述PMOS管M13的漏极接NMOS管M12的漏极，NMOS管M12的栅极接基准电流源Iref的一端以及NMOS管M11的栅极和漏 极，NMOS管M11和M12的源极接地，基准电流源Iref的另一端接电源电压vdd。
本发明提供的基于自偏置共源共栅结构的跨导放大器，第一级放大器的输入管和负载管均采用了自偏置共源共栅结构，和传统结构相比，明显提高了第一级放大器的输出阻抗，增加了第一级放大器的直流增益；第一级放大器的PMOS管M3和M4以及NMOS管M5和M6的衬底电压由放大器偏置电路提供，不需要外加偏置电压；另外，补偿电容Cc的连接方式，使得放大器的传输函数会产生一个左半平面的零点，可以用这个左半平面的零点来补偿传输函数的第一个非主极点，因此在保持较大相位裕度的同时，大幅度提高了放大器的单位增益带宽，从而实现更高的质量因数。
进一步，所述PMOS输入管M1和M3的沟道长度之比为1：4，所述NMOS管M5和M7的沟道长度之比为1：4。
进一步，所述补偿电容Cc的电容值为2～4pF。
本发明还公开一种采用NMOS管作为输入管的基于自偏置共源共栅结构的跨导放大器，包括NMOS输入管M1、M2、M3和M4构成的自偏置共源共栅输入级结构，PMOS管M5、M6、M7和M8构成的自偏置共源共栅第一级负载结构，NMOS管M9和PMOS管M10构成的第二级共源放大器结构，NMOS管M11、M12和PMOS管M13构成的偏置电路结构，放大器补偿电容CC，放大器负载电容CL，基准电流源Iref和提供恒流源功能的PMOS管M0；其中，
所述NMOS输入管M1和M2的源极接地，NMOS输入管M1和M3的栅极接输入信号VIN，NMOS输入管M2和M4的栅极接输入信号VIP，NMOS输入管M1的漏极接NMOS输入管M3的源极，NMOS输入管M2的漏极接NMOS输入管M4的源极，NMOS输入管M3和M4的衬底接偏置电压Vn，该偏置电压Vn由放大器偏置电 路中栅漏相连的NMOS管M11的栅压提供；
所述PMOS管M5的栅极和漏极均与PMOS管M6、M7、M8的栅极以及NMOS输入管M3的漏极连接，PMOS管M6的漏极接NMOS输入管M4的漏极，PMOS管M5的源极接PMOS管M7的漏极，PMOS管M6的源极接PMOS管M8的漏极，PMOS管M7和M8的源极接PMOS管M0的漏极，PMOS管M5和M6的衬底接偏置电压Vp，该偏置电压Vp由放大器偏置电路中栅漏相连的PMOS管M13的栅压提供；
所述PMOS管M10的源极接电源电压vdd，PMOS管M10的漏极、补偿电容Cc的一端、NMOS管M9的漏极和负载电容CL的一端相互连接形成一个连接节点，且该连接节点为所述跨导放大器的输出端Vout，PMOS管M10的栅极接NMOS输入管M4的漏极，补偿电容Cc的另一端接PMOS输入管M2的漏极，负载电容CL的另一端和NMOS管M9的源极接地，NMOS管M9的栅极接NMOS输入管M12的栅极；
所述PMOS管M0和M13的源极接电源电压vdd，PMOS管M0的栅极接PMOS管M13的栅极和漏极，PMOS管M13的漏极接NMOS管M12的漏极，NMOS管M12的栅极接基准电流源Iref的一端以及NMOS管M11的栅极和漏极，NMOS管M11和M12的源极接地，基准电流源Iref的另一端接电源电压vdd。
进一步，所述NMOS输入管M1和M3的沟道长度之比为1：4，所述PMOS管M5和M7的沟道长度之比为1：4。
进一步，所述补偿电容Cc的电容值为2～4pF。
附图说明
图1为传统两级跨导放大器原理图。
图2为传统自偏置共源共栅跨导放大器原理图。
图3为图2自偏置共源共栅结构小信号等效电路示意图。
图4为本发明提供的一种基于自偏置共源共栅结构的跨导放大器原理图。
图5为图4基于自偏置共源共栅结构的跨导放大器小信号等效电路。
图6为图4基于自偏置共源共栅跨导放大器交流特性随补偿电容Cc变化趋势示意图。
图7为图1、图2和图4三种结构交流特性仿真结果对比示意图。
图8为本发明提供的另一种基于自偏置共源共栅结构的跨导放大器原理图。
具体实施方式
为了使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解，下面结合具体图示，进一步阐述本发明。
请参考图4所示，本发明提供一种基于自偏置共源共栅结构的跨导放大器，包括PMOS输入管M1、M2、M3和M4构成的自偏置共源共栅输入级结构，NMOS管M5、M6、M7和M8构成的自偏置共源共栅第一级负载结构，NMOS管M9和PMOS管M10构成的第二级共源放大器结构，NMOS管M11、M12和PMOS管M13构成的偏置电路结构，放大器补偿电容CC，放大器负载电容CL，基准电流源Iref和提供恒流源功能的PMOS管M0；其中，
所述PMOS输入管M1、M2、M3和M4构成自偏置共源共栅结构，提供较高输出阻抗的同时保持较大的跨导，PMOS管M1和M3串联，PMOS管M2和M4串联，PMOS输入管M1和M2的源极接PMOS管M0的漏极，PMOS输入管M1和M3的栅极接输入信号VIN， PMOS输入管M2和M4的栅极接输入信号VIP，PMOS输入管M1的漏极接PMOS输入管M3的源极，PMOS输入管M2的漏极接PMOS输入管M4的源极，PMOS输入管M3和M4的衬底接偏置电压Vp，该偏置电压Vp由放大器偏置电路中栅漏相连的PMOS管M13的栅压提供；
所述NMOS管M5、M6、M7和M8构成自偏置共源共栅结构提供高的输出阻抗，NMOS管M5和M7串联，NMOS管M6和M8串联，NMOS管M5的栅极和漏极均与NMOS管M6、M7、M8的栅极以及PMOS输入管M3的漏极连接，NMOS管M6的漏极接PMOS输入管M4的漏极，NMOS管M5的源极接NMOS管M7的漏极，NMOS管M6的源极接NMOS管M8的漏极，NMOS管M7和M8的源极接地，NMOS管M5和M6的衬底接偏置电压Vn，该偏置电压Vn由放大器偏置电路中栅漏相连的NMOS管M11的栅压提供；
所述PMOS管M10、M0、M13的源极接电源电压vdd，PMOS管M10的栅极接PMOS管M0和M13的栅极，PMOS管M10的漏极、补偿电容Cc的一端、NMOS管M9的漏极和负载电容CL的一端相互连接形成一个连接节点，且该连接节点为所述跨导放大器的输出端Vout，补偿电容Cc的另一端接PMOS输入管M2的漏极，负载电容CL的另一端和NMOS管M9的源极接地，NMOS管M9的栅极接PMOS输入管M4的漏极；
所述PMOS管M13的漏极接NMOS管M12的漏极，NMOS管M12的栅极接基准电流源Iref的一端以及NMOS管M11的栅极和漏极，NMOS管M11和M12的源极接地，基准电流源Iref的另一端接电源电压vdd。
本发明提供的基于自偏置共源共栅结构的跨导放大器，第一级放大器的输入管和负载管均采用了自偏置共源共栅结构，和传统结构相 比，明显提高了第一级放大器的输出阻抗，增加了第一级放大器的直流增益；第一级放大器的PMOS管M3和M4以及NMOS管M5和M6的衬底电压由放大器偏置电路提供，不需要外加偏置电压；另外，补偿电容Cc的连接方式，使得放大器的传输函数会产生一个左半平面的零点，可以用这个左半平面的零点来补偿传输函数的第一个非主极点，因此在保持较大相位裕度的同时，大幅度提高了放大器的单位增益带宽，从而实现更高的质量因数。
分析半边电路，将图4中PMOS管M1和M3的沟道宽度均设计成和图1中PMOS管M1的宽度相同，同时将图4中PMOS管M1和M3的沟道长度之和设计成和图1中PMOS管M1的长度相同；另一方面，将图4中NMOS管M5和M7的沟道宽度均设计成和图1中NMOS管M3的宽度相同，同时将图4中NMOS管M5和M7的沟道长度之和设计成和图1中NMOS管M3的长度相同；这样，图1中的输入管M1和负载管M3与图4中的输入管M1和M3以及负载管M5和M7所占版图面积相同。根据对图2所示结构的分析可知，如果合理的分配图4中串联PMOS管M1和M3以及NMOS管M5和M7的沟道长度，图4中放大器的直流增益可表示为：
Gain[proposed]＝gm1,2·((gm3·ro1·ro3)||(gm5·ro5·ro7))·gm9·(ro9||ro10)  (6)
由(6)式可知，图4所示基于自偏置共源共栅结构的跨导放大器结构的直流增益，明显大于图2所示结构。作为一种合理分配图4中串联PMOS管M1和M3以及NMOS管M5和M7沟道长度的具体实施方式，所述PMOS输入管M1和M3的沟道长度之比为1：4，所述NMOS管M5和M7的沟道长度之比也为1：4。
下面来分析图4所示结构的补偿方式，仍然分析半边电路，图4所示结构的小信号等效电路原理图如图5所示，对其列KCL节点方程如下：
Figure PCTCN2016072178-appb-000002
方程组(7)中，gm5·ro5·ro7为图4所示结构串联结构NMOS管M5和M7的小信号等效输出阻抗，通过对方程组(7)求解可得，图5所示小信号等效电路传输函数存在一个左半平面零点，其表达式为：
Figure PCTCN2016072178-appb-000003
其中，在(8)式中，k为常数，由(8)式可知，本发明所示电路结构的传输函数中，存在一个左半平面零点，这个左半平面零点随着补偿电容Cc的增加会向低频移动，其具体变化趋势如图6所示。从图6中可以看到，随着补偿电容Cc的增加，本发明所示电路结构的幅频特性和相频特性均向上翘起，这说明仿真结果和前面的理论推导是符合的。因此可以用这个左半平面零点来补偿传输函数的第一个非主极点，使得本发明所示电路结构可以获得更大的单位增益带宽。
为了进一步验证本发明的上述优点，现以在0.18μm CMOS工艺下，对上述三种结构进行了仔细的设计，并采用相同的输入/输出管和负载管尺寸，补偿电容Cc都取2pF，负载电容都取15pF，最终三种结构的交流特性仿真结果对比图如图7所示；其中，实线代表的是本发明的交流特性仿真结果，虚线代表的是图2结构的交流特性仿真结果，中心线代表的是图1结构的交流特性仿真结果。从图7中可以看出，本发明与传统结构1和2相比，由于第一级的输入管和负载管均采用自偏置共源共栅结构，本发明的直流增(gain)明显提高，同时由于采用的补偿方式产生了一个左半平面零点，单位增益带宽(Unity-gain bandwidth)明显增加，并且能够获得更大的相位裕度 (Phase margin)；换言之，在获得相同单位增益带宽的情况下，本发明需要使用的补偿电容Cc面积更小，更节省面积。
同时，三种结构的基本参数对照结果如下表1所示，从表1所述仿真结果可以看出，本发明所提出的低自偏置跨导放大器结构，和传统的两种结构相比，在功耗相同的情况下，直流增益(DC gain)至少提高26％，单位增益带宽(Unity-gain bandwidth)至少提高140％，质量因数(FOM)至少提高210％。
表1：
Parameter 结构1 结构2 本发明
Power supply(V) 1.8 1.8 1.8
Technology(μm) 0.18 0.18 0.18
Capacitive load(pF) 15 15 15
Unity-gain bandwidth(MHz) 56 60 146
Phase margin(°) 60 63 71
DC gain(dB) 71 76 96
Power consumption(μW) 720 720 720
FOM(dB.MHz/μW) 5.5 6.3 19.5
作为一种优选实施例，所述补偿电容Cc的电容值为2～4pF，由此可以在不占据太大芯片面积的情况下，实现较好的补偿效果。
图4所示的结构为PMOS管作为输入管的结构，同理可知，针对本发明的所有分析，同样适用于NMOS管作为输入管的情况，其原理图如图8所示。据此，本发明还公开一种采用NMOS管作为输入管的基于自偏置共源共栅结构的跨导放大器，包括NMOS输入管M1、M2、M3和M4构成的自偏置共源共栅输入级结构，PMOS管M5、M6、M7和M8构成的自偏置共源共栅第一级负载结构，NMOS管M9和PMOS管M10构成的第二级共源放大器结构，NMOS管 M11、M12和PMOS管M13构成的偏置电路结构，放大器补偿电容CC，放大器负载电容CL，基准电流源Iref和提供恒流源功能的PMOS管M0；其中，
所述NMOS输入管M1和M2的源极接地，NMOS输入管M1和M3的栅极接输入信号VIN，NMOS输入管M2和M4的栅极接输入信号VIP，NMOS输入管M1的漏极接NMOS输入管M3的源极，NMOS输入管M2的漏极接NMOS输入管M4的源极，NMOS输入管M3和M4的衬底接偏置电压Vn，该偏置电压Vn由放大器偏置电路中栅漏相连的NMOS管M11的栅压提供；
所述PMOS管M5的栅极和漏极均与PMOS管M6、M7、M8的栅极以及NMOS输入管M3的漏极连接，PMOS管M6的漏极接NMOS输入管M4的漏极，PMOS管M5的源极接PMOS管M7的漏极，PMOS管M6的源极接PMOS管M8的漏极，PMOS管M7和M8的源极接PMOS管M0的漏极，PMOS管M5和M6的衬底接偏置电压Vp，该偏置电压Vp由放大器偏置电路中栅漏相连的PMOS管M13的栅压提供；
所述PMOS管M10的源极接电源电压vdd，PMOS管M10的漏极、补偿电容Cc的一端、NMOS管M9的漏极和负载电容CL的一端相互连接形成一个连接节点，且该连接节点为所述跨导放大器的输出端Vout，PMOS管M10的栅极接NMOS输入管M4的漏极，补偿电容Cc的另一端接PMOS输入管M2的漏极，负载电容CL的另一端和NMOS管M9的源极接地，NMOS管M9的栅极接NMOS输入管M12的栅极；
所述PMOS管M0和M13的源极接电源电压vdd，PMOS管M0的栅极接PMOS管M13的栅极和漏极，PMOS管M13的漏极接NMOS管M12的漏极，NMOS管M12的栅极接基准电流源Iref的一端以及 NMOS管M11的栅极和漏极，NMOS管M11和M12的源极接地，基准电流源Iref的另一端接电源电压vdd。
作为具体实施例，图8所示的结构除了采用NMOS管作为输入管外，其相应的电路分析与图4所示的结构类似，在此不再赘述。同理，作为一种合理分配图8中串联NMOS管M1和M3以及PMOS管M5和M7沟道长度的具体实施方式，所述PMOS输入管M1和M3的沟道长度之比为1：4，所述NMOS管M5和M7的沟道长度之比为1：4。作为一种优选实施例，所述补偿电容Cc的电容值为2～4pF，由此可以在不占据太大芯片面积的情况下，实现较好的补偿效果。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构，直接或间接运用在其他相关的技术领域，均同理在本发明的专利保护范围之内。

Claims (6)

  1. 一种基于自偏置共源共栅结构的跨导放大器，其特征在于，包括PMOS输入管M1、M2、M3和M4构成的自偏置共源共栅输入级结构，NMOS管M5、M6、M7和M8构成的自偏置共源共栅第一级负载结构，NMOS管M9和PMOS管M10构成的第二级共源放大器结构，NMOS管M11、M12和PMOS管M13构成的偏置电路结构，放大器补偿电容CC，放大器负载电容CL，基准电流源Iref和提供恒流源功能的PMOS管M0；其中，
    所述PMOS输入管M1和M2的源极接PMOS管M0的漏极，PMOS输入管M1和M3的栅极接输入信号VIN，PMOS输入管M2和M4的栅极接输入信号VIP，PMOS输入管M1的漏极接PMOS输入管M3的源极，PMOS输入管M2的漏极接PMOS输入管M4的源极，PMOS输入管M3和M4的衬底接偏置电压Vp，该偏置电压Vp由放大器偏置电路中栅漏相连的PMOS管M13的栅压提供；
    所述NMOS管M5的栅极和漏极均与NMOS管M6、M7、M8的栅极以及PMOS输入管M3的漏极连接，NMOS管M6的漏极接PMOS输入管M4的漏极，NMOS管M5的源极接NMOS管M7的漏极，NMOS管M6的源极接NMOS管M8的漏极，NMOS管M7和M8的源极接地，NMOS管M5和M6的衬底接偏置电压Vn，该偏置电压Vn由放大器偏置电路中栅漏相连的NMOS管M11的栅压提供；
    所述PMOS管M10、M0、M13的源极接电源电压vdd，PMOS管M10的栅极接PMOS管M0和M13的栅极，PMOS管M10的漏极、补偿电容Cc的一端、NMOS管M9的漏极和负载电容CL的一端相互连接形成一个连接节点，且该连接节点为所述跨导放大器的输出端Vout，补偿电容Cc的另一端接PMOS输入管M2的漏极，负载电 容CL的另一端和NMOS管M9的源极接地，NMOS管M9的栅极接PMOS输入管M4的漏极；
    所述PMOS管M13的漏极接NMOS管M12的漏极，NMOS管M12的栅极接基准电流源Iref的一端以及NMOS管M11的栅极和漏极，NMOS管M11和M12的源极接地，基准电流源Iref的另一端接电源电压vdd。
  2. 根据权利要求1所述的基于自偏置共源共栅结构的跨导放大器，其特征在于，所述PMOS输入管M1和M3的沟道长度之比为1：4，所述NMOS管M5和M7的沟道长度之比为1：4。
  3. 根据权利要求1所述的基于自偏置共源共栅结构的跨导放大器，其特征在于，所述补偿电容Cc的电容值为2～4pF。
  4. 一种基于自偏置共源共栅结构的跨导放大器，其特征在于，包括NMOS输入管M1、M2、M3和M4构成的自偏置共源共栅输入级结构，PMOS管M5、M6、M7和M8构成的自偏置共源共栅第一级负载结构，NMOS管M9和PMOS管M10构成的第二级共源放大器结构，NMOS管M11、M12和PMOS管M13构成的偏置电路结构，放大器补偿电容CC，放大器负载电容CL，基准电流源Iref和提供恒流源功能的PMOS管M0；其中，
    所述NMOS输入管M1和M2的源极接地，NMOS输入管M1和M3的栅极接输入信号VIN，NMOS输入管M2和M4的栅极接输入信号VIP，NMOS输入管M1的漏极接NMOS输入管M3的源极，NMOS输入管M2的漏极接NMOS输入管M4的源极，NMOS输入管M3和M4的衬底接偏置电压Vn，该偏置电压Vn由放大器偏置电路中栅漏相连的NMOS管M11的栅压提供；
    所述PMOS管M5的栅极和漏极均与PMOS管M6、M7、M8的栅极以及NMOS输入管M3的漏极连接，PMOS管M6的漏极接 NMOS输入管M4的漏极，PMOS管M5的源极接PMOS管M7的漏极，PMOS管M6的源极接PMOS管M8的漏极，PMOS管M7和M8的源极接PMOS管M0的漏极，PMOS管M5和M6的衬底接偏置电压Vp，该偏置电压Vp由放大器偏置电路中栅漏相连的PMOS管M13的栅压提供；
    所述PMOS管M10的源极接电源电压vdd，PMOS管M10的漏极、补偿电容Cc的一端、NMOS管M9的漏极和负载电容CL的一端相互连接形成一个连接节点，且该连接节点为所述跨导放大器的输出端Vout，PMOS管M10的栅极接NMOS输入管M4的漏极，补偿电容Cc的另一端接PMOS输入管M2的漏极，负载电容CL的另一端和NMOS管M9的源极接地，NMOS管M9的栅极接NMOS输入管M12的栅极；
    所述PMOS管M0和M13的源极接电源电压vdd，PMOS管M0的栅极接PMOS管M13的栅极和漏极，PMOS管M13的漏极接NMOS管M12的漏极，NMOS管M12的栅极接基准电流源Iref的一端以及NMOS管M11的栅极和漏极，NMOS管M11和M12的源极接地，基准电流源Iref的另一端接电源电压vdd。
  5. 根据权利要求4所述的基于自偏置共源共栅结构的跨导放大器，其特征在于，所述NMOS输入管M1和M3的沟道长度之比为1：4，所述PMOS管M5和M7的沟道长度之比为1：4。
  6. 根据权利要求4所述的基于自偏置共源共栅结构的跨导放大器，其特征在于，所述补偿电容Cc的电容值为2～4pF。
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