WO2017211134A1 - 两级运算放大器 - Google Patents

两级运算放大器 Download PDF

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Publication number
WO2017211134A1
WO2017211134A1 PCT/CN2017/081327 CN2017081327W WO2017211134A1 WO 2017211134 A1 WO2017211134 A1 WO 2017211134A1 CN 2017081327 W CN2017081327 W CN 2017081327W WO 2017211134 A1 WO2017211134 A1 WO 2017211134A1
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Prior art keywords
transistor
bias voltage
drain
source
stage operational
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PCT/CN2017/081327
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English (en)
French (fr)
Inventor
孙高明
郑喆奎
栗首
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京东方科技集团股份有限公司
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Priority to US15/572,307 priority Critical patent/US10404220B2/en
Publication of WO2017211134A1 publication Critical patent/WO2017211134A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/3022—CMOS common source output SEPP amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
    • H03F3/45408—Complementary long tailed pairs having parallel inputs and being supplied in parallel
    • H03F3/45417—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45096—Indexing scheme relating to differential amplifiers the difference of two signals being made by, e.g. combining two or more current mirrors, e.g. differential current mirror
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45644—Indexing scheme relating to differential amplifiers the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors

Definitions

  • the present invention relates to the field of circuit design, and in particular, to a two-stage operational amplifier.
  • Op amps are an important part of many analog and mixed-signal systems, and high DC gain is undoubtedly an important design indicator for op amps. Since op amps are typically used to implement a feedback system, the magnitude of the open-loop DC gain determines the accuracy of the feedback system using the op amp.
  • a two-stage operational amplifier based on a folded cascode structure provides a higher output voltage swing while providing higher gain. Specifically, the first stage amplifier is used to achieve high gain and the appropriate swing is provided, and the second stage amplifier is used to increase the output swing.
  • existing two-stage operational amplifiers provide high gain, but their own noise (flicker noise and thermal noise) are large, which limits the overall performance of the amplifier.
  • the present invention provides a two-stage operational amplifier designed to address at least one of the prior art problems.
  • an embodiment of the present invention provides a two-stage operational amplifier, including: a bias voltage generating unit, a first-stage operational amplifying unit, and a second-stage operational amplifying unit;
  • the bias voltage generating unit is connected to the first-stage operational amplifying unit and the second-stage operational amplifying unit, and is configured to provide a correspondence to the first-stage operational amplifying unit and the second-stage operational amplifying unit. Bias voltage
  • the first-stage operational amplification unit is coupled to the second-stage operational amplification unit for providing high gain, and includes: a folded cascode amplifying circuit and a cross-coupling load, the cross-coupling load and the folding Load differential pair in cascode amplifier circuit Connected, the cross-coupled load includes two transistors, and two of the cross-coupled loads respectively correspond to two transistors of the corresponding load differential pair, and constitute two current mirror structures, two The current mirror structure is cross-coupled;
  • the second stage operational amplification unit is configured to increase an output swing of the signal output by the first stage operational amplification unit.
  • the folded cascode amplifying circuit comprises:
  • a first transistor having a gate connected to a fourth bias voltage output terminal of the bias voltage generating unit, and a source connected to the first power terminal;
  • a second transistor having a gate connected to the first signal input terminal and a source connected to the drain of the first transistor
  • a third transistor having a gate connected to the second signal input terminal and a source connected to the drain of the first transistor
  • a fourth transistor having a gate connected to the fourth bias voltage output terminal, a source connected to the second power terminal, and a drain connected to the drain of the second transistor;
  • a fifth transistor having a gate connected to the fourth bias voltage output terminal, a source connected to the second power terminal, and a drain connected to a drain of the third transistor;
  • a sixth transistor having a gate connected to a third bias voltage output terminal of the bias voltage generating unit, and a source connected to a drain of the fourth transistor;
  • a seventh transistor having a gate connected to the third bias voltage output terminal, a source connected to the drain of the fifth transistor, and a drain connected to the second stage operational amplification unit;
  • An eighth transistor having a gate connected to a second bias voltage output terminal of the bias voltage generating unit, and a drain connected to a drain of the sixth transistor;
  • a ninth transistor having a gate connected to the second bias voltage output terminal and a drain connected to a drain of the seventh transistor;
  • a tenth transistor having a gate connected to a source of the eighth transistor, a drain connected to a source of the eighth transistor, and a source connected to the first power terminal;
  • An eleventh transistor having a gate connected to a source of the ninth transistor, a drain connected to a source of the ninth transistor, and a source connected to the first power terminal;
  • the tenth transistor and the eleventh transistor constitute the load differential pair.
  • the cross-coupling load comprises:
  • a twelfth transistor having a gate connected to a source of the eighth transistor, a drain connected to a source of the ninth transistor, and a source connected to the first power terminal;
  • a thirteenth transistor having a gate connected to a source of the ninth transistor, a drain connected to a source of the eighth transistor, and a source connected to the first power terminal;
  • the twelfth transistor and the tenth transistor form a current mirror structure
  • the thirteenth transistor and the eleventh transistor form a current mirror structure
  • the first transistor, the second transistor, the third transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the first The twelve transistors and the thirteenth transistor are both N-type MOS transistors;
  • the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type MOS transistors.
  • the channel of the first transistor has a width of 1 um and a length of 600 nm;
  • the channels of the second transistor and the third transistor have a width of 1.2 um and a length of 600 nm;
  • the channels of the fourth transistor and the fifth transistor have a width of 1 um and a length of 5 um;
  • the channels of the sixth transistor and the seventh transistor have a width of 1 um and a length of 2.5 um;
  • the channels of the eighth transistor and the ninth transistor have a width of 1 um and a length of 8 um;
  • the tenth transistor and the eleventh transistor have a width of 600 nm and a length of 600 nm;
  • the channels of the twelfth transistor and the thirteenth transistor have a width of 600 nm and a length of 600 nm.
  • the bias voltage generating unit includes:
  • a fourteenth transistor having a gate connected to the first bias current input terminal and the second bias voltage output terminal, the drain being connected to the first bias current input terminal;
  • a fifteenth transistor having a gate connected to the second bias voltage output terminal and a drain connected to the second bias current input terminal;
  • a sixteenth transistor having a gate connected to the second bias voltage output terminal and a drain Connected to the source of the fourteenth transistor, and the source is connected to the first power terminal;
  • a seventeenth transistor having a gate connected to a source of the fifteenth transistor and a third bias voltage output, the source being connected to the first power terminal;
  • the eighteenth transistor has a gate connected to the first bias voltage output terminal, and a source connected to the second power terminal;
  • a nineteenth transistor having a gate connected to the fourth bias voltage output terminal, a source connected to the second power supply terminal, and a drain connected to the fourth bias voltage output terminal;
  • a twentieth transistor having a gate connected to the first bias voltage output terminal, a source connected to a drain of the eighteenth transistor, and a drain connected to the first bias voltage output terminal;
  • a twenty-first transistor having a gate connected to the first bias voltage output terminal and a source connected to a drain of the nineteenth transistor
  • a twenty-second transistor having a gate connected to the second bias voltage output terminal and a drain connected to a drain of the twentieth transistor;
  • a twenty-third transistor having a gate connected to the second bias voltage output terminal and a drain connected to a drain of the second eleven transistor;
  • a twenty-fourth transistor having a gate connected to the third bias voltage output terminal, a drain connected to a source of the twenty-second transistor, and a source connected to the first power terminal;
  • the twenty-fifth transistor has a gate connected to the third bias voltage output terminal, a drain connected to a source of the twenty-third transistor, and a source connected to the first power terminal.
  • the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the twenty-second transistor, the twenty-third transistor, the The twenty-fourth transistor and the twenty-fifth transistor are both N-type MOS transistors;
  • the eighteenth transistor, the nineteenth transistor, the twentieth transistor, and the twenty first transistor are all P-type MOS transistors.
  • the channel of the fourteenth transistor has a width of 910 nm and a length of 10 um;
  • the channel of the fifteenth transistor has a width of 1 um and a length of 7.5 um;
  • the widths of the channels of the sixteenth transistor and the seventeenth transistor are both 600 nm and the length is 10 um;
  • the channel of the eighteenth transistor has a width of 750 nm and a length of 10 um;
  • the channel of the nineteenth transistor has a width of 600 nm and a length of 10 um;
  • the channel of the twentieth transistor has a width of 1.65 um and a length of 10 um;
  • the channel of the twenty-first transistor has a width of 10 um and a length of 500 nm;
  • the channel of the twenty-second transistor has a width of 3.2 um and a length of 1 um;
  • the channel of the twenty-third transistor has a width of 1 um and a length of 10 um;
  • the channel of the twenty-fourth transistor has a width of 5 um and a length of 4 um;
  • the channel of the twenty-fifth transistor has a width of 600 nm and a length of 10 um.
  • the second-stage operational amplification unit includes:
  • a twenty-sixth transistor having a gate connected to the first-stage operational amplification unit, a source connected to the second power supply terminal, and a drain connected to the signal output end;
  • the twenty-seventh transistor has a gate connected to the first bias voltage output terminal of the bias voltage generating unit, a drain connected to the signal output terminal, and a source connected to the first power terminal.
  • the twenty-sixth transistor is a P-type MOS transistor
  • the twenty-seventh transistor is an N-type MOS transistor.
  • the channel of the twenty-sixth transistor has a width of 9 um and a length of 1 um;
  • the channel of the twenty-seventh transistor has a width of 8 um and a length of 800 nm.
  • the two-stage operational amplifier further includes: a Miller compensation unit, the Miller compensation unit includes: a resistor and a capacitor;
  • a first end of the capacitor is connected to an output end of the first stage operational amplification unit, and a second end of the capacitor is connected to a first end of the resistor;
  • the second end of the resistor is coupled to the signal output of the two-stage operational amplifier.
  • the present invention provides a two-stage operational amplifier that increases the cross-coupling load on a load differential pair in a folded cascode amplifier circuit to achieve a positive feedback negative conductance gain enhancement technique to increase the gain of the two-stage operational amplifier
  • the parameters of the MOS tube in the folded cascode amplifying circuit are properly set to reduce the noise of the two-stage operational amplifier, so that the high gain and the low noise performance are simultaneously satisfied;
  • the stage operational amplifier performs Miller compensation to ensure its stability.
  • FIG. 1 is a schematic structural diagram of a two-stage operational amplifier according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a noise characteristic curve of a two-stage operational amplifier in the prior art
  • FIG. 3 is a schematic diagram of an AC response curve of a two-stage operational amplifier in the prior art
  • FIG. 4 is a schematic diagram of a noise characteristic curve of a two-stage operational amplifier according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an AC response curve of a two-stage operational amplifier according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a two-stage operational amplifier according to an embodiment of the present invention.
  • the two-stage operational amplifier includes: a bias voltage generating unit 1, a first-stage operational amplifying unit 2, and a second stage.
  • the operation amplifying unit 4 is operated.
  • the bias voltage generating unit 1 is connected to both the first-stage operational amplifying unit 2 and the second-stage operational amplifying unit 4 for providing corresponding offsets to the first-stage operational amplifying unit 2 and the second-stage operational amplifying unit 4. Voltage.
  • the first-stage operational amplification unit 2 is connected to the second-stage operational amplification unit 4 for providing high gain, and includes: a folded cascode amplifying circuit and a cross-coupling load 3, and the cross-coupling load 3 is shared with the folded conjugate
  • the cross-coupling load 3 includes two transistors, and two of the cross-coupled loads 3 respectively form two current mirror structures with two transistors of the corresponding load differential pair, and two The current mirror structure is cross-coupled.
  • the second-stage operational amplification unit 4 is for increasing the output swing of the signal output by the first-stage operational amplification unit 2.
  • a cross-coupling load 3 also referred to as -gm compensation
  • two cross-coupled current mirror structures can be constructed.
  • Equivalent output resistance of current mirror structure four transistors in total
  • the resistance is equal to the reciprocal of the difference in the transconductance of the two current mirror structures.
  • the performance parameters of the two transistors in the cross-coupling load 3 can be set to be identical to the two transistors in the differential pair of loads, and thus can be configured.
  • the difference between the transconductances of the two current mirror structures is equal to 0 (in practical applications, the difference between the transconductances of the two current mirror structures approaches 0), the two current mirror structures, etc.
  • the effective output impedance can be infinitely large.
  • the total output impedance of the first-stage operational amplifying unit is correspondingly increased, and the gain of the first-stage operational amplifying unit is correspondingly increased, that is, the two-stage operational amplifier provided in this embodiment can achieve high gain.
  • the folded cascode amplifying circuit includes:
  • a first transistor M1 having a gate connected to a fourth bias voltage output terminal Vbias4 of the bias voltage generating unit 1 and a source connected to the first power terminal 6;
  • a second transistor M2 having a gate connected to the first signal input terminal Vin1 and a source connected to the drain of the first transistor M1;
  • a third transistor M3 having a gate connected to the second signal input terminal Vin2 and a source connected to the drain of the first transistor M1;
  • a fourth transistor M4 having a gate connected to the fourth bias voltage output terminal Vbias4, a source connected to the second power terminal 7, and a drain connected to the drain of the second transistor M2;
  • a fifth transistor M5 having a gate connected to the fourth bias voltage output terminal Vbias4, a source connected to the second power terminal 7, and a drain connected to the drain of the third transistor M3;
  • a sixth transistor M6 having a gate connected to a third bias voltage output terminal Vbias3 of the bias voltage generating unit 1 and a drain connected to the source fourth transistor M4;
  • a seventh transistor M7 having a gate connected to the third bias voltage output terminal Vbias3, a source connected to the drain of the fifth transistor M5, and a drain connected to the second-stage operational amplification unit 4;
  • the eighth transistor M8 has a gate connected to the second bias voltage output terminal Vbias2 of the bias voltage generating unit 1, and a drain connected to the drain of the sixth transistor M6;
  • a ninth transistor M9 having a gate connected to the second bias voltage output terminal Vbias2 and a drain connected to the drain of the seventh transistor M7;
  • a tenth transistor M10 having a gate connected to a source of the eighth transistor M8, a drain connected to a source of the eighth transistor M8, and a source connected to the first power terminal 6;
  • the eleventh transistor M11 has a gate connected to the source of the ninth transistor M9, a drain connected to the source of the ninth transistor M9, and a source first power terminal 6 connected;
  • the tenth transistor M10 and the eleventh transistor M11 constitute a load differential pair.
  • the cross-coupling load 3 comprises:
  • a twelfth transistor M12 having a gate connected to a source of the eighth transistor M8, a drain connected to a source of the ninth transistor M9, and a source connected to the first power terminal 6;
  • a thirteenth transistor M13 having a gate connected to a source of the ninth transistor M9, a drain connected to a source of the eighth transistor M8, and a source connected to the first power terminal 6;
  • the twelfth transistor M12 and the tenth transistor M10 form a current mirror structure
  • the thirteenth transistor M13 and the eleventh transistor M11 form a current mirror structure
  • the second transistor M2 is the same as the third transistor M3, the fourth transistor M4 is the same as the fifth transistor M5, the sixth transistor M6 is the same as the seventh transistor M7, the eighth transistor M8 is the same as the ninth transistor M9, and the tenth transistor M10 is the same.
  • the twelfth transistor M12 is the same as the thirteenth transistor M13.
  • g m6 and g mb6 represent the transconductance of the sixth transistor M6 and the substrate transconductance (which is generally small) when considering the bulk effect, respectively, and g m8 and g mb8 represent the transconductance and consideration of the eighth transistor M8, respectively.
  • r o2 , r o4 , r o6 and r o8 represent the outputs of the second transistor M2, the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8, respectively.
  • r o (10,11,12,13) represents a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 equivalent output impedance of a total of four transistors.
  • g m2 represents the transconductance of the second transistor M2.
  • the first stage The gain of the operational amplification unit can also be increased accordingly.
  • the bias voltage generating unit 1 includes:
  • a fourteenth transistor M14 having a gate connected to the first bias current input terminal Ibias1 and a second bias voltage output terminal Vbias2, and a drain connected to the first bias current input terminal Ibias1;
  • a fifteenth transistor M15 having a gate connected to the second bias voltage output terminal Vbias2 and a drain connected to the second bias current input terminal Ibias2;
  • a sixteenth transistor M16 having a gate connected to the second bias voltage output terminal Vbias2, a drain connected to the source of the fourteenth transistor M14, and a source connected to the first power terminal 6;
  • a seventeenth transistor M17 having a gate connected to a source of the fifteenth transistor M15 and a third bias voltage output terminal Vbias3, the source being connected to the first power terminal 6;
  • the eighteenth transistor M18 has a gate connected to the first bias voltage output terminal Vbias 1 and a source connected to the second power terminal 7;
  • a nineteenth transistor M19 having a gate connected to the fourth bias voltage output terminal Vbias4, a source connected to the second power terminal 7, and a drain connected to the fourth bias voltage output terminal Vbias4;
  • a twentieth transistor M20 having a gate connected to the first bias voltage output terminal Vbias 1, a source connected to the drain of the eighteenth transistor M18, and a drain connected to the first bias voltage output terminal Vbias1;
  • a twenty-first transistor M21 having a gate connected to the first bias voltage output terminal Vbias 1 and a source connected to a drain of the nineteenth transistor M19;
  • a twenty-second transistor M22 having a gate connected to the second bias voltage output terminal Vbias2 and a drain connected to the drain of the twentieth transistor M20;
  • a twenty-third transistor M23 having a gate connected to the second bias voltage output terminal Vbias2 and a drain connected to the drain of the twenty-first transistor M21;
  • a twenty-fourth transistor M24 having a gate connected to the third bias voltage output terminal Vbias3, a drain connected to the source of the twenty-second transistor M22, and a source connected to the first power terminal 6;
  • the twenty-fifth transistor M25 has a gate connected to the third bias voltage output terminal Vbias3, a drain connected to the source of the twenty-third transistor M23, and a source connected to the first power terminal 6.
  • the second-stage operational amplification unit 4 includes:
  • the twenty-sixth transistor M26 has its gate connected to the first-stage operational amplification unit 2, the source The pole is connected to the second power terminal 7, and the drain is connected to the signal output terminal Out.
  • the twenty-seventh transistor M27 has a gate connected to the first bias voltage output terminal Vbias1 of the bias voltage generating unit 1, a drain connected to the signal output terminal Out, and a source connected to the first power source terminal 6.
  • the noise of the second-stage operational amplification unit 4 is negligible.
  • the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 function as The main source of noise.
  • the flicker noise V flicker and thermal noise V thermal of the two-stage operational amplifier are respectively:
  • K m2 and K m4 represent the flicker noise figure of the second transistor M2 and the fourth transistor M4, respectively
  • (WL) 2 and (WL) 4 represent the channel areas of the second transistor M2 and the fourth transistor M4, respectively (channel The product of length and width)
  • C ox represents the gate oxide capacitance per unit area
  • f is the frequency of the signal to be processed
  • ⁇ is constant (for long channel transistors, the value of ⁇ is generally 2/3, in submicron In the MOSFET, the value of ⁇ will be larger, and the magnitude of ⁇ will also change to some extent with the change of the drain-source voltage.)
  • k is the Boltzmann constant and T is the absolute temperature.
  • flicker noise V can be made by increasing the transconductance of the second transistor M2 (third transistor M3) and/or reducing the transconductance of the fourth transistor M4 (fifth transistor M5) Both the flicker and the thermal noise V thermal are reduced.
  • the transconductance g m4 of the fourth transistor M4 is:
  • ⁇ m2 and ⁇ m4 are carrier mobility of the second transistor M2 and the fourth transistor M4, respectively, and (W/L) 2 and (W/L) 4 are the second transistor M2 and the fourth transistor M4, respectively.
  • the aspect ratio of the channel, I D2 and I D4 are the leakage currents assigned to the second transistor M2 and the fourth transistor M4, respectively.
  • the second transistor M2 (the third transistor in this embodiment) M3) is preferably an N-type MOS transistor, so that the transconductance of the second transistor M2 can be effectively improved;
  • the fourth transistor M4 (fifth transistor M5) is preferably a P-type MOS transistor, so that the transconductance of the fourth transistor M4 can be effectively reduced.
  • the widths of the channels of the second transistor M2 and the third transistor M3 are both 1.2 ⁇ m and the length is 600 nm; the widths of the channels of the fourth transistor M4 and the fifth transistor M5 are both It is 1um and the length is 5um. At this time, low noise can be achieved while ensuring high gain of the two-stage operational amplifier.
  • the channel of the first transistor M1 has a width of 1 um and a length of 600 nm.
  • the first transistor M1 has a larger channel area and a larger aspect ratio, thereby causing leakage to the second transistor M2.
  • the current is as large as possible, so that the transconductance of the second transistor M2 can be effectively improved, thereby contributing to noise reduction.
  • the seven transistors M27 are all N-type MOS transistors; the sixth transistor M6, the seventh transistor M7, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21 and the twenty-sixth transistor M26 is a P-type MOS tube.
  • the widths of the channels of the sixth transistor M6 and the seventh transistor M7 are both 1 um and the length is 2.5 um; the widths of the channels of the eighth transistor M8 and the ninth transistor M9 are both 1 um, and the lengths are both 8 um; the width of the channel of the tenth transistor M10 and the eleventh transistor M11 is 600 nm and the length is 600 nm; the widths of the channels of the twelfth transistor M12 and the thirteenth transistor M13 are both 600 nm, and the length is 600 nm; the width of the channel of the fourteenth transistor M14 is 910 nm, the length is 10 um; the width of the channel of the fifteenth transistor M15 is 1 um, the length is 7.5 um; the groove of the sixteenth transistor M16 and the seventeenth transistor M17 The width of the track is 600nm and the length is 10um; the width of the channel of the eighteenth transistor M18 is 750nm and the length is 10um; the width of the channel of the nineteenth transistor M
  • the width of the channel of the twenty-third transistor M23 is 1um
  • the length of the channel is 10um
  • the width of the channel of the twenty-fourth transistor M24 is 5um, the length is 4um
  • the width of the channel of the twenty-fifth transistor M25 is 600nm, the length is 10um
  • the channel of the twenty-sixth transistor M26 The width is 9 um and the length is 1 um
  • the channel of the twenty-seventh transistor M27 has a width of 8 um and a length of 800 nm.
  • the first power terminal 6 is a low-level terminal Vss
  • the second power terminal 7 is a high-level terminal Vdd
  • the substrates of each N-type MOS transistor are connected to a low-level terminal Vss
  • each P-type The substrates of the MOS transistors are all connected to the high level terminal Vdd.
  • the two-stage operational amplifier further includes: a Miller compensation unit 5 for performing Miller compensation.
  • the Miller compensation unit 5 includes a resistor R and a capacitor C. The first end of the capacitor C is connected to the output terminal A of the first-stage operational amplification unit 2, and the second end of the capacitor C and the resistor R are The first end is connected, and the second end of the resistor R is connected to the signal output terminal Out of the two-stage operational amplifier.
  • the Miller compensation unit 5 by setting the Miller compensation unit 5, the poles of the main pole and the non-pole pole can be separated to the low frequency and the high frequency respectively, and the resistor moves the zero point of the right half plane to the high frequency, which can be reduced or even offset. Zero point system The impact of stability.
  • FIG. 2 is a schematic diagram of a noise characteristic curve of a two-stage operational amplifier in the prior art
  • FIG. 3 is a schematic diagram of an AC response curve of a two-stage operational amplifier in the prior art, as shown in FIG. 2 and FIG. Spectre simulates the two-stage operational amplifier in the prior art.
  • the simulation results show that the two-stage operational amplifier in the prior art has a unity gain bandwidth of about 10 MHz, a DC gain of 125.7 dB, and a phase margin of 59.2 ° .
  • the input reference noise at 1MHz is approximately It can be seen that the gain and noise of the two-stage operational amplifier in the prior art are large, and the high gain and low noise performance cannot be simultaneously satisfied.
  • FIG. 4 is a schematic diagram of a noise characteristic curve of a two-stage operational amplifier according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of an AC response curve of a two-stage operational amplifier according to an embodiment of the present invention, as shown in FIG. 4 and FIG.
  • the simulation tool Spectre performs simulation analysis on the two-stage operational amplifier in the embodiment of the present invention.
  • the simulation result shows that the DC gain of the two-stage operational amplifier provided by the embodiment of the present invention is 114.3 dB, that is, the amplification capability is still strong, at the frequency of 1 MHz.
  • Input reference noise is approximately
  • the two-stage operational amplifier provided by the embodiment of the present invention has a noise reduction of about 2/3. It can be seen that the two-stage operational amplifier provided by the embodiment of the invention has large gain and low noise, and high gain and low noise performance are simultaneously satisfied.

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Abstract

本发明公开了一种两级运算放大器，包括偏置电压生成单元、第一级运算放大单元和第二级运算放大单元，其中第一级运算放大单元包括折叠式共源共栅放大电路和交叉耦合负载，交叉耦合负载与折叠式共源共栅放大电路中的负载差分对连接，交叉耦合负载包括两个晶体管，交叉耦合负载中的两个晶体管分别与对应的负载差分对中的两个晶体管构成两个电流镜结构，且两个电流镜结构交叉耦合。本发明的技术方案通过在折叠式共源共栅放大电路中的负载差分对上增加交叉耦合负载，以实现采取正反馈负电导增益增强技术来增加两级运算放大器的增益；与此同时，通过对折叠式共源共栅放大电路中的MOS管的参数进行合理设置，可降低两级运算放大器的噪声。

Description

两级运算放大器 技术领域
本发明涉及电路设计领域，特别涉及一种两级运算放大器。
背景技术
运算放大器是许多模拟系统和混合信号系统中的一个重要部分，高的直流增益无疑是运算放大器重要的设计指标。由于运算放大器一般用来实现一个反馈系统，其开环直流增益的大小决定了使用运算放大器的反馈系统的精度。
目前，基于折叠式共源共栅结构的两级运算放大器，在提供较高增益的同时，还可以提供较大的输出电压摆幅。具体地，第一级放大器用于实现高增益和提供适当摆幅，第二级放大器用来增大输出摆幅。然而，现有的两级运算放大器虽能提供高增益，但是其自身噪声(闪烁噪声和热噪声)较大，使得放大器的整体性能提升受到限制。
由上述内容可见，提供一种高增益、低噪声的两级运算放大器，是本领域中亟需解决的技术问题。
发明内容
本发明提供一种两级运算放大器，旨在至少解决现有技术中存在技术问题之一。
为实现上述目的，本发明实施例提供了一种两级运算放大器，包括：偏置电压生成单元、第一级运算放大单元和第二级运算放大单元；其中，
所述偏置电压生成单元与所述第一级运算放大单元和所述第二级运算放大单元均连接，用于向所述第一级运算放大单元和所述第二级运算放大单元提供对应的偏置电压；
所述第一级运算放大单元与所述第二级运算放大单元连接，用于提供高增益，并且包括：折叠式共源共栅放大电路和交叉耦合负载，所述交叉耦合负载与所述折叠式共源共栅放大电路中的负载差分对 连接，所述交叉耦合负载包括两个晶体管，所述交叉耦合负载中的两个晶体管分别与对应的所述负载差分对中的两个晶体管一一对应，且构成两个电流镜结构，两个所述电流镜结构交叉耦合；以及
第二级运算放大单元用于增大所述第一级运算放大单元所输出信号的输出摆幅。
可选地，所述折叠式共源共栅放大电路包括：
第一晶体管，其栅极与所述的偏置电压生成单元的第四偏置电压输出端连接，源极与第一电源端连接；
第二晶体管，其栅极与第一信号输入端连接，源极与所述第一晶体管的漏极连接；
第三晶体管，其栅极与第二信号输入端连接，源极与所述第一晶体管的漏极连接；
第四晶体管，其栅极与所述第四偏置电压输出端连接，源极与第二电源端连接，漏极与所述第二晶体管的漏极连接；
第五晶体管，其栅极与所述第四偏置电压输出端连接，源极与所述第二电源端连接，漏极与所述第三晶体管的漏极连接；
第六晶体管，其栅极与所述偏置电压生成单元的第三偏置电压输出端连接，源极与所述第四晶体管的漏极连接；
第七晶体管，其栅极与所述第三偏置电压输出端连接，源极与所述第五晶体管的漏极连接，漏极与所述第二级运算放大单元连接；
第八晶体管，其栅极与所述偏置电压生成单元的第二偏置电压输出端连接，漏极与所述第六晶体管的漏极连接；
第九晶体管，其栅极与所述第二偏置电压输出端连接，漏极与所述第七晶体管的漏极连接；
第十晶体管，其栅极与所述第八晶体管的源极连接，漏极与所述第八晶体管的源极连接，源极与所述第一电源端连接；
第十一晶体管，其栅极与所述第九晶体管的源极连接，漏极与所述第九晶体管的源极连接，源极所述第一电源端连接；
所述第十晶体管和第十一晶体管构成所述负载差分对。
可选地，所述交叉耦合负载包括：
第十二晶体管，其栅极与所述第八晶体管的源极连接，漏极与所述第九晶体管的源极连接，源极与所述第一电源端连接；
第十三晶体管，其栅极与所述第九晶体管的源极连接，漏极与所述第八晶体管的源极连接，源极与所述第一电源端连接；
所述第十二晶体管与所述第十晶体管构成电流镜结构，所述第十三晶体管与所述第十一晶体管构成电流镜结构。
可选地，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管和所述第十三晶体管均为N型MOS管；
所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型MOS管。
可选地，所述第一晶体管的沟道的宽度为1um，长度为600nm；
所述第二晶体管和所述第三晶体管的沟道的宽度均为1.2um，长度均为600nm；
所述第四晶体管和所述第五晶体管的沟道的宽度均为1um，长度均为5um；
所述第六晶体管和所述第七晶体管的沟道的宽度均为1um，长度均为2.5um；
所述第八晶体管和所述第九晶体管的沟道的宽度均为1um，长度均为8um；
所述第十晶体管和所述第十一晶体管的沟道的宽度均为600nm，长度均为600nm；
所述第十二晶体管和所述第十三晶体管的沟道的宽度均为600nm，长度均为600nm。
可选地，所述偏置电压生成单元包括：
第十四晶体管，其栅极与第一偏置电流输入端和第二偏置电压输出端连接，漏极与所述第一偏置电流输入端连接；
第十五晶体管，其栅极与所述第二偏置电压输出端连接，漏极与第二偏置电流输入端连接；
第十六晶体管，其栅极与所述第二偏置电压输出端连接，漏极 与所述第十四晶体管的源极连接，源极与第一电源端连接；
第十七晶体管，其栅极与所述第十五晶体管的源极和第三偏置电压输出端连接，源极与所述第一电源端连接；
第十八晶体管，其栅极与第一偏置电压输出端连接，源极与第二电源端连接；
第十九晶体管，其栅极与第四偏置电压输出端连接，源极与所述第二电源端连接，漏极与所述第四偏置电压输出端连接；
第二十晶体管，其栅极与所述第一偏置电压输出端连接，源极与所述第十八晶体管的漏极连接，漏极与所述第一偏置电压输出端连接；
第二十一晶体管，其栅极与所述第一偏置电压输出端连接，源极与所述第十九晶体管的漏极连接；
第二十二晶体管，其栅极与所述第二偏置电压输出端连接，漏极与所述第二十晶体管的漏极连接；
第二十三晶体管，其栅极与所述第二偏置电压输出端连接，漏极与所述第二十一晶体管的漏极连接；
第二十四晶体管，其栅极与所述第三偏置电压输出端连接，漏极与所述第二十二晶体管的源极连接，源极与所述第一电源端连接；
第二十五晶体管，其栅极与所述第三偏置电压输出端连接，漏极与所述第二十三晶体管的源极连接，源极与所述第一电源端连接。
可选地，所述第十四晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管、所述第二十二晶体管、所述第二十三晶体管、所述第二十四晶体管和所述第二十五晶体管均为N型MOS管；
所述第十八晶体管、所述第十九晶体管、所述第二十晶体管和所述第二十一晶体管均为P型MOS管。
可选地，所述第十四晶体管的沟道的宽度为910nm，长度为10um；
所述第十五晶体管的沟道的宽度为1um，长度为7.5um；
所述第十六晶体管和所述第十七晶体管的沟道的宽度均为600nm，长度均为10um；
所述第十八晶体管的沟道的宽度为750nm，长度为10um；
所述第十九晶体管的沟道的宽度为600nm，长度为10um；
所述第二十晶体管的沟道的宽度为1.65um，长度为10um；
所述第二十一晶体管的沟道的宽度为10um，长度为500nm；
所述第二十二晶体管的沟道的宽度为3.2um，长度为1um；
所述第二十三晶体管的沟道的宽度为1um，长度为10um；
所述第二十四晶体管的沟道的宽度为5um，长度为4um；
所述第二十五晶体管的沟道的宽度为600nm，长度为10um。
可选地，第二级运算放大单元包括：
第二十六晶体管，其栅极与所述第一级运算放大单元连接，源极与第二电源端连接，漏极与信号输出端连接；
第二十七晶体管，其栅极与所述偏置电压生成单元的第一偏置电压输出端连接，漏极与所述信号输出端连接，源极与所述第一电源端连接。
可选地，所述第二十六晶体管为P型MOS管，所述第二十七晶体管为N型MOS管。
可选地，所述第二十六晶体管的沟道的宽度为9um，长度为1um；
所述第二十七晶体管的沟道的宽度为8um，长度为800nm。
可选地，所述两级运算放大器还包括：密勒补偿单元，所述密勒补偿单元包括：电阻器和电容器；
所述电容器的第一端与所述第一级运算放大单元的输出端连接，所述电容器的第二端与所述电阻器的第一端连接；
所述电阻器的第二端与所述两级运算放大器的信号输出端连接。
本发明具有以下有益效果：
本发明提供了一种两级运算放大器，通过在折叠式共源共栅放大电路中的负载差分对上增加交叉耦合负载，以实现采取正反馈负电导增益增强技术来增加两级运算放大器的增益；与此同时，通过对折叠式共源共栅放大电路中的MOS管的参数进行合理设置，以降低两级运算放大器的噪声，从而使得高增益与低噪声性能同时满足；此外，通过对两级运算放大器进行密勒补偿，可有效保证其稳定性。
附图说明
图1为本发明实施例提供的一种两级运算放大器的结构示意图；
图2为现有技术中的两级运算放大器的噪声特性曲线的示意图；
图3为现有技术中的两级运算放大器的交流响应曲线的示意图；
图4为本发明实施例提供的两级运算放大器的噪声特性曲线的示意图；以及
图5为本发明实施例提供的两级运算放大器的交流响应曲线的示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的一种两级运算放大器进行详细描述。
图1为本发明实施例提供的一种两级运算放大器的结构示意图，如图1所示，该两级运算放大器包括：偏置电压生成单元1、第一级运算放大单元2和第二级运算放大单元4。
其中，偏置电压生成单元1与第一级运算放大单元2和第二级运算放大单元4均连接，用于向第一级运算放大单元2和第二级运算放大单元4提供对应的偏置电压。
第一级运算放大单元2与第二级运算放大单元4连接，用于提供高增益，并且包括：折叠式共源共栅放大电路和交叉耦合负载3，交叉耦合负载3与折叠式共源共栅放大电路中的负载差分对连接，交叉耦合负载3包括两个晶体管，交叉耦合负载3中的两个晶体管分别与对应的负载差分对中的两个晶体管构成两个电流镜结构，且两个电流镜结构交叉耦合。
第二级运算放大单元4用于增大第一级运算放大单元2所输出信号的输出摆幅。
在本发明中，通过在折叠式共源共栅放大电路中的负载差分对上增加交叉耦合负载3(又称为-gm补偿)，可以构成两个交叉耦合的电流镜结构，此时两个电流镜结构(共四个晶体管)的等效输出阻 抗等于两个电流镜结构的跨导之差的倒数。本实施例中，优选地，可将交叉耦合负载3中的两个晶体管的性能参数(例如，沟道的宽长比)设置为与负载差分对中的两个晶体管完全相同，此时可构成两个完全相同的电流镜结构，两个电流镜结构的跨导之差等于0(在实际应用中，两个电流镜结构的跨导之差趋近于0)，两个电流镜结构的等效输出阻抗可以无限大，此时第一级运算放大单元的总输出阻抗相应变大，第一级运算放大单元的增益相应提升，即本实施例提供的两级运算放大器可以实现高增益。
作为本实施例中一种具体方案，可选地，折叠式共源共栅放大电路包括：
第一晶体管M1，其栅极与偏置电压生成单元1的第四偏置电压输出端Vbias4连接，源极与第一电源端6连接；
第二晶体管M2，其栅极与第一信号输入端Vin1连接，源极与第一晶体管M1的漏极连接；
第三晶体管M3，其栅极与第二信号输入端Vin2连接，源极与第一晶体管M1的漏极连接；
第四晶体管M4，其栅极与第四偏置电压输出端Vbias4连接，源极与第二电源端7连接，漏极与第二晶体管M2的漏极连接；
第五晶体管M5，其栅极与第四偏置电压输出端Vbias4连接，源极与第二电源端7连接，漏极与第三晶体管M3的漏极连接；
第六晶体管M6，其栅极与偏置电压生成单元1的第三偏置电压输出端Vbias3连接，源极第四晶体管M4的漏极连接；
第七晶体管M7，其栅极与第三偏置电压输出端Vbias3连接，源极与第五晶体管M5的漏极连接，漏极与第二级运算放大单元4连接；
第八晶体管M8，其栅极与偏置电压生成单元1的第二偏置电压输出端Vbias2连接，漏极与第六晶体管M6的漏极连接；
第九晶体管M9，其栅极与第二偏置电压输出端Vbias2连接，漏极与第七晶体管M7的漏极连接；
第十晶体管M10，其栅极与第八晶体管M8的源极连接，漏极与第八晶体管M8的源极连接，源极与第一电源端6连接；
第十一晶体管M11，其栅极与第九晶体管M9的源极连接，漏极与第九晶体管M9的源极连接，源极第一电源端6连接；
其中，第十晶体管M10和第十一晶体管M11构成负载差分对。
可选地，交叉耦合负载3包括：
第十二晶体管M12，其栅极与第八晶体管M8的源极连接，漏极与第九晶体管M9的源极连接，源极与第一电源端6连接；
第十三晶体管M13，其栅极与第九晶体管M9的源极连接，漏极与第八晶体管M8的源极连接，源极与第一电源端6连接；
其中，第十二晶体管M12与第十晶体管M10构成电流镜结构，第十三晶体管M13与第十一晶体管M11构成电流镜结构。
其中，第二晶体管M2与第三晶体管M3相同，第四晶体管M4与第五晶体管M5相同，第六晶体管M6与第七晶体管M7相同，第八晶体管M8与第九晶体管M9相同，第十晶体管M10与第十一晶体管M11相同，第十二晶体管M12与第十三晶体管M13相同。
此时，第一级运算放大单元2的总电阻Rout：
Rout＝[(gm6+gmb6)*ro6*(ro4||ro2)]||[(gm8+gmb8)*ro8*ro(10,11,12,13)]…(1)
其中，gm6和gmb6分别表示第六晶体管M6的跨导和考虑体效应时的衬底跨导(其值一般较小)，gm8和gmb8分别表示第八晶体管M8的跨导和考虑体效应时的衬底跨导(其值一般较小)，ro2、ro4、ro6和ro8分别表示第二晶体管M2、第四晶体管M4、第六晶体管M6、第八晶体管M8的输出阻抗，ro(10,11,12,13)表示第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13共四个晶体管的等效输出阻抗。
第一级运算放大单元2的增益|A1|：
Figure PCTCN2017081327-appb-000001
其中，gm2表示第二晶体管M2的跨导。
基于上式(1)和(2)，当第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13共四个晶体管的等效输出阻抗增大时，第一级运算放大单元的增益也可相应增大。
在本实施例中，可选地，偏置电压生成单元1包括：
第十四晶体管M14，其栅极与第一偏置电流输入端Ibias1和第二偏置电压输出端Vbias2连接，漏极与第一偏置电流输入端Ibias1连接；
第十五晶体管M15，其栅极与第二偏置电压输出端Vbias2连接，漏极与第二偏置电流输入端Ibias2连接；
第十六晶体管M16，其栅极与第二偏置电压输出端Vbias2连接，漏极与第十四晶体管M14的源极连接，源极与第一电源端6连接；
第十七晶体管M17，其栅极与第十五晶体管M15的源极和第三偏置电压输出端Vbias3连接，源极与第一电源端6连接；
第十八晶体管M18，其栅极与第一偏置电压输出端Vbias 1连接，源极与第二电源端7连接；
第十九晶体管M19，其栅极与第四偏置电压输出端Vbias4连接，源极与第二电源端7连接，漏极与第四偏置电压输出端Vbias4连接；
第二十晶体管M20，其栅极与第一偏置电压输出端Vbias 1连接，源极与第十八晶体管M18的漏极连接，漏极与第一偏置电压输出端Vbias1连接；
第二十一晶体管M21，其栅极与第一偏置电压输出端Vbias 1连接，源极与第十九晶体管M19的漏极连接；
第二十二晶体管M22，其栅极与第二偏置电压输出端Vbias2连接，漏极与第二十晶体管M20的漏极连接；
第二十三晶体管M23，其栅极与第二偏置电压输出端Vbias2连接，漏极与第二十一晶体管M21的漏极连接；
第二十四晶体管M24，其栅极与第三偏置电压输出端Vbias3连接，漏极与第二十二晶体管M22的源极连接，源极与第一电源端6连接；
第二十五晶体管M25，其栅极与第三偏置电压输出端Vbias3连接，漏极与第二十三晶体管M23的源极连接，源极与第一电源端6连接。
第二级运算放大单元4包括：
第二十六晶体管M26，其栅极与第一级运算放大单元2连接，源 极与第二电源端7连接，漏极与信号输出端Out连接。
第二十七晶体管M27，其栅极与偏置电压生成单元1的第一偏置电压输出端Vbias1连接，漏极与信号输出端Out连接，源极与第一电源端6连接。
与第一级运算放大单元2的折叠式共源共栅结构相比，第二级运算放大单元4的噪声可忽略不计。在频率相对较低时，第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13作为主要的噪声源。此时该两级运算放大器的闪烁噪声Vflicker和热噪声Vthermal分别为：
Figure PCTCN2017081327-appb-000002
Figure PCTCN2017081327-appb-000003
其中，Km2和Km4分别表示第二晶体管M2和第四晶体管M4的闪烁噪声系数，(WL)2和(WL)4分别表示第二晶体管M2和第四晶体管M4的沟道面积(沟道长度和宽度的乘积)，Cox表示单位面积的栅氧化层电容，f为待处理信号的频率，γ为常数(对长沟道晶体管而言，γ的值一般为2/3，在亚微米MOSFET中，γ取值会更大，另外γ的大小在某种程度上也会随着漏源电压的变化而发生改变)，k为玻尔兹曼常数，T为绝对温度。
基于上式(3)和(4)，通过增大第二晶体管M2(第三晶体管M3)的跨导和/或降低第四晶体管M4(第五晶体管M5)的跨导，可使得闪烁噪声Vflicker和热噪声Vthermal均降低。
由于，第二晶体管M2的跨导gm2为：
Figure PCTCN2017081327-appb-000004
第四晶体管M4的跨导gm4为：
Figure PCTCN2017081327-appb-000005
其中，μm2和μm4分别为第二晶体管M2和第四晶体管M4的载流子迁移率，(W/L)2和(W/L)4分别为第二晶体管M2和第四晶体管M4的 沟道的宽长比，ID2和ID4分别为分配给第二晶体管M2和第四晶体管M4的漏电流。
基于上式(5)和(6)，考虑到N型MOS管中的载流子迁移率比P型MOS管中的载流子迁移率大，本实施例中第二晶体管M2(第三晶体管M3)优选为N型MOS管，从而可有效提升第二晶体管M2的跨导；第四晶体管M4(第五晶体管M5)优选为P型MOS管，从而可有效降低第四晶体管M4的跨导。与此同时，参见上式(3)，由于N型MOS管的闪烁噪声系数小于P型MOS管的闪烁噪声系数，因而当第二晶体管M2为N型MOS管时更有利于减小闪烁噪声Vflicker。
此外，基于上式(3)可见，提升第二晶体管M2和第四晶体管M4的沟道面积也有利于减小闪烁噪声Vflicker。与此同时，基于上式(5)和(6)可见，在提升第二晶体管M2和第四晶体管M4的沟道面积的同时，还需要使得第二晶体管M2的沟道的宽长比尽量大(提高第二晶体管M2的跨导)，而第四晶体管M4的沟道的宽长比尽量小(降低第四晶体管M4的跨导)。因此，在保证沟道面积一定的前提下，应使得第二晶体管M2的沟道的宽度尽量较大，且使得第四晶体管M4的沟道的长度尽量较大。
基于上述考虑，本实施例中优选地，第二晶体管M2和第三晶体管M3的沟道的宽度均为1.2um，长度均为600nm；第四晶体管M4和第五晶体管M5的沟道的宽度均为1um，长度均为5um。此时，可在保证两级运算放大器实现了高增益的同时，也实现了低噪声。
可选地，第一晶体管M1的沟道的宽度为1um，长度为600nm，此时第一晶体管M1具备较大的沟道面积和较大的宽长比，从而使得流向第二晶体管M2的漏电流尽可能大，从而能有效提升第二晶体管M2的跨导，进而有利于减小噪声。
本实施例中，进一步可选地，第一晶体管M1、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第十四晶体管M14、第十五晶体管M15、第十六晶体管M16、第十七晶体管M17、第二十二晶体管M22、第二十三晶体管M23、第二十四晶体管M24、第二十五晶体管M25和第二十 七晶体管M27均为N型MOS管；第六晶体管M6、第七晶体管M7、第十八晶体管M18、第十九晶体管M19、第二十晶体管M20、第二十一晶体管M21和第二十六晶体管M26均为P型MOS管。
更进一步可选地，第六晶体管M6和第七晶体管M7的沟道的宽度均为1um，长度均为2.5um；第八晶体管M8和第九晶体管M9的沟道的宽度均为1um，长度均为8um；第十晶体管M10和第十一晶体管M11的沟道的宽度均为600nm，长度均为600nm；第十二晶体管M12和第十三晶体管M13的沟道的宽度均为600nm，长度均为600nm；第十四晶体管M14的沟道的宽度为910nm，长度为10um；第十五晶体管M15的沟道的宽度为1um，长度为7.5um；第十六晶体管M16和第十七晶体管M17的沟道的宽度均为600nm，长度均为10um；第十八晶体管M18的沟道的宽度为750nm，长度为10um；第十九晶体管M19的沟道的宽度为600nm，长度为10um；第二十晶体管M20的沟道的宽度为1.65um，长度为10um；第二十一晶体管M21的沟道的宽度为10um，长度为500nm；第二十二晶体管M22的沟道的宽度为3.2um，长度为1um；第二十三晶体管M23的沟道的宽度为1um，长度为10um；第二十四晶体管M24的沟道的宽度为5um，长度为4um；第二十五晶体管M25的沟道的宽度为600nm，长度为10um；第二十六晶体管M26的沟道的宽度为9um，长度为1um；第二十七晶体管M27的沟道的宽度为8um，长度为800nm。
需要说明的是，本实施例中的第一电源端6为低电平端Vss，第二电源端7为高电平端Vdd，各N型MOS管的衬底均连接低电平端Vss，各P型MOS管的衬底均连接高电平端Vdd。
可选地，该两级运算放大器还包括：密勒补偿单元5，以用于进行密勒补偿。具体地，密勒补偿单元5包括：电阻器R和电容器C，该电容器C的第一端与第一级运算放大单元2的输出端A连接，该电容器C的第二端与电阻器R的第一端连接，该电阻器R的第二端与两级运算放大器的信号输出端Out连接。本实施例中，通过设置密勒补偿单元5，可使得主极点和非主极点分别向低频和高频移动实现极点分离，电阻器将右半平面的零点移向高频，可减小甚至抵消零点对系 统稳定性的影响。
图2为现有技术中的两级运算放大器的噪声特性曲线的示意图，图3为现有技术中的两级运算放大器的交流响应曲线的示意图，如图2和图3所示，通过仿真工具Spectre对现有技术中的两级运算放大器进行仿真分析，其仿真结果显示，现有技术中的两级运算放大器的单位增益带宽约为10MHz，直流增益为125.7dB，相位裕度为59.2°，在1MHz频率处的输入参考噪声大约为
Figure PCTCN2017081327-appb-000006
由此可见，现有技术中的两级运算放大器的增益与噪声都很大，高增益与低噪声性能不可同时满足。
图4为本发明实施例提供的两级运算放大器的噪声特性曲线的示意图，图5为本发明实施例提供的两级运算放大器的交流响应曲线的示意图，如图4和图5所示，通过仿真工具Spectre对本发明实施例中的两级运算放大器进行仿真分析，其仿真结果显示，本发明实施例提供的两级运算放大器的直流增益为114.3dB，即放大能力依然很强，在1MHz频率处的输入参考噪声约为
Figure PCTCN2017081327-appb-000007
相比现有技术而言，本发明实施例提供的两级运算放大器其噪声下降约2/3。由此可见，本发明实施例提供的两级运算放大器的增益大与噪声小，高增益与低噪声性能同时满足。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

  1. 一种两级运算放大器，包括：偏置电压生成单元、第一级运算放大单元和第二级运算放大单元；其中，
    所述偏置电压生成单元与所述第一级运算放大单元和所述第二级运算放大单元均连接，用于向所述第一级运算放大单元和所述第二级运算放大单元提供对应的偏置电压；
    所述第一级运算放大单元与所述第二级运算放大单元连接，用于提供高增益，并且包括：折叠式共源共栅放大电路和交叉耦合负载，所述交叉耦合负载与所述折叠式共源共栅放大电路中的负载差分对连接，所述交叉耦合负载包括两个晶体管，所述交叉耦合负载中的两个晶体管分别与对应的所述负载差分对中的两个晶体管一一对应，且构成两个电流镜结构，两个所述电流镜结构交叉耦合；以及
    第二级运算放大单元用于增大所述第一级运算放大单元所输出信号的输出摆幅。
  2. 根据权利要求1所述的两级运算放大器，其中，所述折叠式共源共栅放大电路包括：
    第一晶体管，其栅极与所述的偏置电压生成单元的第四偏置电压输出端连接，源极与第一电源端连接；
    第二晶体管，其栅极与第一信号输入端连接，源极与所述第一晶体管的漏极连接；
    第三晶体管，其栅极与第二信号输入端连接，源极与所述第一晶体管的漏极连接；
    第四晶体管，其栅极与所述第四偏置电压输出端连接，源极与第二电源端连接，漏极与所述第二晶体管的漏极连接；
    第五晶体管，其栅极与所述第四偏置电压输出端连接，源极与所述第二电源端连接，漏极与所述第三晶体管的漏极连接；
    第六晶体管，其栅极与所述偏置电压生成单元的第三偏置电压输出端连接，源极与所述第四晶体管的漏极连接；
    第七晶体管，其栅极与所述第三偏置电压输出端连接，源极与所述第五晶体管的漏极连接，漏极与所述第二级运算放大单元连接；
    第八晶体管，其栅极与所述偏置电压生成单元的第二偏置电压输出端连接，漏极与所述第六晶体管的漏极连接；
    第九晶体管，其栅极与所述第二偏置电压输出端连接，漏极与所述第七晶体管的漏极连接；
    第十晶体管，其栅极与所述第八晶体管的源极连接，漏极与所述第八晶体管的源极连接，源极与所述第一电源端连接；
    第十一晶体管，其栅极与所述第九晶体管的源极连接，漏极与所述第九晶体管的源极连接，源极与所述第一电源端连接；
    所述第十晶体管和第十一晶体管构成所述负载差分对。
  3. 根据权利要求2所述的两级运算放大器，其中，所述交叉耦合负载包括：
    第十二晶体管，其栅极与所述第八晶体管的源极连接，漏极与所述第九晶体管的源极连接，源极与所述第一电源端连接；
    第十三晶体管，其栅极与所述第九晶体管的源极连接，漏极与所述第八晶体管的源极连接，源极与所述第一电源端连接；
    所述第十二晶体管与所述第十晶体管构成电流镜结构，所述第十三晶体管与所述第十一晶体管构成电流镜结构。
  4. 根据权利要求3所述的两级运算放大器，其中，
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管和所述第十三晶体管均为N型MOS管；
    所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型MOS管。
  5. 根据权利要求4所述的两级运算放大器，其中，
    所述第一晶体管的沟道的宽度为1um，长度为600nm；
    所述第二晶体管和所述第三晶体管的沟道的宽度均为1.2um，长度均为600nm；
    所述第四晶体管和所述第五晶体管的沟道的宽度均为1um，长度均为5um；
    所述第六晶体管和所述第七晶体管的沟道的宽度均为1um，长度均为2.5um；
    所述第八晶体管和所述第九晶体管的沟道的宽度均为1um，长度均为8um；
    所述第十晶体管和所述第十一晶体管的沟道的宽度均为600nm，长度均为600nm；
    所述第十二晶体管和所述第十三晶体管的沟道的宽度均为600nm，长度均为600nm。
  6. 根据权利要求1至5中任一项所述的两级运算放大器，其中，所述偏置电压生成单元包括：
    第十四晶体管，其栅极与第一偏置电流输入端和第二偏置电压输出端连接，漏极与所述第一偏置电流输入端连接；
    第十五晶体管，其栅极与所述第二偏置电压输出端连接，漏极与第二偏置电流输入端连接；
    第十六晶体管，其栅极与所述第二偏置电压输出端连接，漏极与所述第十四晶体管的源极连接，源极与第一电源端连接；
    第十七晶体管，其栅极与所述第十五晶体管的源极和第三偏置电压输出端连接，源极与所述第一电源端连接；
    第十八晶体管，其栅极与第一偏置电压输出端连接，源极与第二电源端连接；
    第十九晶体管，其栅极与第四偏置电压输出端连接，源极与所述第二电源端连接，漏极与所述第四偏置电压输出端连接；
    第二十晶体管，其栅极与所述第一偏置电压输出端连接，源极与所述第十八晶体管的漏极连接，漏极与所述第一偏置电压输出端连接；
    第二十一晶体管，其栅极与所述第一偏置电压输出端连接，源极与所述第十九晶体管的漏极连接；
    第二十二晶体管，其栅极与所述第二偏置电压输出端连接，漏极与所述第二十晶体管的漏极连接；
    第二十三晶体管，其栅极与所述第二偏置电压输出端连接，漏极与所述第二十一晶体管的漏极连接；
    第二十四晶体管，其栅极与所述第三偏置电压输出端连接，漏极与所述第二十二晶体管的源极连接，源极与所述第一电源端连接；
    第二十五晶体管，其栅极与所述第三偏置电压输出端连接，漏极与所述第二十三晶体管的源极连接，源极与所述第一电源端连接。
  7. 根据权利要求6所述的两级运算放大器，其中，
    所述第十四晶体管、所述第十五晶体管、所述第十六晶体管、所述第十七晶体管、所述第二十二晶体管、所述第二十三晶体管、所述第二十四晶体管和所述第二十五晶体管均为N型MOS管；
    所述第十八晶体管、所述第十九晶体管、所述第二十晶体管和所述第二十一晶体管均为P型MOS管。
  8. 根据权利要求7所述的两级运算放大器，其中，
    所述第十四晶体管的沟道的宽度为910nm，长度为10um；
    所述第十五晶体管的沟道的宽度为1um，长度为7.5um；
    所述第十六晶体管和所述第十七晶体管的沟道的宽度均为600nm，长度均为10um；
    所述第十八晶体管的沟道的宽度为750nm，长度为10um；
    所述第十九晶体管的沟道的宽度为600nm，长度为10um；
    所述第二十晶体管的沟道的宽度为1.65um，长度为10um；
    所述第二十一晶体管的沟道的宽度为10um，长度为500nm；
    所述第二十二晶体管的沟道的宽度为3.2um，长度为1um；
    所述第二十三晶体管的沟道的宽度为1um，长度为10um；
    所述第二十四晶体管的沟道的宽度为5um，长度为4um；
    所述第二十五晶体管的沟道的宽度为600nm，长度为10um。
  9. 根据权利要求1至8中任一项所述的两级运算放大器，其中，第二级运算放大单元包括：
    第二十六晶体管，其栅极与所述第一级运算放大单元连接，源极与第二电源端连接，漏极与信号输出端连接；
    第二十七晶体管，其栅极与所述偏置电压生成单元的第一偏置电压输出端连接，漏极与所述信号输出端连接，源极与第一电源端连接。
  10. 根据权利要求9所述的两级运算放大器，其中，
    所述第二十六晶体管为P型MOS管，所述第二十七晶体管为N型MOS管。
  11. 根据权利要求10所述的两级运算放大器，其中，
    所述第二十六晶体管的沟道的宽度为9um，长度为1um；
    所述第二十七晶体管的沟道的宽度为8um，长度为800nm。
  12. 根据权利要求9所述的两级运算放大器，还包括：密勒补偿单元，所述密勒补偿单元包括：电阻器和电容器；
    所述电容器的第一端与所述第一级运算放大单元的输出端连接，所述电容器的第二端与所述电阻器的第一端连接；以及
    所述电阻器的第二端与所述两级运算放大器的信号输出端连接。
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