WO2017120994A1 - 电压产生电路及液晶电视 - Google Patents

电压产生电路及液晶电视 Download PDF

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Publication number
WO2017120994A1
WO2017120994A1 PCT/CN2016/073242 CN2016073242W WO2017120994A1 WO 2017120994 A1 WO2017120994 A1 WO 2017120994A1 CN 2016073242 W CN2016073242 W CN 2016073242W WO 2017120994 A1 WO2017120994 A1 WO 2017120994A1
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WIPO (PCT)
Prior art keywords
unit
voltage
output
driving
resistor
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Ceased
Application number
PCT/CN2016/073242
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English (en)
French (fr)
Inventor
郭东胜
王明良
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/032,550 priority Critical patent/US9898994B1/en
Publication of WO2017120994A1 publication Critical patent/WO2017120994A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display, and in particular to a voltage generating circuit and a liquid crystal television.
  • LCD TVs have been widely used due to their light weight, thin thickness and low power consumption. With the improvement of the living standards of the people, large-size, high-resolution, high-frame-rate LCD TVs are becoming more and more popular. However, with the increase of these technical indicators, the power consumption of the data driving chip of the liquid crystal panel is getting larger and larger, and the temperature is getting higher and higher. Therefore, how to reduce the power consumption of the data driving chip and lower the temperature has become an urgent problem to be solved. At present, increasing the chip size and attaching the heat sink can be achieved, but correspondingly, the overall cost is greatly increased.
  • the present invention provides a voltage generating circuit for reducing the temperature of a data driving chip of a liquid crystal television.
  • the invention also provides a liquid crystal television.
  • the present invention provides a voltage generating circuit for connecting to a driving unit of a data driving chip of a liquid crystal television to provide a driving voltage for the driving unit, the voltage generating circuit including a control unit, a controlled unit, and an output unit,
  • the control unit is configured to receive a trigger signal to generate a control signal having a preset delay, and the control unit is further connected to the controlled unit to control, by the control signal, the controlled unit at the preset delay a time period in a first state, in a second state during a non-preset delay time period, the output unit being coupled between the controlled unit and the drive unit to be in the controlled unit Outputting a first driving voltage to the driving unit in a first state, and outputting a second driving voltage to the driving unit when the controlled unit is in a second state, wherein the first driving voltage is smaller than the second Driving a voltage to thereby reduce a driving voltage output to the driving unit
  • the power consumption of the data driving chip is reduced.
  • the control unit includes a first electrical switch, a first resistor, a second resistor, a first capacitor, a second capacitor, and a timer chip, and the control end of the first electrical switch receives the trigger signal, where the a first end of an electrical switch is connected to the voltage source through the second resistor, and is further connected to a low trigger end of the timer chip, the second end of the first electrical switch is grounded, and the first end of the first resistor Connected to the voltage source, the second end of the first resistor is grounded through the first capacitor, and the high trigger end and the discharge end of the timer chip are connected between the first resistor and the first capacitor a voltage terminal of the timer chip is connected to the voltage source, a reset end of the timer chip is connected to the voltage source, and a control voltage end of the timer chip is grounded through the second capacitor
  • the ground terminal of the timer chip is connected to the controlled unit to control the controlled unit to output the first or second driving voltage.
  • the output unit includes a third resistor, a fourth resistor, a diode, an inductor, and a pulse width modulation chip, and the third and fourth resistors are connected in series between the output end of the controlled unit and the ground, the pulse a feedback terminal of the width modulation chip is coupled to a node between the third and fourth resistors, an input end of the pulse width modulation chip is coupled to the input voltage source through the inductor, and is coupled to an anode of the diode, The cathode of the diode is connected to the output of the controlled unit.
  • the controlled unit includes a second electrical switch and a fifth resistor, a control end of the second electrical switch is connected to an output end of the timer chip, and a first end of the second electrical switch is connected to the A first end of the fifth resistor, the second end of the fifth resistor being connected to the driving unit as an output of the controlled unit to output a first or second output voltage.
  • the first and second electrical switches are all NPN-type transistors, and the control terminals, the first ends and the second ends of the first and second switches are respectively a gate, a drain and a source of the transistors .
  • the present invention also provides a liquid crystal television comprising a data driving chip and a voltage generating circuit, the voltage generating circuit being connected to a driving unit of the data driving chip to provide a driving voltage for the driving unit, the voltage generating circuit comprising a control unit, a controlled unit and a output unit, the control unit is configured to receive a trigger signal to generate a control signal having a preset delay, and the control unit is further connected to the controlled unit to control the control signal by using the control signal
  • the controlled unit is in a first state during the preset delay time period, is in a second state during a non-preset delay time period, and the output unit is connected between the controlled unit and the driving unit To output the first when the controlled unit is in the first state Driving a voltage to the driving unit, outputting a second driving voltage to the driving unit when the controlled unit is in a second state, wherein the first driving voltage is smaller than the second driving voltage, thereby achieving a reduced output Driving voltage to the driving unit to reduce power consumption of the data driving chip.
  • the control unit includes a first electrical switch, a first resistor, a second resistor, a first capacitor, a second capacitor, and a timer chip, and the control end of the first electrical switch receives the trigger signal, where the a first end of an electrical switch is connected to the voltage source through the second resistor, and is further connected to a low trigger end of the timer chip, the second end of the first electrical switch is grounded, and the first end of the first resistor Connected to the voltage source, the second end of the first resistor is grounded through the first capacitor, and the high trigger end and the discharge end of the timer chip are connected between the first resistor and the first capacitor a voltage terminal of the timer chip is connected to the voltage source, a reset end of the timer chip is connected to the voltage source, and a control voltage end of the timer chip is grounded through the second capacitor
  • the ground terminal of the timer chip is connected to the controlled unit to control the controlled unit to output the first or second driving voltage.
  • the output unit includes a third resistor, a fourth resistor, a diode, an inductor, and a pulse width modulation chip, and the third and fourth resistors are connected in series between the output end of the controlled unit and the ground, the pulse a feedback terminal of the width modulation chip is coupled to a node between the third and fourth resistors, an input end of the pulse width modulation chip is coupled to the input voltage source through the inductor, and is coupled to an anode of the diode, The cathode of the diode is connected to the output of the controlled unit.
  • the controlled unit includes a second electrical switch and a fifth resistor, a control end of the second electrical switch is connected to an output end of the timer chip, and a first end of the second electrical switch is connected to the A first end of the fifth resistor, the second end of the fifth resistor being connected to the driving unit as an output of the controlled unit to output a first or second output voltage.
  • the driving unit includes an operational amplifier, third and fourth transistors, and an input end of the operational amplifier is connected to a logic control module of the data driving chip, and an output end of the operational amplifier is connected to the third a gate of the fourth transistor, a first end of the third transistor is coupled to a second end of the fifth resistor, and a second end of the third transistor is coupled to a first end of the fourth transistor The second end of the fourth transistor is grounded, and a node between the second end of the third transistor and the first end of the fourth transistor is connected to the liquid crystal cell of the liquid crystal television to provide a liquid crystal voltage.
  • a voltage generating circuit for connecting to a data driving chip of a liquid crystal television a unit for providing a driving voltage for the driving unit, the voltage generating circuit comprising a control unit, a controlled unit and an output unit, the control unit is configured to receive a trigger signal to generate a control signal with a preset delay, the control The unit is further connected to the controlled unit to control, by the control signal, that the controlled unit is in a first state during the preset delay time period, and is in a second time in a non-preset delay time period a state, the output unit is connected between the controlled unit and the driving unit to output a first driving voltage to the driving unit when the controlled unit is in a first state, in the controlled unit Outputting a second driving voltage to the driving unit when in the second state, wherein the first driving voltage is smaller than the second driving voltage, thereby reducing driving voltage output to the driving unit to reduce the data driving The power consumption of the chip. Therefore, the present invention achieves the purpose of reducing the function and temperature of the data driving chip.
  • FIG. 1 is a block diagram of a voltage generating circuit according to a first embodiment of the present invention.
  • FIG. 2 is a circuit diagram of FIG. 1.
  • FIG. 3 is a block diagram of a liquid crystal television according to a second embodiment of the present invention.
  • FIG. 4 is a circuit diagram of FIG. 3.
  • a first embodiment of the present invention provides a voltage generating circuit 100.
  • the voltage generating circuit 100 is for connecting to a driving unit of a data driving chip of a liquid crystal television to supply a driving voltage to the driving unit.
  • the voltage generating circuit 100 includes a control unit 10, a controlled unit 20, and Output unit 30.
  • the control unit 10 is configured to receive a trigger signal to generate a control signal having a preset delay.
  • the control unit 10 is further connected to the controlled unit 20 to control the controlled unit 20 to be in the first state during the preset delay time period by the control signal, in a non-preset delay
  • the second state is in the time period.
  • the output unit 30 is connected between the controlled unit 20 and the driving unit to output a first driving voltage to the driving unit when the controlled unit 20 is in a first state, in the controlled
  • the second driving voltage is output to the driving unit when the unit is in the second state.
  • the first driving voltage is smaller than the second driving voltage, thereby reducing a driving voltage output to the driving unit to reduce power consumption of the data driving chip.
  • the operating voltage received by the driving unit is the second driving voltage.
  • the operating voltage received by the driving unit is the first driving voltage, and the first driving voltage is less than the second driving voltage, so that The charging start current is also reduced, so the power consumption is also reduced, and the temperature of the data driving chip is also reduced.
  • the control unit 10 includes a first electrical switch Q1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a timer chip U1.
  • the control end of the first electrical switch Q1 receives the trigger signal.
  • the first end of the first electrical switch Q1 is connected to the voltage source V through the second resistor R2, and is also connected to the low trigger terminal /TR of the timer chip U1.
  • the second end of the first electrical switch Q1 is grounded.
  • the first end of the first resistor R1 is connected to the voltage source V, the second end of the first resistor R1 is grounded through the first capacitor C1, and the high trigger terminal TH of the timer chip U1 and
  • the discharge terminal DIS is connected to a node between the first resistor R1 and the first capacitor C1, and the voltage terminal VCC of the timer chip U1 is connected to the voltage source V, and the reset end of the timer chip U1
  • the RES is connected to the voltage source V, the control voltage terminal CO of the timer chip U1 is grounded through the second capacitor C2, the ground terminal GND of the timer chip U1 is grounded, and the output end of the timer chip U1 is An OUT is connected to the controlled unit 20 to control the controlled unit 20 to output a first or second driving voltage.
  • timer chip U1 is a 555 timer chip.
  • the trigger signal is a TP pulse signal.
  • the output unit 30 includes a third resistor R3, a fourth resistor R4, a diode D1, an inductor L, and a pulse width modulation chip U2.
  • the third and fourth resistors R3 and R4 are connected in series to the controlled unit 20 The output is between the ground and the ground.
  • the feedback end of the pulse width modulation chip U2 is connected to a node between the third and fourth resistors R3 and R4.
  • the input terminal Input of the pulse width modulation chip U2 is connected to the input voltage source Vin through the inductor L, and is connected to the anode of the diode D1.
  • the cathode of the diode D1 is connected to the output of the controlled unit 20.
  • the controlled unit 20 includes a second electrical switch Q2 and a fifth resistor R5.
  • the control end of the second electrical switch Q2 is connected to the output end OUT of the timer chip U, and the first end of the second electrical switch Q2 is connected to the first end of the fifth resistor R5, the first A second end of the five resistor R5 is connected to the driving unit as an output of the controlled unit 20 to output a first or second output voltage.
  • first and second electrical switches Q1 and Q2 are all NPN type transistors.
  • the control terminal, the first terminal and the second terminal of the first and second switches Q1 and Q2 are respectively a gate, a drain and a source of the transistor.
  • the first and second electrical switches Q1 and Q2 can also be other types of transistors as needed.
  • a second aspect of the present invention further provides a liquid crystal television 300.
  • the liquid crystal television 300 includes a data driving chip 310 and a voltage generating circuit.
  • the voltage generating circuit is the voltage generating circuit 100 provided by the first aspect described above.
  • the voltage generating circuit 100 is connected to the driving unit 320 of the data driving chip 310 to supply a driving voltage to the driving unit 320.
  • the voltage generating circuit 100 includes a control unit 10, a controlled unit 20, and an output unit 30.
  • the control unit 10 is configured to receive a trigger signal A control signal with a preset delay is generated.
  • the control unit 10 is further connected to the controlled unit 20 to control the controlled unit 20 to be in the first state during the preset delay time period by the control signal, in a non-preset delay
  • the second state is in the time period.
  • the output unit 30 is connected between the controlled unit 20 and the driving unit 320 to output a first driving voltage to the driving unit 320 when the controlled unit 20 is in the first state,
  • the controlled unit is in the second state and outputs a second driving voltage to the driving unit 320.
  • the first driving voltage is smaller than the second driving voltage, thereby reducing a driving voltage output to the driving unit 320 to reduce power consumption of the data driving chip.
  • the operating voltage received by the driving unit 320 is the second driving voltage.
  • the operating voltage received by the driving unit 320 is the first driving voltage, and the first driving voltage is less than the second driving voltage, when the charging delay is instantaneous.
  • the charging start current is also reduced, so the power consumption is also reduced, and the temperature of the data driving chip is also reduced.
  • the control unit 10 includes a first electrical switch Q1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a timer chip U1.
  • the control end of the first electrical switch Q1 receives the trigger signal.
  • the first end of the first electrical switch Q1 is connected to the voltage source V through the second resistor R2, and is also connected to the low trigger terminal /TR of the timer chip U1.
  • the second end of the first electrical switch Q1 is grounded.
  • the first end of the first resistor R1 is connected to the voltage source V, the second end of the first resistor R1 is grounded through the first capacitor C1, and the high trigger terminal TH of the timer chip U1 and
  • the discharge terminal DIS is connected to a node between the first resistor R1 and the first capacitor C1, and the voltage terminal VCC of the timer chip U1 is connected to the voltage source V, and the reset end of the timer chip U1
  • the RES is connected to the voltage source V, the control voltage terminal CO of the timer chip U1 is grounded through the second capacitor C2, the ground terminal GND of the timer chip U1 is grounded, and the output end of the timer chip U1 is An OUT is connected to the controlled unit 20 to control the controlled unit 20 to output a first or second driving voltage.
  • timer chip U1 is a 555 timer chip.
  • the trigger signal is a TP pulse signal.
  • the output unit 30 includes a third resistor R3, a fourth resistor R4, a diode D1, an inductor L, and a pulse width modulation chip U2.
  • the third and fourth resistors R3 and R4 are connected in series to the controlled unit 20 The output is between the ground and the ground.
  • the feedback end of the pulse width modulation chip U2 is connected to a node between the third and fourth resistors R3 and R4.
  • the input terminal Input of the pulse width modulation chip U2 is connected to the input voltage source Vin through the inductor L, and is connected to the anode of the diode D1.
  • the cathode of the diode D1 is connected to the output of the controlled unit 20.
  • the controlled unit 20 includes a second electrical switch Q2 and a fifth resistor R5.
  • the control end of the second electrical switch Q2 is connected to the output end OUT of the timer chip U, and the first end of the second electrical switch Q2 is connected to the first end of the fifth resistor R5, the first A second end of the five resistor R5 is connected to the driving unit 320 as an output of the controlled unit 20 to output a first or second output voltage.
  • the driving unit 320 includes an operational amplifier U3, third and fourth transistors Q3 and Q4.
  • the input of the operational amplifier U3 is for connection to a logic control module 330 of the data drive chip 310.
  • An output terminal of the operational amplifier U3 is connected to gates of the third and fourth transistors Q3 and Q4, and a first end of the third transistor Q3 is connected to a second end of the fifth resistor R5, A second end of the third transistor Q3 is coupled to the first terminal of the fourth transistor Q4.
  • the second end of the fourth crystal Q4 is grounded.
  • a node between the second end of the third transistor Q3 and the first end of the fourth transistor Q4 is connected to the liquid crystal cell 340 of the liquid crystal television to provide a liquid crystal voltage.
  • first and second electrical switches Q1 and Q2 are all NPN type transistors.
  • the control terminal, the first terminal and the second terminal of the first and second switches Q1 and Q2 are respectively a gate, a drain and a source of the transistor.
  • the first and second electrical switches Q1 and Q2 can also be other types of transistors as needed.
  • the time for the first driving voltage to decrease can be controlled, and by controlling the value of the fifth resistor R5, the driving can be controlled.
  • the voltage level of the driving voltage output by the circuit 30 According to this, a variety of different degrees of setting can be achieved.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Abstract

提供一种电压产生电路（100），包括控制单元（10）、受控单元（20）及输出单元（30），控制单元（10）用于接收触发信号来产生具有预设延时的控制信号，控制单元（10）还连接至受控单元（20），以通过控制信号来控制受控单元（20）在预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态，输出单元（30）连接在受控单元（20）及数据驱动芯片的驱动单元之间，以在受控单元（20）处于第一状态时输出第一驱动电压至驱动单元，在受控单元（20）处于第二状态时输出第二驱动电压至驱动单元，第一驱动电压小于第二驱动电压。还提供了一种液晶电视（300）。

Description

电压产生电路及液晶电视
本发明要求2016年1月15日递交的发明名称为“电压产生电路及液晶电视”的申请号201610028991.3的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种电压产生电路及液晶电视。
背景技术
液晶电视因其重量轻，厚度薄，功耗小，已被广泛普及。随着国民生活水平的提高，大尺寸，高解析度，高帧频的液晶电视愈来愈受欢迎。但随着这些技术指标的升高，液晶面板搭配的数据驱动芯片的功耗越来越大，温度也越来越高。因此，怎样降低数据驱动芯片的功耗从而降低温度已成为亟待解决的问题。目前，增加芯片尺寸以及贴散热片可以实现，但其相应地造成了整体成本的大幅攀升。
发明内容
本发明提供一种电压产生电路，以降低液晶电视的数据驱动芯片的温度。本发明还提供一种液晶电视。
本发明提供一种电压产生电路，用于连接至液晶电视的数据驱动芯片的驱动单元，以为所述驱动单元提供驱动电压，所述电压产生电路包括控制单元、受控单元及输出单元，所述控制单元用于接收触发信号来产生具有预设延时的控制信号，所述控制单元还连接至所述受控单元，以通过所述控制信号来控制所述受控单元在所述预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态，所述输出单元连接在所述受控单元及所述驱动单元之间，以在所述受控单元处于第一状态时输出第一驱动电压至所述驱动单元，在所述受控单元处于第二状态时输出第二驱动电压至所述驱动单元，其中，所述第一驱动电压小于所述第二驱动电压，从而实现降低输出至所述驱动单元的驱动电压来 降低所述数据驱动芯片的功耗。
其中，所述控制单元包括第一电开关、第一电阻、第二电阻、第一电容、第二电容及定时器芯片，所述第一电开关的控制端接收所述触发信号，所述第一电开关的第一端通过所述第二电阻连接至电压源，还连接至定时器芯片的低触发端，所述第一电开关的第二端接地，所述第一电阻的第一端连接至所述电压源，所述第一电阻的第二端通过所述第一电容接地，所述定时器芯片的高触发端及放电端均连接至所述第一电阻及第一电容之间的节点上，所述定时器芯片的电压端连接至所述电压源，所述定时器芯片的复位端连接至所述电压源，所述定时器芯片的控制电压端通过所述第二电容接地，所述定时器芯片的接地端基地，所述定时器芯片的输出端连接至所述受控单元，以控制所述受控单元输出第一或第二驱动电压。
其中，所述输出单元包括第三电阻、第四电阻、二极管、电感及脉冲宽度调制芯片，所述第三及第四电阻串联在所述受控单元的输出端与地之间，所述脉冲宽度调制芯片的反馈端连接至所述第三及第四电阻之间的节点，所述脉冲宽度调制芯片的输入端通过所述电感连接输入电压源，并连接至所述二极管的阳极，所述二极管的阴极连接至所述受控单元的输出端。
其中，所述受控单元包括第二电开关及第五电阻，所述第二电开关的控制端连接至所述定时器芯片的输出端，所述第二电开关的第一端连接至所述第五电阻的第一端，所述第五电阻的第二端作为所述受控单元的输出端连接至所述驱动单元，以输出第一或第二输出电压。
其中，所述第一及第二电开关均为NPN型三极管，所述第一及第二开关的控制端、第一端及第二端分别为所述三极管的栅极、漏极及源极。
本发明还提供一种液晶电视，包括数据驱动芯片及电压产生电路，所述电压产生电路连接至所述数据驱动芯片的驱动单元，以为驱动单元提供驱动电压，所述电压产生电路包括控制单元、受控单元及输出单元，所述控制单元用于接收触发信号来产生具有预设延时的控制信号，所述控制单元还连接至所述受控单元，以通过所述控制信号来控制所述受控单元在所述预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态，所述输出单元连接在所述受控单元及所述驱动单元之间，以在所述受控单元处于第一状态时输出第一 驱动电压至所述驱动单元，在所述受控单元处于第二状态时输出第二驱动电压至所述驱动单元，其中，所述第一驱动电压小于所述第二驱动电压，从而实现降低输出至所述驱动单元的驱动电压来降低所述数据驱动芯片的功耗。
其中，所述控制单元包括第一电开关、第一电阻、第二电阻、第一电容、第二电容及定时器芯片，所述第一电开关的控制端接收所述触发信号，所述第一电开关的第一端通过所述第二电阻连接至电压源，还连接至定时器芯片的低触发端，所述第一电开关的第二端接地，所述第一电阻的第一端连接至所述电压源，所述第一电阻的第二端通过所述第一电容接地，所述定时器芯片的高触发端及放电端均连接至所述第一电阻及第一电容之间的节点上，所述定时器芯片的电压端连接至所述电压源，所述定时器芯片的复位端连接至所述电压源，所述定时器芯片的控制电压端通过所述第二电容接地，所述定时器芯片的接地端基地，所述定时器芯片的输出端连接至所述受控单元，以控制所述受控单元输出第一或第二驱动电压。
其中，所述输出单元包括第三电阻、第四电阻、二极管、电感及脉冲宽度调制芯片，所述第三及第四电阻串联在所述受控单元的输出端与地之间，所述脉冲宽度调制芯片的反馈端连接至所述第三及第四电阻之间的节点，所述脉冲宽度调制芯片的输入端通过所述电感连接输入电压源，并连接至所述二极管的阳极，所述二极管的阴极连接至所述受控单元的输出端。
其中，所述受控单元包括第二电开关及第五电阻，所述第二电开关的控制端连接至所述定时器芯片的输出端，所述第二电开关的第一端连接至所述第五电阻的第一端，所述第五电阻的第二端作为所述受控单元的输出端连接至所述驱动单元，以输出第一或第二输出电压。
其中，所述驱动单元包括运算放大器、第三及第四晶体管，所述运算放大器的输入端用于连接至数据驱动芯片的逻辑控制模块，所述运算放大器的输出端连接至所述第三及第四晶体管的栅极，所述第三晶体管的第一端连接至所述第五电阻的第二端，所述第三晶体管的第二端连接至所述第四晶体管的第一端，所述第四晶体管的第二端接地，所述第三晶体管的第二端与所述第四晶体管的第一端之间的节点连接至液晶电视的液晶单元，以提供液晶电压。
本发明的一种电压产生电路，用于连接至液晶电视的数据驱动芯片的驱动 单元，以为所述驱动单元提供驱动电压，所述电压产生电路包括控制单元、受控单元及输出单元，所述控制单元用于接收触发信号来产生具有预设延时的控制信号，所述控制单元还连接至所述受控单元，以通过所述控制信号来控制所述受控单元在所述预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态，所述输出单元连接在所述受控单元及所述驱动单元之间，以在所述受控单元处于第一状态时输出第一驱动电压至所述驱动单元，在所述受控单元处于第二状态时输出第二驱动电压至所述驱动单元，其中，所述第一驱动电压小于所述第二驱动电压，从而实现降低输出至所述驱动单元的驱动电压来降低所述数据驱动芯片的功耗。因此，本发明实现了降低数据驱动芯片的功能及温度的目的。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一方案实施例提供的电压产生电路的框图。
图2为图1的电路图。
图3为本发明第二方案实施例提供的液晶电视的框图。
图4为图3的电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明第一实施例提供了一种电压产生电路100。所述电压产生电路100用于连接至液晶电视的数据驱动芯片的驱动单元，以为所述驱动单元提供驱动电压。所述电压产生电路100包括控制单元10、受控单元20及 输出单元30。所述控制单元10用于接收触发信号来产生具有预设延时的控制信号。所述控制单元10还连接至所述受控单元20，以通过所述控制信号来控制所述受控单元20在所述预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态。所述输出单元30连接在所述受控单元20及所述驱动单元之间，以在所述受控单元20处于第一状态时输出第一驱动电压至所述驱动单元，在所述受控单元处于第二状态时输出第二驱动电压至所述驱动单元。其中，所述第一驱动电压小于所述第二驱动电压，从而实现降低输出至所述驱动单元的驱动电压来降低所述数据驱动芯片的功耗。
需要说明的是，通常，所述驱动单元均接收到的工作电压为第二驱动电压。而在本实施例中，在充电瞬间时，经过所述预设延时时间，所述驱动单元接收到的工作电压为第一驱动电压，且第一驱动电压小于所述第二驱动电压，使得充电起始电流也会降低，因此功耗也会降低，进而数据驱动芯片的温度也会随之降低。
请参阅图2，所述控制单元10包括第一电开关Q1、第一电阻R1、第二电阻R2、第一电容C1、第二电容C2及定时器芯片U1。所述第一电开关Q1的控制端接收所述触发信号。所述第一电开关Q1的第一端通过所述第二电阻R2连接至电压源V，还连接至定时器芯片U1的低触发端/TR，所述第一电开关Q1的第二端接地，所述第一电阻R1的第一端连接至所述电压源V，所述第一电阻R1的第二端通过所述第一电容C1接地，所述定时器芯片U1的高触发端TH及放电端DIS均连接至所述第一电阻R1及第一电容C1之间的节点上，所述定时器芯片U1的电压端VCC连接至所述电压源V，所述定时器芯片U1的复位端RES连接至所述电压源V，所述定时器芯片U1的控制电压端CO通过所述第二电容C2接地，所述定时器芯片U1的接地端GND基地，所述定时器芯片U1的输出端OUT连接至所述受控单元20，以控制所述受控单元20输出第一或第二驱动电压。
需要说明的是，所述定时器芯片U1为555定时器芯片。触发信号为TP脉冲信号。
所述输出单元30包括第三电阻R3、第四电阻R4、二极管D1、电感L及脉冲宽度调制芯片U2，所述第三及第四电阻R3及R4串联在所述受控单元20 的输出端与地之间。所述脉冲宽度调制芯片U2的反馈端Feedback连接至所述第三及第四电阻R3及R4之间的节点。所述脉冲宽度调制芯片U2的输入端Input通过所述电感L连接输入电压源Vin，并连接至所述二极管D1的阳极。所述二极管D1的阴极连接至所述受控单元20的输出端。
所述受控单元20包括第二电开关Q2及第五电阻R5。所述第二电开关Q2的控制端连接至所述定时器芯片U的输出端OUT，所述第二电开关Q2的第一端连接至所述第五电阻R5的第一端，所述第五电阻R5的第二端作为所述受控单元20的输出端连接至所述驱动单元，以输出第一或第二输出电压。
需要说明的是，所述第一及第二电开关Q1及Q2均为NPN型三极管。所述第一及第二开关Q1及Q2的控制端、第一端及第二端分别为所述三极管的栅极、漏极及源极。在其他实施例中，所述第一及第二电开关Q1及Q2也可以根据需要为其他类型的晶体管。
具体的工作原理如下：所述触发信号经过所述第一电开关反相后，输入给所述定时器芯片U1的低触发端/TR，当低触发端/TR侦测到低电平时，所述定时器芯片U1输出高电平，打开所述第二电开关Q2，由于此时VAA1＝VFB*(1+R5R3/R4(R5+R3))，VAA电压即开始降低，经过时间T＝1.1*R1*C1后，所述定时器芯片U1输出由高电平切换为低电平，VAA2＝VFB*(1+R2/R3)，电压即开始恢复至正常准位。其中，VAA1为第一驱动电压；VAA2为第二驱动电压。因此，起始驱动电压降低，使得起始电流也会降低，因此功耗也会降低，进而数据驱动芯片的温度也会随之降低。
需要说明的是，通过控制R1与C1的取值，可以控制第一驱动电压降低的时间，通过控制R5的取值，可以控制所述驱动电路30输出的驱动电压的电压准位。据此可以实现多种不同程度的设定。
请参阅图3，本发明第二方案还提供一种液晶电视300。所述液晶电视300包括数据驱动芯片310及电压产生电路。其中，所述电压产生电路为上述第一方案提供的电压产生电路100。
具体地，所述电压产生电路100连接至所述数据驱动芯片310的驱动单元320，以为所述驱动单元320提供驱动电压。所述电压产生电路100包括控制单元10、受控单元20及输出单元30。所述控制单元10用于接收触发信号来 产生具有预设延时的控制信号。所述控制单元10还连接至所述受控单元20，以通过所述控制信号来控制所述受控单元20在所述预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态。所述输出单元30连接在所述受控单元20及所述驱动单元320之间，以在所述受控单元20处于第一状态时输出第一驱动电压至所述驱动单元320，在所述受控单元处于第二状态时输出第二驱动电压至所述驱动单元320。其中，所述第一驱动电压小于所述第二驱动电压，从而实现降低输出至所述驱动单元320的驱动电压来降低所述数据驱动芯片的功耗。
需要说明的是，通常，所述驱动单元320均接收到的工作电压为第二驱动电压。而在本实施例中，在充电瞬间时，经过所述预设延时时间，所述驱动单元320接收到的工作电压为第一驱动电压，且第一驱动电压小于所述第二驱动电压，使得充电起始电流也会降低，因此功耗也会降低，进而数据驱动芯片的温度也会随之降低。
请参阅图4，所述控制单元10包括第一电开关Q1、第一电阻R1、第二电阻R2、第一电容C1、第二电容C2及定时器芯片U1。所述第一电开关Q1的控制端接收所述触发信号。所述第一电开关Q1的第一端通过所述第二电阻R2连接至电压源V，还连接至定时器芯片U1的低触发端/TR，所述第一电开关Q1的第二端接地，所述第一电阻R1的第一端连接至所述电压源V，所述第一电阻R1的第二端通过所述第一电容C1接地，所述定时器芯片U1的高触发端TH及放电端DIS均连接至所述第一电阻R1及第一电容C1之间的节点上，所述定时器芯片U1的电压端VCC连接至所述电压源V，所述定时器芯片U1的复位端RES连接至所述电压源V，所述定时器芯片U1的控制电压端CO通过所述第二电容C2接地，所述定时器芯片U1的接地端GND基地，所述定时器芯片U1的输出端OUT连接至所述受控单元20，以控制所述受控单元20输出第一或第二驱动电压。
需要说明的是，所述定时器芯片U1为555定时器芯片。触发信号为TP脉冲信号。
所述输出单元30包括第三电阻R3、第四电阻R4、二极管D1、电感L及脉冲宽度调制芯片U2，所述第三及第四电阻R3及R4串联在所述受控单元20 的输出端与地之间。所述脉冲宽度调制芯片U2的反馈端Feedback连接至所述第三及第四电阻R3及R4之间的节点。所述脉冲宽度调制芯片U2的输入端Input通过所述电感L连接输入电压源Vin，并连接至所述二极管D1的阳极。所述二极管D1的阴极连接至所述受控单元20的输出端。
所述受控单元20包括第二电开关Q2及第五电阻R5。所述第二电开关Q2的控制端连接至所述定时器芯片U的输出端OUT，所述第二电开关Q2的第一端连接至所述第五电阻R5的第一端，所述第五电阻R5的第二端作为所述受控单元20的输出端连接至所述驱动单元320，以输出第一或第二输出电压。
所述驱动单元320包括运算放大器U3、第三及第四晶体管Q3及Q4。所述运算放大器U3的输入端用于连接至数据驱动芯片310的逻辑控制模块330。所述运算放大器U3的输出端连接至所述第三及第四晶体管Q3及Q4的栅极，所述第三晶体管Q3的第一端连接至所述第五电阻R5的第二端，所述第三晶体管Q3的第二端连接至所述第四晶体管Q4的第一端。所述第四晶体Q4的第二端接地。所述第三晶体管Q3的第二端与所述第四晶体管Q4的第一端之间的节点连接至液晶电视的液晶单元340，以提供液晶电压。
需要说明的是，所述第一及第二电开关Q1及Q2均为NPN型三极管。所述第一及第二开关Q1及Q2的控制端、第一端及第二端分别为所述三极管的栅极、漏极及源极。在其他实施例中，所述第一及第二电开关Q1及Q2也可以根据需要为其他类型的晶体管。
具体的工作原理如下：所述触发信号经过所述第一电开关反相后，输入给所述定时器芯片U1的低触发端/TR，当低触发端/TR侦测到低电平时，所述定时器芯片U1输出高电平，打开所述第二电开关Q2，由于此时VAA1＝VFB*(1+R5R3/R4(R5+R3))，VAA电压即开始降低，经过时间T＝1.1*R1*C1后，所述定时器芯片U1输出由高电平切换为低电平，VAA2＝VFB*(1+R2/R3)，电压即开始恢复至正常准位。其中，VAA1为第一驱动电压；VAA2为第二驱动电压。因此，起始驱动电压降低，使得起始电流也会降低，因此功耗也会降低，进而数据驱动芯片的温度也会随之降低。
需要说明的是，通过控制第一电阻R1与第一电容C1的取值，可以控制第一驱动电压降低的时间，通过控制第五电阻R5的取值，可以控制所述驱动 电路30输出的驱动电压的电压准位。据此可以实现多种不同程度的设定。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种电压产生电路，用于连接至液晶电视的数据驱动芯片的驱动单元，以为所述驱动单元提供驱动电压，所述电压产生电路包括控制单元、受控单元及输出单元，所述控制单元用于接收触发信号来产生具有预设延时的控制信号，所述控制单元还连接至所述受控单元，以通过所述控制信号来控制所述受控单元在所述预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态，所述输出单元连接在所述受控单元及所述驱动单元之间，以在所述受控单元处于第一状态时输出第一驱动电压至所述驱动单元，在所述受控单元处于第二状态时输出第二驱动电压至所述驱动单元，其中，所述第一驱动电压小于所述第二驱动电压，从而实现降低输出至所述驱动单元的驱动电压来降低所述数据驱动芯片的功耗。
  2. 如权利要求1所述的电压产生电路，其中，所述控制单元包括第一电开关、第一电阻、第二电阻、第一电容、第二电容及定时器芯片，所述第一电开关的控制端接收所述触发信号，所述第一电开关的第一端通过所述第二电阻连接至电压源，还连接至定时器芯片的低触发端，所述第一电开关的第二端接地，所述第一电阻的第一端连接至所述电压源，所述第一电阻的第二端通过所述第一电容接地，所述定时器芯片的高触发端及放电端均连接至所述第一电阻及第一电容之间的节点上，所述定时器芯片的电压端连接至所述电压源，所述定时器芯片的复位端连接至所述电压源，所述定时器芯片的控制电压端通过所述第二电容接地，所述定时器芯片的接地端基地，所述定时器芯片的输出端连接至所述受控单元，以控制所述受控单元输出第一或第二驱动电压。
  3. 如权利要求2所述的电压产生电路，其中，所述输出单元包括第三电阻、第四电阻、二极管、电感及脉冲宽度调制芯片，所述第三及第四电阻串联在所述受控单元的输出端与地之间，所述脉冲宽度调制芯片的反馈端连接至所述第三及第四电阻之间的节点，所述脉冲宽度调制芯片的输入端通过所述电感连接输入电压源，并连接至所述二极管的阳极，所述二极管的阴极连接至所述受控单元的输出端。
  4. 如权利要求3所述的电压产生电路，其中，所述受控单元包括第二电开 关及第五电阻，所述第二电开关的控制端连接至所述定时器芯片的输出端，所述第二电开关的第一端连接至所述第五电阻的第一端，所述第五电阻的第二端作为所述受控单元的输出端连接至所述驱动单元，以输出第一或第二输出电压。
  5. 如权利要求4所述的电压产生电路，其中，所述第一及第二电开关均为NPN型三极管，所述第一及第二开关的控制端、第一端及第二端分别为所述三极管的栅极、漏极及源极。
  6. 一种液晶电视，包括数据驱动芯片及电压产生电路，所述电压产生电路连接至所述数据驱动芯片的驱动单元，以为驱动单元提供驱动电压，所述电压产生电路包括控制单元、受控单元及输出单元，所述控制单元用于接收触发信号来产生具有预设延时的控制信号，所述控制单元还连接至所述受控单元，以通过所述控制信号来控制所述受控单元在所述预设延时时间段内处于第一状态，在非预设延时时间段内处于第二状态，所述输出单元连接在所述受控单元及所述驱动单元之间，以在所述受控单元处于第一状态时输出第一驱动电压至所述驱动单元，在所述受控单元处于第二状态时输出第二驱动电压至所述驱动单元，其中，所述第一驱动电压小于所述第二驱动电压，从而实现降低输出至所述驱动单元的驱动电压来降低所述数据驱动芯片的功耗。
  7. 如权利要求6所述的液晶电视，其中，所述控制单元包括第一电开关、第一电阻、第二电阻、第一电容、第二电容及定时器芯片，所述第一电开关的控制端接收所述触发信号，所述第一电开关的第一端通过所述第二电阻连接至电压源，还连接至定时器芯片的低触发端，所述第一电开关的第二端接地，所述第一电阻的第一端连接至所述电压源，所述第一电阻的第二端通过所述第一电容接地，所述定时器芯片的高触发端及放电端均连接至所述第一电阻及第一电容之间的节点上，所述定时器芯片的电压端连接至所述电压源，所述定时器芯片的复位端连接至所述电压源，所述定时器芯片的控制电压端通过所述第二电容接地，所述定时器芯片的接地端基地，所述定时器芯片的输出端连接至所述受控单元，以控制所述受控单元输出第一或第二驱动电压。
  8. 如权利要求7所述的液晶电视，其中，所述输出单元包括第三电阻、第四电阻、二极管、电感及脉冲宽度调制芯片，所述第三及第四电阻串联在所述 受控单元的输出端与地之间，所述脉冲宽度调制芯片的反馈端连接至所述第三及第四电阻之间的节点，所述脉冲宽度调制芯片的输入端通过所述电感连接输入电压源，并连接至所述二极管的阳极，所述二极管的阴极连接至所述受控单元的输出端。
  9. 如权利要求8所述的液晶电视，其中，所述受控单元包括第二电开关及第五电阻，所述第二电开关的控制端连接至所述定时器芯片的输出端，所述第二电开关的第一端连接至所述第五电阻的第一端，所述第五电阻的第二端作为所述受控单元的输出端连接至所述驱动单元，以输出第一或第二输出电压。
  10. 如权利要求9所述的液晶电视，其中，所述驱动单元包括运算放大器、第三及第四晶体管，所述运算放大器的输入端用于连接至数据驱动芯片的逻辑控制模块，所述运算放大器的输出端连接至所述第三及第四晶体管的栅极，所述第三晶体管的第一端连接至所述第五电阻的第二端，所述第三晶体管的第二端连接至所述第四晶体管的第一端，所述第四晶体管的第二端接地，所述第三晶体管的第二端与所述第四晶体管的第一端之间的节点连接至液晶电视的液晶单元，以提供液晶电压。
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