WO2017117983A1 - 像素补偿电路及amoled显示装置 - Google Patents

像素补偿电路及amoled显示装置 Download PDF

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Publication number
WO2017117983A1
WO2017117983A1 PCT/CN2016/092045 CN2016092045W WO2017117983A1 WO 2017117983 A1 WO2017117983 A1 WO 2017117983A1 CN 2016092045 W CN2016092045 W CN 2016092045W WO 2017117983 A1 WO2017117983 A1 WO 2017117983A1
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Prior art keywords
transistor
reference voltage
drain
capacitor
driving transistor
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PCT/CN2016/092045
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English (en)
French (fr)
Inventor
何小祥
祁小敬
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US15/516,268 priority Critical patent/US10255858B2/en
Publication of WO2017117983A1 publication Critical patent/WO2017117983A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel compensation circuit and an AMOLED display device.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and the like, and thus has been widely used.
  • the conventional flat display device mainly includes a liquid crystal display device (hereinafter referred to as LCD) and an organic light emitting diode (hereinafter referred to as OLED) display device.
  • LCD liquid crystal display device
  • OLED organic light emitting diode
  • the OLED display device realizes display by self-illumination, so that it does not need a backlight, and the OLED display device has high contrast, small thickness, wide viewing angle, fast response speed, can be made into a flexible display panel, has a wide temperature range, and is constructed and processed. It is a simpler and other excellent feature, so it is considered as a next-generation display device that can replace LCD.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely, direct addressing and thin film transistor (TFT). ) Matrix addressing two categories.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • TFT thin film transistor
  • FIG. 1 is a circuit diagram of a conventional AMOLED pixel circuit.
  • the pixels are arranged in a matrix including a plurality of rows and columns, and each pixel is usually driven by a pixel circuit composed of two thin film transistors and a capacitor (Capacitor), that is, using 2T1C.
  • Capacitor Capacitor
  • the source of the second transistor T2 is electrically connected to the high voltage signal terminal VDD, and the drain of the second transistor T2 is electrically connected to the anode of the organic light emitting diode D.
  • the cathode of the organic light emitting diode D is electrically connected to the common ground electrode VSS.
  • one end of the capacitor C is electrically connected to the drain of the first transistor T1, and the other end of the capacitor C is electrically connected to the source of the second transistor T2.
  • the gate voltage of the second transistor T2 can still remain as the data signal voltage, so that the second transistor T2 is in an on state, and the driving current corresponding to the high voltage signal terminal VDD and the data signal voltage passes through the second The transistor T2 enters the organic light emitting diode D to drive the organic light emitting diode D to emit light.
  • the organic light emitting diode D emits light according to a driving current generated by the second transistor T2 in a saturated state. Due to the non-uniformity in the TFT process, the threshold voltage of the second transistor T2 in each pixel is different, and the threshold voltage Vth of the second transistor T2 may drift to different degrees during the illumination process of the organic light emitting diode D, When the driving circuit of the 2T1C is driven, the brightness uniformity of each pixel is poor, resulting in uneven display.
  • the present disclosure provides a pixel compensation circuit and an AMOLED display device including the pixel compensation circuit, which can prevent a luminance change of a light-emitting device during a light-emitting process, thereby improving illumination. Luminance uniformity of the device during illumination.
  • Embodiments of the present invention provide a pixel compensation circuit including a data signal writing module, a high voltage signal writing module, a first reference voltage writing module, a second reference voltage writing module, a voltage maintaining module, a driving transistor, and a capacitor. And light emitting devices.
  • the data signal writing module is connected to the first end of the capacitor, the first reference voltage writing module is connected to the control electrode of the driving transistor, and the second reference voltage writing module is connected to the drain of the driving transistor.
  • the high voltage signal writing module is coupled to a second end of the capacitor, the voltage maintaining module being coupled to the first end of the capacitor and the control electrode of the driving transistor.
  • a source of the driving transistor is coupled to a second end of the capacitor, and a drain of the driving transistor is coupled to an anode of the light emitting device.
  • the cathode of the light emitting device is connected to a common ground electrode.
  • the pixel compensation circuit further includes a connection control module connected between the drain of the driving transistor and the anode of the light emitting device for controlling on and off between the driving transistor and the light emitting device.
  • the data signal writing module includes a data signal line and a first transistor, a control electrode of the first transistor is connected to a gate line, and a source of the first transistor is connected to a data signal line, where the A drain of a transistor is coupled to the first end of the capacitor.
  • the first reference voltage writing module includes a first reference voltage terminal and a second transistor, a control electrode of the second transistor is connected to the gate line, a source of the second transistor and a first reference voltage The terminal is connected, and the drain of the second transistor is connected to the control electrode of the driving transistor.
  • the second reference voltage writing module includes a second reference voltage terminal and a third transistor, a control electrode of the third transistor is connected to the gate line, and a source of the third transistor and a second reference voltage The terminal is connected, and the drain of the third transistor is connected to the drain of the driving transistor and the anode of the light emitting device.
  • the second reference voltage writing module includes a second reference voltage terminal and a third transistor, a control electrode of the third transistor is connected to the gate line, a source of the third transistor and a second reference voltage The terminal is connected, and the drain of the third transistor is connected to the drain of the driving transistor and the connection control module.
  • the high voltage signal writing module includes a high voltage signal terminal and a fourth transistor, a control electrode of the fourth transistor is connected to the first lighting signal terminal, and a source and a high voltage signal of the fourth transistor are The terminal is connected, and the drain of the fourth transistor is connected to the second end of the capacitor.
  • the voltage maintaining module includes a fifth transistor, a control electrode of the fifth transistor is connected to the first lighting signal end, and a source of the fifth transistor is connected to the first end of the capacitor, A drain of the fifth transistor is coupled to a gate of the drive transistor.
  • connection control module includes a sixth transistor, a control electrode of the sixth transistor is connected to the second illuminating signal end, and a source of the sixth transistor and a drain of the driving transistor and a second reference voltage are written.
  • the input module is connected, and the drain of the sixth transistor is connected to the anode of the light emitting device.
  • An embodiment of the present invention further provides an AMOLED display device including the above pixel compensation circuit.
  • the first reference voltage writing module and the second reference voltage writing module respectively write the first reference voltage to the gate and the drain of the driving transistor in the pre-lighting stage of the light emitting device.
  • a second reference voltage such that a voltage of a source of the driving transistor includes a component of a threshold voltage Vth of the driving transistor, thereby causing a driving current generated in a light emitting phase of the light emitting device and a threshold voltage of the driving transistor and a high voltage signal terminal
  • the voltage is independent, so that the uniformity of the manufacturing process of the driving transistor, the drift of the threshold voltage Vth of the driving transistor during the light emitting process, and the voltage drop of the high voltage signal end do not affect the luminance of the light emitting device, thereby avoiding the light emitting device being
  • the brightness during the illuminating process changes, and the brightness uniformity of the illuminating device during the illuminating process is improved.
  • the capacitor in the light-emitting phase of the light-emitting device, the capacitor remains in a suspended state such that a voltage difference across the two ends (ie, a voltage difference between a gate and a source of the driving transistor) remains unchanged, so that the driving current It does not change due to the voltage change of the high voltage signal terminal, thereby further avoiding the change of the brightness of the light emitting device during the light emitting process, and improving the brightness uniformity of the light emitting device during the light emitting process.
  • a voltage difference across the two ends ie, a voltage difference between a gate and a source of the driving transistor
  • the AMOLED display device of the embodiment of the invention adopts the above-mentioned pixel compensation circuit of the embodiment of the invention, which can avoid the change of the illumination brightness of the light-emitting device in each pixel in one frame, and can avoid the process of driving the transistor in each pixel.
  • the process causes the luminance of the light-emitting device in each pixel to be uneven, thereby improving the display effect and display uniformity.
  • FIG. 1 is a circuit diagram of a conventional AMOLED pixel circuit
  • FIG. 2 is a circuit diagram of a pixel compensation circuit in accordance with an embodiment of the present invention.
  • FIG. 3 is a timing chart of signals in the pixel compensation circuit shown in FIG. 2;
  • Figure 4 is an equivalent circuit diagram of the t1 phase
  • Figure 5 is an equivalent circuit diagram of the t2 phase
  • FIG. 6 is a circuit diagram of a pixel compensation circuit in accordance with an embodiment of the present invention.
  • Fig. 7 is a timing chart of signals in the pixel compensation circuit shown in Fig. 6.
  • the pixel compensation circuit includes a data signal writing module 1, a high voltage signal writing module 2, a first reference voltage writing module 3, and a second reference voltage writing module 4.
  • the data signal writing module 1 is connected to the first end of the capacitor C.
  • the first reference voltage writing module 3 is connected to the control electrode of the driving transistor DTFT.
  • the second reference voltage writing module 4 is connected to the drain of the driving transistor DTFT.
  • the high voltage signal writing module 2 is connected to the second end of the capacitor C.
  • the voltage maintaining module 5 is connected to the first end of the capacitor C and the control electrode of the driving transistor DTFT.
  • the source of the driving transistor DTFT is connected to the second end of the capacitor C, and the drain of the driving transistor DTFT is connected to the anode of the light emitting device 6.
  • the cathode of the light emitting device 6 is connected to a common ground electrode VSS.
  • the light emitting device 6 may include an OLED (Organic Light Emitting Diode).
  • the data signal writing module 1 includes a data signal line DATA and a first transistor T1.
  • the data signal line DATA outputs a data signal DATA whose voltage value is VDATA.
  • a control electrode (ie, a gate) of the first transistor T1 is connected to a gate line Scan, a source of the first transistor T1 is connected to a data signal line DATA, and a drain of the first transistor T1 and the capacitor C The first end of the connection.
  • the first reference voltage writing module 3 includes a first reference voltage terminal Vf and a second transistor T2.
  • the first reference voltage terminal Vf outputs a first reference voltage Vf.
  • a control electrode (ie, a gate) of the second transistor T2 is connected to a gate line Scan, a source of the second transistor T2 is connected to a first reference voltage terminal Vf, and a drain of the second transistor T2 is The gate (ie, gate) of the driving transistor DTFT is connected.
  • the second reference voltage writing module 4 includes a second reference voltage terminal Vi and a third transistor T3.
  • the second reference voltage terminal Vi outputs a second reference voltage Vi.
  • a control electrode (ie, a gate) of the third transistor T3 is connected to a gate line Scan, a source of the third transistor T3 is connected to a second reference voltage terminal Vi, and a drain of the third transistor T3 is The drain of the driving transistor DTFT is connected to the anode of the light emitting device 6.
  • the high voltage signal writing module 2 includes a high voltage signal terminal VDD and a fourth transistor T4.
  • the high voltage signal terminal VDD outputs a high voltage signal VDD.
  • the control electrode (ie, the gate) of the fourth transistor T4 is connected to the first light-emitting signal terminal EM1, the source of the fourth transistor T4 is connected to the high-voltage signal terminal VDD, and the drain of the fourth transistor T4 is The second end of the capacitor C is connected.
  • the voltage maintaining module 5 includes a fifth transistor T5.
  • a control electrode (ie, a gate) of the fifth transistor T5 is connected to the first light-emitting signal terminal EM1
  • a source of the fifth transistor T5 is connected to a first end of the capacitor C
  • the fifth transistor T5 is The drain is connected to a gate (ie, a gate) of the driving transistor DTFT.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the driving transistor DTFT are P-type transistors.
  • the timing of each signal is as shown in FIG.
  • the process of driving the light-emitting device 6 to emit light by the pixel compensation circuit shown in FIG. 2 will be described in detail below with reference to the timing shown in FIG.
  • the first stage t1 is a period in which the light-emitting device 6 does not emit light (i.e., a pre-lighting stage). Specifically, at this stage, the scan signal output by the gate line Scan is at a low level, the light-emitting signal outputted by the first light-emitting signal terminal EM1 is at a high level, and the data signal output from the data signal line DATA is at a high level. In this case, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off. At this time, an equivalent circuit diagram is shown in FIG.
  • the data signal line DATA is in communication with the first end of the capacitor C, which inputs the data signal DATA to the first terminal of the capacitor C such that the voltage at the first terminal of the capacitor C is VDATA.
  • the first reference voltage terminal Vf is connected to the gate of the driving transistor DTFT such that the gate voltage of the driving transistor DTFT is equal to the first reference voltage Vf.
  • the second reference voltage terminal Vi is connected to the drain of the driving transistor DTFT to drive The drain voltage of the transistor DTFT is equal to the second reference voltage Vi.
  • the drain of the driving transistor DTFT maintains the voltage at the end of the previous frame picture, the voltage of which is specifically VDD.
  • the first reference voltage terminal Vf and the second reference voltage are respectively connected to the gate and the drain of the driving transistor DTFT.
  • the source voltage of the driving transistor DTFT i.e., the voltage on the second terminal of the capacitor C
  • it satisfies the following formula (1):
  • Vs Vf-Vth ⁇ (1)
  • Vs is the voltage of the source of the driving transistor DTFT
  • Vth is the threshold voltage of the driving transistor DTFT
  • the voltage of the source of the driving transistor DTFT contains the component of the threshold voltage Vth of the driving transistor DTFT, thereby achieving the grabbing of the threshold voltage Vth. Further, in the present embodiment, by setting the value of the second reference voltage Vi, it is possible to grasp the threshold voltage Vth in the case of different Vds (that is, the voltage difference between the source and the drain of the driving transistor DTFT).
  • the second reference voltage terminal Vi may also be connected to the anode of the light emitting device 6, and the second reference voltage Vi is written to the anode of the light emitting device 6, thereby clearing the light emitting device 6 in the t1 phase.
  • the voltage of the previous frame is maintained by the anode, so that the luminance of the light-emitting device 6 in the light-emitting phase of the frame can be made accurate without deviation.
  • the second phase t2 is the illumination phase of the light emitting device 6.
  • the scan signal output by the gate line Scan is at a high level
  • the light-emitting signal outputted by the first light-emitting signal terminal EM1 is at a low level
  • the data signal DATA output by the data signal line DATA is at a low level.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are turned off
  • the fourth transistor T4 and the fifth transistor T5 are turned on.
  • an equivalent circuit diagram is shown in FIG.
  • the gate of the driving transistor DTFT is connected to the first end of the capacitor C, and the source of the driving transistor DTFT is connected to the second end of the capacitor C. Therefore, the voltage difference Vgs between the gate and the source of the driving transistor DTFT is equal to the voltage difference ⁇ s between both ends of the capacitor C.
  • the high voltage signal terminal VDD and capacitor The second end of the device C and the source of the driving transistor DTFT are connected such that the voltage of the second terminal of the capacitor C and the source of the driving transistor DTFT becomes VDD.
  • I OLED k(Vgs-Vth) 2
  • the current I OLED that drives the light-emitting device 6 to emit light is independent of the threshold voltage Vth of the driving transistor DTFT, and is also independent of VDD. Therefore, the uniformity of the process of driving the transistor DTFT, the drift of the threshold voltage Vth of the driving transistor DTFT during the light emission, and the voltage drop of VDD (IR Drop) do not affect the luminance of the light emitting device 6, thereby avoiding The brightness of the light-emitting device 6 during the light-emitting process changes, and the brightness uniformity of the light-emitting device 6 during the light-emitting process is improved.
  • the capacitor C is in the floating state, when the voltage of the high voltage signal terminal VDD changes, the voltage difference ⁇ s between the both ends of the capacitor C does not change, that is, the gate and source of the driving transistor DTFT The voltage difference Vgs between the poles is maintained, so that the generated driving current I OLED does not fluctuate due to the voltage change of VDD, so that the driving current I OLED can be further ensured to be stable, and the light-emitting device 6 is prevented from being illuminated.
  • the brightness changes to improve the brightness uniformity of the light-emitting device 6 during the light-emitting process.
  • the threshold voltage Vth under different Vds values can be captured, so that the influence of the threshold voltage Vth under different Vds can be specifically eliminated, thereby obtaining more
  • the good compensation effect makes the current for driving the light-emitting device 6 generated in the t2 stage more stable, and ensures the uniformity of the light-emitting brightness of the light-emitting device 6.
  • the pixel compensation circuit of the present embodiment further includes a connection control module 7 connected between the drain of the driving transistor DTFT and the anode of the light emitting device 6 for control. The switching between the transistor DTFT and the light emitting device 6 is turned on and off.
  • the second reference voltage writing module 4 includes a second reference voltage terminal Vi and a third transistor T3, and a control electrode (ie, a gate) and a gate line Scan of the third transistor T3.
  • the source of the third transistor T3 is connected to the second reference voltage terminal Vi
  • the drain of the third transistor T3 is connected to the drain of the driving transistor DTFT and the connection control module 7.
  • the connection control module 7 includes a sixth transistor T6, and a control electrode (ie, a gate) of the sixth transistor T6 is connected to the second light-emitting signal terminal EM2, and a source of the sixth transistor T6 and a driving transistor DTFT.
  • the drain is connected to the second reference voltage writing module 4, and the drain of the sixth transistor T6 is connected to the anode of the light emitting device 6.
  • Fig. 7 is a timing chart of signals in the pixel compensation circuit shown in Fig. 6.
  • the pre-lighting stage of the light-emitting device 6 is divided into two stages of t1 and t2, and the light-emitting stage of the light-emitting device 6 is the third stage, that is, the stage t3.
  • the illumination signal output by the first illumination signal terminal EM1 is at a low level
  • the scan signal outputted by the gate line Scan is at a high level
  • the illumination signal outputted by the second illumination signal terminal EM2 is at a high level.
  • the data signal DATA output by the data signal line DATA is at a low level.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are turned off
  • the fourth transistor T4 and the fifth transistor T5 are turned on
  • the sixth transistor T6 is turned off.
  • the high voltage signal terminal VDD is connected to the second terminal of the capacitor C and the source of the driving transistor DTFT, so that the voltage of the second terminal of the capacitor C and the source of the driving transistor DTFT is VDD.
  • the t2 phase is the same as the t1 phase in the above embodiment, and the t3 phase is the same as the t2 phase in the above embodiment, and will not be described again here.
  • a phase is added before the t1 phase in the above embodiment, and a voltage VDD is written to the second terminal of the capacitor C and the source of the driving transistor DTFT at this stage, which can be ended in the previous frame. And when the voltage of the second end of the capacitor C and the source of the driving transistor DTFT is abnormal, the capacitor C in the frame of the frame is guaranteed.
  • the initial voltage of the second terminal and the source of the driving transistor DTFT is VDD.
  • the first reference voltage writing module 3 and the second reference voltage writing module 4 are respectively driven to the driving transistor DTFT.
  • the gate and the drain write the first reference voltage Vf and the second reference voltage Vi such that the voltage of the source of the driving transistor DTFT includes a component of the threshold voltage Vth of the driving transistor DTFT, thereby causing the light emitting phase of the light emitting device 6
  • the generated driving current is independent of the threshold voltage of the driving transistor DTFT and the voltage of the high voltage signal terminal VDD, such that the uniformity of the process of driving the transistor DTFT, the drift of the threshold voltage Vth of the driving transistor DTFT during the light emission, and the high voltage
  • the voltage drop of the signal terminal VDD does not affect the luminance of the light-emitting device 6, so that the luminance of the light-emitting device 6 during the light-emitting process can be prevented from being changed, and the brightness uniformity of the light-
  • the capacitor C is kept in a suspended state such that the voltage difference across it (ie, the voltage difference between the gate and the source of the driving transistor DTFT) remains unchanged, thereby The driving current does not fluctuate due to the voltage change of the high voltage signal terminal VDD, thereby further preventing the luminance of the light emitting device 6 from changing during the light emitting process, and improving the brightness uniformity of the light emitting device 6 during the light emitting process.
  • an embodiment of the present invention further provides an AMOLED display device.
  • the AMOLED display device includes the pixel compensation circuit provided by the above embodiment.
  • the AMOLED display device of the embodiment of the present invention includes the pixel compensation circuit of the above embodiment of the present invention, which can prevent the luminance of the light-emitting device in each pixel from changing in one frame, and can avoid the process of driving the transistor in each pixel.
  • the process causes the luminance of the light-emitting device in each pixel to be uneven, thereby improving the display effect and display uniformity.

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Abstract

一种像素补偿电路及AMOLED显示装置。像素补偿电路包括数据信号写入模块（1）、高电压信号写入模块(2)、第一基准电压写入模块(3)、第二基准电压写入模块(4)、电压维持模块(5)、驱动晶体管(DTFT)、电容器(C)和发光器件(6)。数据信号写入模块(1)与电容器(C)的第一端连接，第一基准电压写入模块(1)与驱动晶体管（DTFT）的控制极连接，第二基准电压写入模块(4)与驱动晶体管（DTFT）的漏极连接。高电压信号写入模块(2)与电容器(C)的第二端连接，电压维持模块(5)与电容器(C)的第一端以及驱动晶体管（DTFT）的控制极连接。驱动晶体管（DTFT）的源极与电容器(C)的第二端连接，漏极与发光器件的阳极连接。发光器件的阴极与公共接地电极(VSS)连接。

Description

像素补偿电路及AMOLED显示装置 技术领域
本发明涉及显示技术领域，具体地涉及像素补偿电路及AMOLED显示装置。
背景技术
平面显示装置具有机身薄、省电、无辐射等众多优点，因而得到了广泛的应用。现有的平面显示装置主要包括液晶显示装置(Liquid Crystal Display，以下称为LCD)及有机发光二极管(Organic Light Emitting Diode，以下称为OLED)显示装置。
OLED显示装置通过自发光实现显示，因而其不需背光源，并且OLED显示装置具有对比度高、厚度小、视角广、反应速度快、可被制成柔性显示面板、使用温度范围广、构造及制程较简单等优异特性，因而其被视为可以取代LCD的下一代显示装置。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即，直接寻址和薄膜晶体管(Thin Film Transistor，TFT)矩阵寻址两类。PMOLED的功耗较高，阻碍了其在大尺寸显示装置中的应用，所以PMOLED通常用于小尺寸的显示装置。AMOLED因其高发光效能，通常用于高清晰度的大尺寸显示装置。
图1为现有的AMOLED像素电路的电路图。在AMOLED显示装置的显示区域内，像素被设置成包括多行、多列的矩阵状，每一像素通常采用由两个薄膜晶体管与一个电容器(Capacitor)组成的像素电路进行驱动，即，采用2T1C的驱动方式。具体地，第一晶体管T1的栅极电性连接栅线Scan，第一晶体管T1的源极电性连接数据信号线DATA，第一晶体管T1的漏极与第二晶体管T2的栅极及电容器C的一端电性连接。第二晶体管T2的源极电性连接高电压信号端VDD，第二晶体管T2的漏极电性连接有机发光二级管D的阳极。 有机发光二级管D的阴极电性连接公共接地电极VSS。此外，电容器C的一端电性连接第一晶体管T1的漏极，电容器C的另一端电性连接第二晶体管T2的源极。该像素显示时，栅线Scan控制第一晶体管T1导通，数据信号线DATA的数据信号电压经过第一晶体管T1进入到第二晶体管T2的栅极及电容器C；然后第一晶体管T1关断，由于电容器C的作用，第二晶体管T2的栅极电压仍可继续保持为数据信号电压，使得第二晶体管T2处于导通状态，与高电压信号端VDD和数据信号电压对应的驱动电流通过第二晶体管T2进入有机发光二级管D，以驱动有机发光二级管D发光。
上述AMOLED显示装置中，有机发光二极管D根据第二晶体管T2在饱和状态下产生的驱动电流发光。由于TFT制程上的不均匀性，各像素中第二晶体管T2的阈值电压不同，以及由于第二晶体管T2的阈值电压Vth在有机发光二极管D的发光过程中会发生不同程度的漂移，在采用上述2T1C的驱动电路进行驱动时，各像素的亮度均一性很差，造成显示不均等不良。
发明内容
为了至少解决现有技术中存在的技术问题之一，本公开提出了一种像素补偿电路及包含该像素补偿电路的AMOLED显示装置，其可以避免发光器件在发光过程中发生亮度变化，从而提高发光器件在发光过程中的亮度均一性。
本发明实施例提供一种像素补偿电路，其包括数据信号写入模块、高电压信号写入模块、第一基准电压写入模块、第二基准电压写入模块、电压维持模块、驱动晶体管、电容器和发光器件。所述数据信号写入模块与电容器的第一端连接，所述第一基准电压写入模块与驱动晶体管的控制极连接，所述第二基准电压写入模块与驱动晶体管的漏极连接。所述高电压信号写入模块与电容器的第二端连接，所述电压维持模块与电容器的第一端以及驱动晶体管的控制极连接。所述驱动晶体管的源极与电容器的第二端连接，所述驱动晶体管的漏极与发光器件的阳极连接。所述发光器件的阴极与公共接地电极连接。
可选地，所述像素补偿电路还包括连接控制模块，所述连接控制模块连接在驱动晶体管的漏极和发光器件的阳极之间，用于控制驱动晶体管和发光器件之间的通断。
可选地，所述数据信号写入模块包括数据信号线和第一晶体管，所述第一晶体管的控制极与栅线连接，所述第一晶体管的源极与数据信号线连接，所述第一晶体管的漏极与所述电容器的第一端连接。
可选地，所述第一基准电压写入模块包括第一基准电压端和第二晶体管，所述第二晶体管的控制极与栅线连接，所述第二晶体管的源极与第一基准电压端连接，所述第二晶体管的漏极与所述驱动晶体管的控制极连接。
可选地，所述第二基准电压写入模块包括第二基准电压端和第三晶体管，所述第三晶体管的控制极与栅线连接，所述第三晶体管的源极与第二基准电压端连接，所述第三晶体管的漏极与所述驱动晶体管的漏极和发光器件的阳极连接。
可替代地，所述第二基准电压写入模块包括第二基准电压端和第三晶体管，所述第三晶体管的控制极与栅线连接，所述第三晶体管的源极与第二基准电压端连接，所述第三晶体管的漏极与所述驱动晶体管的漏极和连接控制模块连接。
可选地，所述高电压信号写入模块包括高电压信号端和第四晶体管，所述第四晶体管的控制极与第一发光信号端连接，所述第四晶体管的源极与高电压信号端连接，所述第四晶体管的漏极与所述电容器的第二端连接。
可选地，所述电压维持模块包括第五晶体管，所述第五晶体管的控制极与第一发光信号端连接，所述第五晶体管的源极与所述电容器的第一端连接，所述第五晶体管的漏极与所述驱动晶体管的控制极连接。
可选地，所述连接控制模块包括第六晶体管，所述第六晶体管的控制极与第二发光信号端连接，所述第六晶体管的源极与驱动晶体管的漏极和第二基准电压写入模块连接，所述第六晶体管的漏极与发光器件的阳极连接。
本发明实施例还提供一种AMOLED显示装置，其包括上述像素补偿电路。
本发明实施例的像素补偿电路中，在发光器件的发光前阶段，通过第一基准电压写入模块和第二基准电压写入模块分别向驱动晶体管的栅极和漏极写入第一基准电压和第二基准电压，使得所述驱动晶体管的源极的电压包含驱动晶体管的阈值电压Vth的分量，从而使得在发光器件的发光阶段所生成的驱动电流与驱动晶体管的阈值电压以及高电压信号端的电压无关，这样驱动晶体管的制程工艺的均匀性、驱动晶体管的阈值电压Vth在发光过程中的漂移、以及高电压信号端的压降不会对发光器件的发光亮度造成影响，从而可以避免发光器件在发光过程中的亮度发生变化，提高发光器件在发光过程中的亮度均一性。而且，在发光器件的发光阶段，所述电容器保持悬置状态，使其两端的电压差(即，驱动晶体管的栅极和源极之间的电压差值)保持不变，从而所述驱动电流不会因高电压信号端的电压变化而变动，从而进一步避免发光器件在发光过程中的亮度发生变化，提高发光器件在发光过程中的亮度均一性。
本发明实施例的AMOLED显示装置采用本发明实施例的上述像素补偿电路，可以避免每个像素内的发光器件在一帧画面中的发光亮度发生变化，以及可以避免各像素内的驱动晶体管的制程工艺造成各像素内发光器件的发光亮度不均匀，从而提高显示效果和显示均匀性。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，其与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1为现有的AMOLED像素电路的电路图；
图2为根据本发明实施例的像素补偿电路的电路图；
图3为图2所示的像素补偿电路中各信号的时序图；
图4为t1阶段的等效电路图；
图5为t2阶段的等效电路图；
图6为根据本发明实施例的像素补偿电路的电路图；以及
图7为图6所示的像素补偿电路中各信号的时序图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
图2为根据本发明实施例的像素补偿电路的电路图。如图2所示，在本实施例中，所述像素补偿电路包括数据信号写入模块1、高电压信号写入模块2、第一基准电压写入模块3、第二基准电压写入模块4、电压维持模块5、驱动晶体管DTFT、电容器C和发光器件6。所述数据信号写入模块1与电容器C的第一端连接。所述第一基准电压写入模块3与驱动晶体管DTFT的控制极连接。所述第二基准电压写入模块4与驱动晶体管DTFT的漏极连接。所述高电压信号写入模块2与电容器C的第二端连接。所述电压维持模块5与电容器C的第一端以及驱动晶体管DTFT的控制极连接。所述驱动晶体管DTFT的源极与电容器C的第二端连接，所述驱动晶体管DTFT的漏极与发光器件6的阳极连接。所述发光器件6的阴极与公共接地电极VSS连接。所述发光器件6可以包括OLED(有机发光二极管)。
具体地，如图2所示，所述数据信号写入模块1包括数据信号线DATA和第一晶体管T1。数据信号线DATA输出数据信号DATA，其电压值为VDATA。所述第一晶体管T1的控制极(即栅极)与栅线Scan连接，所述第一晶体管T1的源极与数据信号线DATA连接，所述第一晶体管T1的漏极与所述电容器C的第一端连接。
所述第一基准电压写入模块3包括第一基准电压端Vf和第二晶体管T2。第一基准电压端Vf输出第一基准电压Vf。所述第二晶体管T2的控制极(即栅极)与栅线Scan连接，所述第二晶体管T2的源极与第一基准电压端Vf连接，所述第二晶体管T2的漏极与所述驱动晶体管DTFT的控制极(即栅极)连接。
所述第二基准电压写入模块4包括第二基准电压端Vi和第三晶体管T3。第二基准电压端Vi输出第二基准电压Vi。所述第三晶体管T3的控制极(即栅极)与栅线Scan连接，所述第三晶体管T3的源极与第二基准电压端Vi连接，所述第三晶体管T3的漏极与所述驱动晶体管DTFT的漏极和发光器件6的阳极连接。
所述高电压信号写入模块2包括高电压信号端VDD和第四晶体管T4。高电压信号端VDD输出高电压信号VDD。所述第四晶体管T4的控制极(即栅极)与第一发光信号端EM1连接，所述第四晶体管T4的源极与高电压信号端VDD连接，所述第四晶体管T4的漏极与所述电容器C的第二端连接。
此外，所述电压维持模块5包括第五晶体管T5。所述第五晶体管T5的控制极(即栅极)与第一发光信号端EM1连接，所述第五晶体管T5的源极与所述电容器C的第一端连接，所述第五晶体管T5的漏极与所述驱动晶体管DTFT的控制极(即栅极)连接。
在本实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及驱动晶体管DTFT为P型晶体管。在此情况下，各信号的时序如图3所示。下面结合图3所示的时序对图2所示的像素补偿电路驱动发光器件6发光的过程进行详细描述。
第一阶段t1为发光器件6不发光阶段(即发光前阶段)。具体地，在该阶段，栅线Scan所输出的扫描信号为低电平，第一发光信号端EM1输出的发光信号为高电平，数据信号线DATA输出的数据信号为高电平。在此情况下，第一晶体管T1、第二晶体管T2、第三晶体管T3导通，第四晶体管T4、第五晶体管T5断开，此时等效的电路图如图4所示。
参看图4，数据信号线DATA与电容器C的第一端连通，其将数据信号DATA输入至电容器C的第一端，使电容器C的第一端的电压为VDATA。同时，第一基准电压端Vf与驱动晶体管DTFT的栅极连接，使驱动晶体管DTFT的栅极电压等于第一基准电压Vf。同时，第二基准电压端Vi与驱动晶体管DTFT的漏极连接，使驱动 晶体管DTFT的漏极电压等于第二基准电压Vi。
在t1阶段开始时，驱动晶体管DTFT的漏极保持上一帧画面结束时的电压，其电压具体为VDD。而在t1阶段持续的过程中，由于驱动晶体管DTFT在t1阶段与高电压信号端VDD断开连接，因而在驱动晶体管DTFT的栅极和漏极分别连接第一基准电压端Vf和第二基准电压端Vi的情况下，驱动晶体管DTFT的源极电压(即所述电容器C的第二端上的电压)会发生变化，最终其满足下述公式(1)：
Vs＝Vf-Vth·········(1)
其中，Vs为驱动晶体管DTFT的源极的电压，Vth为所述驱动晶体管DTFT的阈值电压。
根据该公式，驱动晶体管DTFT的源极的电压包含了驱动晶体管DTFT的阈值电压Vth的分量，从而实现了对阈值电压Vth的抓取。此外，在本实施例中，通过设置第二基准电压Vi的数值，可以抓取不同Vds(即，驱动晶体管DTFT的源极和漏极之间的电压差值)情况下的阈值电压Vth。
另外，在该t1阶段，所述第二基准电压端Vi还可以与发光器件6的阳极连接，将第二基准电压Vi写入到发光器件6的阳极上，从而在t1阶段清除掉发光器件6的阳极所保持的在上一帧画面的电压，这样能够使所述发光器件6在本帧画面的发光阶段中的发光亮度准确，而不会出现偏差。
第二阶段t2为发光器件6的发光阶段。具体地，在该阶段，栅线Scan所输出的扫描信号为高电平，第一发光信号端EM1所输出的发光信号为低电平，数据信号线DATA所输出的数据信号DATA为低电平。在此情况下，第一晶体管T1、第二晶体管T2、第三晶体管T3断开，第四晶体管T4、第五晶体管T5导通，此时等效的电路图如图5所示。
参看图5，驱动晶体管DTFT的栅极与所述电容器C的第一端连接，驱动晶体管DTFT的源极与所述电容器C的第二端连接。因此，驱动晶体管DTFT的栅极和源极之间的电压差Vgs等于所述电容器C的两端之间的电压差Δs。此外，高电压信号端VDD与电容 器C的第二端以及驱动晶体管DTFT的源极连接，使电容器C的第二端以及驱动晶体管DTFT的源极的电压变为VDD。另一方面，由于电容器C的第一端处于悬置状态(floating)，因此电容器C的第二端的电压变化并不会导致电容器C两端的电压差值的改变，电容器C两端的电压差Δs会维持在t1阶段的数值。最终，驱动晶体管DTFT的栅极和源极之间的电压差值Vgs满足以下公式(2)：
Vgs＝Vg-Vs＝VDATA-Vf+Vth·········(2)
至此，可以得出在该t2阶段根据驱动晶体管DTFT而生成的用以驱动发光器件6发光的电流为：
IOLED＝k(Vgs-Vth)2
＝k(VDATA-Vf+Vth-Vth)2
＝k(VDATA-Vf)2·········(3)
根据所述公式(3)，驱动发光器件6发光的电流IOLED与驱动晶体管DTFT的阈值电压Vth无关，也与VDD无关。因此，驱动晶体管DTFT的制程工艺的均匀性、驱动晶体管DTFT的阈值电压Vth在发光过程中的漂移、以及VDD的压降(IR Drop)不会对发光器件6的发光亮度造成影响，从而可以避免发光器件6在发光过程中的亮度发生变化，提高发光器件6在发光过程中的亮度均一性。
另一方面，在t2阶段，由于电容器C处于floating状态，当高电压信号端VDD的电压变化时，电容器C的两端之间的电压差Δs不变，即，驱动晶体管DTFT的栅极和源极之间的电压差Vgs会维持不变，从而所生成的驱动电流IOLED也不会因VDD的电压变化而变动，从而可以进一步确保驱动电流IOLED保持稳定，避免发光器件6在发光过程中的亮度发生变化，提高发光器件6在发光过程中的亮度均一性。
此外，在本实施例中，通过设置第二基准电压Vi的数值，可以抓取不同Vds数值下的阈值电压Vth，这样可以有针对性地消除不同Vds下的阈值电压Vth的影响，从而获得更好的补偿效果，使得在t2阶段生成的驱动发光器件6发光的电流更加稳定，保证发光器件6发光亮度的均一性。
图6为根据本发明实施例的像素补偿电路的电路图。如图6所 示，与上述实施例不同的是，本实施例的像素补偿电路还包括连接控制模块7，所述连接控制模块7连接在驱动晶体管DTFT的漏极和发光器件6的阳极之间，用于控制驱动晶体管DTFT和发光器件6之间的通断。
具体地，在本实施例中，所述第二基准电压写入模块4包括第二基准电压端Vi和第三晶体管T3，所述第三晶体管T3的控制极(即栅极)与栅线Scan连接，所述第三晶体管T3的源极与第二基准电压端Vi连接，所述第三晶体管T3的漏极与所述驱动晶体管DTFT的漏极和连接控制模块7连接。此外，所述连接控制模块7包括第六晶体管T6，所述第六晶体管T6的控制极(即栅极)与第二发光信号端EM2连接，所述第六晶体管T6的源极与驱动晶体管DTFT的漏极和第二基准电压写入模块4连接，所述第六晶体管T6的漏极与发光器件6的阳极连接。
图7为图6所示的像素补偿电路中各信号的时序图。如图7所示，在本实施例中，发光器件6的发光前阶段分为t1和t2两个阶段，发光器件6的发光阶段为第三个阶段，即，t3阶段。
具体地，在t1阶段，第一发光信号端EM1所输出的发光信号为低电平，栅线Scan输出的扫描信号为高电平，第二发光信号端EM2所输出的发光信号为高电平，数据信号线DATA所输出的数据信号DATA为低电平。在此情况下，第一晶体管T1、第二晶体管T2、第三晶体管T3断开，第四晶体管T4、第五晶体管T5导通，第六晶体管T6断开。此外，高电压信号端VDD与所述电容器C的第二端以及驱动晶体管DTFT的源极连接，从而所述电容器C的第二端以及驱动晶体管DTFT的源极的电压为VDD。t2阶段与上述实施例中的t1阶段相同，t3阶段与上述实施例中的t2阶段相同，在此就不再赘述。
本实施例中，在上述实施例中的t1阶段前增加了一个阶段，并在该阶段向电容器C的第二端以及驱动晶体管DTFT的源极写入电压VDD，其可以在上一帧画面结束并且所述电容器C的第二端和驱动晶体管DTFT的源极的电压异常时，保证本帧画面中电容器C的 第二端以及驱动晶体管DTFT的源极的初始电压为VDD。
综上所述，在根据本发明实施例的像素补偿电路中，在发光器件6的发光前阶段，通过第一基准电压写入模块3和第二基准电压写入模块4分别向驱动晶体管DTFT的栅极和漏极写入第一基准电压Vf和第二基准电压Vi，使得所述驱动晶体管DTFT的源极的电压包含驱动晶体管DTFT的阈值电压Vth的分量，从而使得在发光器件6的发光阶段所生成的驱动电流与驱动晶体管DTFT的阈值电压以及高电压信号端VDD的电压无关，这样驱动晶体管DTFT的制程工艺的均匀性、驱动晶体管DTFT的阈值电压Vth在发光过程中的漂移、以及高电压信号端VDD的压降不会对发光器件6的发光亮度造成影响，从而可以避免发光器件6在发光过程中的亮度发生变化，提高发光器件6在发光过程中的亮度均一性。而且，在发光器件6的发光阶段，所述电容器C保持悬置状态，使其两端的电压差(即，驱动晶体管DTFT的栅极和源极之间的电压差值)保持不变，从而所述驱动电流不会因高电压信号端VDD的电压变化而变动，从而进一步避免发光器件6在发光过程中的亮度发生变化，提高发光器件6在发光过程中的亮度均一性。
在另一个方面，本发明实施例还提供一种AMOLED显示装置。在本实施例中，所述AMOLED显示装置包括上述实施例提供的像素补偿电路。
本发明实施例的AMOLED显示装置包括本发明上述实施例的像素补偿电路，可以避免每个像素内的发光器件在一帧画面中的发光亮度发生变化，以及可以避免各像素内的驱动晶体管的制程工艺造成各像素内发光器件的发光亮度不均匀，从而提高显示效果和显示均匀性。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也落入本发明的保护范围。

Claims (10)

  1. 一种像素补偿电路，包括数据信号写入模块、高电压信号写入模块、第一基准电压写入模块、第二基准电压写入模块、电压维持模块、驱动晶体管、电容器和发光器件，其中
    所述数据信号写入模块与所述电容器的第一端连接，所述第一基准电压写入模块与所述驱动晶体管的控制极连接，所述第二基准电压写入模块与所述驱动晶体管的漏极连接；
    所述高电压信号写入模块与所述电容器的第二端连接，所述电压维持模块与所述电容器的第一端以及驱动晶体管的控制极连接；
    所述驱动晶体管的源极与所述电容器的第二端连接，所述驱动晶体管的漏极与所述发光器件的阳极连接；以及
    所述发光器件的阴极与公共接地电极连接。
  2. 根据权利要求1所述的像素补偿电路，还包括连接控制模块，所述连接控制模块连接在所述驱动晶体管的漏极和所述发光器件的阳极之间，用于控制所述驱动晶体管和所述发光器件之间的通断。
  3. 根据权利要求1或2所述的像素补偿电路，其中所述数据信号写入模块包括数据信号线和第一晶体管，
    所述第一晶体管的控制极与栅线连接，所述第一晶体管的源极与所述数据信号线连接，所述第一晶体管的漏极与所述电容器的第一端连接。
  4. 根据权利要求1或2所述的像素补偿电路，其中所述第一基准电压写入模块包括第一基准电压端和第二晶体管，
    所述第二晶体管的控制极与栅线连接，所述第二晶体管的源极与所述第一基准电压端连接，所述第二晶体管的漏极与所述驱动晶体管的控制极连接。
  5. 根据权利要求1所述的像素补偿电路，其中所述第二基准电压写入模块包括第二基准电压端和第三晶体管，
    所述第三晶体管的控制极与栅线连接，所述第三晶体管的源极与所述第二基准电压端连接，所述第三晶体管的漏极与所述驱动晶体管的漏极和所述发光器件的阳极连接。
  6. 根据权利要求2所述的像素补偿电路，其中所述第二基准电压写入模块包括第二基准电压端和第三晶体管，
    所述第三晶体管的控制极与栅线连接，所述第三晶体管的源极与所述第二基准电压端连接，所述第三晶体管的漏极与所述驱动晶体管的漏极和所述连接控制模块连接。
  7. 根据权利要求1或2所述的像素补偿电路，其中所述高电压信号写入模块包括高电压信号端和第四晶体管，
    所述第四晶体管的控制极与第一发光信号端连接，所述第四晶体管的源极与所述高电压信号端连接，所述第四晶体管的漏极与所述电容器的第二端连接。
  8. 根据权利要求1或2所述的像素补偿电路，其中所述电压维持模块包括第五晶体管，
    所述第五晶体管的控制极与第一发光信号端连接，所述第五晶体管的源极与所述电容器的第一端连接，所述第五晶体管的漏极与所述驱动晶体管的控制极连接。
  9. 根据权利要求2所述的像素补偿电路，其中所述连接控制模块包括第六晶体管，
    所述第六晶体管的控制极与第二发光信号端连接，所述第六晶体管的源极与所述驱动晶体管的漏极和所述第二基准电压写入模块连接，所述第六晶体管的漏极与所述发光器件的阳极连接。
  10. 一种AMOLED显示装置，包括权利要求1至9中任意一项所述的像素补偿电路。
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US12062331B2 (en) * 2019-07-23 2024-08-13 Fuzhou Boe Optoelectronics Technology Co., Ltd. OLED pixel compensation circuit, driving method and display device
CN114299867A (zh) * 2021-12-31 2022-04-08 湖北长江新型显示产业创新中心有限公司 一种显示面板及其驱动方法和显示装置

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