WO2017110738A1 - Multilayer capacitor and package structure of same - Google Patents

Multilayer capacitor and package structure of same Download PDF

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Publication number
WO2017110738A1
WO2017110738A1 PCT/JP2016/087771 JP2016087771W WO2017110738A1 WO 2017110738 A1 WO2017110738 A1 WO 2017110738A1 JP 2016087771 W JP2016087771 W JP 2016087771W WO 2017110738 A1 WO2017110738 A1 WO 2017110738A1
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WO
WIPO (PCT)
Prior art keywords
electrode
external
substrate
multilayer capacitor
external terminal
Prior art date
Application number
PCT/JP2016/087771
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French (fr)
Japanese (ja)
Inventor
岩下 英史
畠中 英文
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京セラ株式会社
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Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP2017558117A priority Critical patent/JP6643358B2/en
Publication of WO2017110738A1 publication Critical patent/WO2017110738A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/252Terminals the terminals being coated on the capacitive element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

Definitions

  • the present invention relates to a multilayer capacitor in which a pair of external electrodes are provided on a multilayer body in which a plurality of dielectric layers and internal electrodes are alternately stacked, and a mounting structure thereof.
  • a multilayer capacitor dielectric layers and internal electrodes are alternately laminated.
  • a ceramic material constituting the dielectric layer a ferroelectric material such as barium titanate having a relatively high dielectric constant is generally used. It is used.
  • the multilayer capacitor is mounted on the substrate via solder or the like, and propagates vibration to the substrate via the solder joint. Furthermore, the multilayer capacitor resonates the substrate by vibration and amplifies the vibration to generate vibration sound on the substrate. Therefore, the substrate generates an audible sound when resonating at a resonance frequency in the audible range, and a so-called sounding phenomenon occurs.
  • Patent Document 1 discloses a multilayer capacitor in which a pair of external electrodes is provided at the center of a pair of side surfaces along the longitudinal direction of a multilayer body.
  • the multilayer capacitor of the present disclosure includes a pair of first surfaces and second surfaces, a pair of first end surfaces and second end surfaces, and a pair of first side surfaces on which a plurality of dielectric layers are stacked. And a rectangular parallelepiped laminate having a second side surface, a plurality of internal electrodes arranged in the stacking direction between the plurality of dielectric layers, the first side surface and the second side surface A first external electrode and a second external electrode electrically connected to the different internal electrodes, which are respectively disposed on the side surfaces; a first external terminal joined to the first external electrode; and the first external electrode And a second external terminal joined to the two external electrodes.
  • the first external electrode and the second external electrode include a side surface portion disposed so as to include a central portion of the side surface, and a first surface extension extending from the side surface portion to the first surface. And a second surface extending portion extending on the second surface.
  • the first external terminal includes a first substrate connecting portion of a plate-like body and the first substrate which are arranged to face each other with a gap between the first surface adjacent to the first end surface. It extended toward the direction of the said 2nd end surface from the connection part along the longitudinal direction of the said laminated body, and the edge part of the extended part was joined to the said 1st surface extension part of the said 1st external electrode.
  • the first electrode connection portion is included.
  • the second external terminal includes a second substrate connecting portion of the plate-like body and the second substrate, which are arranged to face each other with a gap between the first surface adjacent to the second end surface. Extending from the connecting portion along the longitudinal direction of the laminate toward the first end surface, the end of the extended portion is joined to the first surface extending portion of the second external electrode. 2 electrode connections.
  • FIG. 1 is a schematic perspective view showing a multilayer capacitor according to a first embodiment, where (a) is a schematic perspective view seen from the upper surface side, and (b) is a schematic perspective view seen from the lower surface side. It is. 1A is a plan view of the multilayer capacitor shown in FIG. 1 as viewed from above, and FIG. 1B is a plan view of the multilayer capacitor shown in FIG. 1 as viewed from below.
  • FIG. 2 (a) is an end view of a cut portion taken along line AA of the multilayer capacitor shown in FIG. 2 (a), and FIG. 2 (b) is a BB line of the multilayer capacitor shown in FIG. 2 (a).
  • FIG. 1 is a schematic perspective view showing a multilayer capacitor according to a first embodiment, where (a) is a schematic perspective view seen from the upper surface side, and (b) is a schematic perspective view seen from the lower surface side.
  • FIG. 1A is a plan view of the multilayer capacitor shown in FIG. 1 as viewed from above
  • (A)-(c) is a top view for demonstrating an internal electrode.
  • (A) is a schematic perspective view showing a state in which the multilayer capacitor shown in FIG. 1 is mounted on a substrate, and (b) is a multilayer type in a state where the multilayer capacitor shown in FIG. 1 is mounted on a substrate. It is the schematic side view seen from the direction perpendicular
  • (A)-(d) is explanatory drawing for demonstrating the manufacturing method of the multilayer capacitor shown in FIG. FIG.
  • FIG. 3 is a schematic perspective view illustrating a multilayer capacitor according to a second embodiment, where (a) is a schematic perspective view viewed from the upper surface side, and (b) is a schematic perspective view viewed from the lower surface side. It is. (A) is the top view which planarly viewed the multilayer capacitor shown in FIG. 7 from the upper surface side, (b) is the top view which planarly viewed the multilayer capacitor shown in FIG. FIG. 8A is an end view of the multilayer capacitor shown in FIG. 8A cut along line AA. FIG. 8B is a cross-sectional view taken along line BB of the multilayer capacitor shown in FIG. FIG. (A) is a schematic perspective view showing a state in which the multilayer capacitor shown in FIG.
  • FIG. 7 is mounted on a substrate, and (b) is a multilayer type in a state where the multilayer capacitor shown in FIG. 7 is mounted on a substrate.
  • FIGS. 8A to 8D are explanatory views for explaining a method of manufacturing the multilayer capacitor shown in FIG.
  • FIG. 6 is another example of the multilayer capacitor shown in FIG. 1, and is a side view seen from a direction perpendicular to the longitudinal direction of the multilayer capacitor. It is explanatory drawing for demonstrating the external terminal used for the multilayer capacitor
  • FIG. 12 Comprising: (a) is the top view which planarly viewed the multilayer capacitor
  • FIG. 13B is a plan view of the external terminal used in the multilayer capacitor shown in FIG. 12 as viewed from the upper surface side
  • FIG. 10C is a cut end surface cut along the line EE of the external terminal shown in FIG.
  • FIG. 8 is another example of the multilayer capacitor shown in FIG. 7, and is a side view seen from a direction perpendicular to the longitudinal direction of the multilayer capacitor.
  • a conventional multilayer capacitor has a pair of external electrodes on a pair of end faces.
  • the substrate electrode is provided on the substrate in alignment with the pair of external electrodes provided on the pair of end faces, and is disposed at a position in the longitudinal direction of the multilayer body of the multilayer capacitor.
  • a pair of external electrodes is provided at the center of a pair of side surfaces, and a substrate electrode disposed at a position in the longitudinal direction cannot be employed.
  • the arrangement of the substrate electrodes must be changed to the position in the short direction of the multilayer capacitor multilayer body in accordance with the pair of external electrodes provided on the pair of side surfaces. I must.
  • the multilayer capacitor of the present disclosure it is not necessary to change the arrangement of the substrate electrodes in accordance with the pair of external electrodes by providing the pair of external terminals on the pair of external electrodes.
  • the multilayer capacitor of the present disclosure will be described in detail.
  • the multilayer capacitor 10 defines an orthogonal coordinate system XYZ, and uses the terms “upper surface” or “lower surface” with the positive side in the Z direction as the upper side.
  • the lower surface of the pair of surfaces is the first surface 4a
  • the upper surface is the second surface 4b.
  • symbol is used about the same member and the same part, and the overlapping description is abbreviate
  • the term “multilayer capacitor body” may be used for the multilayer capacitor 10 excluding the pair of external terminals 7.
  • FIG. 1A is a schematic perspective view of the multilayer capacitor 10 according to the first embodiment of the present disclosure with the top surface thereof facing upward, and FIG. 1B is the bottom surface of the multilayer capacitor 10.
  • FIG. 1A is a schematic perspective view of the multilayer capacitor 10 according to the first embodiment of the present disclosure with the top surface thereof facing upward
  • FIG. 1B is the bottom surface of the multilayer capacitor 10.
  • the multilayer capacitor 10 includes a multilayer body 1, a pair of external electrodes 3, and a pair of external terminals 7.
  • the laminated body 1 has a rectangular parallelepiped shape, a pair of first surfaces 4a and second surfaces 4b, a pair of first end surfaces 4c and second end surfaces 4d, a pair of first side surfaces 4e and second. Side surface 4f.
  • first internal electrodes 2a and second internal electrodes 2b are alternately stacked via dielectric layers 1a.
  • the pair of external electrodes 3 (the first external electrode 3a and the second external electrode 3b) are provided so as to include the central part of the pair of side surfaces (the first side surface 4e and the second side surface 4f) of the multilayer body 1. Are electrically connected to different internal electrodes 2.
  • the pair of external terminals 7 (first external terminal 7a and second external terminal 7b) are joined to the pair of external electrodes 3 (first external electrode 3a and second external electrode 3b).
  • the laminated body 1 has a rectangular first surface 4a and a second surface 4b facing each other positioned in the stacking direction.
  • a pair of end surfaces (a first end surface 4c and a second end surface 4d) facing each other are located between the first surface 4a and the second surface 4b, and the first surface 4a and the second surface 4b. Adjacent to the short side.
  • a pair of side surfaces (the first side surface 4e and the second side surface 4f) facing each other are located between the first surface 4a and the second surface 4b, and the first surface 4a and the second surface 4b. Adjacent to the long side of the surface 4b.
  • the pair of side surfaces (the first side surface 4e and the second side surface 4f) are positioned along the longitudinal direction (X direction) of the stacked body 1. Further, the pair of end faces (first end face 4 c and second end face 4 d) are located along the short direction (Y direction) of the stacked body 1.
  • the pair of end faces are positioned between the pair of faces and are orthogonal to the pair of faces.
  • a pair of side surface is located between a pair of surface, and is orthogonal to a pair of surface.
  • a pair of end surface and a pair of side surface are orthogonally crossed.
  • the rectangular parallelepiped shape includes not only a cubic shape or a rectangular parallelepiped shape, but also includes, for example, a shape in which a ridge line portion of a cube or a rectangular parallelepiped is chamfered and the ridge line portion has an R shape.
  • the laminate 1 is a sintered body obtained by laminating and firing a plurality of ceramic green sheets in which the internal electrode 2 is formed on the surface of the dielectric layer 1a.
  • each ridge line portion of the multilayer body 1 may be rounded.
  • the pair of external electrodes 3 is provided on a pair of side surfaces, and includes a first external electrode 3a and a second external electrode 3b.
  • the first external electrode 3a has a side surface portion 3a1, a first surface extension portion 3a2, and a second surface extension portion 3a3.
  • the side surface portion 3a1 is provided on the first side surface 4e so as to include the central portion of the first side surface 4e.
  • the first surface extending portion 3a2 extends on the first surface 4a from the side surface portion 3a1 toward the center portion in the short side direction (Y direction) of the multilayer body 1.
  • the second surface extending portion 3a3 extends on the second surface 4b from the side surface portion 3a1 toward the center portion in the short direction (Y direction) of the stacked body 1.
  • the second external electrode 3b has a side surface portion 3b1, a first surface extension portion 3b2, and a second surface extension portion 3b3.
  • the side surface portion 3b1 is provided on the second side surface 4f so as to include the central portion of the second side surface 4f.
  • the first surface extending portion 3b2 extends on the first surface 4a from the side surface portion 3b1 toward the center portion in the short direction (Y direction) of the stacked body 1.
  • the second surface extension portion 3b3 extends on the second surface 4b from the side surface portion 3b1 toward the central portion in the short side direction (Y direction) of the stacked body 1.
  • the first surface extension portion 3a2 (first surface extension portion 3b2) and the second surface extension portion 3a3 (second surface extension portion 3b3) are formed on the first surface.
  • 4a and the 2nd surface 4b are convexly curved toward the center part, for example, are provided in circular arc shape toward the center part.
  • the 1st surface extension part 3a2 (1st surface extension part 3b2) and the 2nd surface extension part 3a3 (2nd surface extension part 3b3) protrude toward the center part side.
  • the bending portion has, for example, an arc shape, a semicircular shape, or a semi-elliptical shape that is curved in a convex shape.
  • the multilayer capacitor 10 includes a first surface extension portion 3a2 (first surface extension portion 3b2) and a second surface extension portion 3a3 (second surface extension portion 3b3). Since it extends in a convex shape toward the center of the second surface 4 b, the external electrode 3 is difficult to peel off from the laminate 1.
  • the internal electrode 2 includes a first internal electrode 2a and a second internal electrode 2b as shown in FIG.
  • the first internal electrode 2a and the second internal electrode 2b are arranged opposite to each other with a predetermined interval in the stacking direction between the plurality of dielectric layers 1a.
  • the internal electrode 2 is provided so as to be substantially parallel to the first surface 4 a and the second surface 4 b of the multilayer body 1.
  • the first external electrode 3a is arranged such that the side surface portion 3a1 includes the central portion of the first side surface 4e, and the first external electrode 3a is drawn to the first side surface 4e.
  • the internal electrode 2a is electrically connected.
  • the second external electrode 3b is disposed such that the side surface portion 3b1 includes the central portion of the second side surface 4f, and electrically connected to the second internal electrode 2b drawn out to the second side surface 4f. It is connected.
  • the first internal electrode 2a has a lead-out portion 2aa to the first side surface 4e at the center on the first side surface 4e side.
  • the lead-out portion 2aa is arranged so as to be drawn out to the first side surface 4e and exposed to the first side surface 4e.
  • the second internal electrode 2b has a lead-out portion 2ba to the second side surface 4f at the central portion on the second side surface 4f side.
  • the lead-out portion 2ba is arranged so as to be drawn out to the second side face 4f facing the first side face 4e and exposed to the second side face 4f.
  • the first internal electrode 2a and the second internal electrode 2b are not exposed on the first end surface 4c and the second end surface 4d.
  • the first internal electrode 2a exposed on the first side face 4e is shown by a solid line
  • the second internal electrode 2b exposed on the second side face 4f is shown by a broken line.
  • the first external electrode 3a is provided so that the side surface portion 3a1 covers the extraction portion 2aa of the first internal electrode 2a extracted to the first side surface 4e.
  • the internal electrode 2a is electrically connected.
  • the second external electrode 3b is provided so that the side surface portion 3b1 covers the extraction portion 2ba of the second internal electrode 2b extracted to the second side surface 4f. It is electrically connected to the second internal electrode 2b.
  • the central portion of the first side surface 4e is a region including a bisector L that bisects the first side surface 4e vertically, and the side portion 3a1 of the first external electrode 3a has this region. It is provided including. Further, the central portion of the second side surface 4f is a region including a bisector L that bisects the second side surface 4f vertically, and the side portion 3b1 of the second external electrode 3b is defined by this region. It is provided including.
  • FIG. 4 shows the bisector L as a long chain line.
  • the internal electrodes 2 are electrically connected to different external electrodes 3 for each layer, and when a voltage is applied to the pair of external electrodes 3, the first internal electrodes 2a And a capacitance is generated in the dielectric layer 1a sandwiched between the second internal electrodes 2b.
  • the length of the multilayer capacitor body in the longitudinal direction (X direction) is, for example, 0.6 (mm) to 2.2 (mm), and the length in the lateral direction (Y direction) is, for example, 0. 3 (mm) to 1.5 (mm), and the length in the height direction (Z direction) is, for example, 0.3 (mm) to 1.2 (mm).
  • the dielectric layer 1a is rectangular in a plan view from the stacking direction (Z direction), and the thickness per layer is, for example, 0.2 ( ⁇ m) to 3 ( ⁇ m).
  • the laminated body 1 for example, a plurality of dielectric layers 1a of 10 (layers) to 1000 (layers) and a plurality of internal electrodes 2 are laminated in the Z direction. Further, the number of internal electrodes 2 in the multilayer body 1 is appropriately set according to the characteristics of the multilayer capacitor 10.
  • the dielectric layer 1a is, for example, barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium zirconate (CaZrO 3 ).
  • the dielectric layer 1a may use barium titanate as a ferroelectric material having a high dielectric constant from the viewpoint of a high dielectric constant.
  • the lead-out part 2aa and the lead-out part 2ba are provided so that the lengths along the longitudinal direction (X direction) of the laminate 1 are substantially the same. Not only this but the drawer part 2aa and the drawer part 2ba may mutually differ in the length along the longitudinal direction (X direction) of the laminated body 1.
  • the exposed portion on the first side face 4e is the first in order to maintain the symmetry of vibration and reduce elements that vibrate the substrate 9. You may provide so that the bisector L of the side surface 4e (2nd side surface 4f) may be included.
  • the conductive material of the internal electrode 2 is a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au).
  • the conductive material of the internal electrode 2 is an alloy material such as an Ag—Pd alloy including one or more of these metal materials.
  • the thicknesses of the first internal electrode 2a and the second internal electrode 2b are, for example, 0.2 ( ⁇ m) to 2 ( ⁇ m), and may be set appropriately depending on the application.
  • the first internal electrode 2a and the second internal electrode 2b may use the same metal material or alloy material.
  • the pair of external electrodes 3 includes a base electrode 5 and a plating layer 6 as shown in FIG.
  • the pair of base electrodes 5 is electrically connected to the internal electrode 2 drawn out to the first side face 4e or the second side face 4f.
  • the plating layer 6 is provided on the surface of the base electrode 5 so as to cover the base electrode 5.
  • the plating layer 6 is provided to protect the base electrode 5.
  • the plating layer 6 can improve the bondability between the external electrode 3 and the external terminal 7 when welding is used for bonding the pair of external terminals 7.
  • the external electrode 3 is not limited to the plating layer 6, and any metal layer that can be bonded to the external terminal 7 may be provided so as to cover the base electrode 5.
  • the external electrode 3 only needs to be provided with a metal layer that can be joined to the external terminal 7 by welding so as to cover the base electrode 5.
  • the conductive material of the base electrode 5 is a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au).
  • the conductive material of the base electrode 5 is an alloy material such as an Ag—Pd alloy including one or more of these metal materials.
  • the pair of base electrodes 5 may use the same metal material or alloy material.
  • the base electrode 5 has a thickness on the first surface 4a and the second surface 4b of, for example, 4 ( ⁇ m) to 10 ( ⁇ m), and a thickness on the first side surface 4e and the second side surface 4f, for example. 10 ( ⁇ m) to 25 ( ⁇ m).
  • the base electrode 5 is provided so that the first base electrode extends from the first side surface 4e to the first surface 4a and the second surface 4b, and the second base electrode is the second base electrode. It is provided to extend from the side surface 4f to the first surface 4a and the second surface 4b.
  • the plating layer 6 is provided on the surface of the base electrode 5 so as to cover the base electrode 5 formed on the surface of the multilayer body 1.
  • the plating layer 6 is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like.
  • the plating layer 6 is formed using, for example, an electrolytic plating method.
  • the plating layer 6 may be provided as a single plating layer on the surface of the base electrode 5.
  • the multilayer capacitor 10 includes a plurality of plating layers 6 and includes a first plating layer 6a and a second plating layer 6b.
  • the plating layer 6 is a laminated body of the first plating layer 6a and the second plating layer 6b formed on the surfaces of the first plating layer 6a.
  • the plating layer 6 is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like.
  • the first plating layer 6a is a nickel (Ni) plating layer
  • the second plating layer 6b is a tin (Sn) plating layer
  • the second plating layer 6b is a first plating layer. It is provided so as to cover the plating layer 6a.
  • the first plating layer 6a has a plating layer thickness of, for example, 5 ( ⁇ m) to 10 ( ⁇ m)
  • the second plating layer 6b has a plating layer thickness of, for example, 3 ( ⁇ m) to 5 ( ⁇ m). ( ⁇ m).
  • the pair of external terminals 7 includes a first external terminal 7a and a second external terminal 7b.
  • the first external terminal 7a is joined to the first surface extending portion 3a2 of the first external electrode 3a.
  • the second external terminal 7b is joined to the first surface extending portion 3b2 of the second external electrode 3b.
  • the first external terminal 7a includes a first substrate connection portion 7a1 and a first electrode connection portion 7a2 as shown in FIGS.
  • the first substrate connection portion 7a1 is opposed to the portion of the first surface 4a that is close to the first end surface 4c, and overlaps the end portion on the first end surface 4c side of the stacked body 1 in plan view. Is provided. In this way, the first substrate connection portion 7a1 is opposed to the first end surface 4c side (negative side in the X direction) in the longitudinal direction of the multilayer body 1 with the gap of the first surface 4a. It is a rectangular plate-shaped body.
  • the first electrode connection portion 7a2 extends from the first substrate connection portion 7a1 along the longitudinal direction of the multilayer body 1 toward the first surface extension portion 3a2 of the first external electrode 3a. The end of the portion is joined to the first surface extension 3a2 of the first external electrode 3a. Thus, the first electrode connection portion 7a2 extends toward the second end face 4d so as to overlap the first surface extension portion 3a2 of the first external electrode 3a, and the first external electrode 3a. The first surface extending portion 3a2 is joined.
  • the second external terminal 7b includes a second substrate connection portion 7b1 and a second electrode connection portion 7b2, as shown in FIGS.
  • the second substrate connection portion 7b1 faces the portion of the first surface 4a that is close to the second end surface 4d, and overlaps the end portion of the stacked body 1 on the second end surface 4d side in plan view. Is provided. In this way, the second substrate connection portion 7b1 is opposed to the portion of the first surface 4a on the second end surface 4d side (the positive side in the X direction) in the longitudinal direction of the multilayer body 1 via the gap. It is a rectangular plate-shaped body.
  • the second electrode connection portion 7b2 extends from the second substrate connection portion 7b1 along the longitudinal direction of the stacked body 1 toward the first surface extension portion 3b2 of the second external electrode 3b. The end of the portion is joined to the first surface extension 3b2 of the second external electrode 3b. Thus, the second electrode connection portion 7b2 extends toward the first end surface 4c so as to overlap the first surface extension portion 3b2 of the second external electrode 3b, and the second external electrode 3b. The first surface extending portion 3b2 is joined.
  • the first electrode connection portion 7a2 is joined to the first surface extension portion 3a2 of the first external electrode 3a by using, for example, soldering or welding.
  • the second electrode connection portion 7b2 is joined to the first surface extension portion 3b2 of the second external electrode 3b by soldering or welding.
  • the first external terminal 7a and the second external terminal 7b are joined to the first external electrode 3a and the second external electrode 3b by welding.
  • the first external terminal 7a is welded to the first external electrode 3a and the first electrode connecting portion 7a2 by using, for example, spot welding.
  • a circular weld 7a3 is formed. Accordingly, the first electrode connection portion 7a2 of the first external terminal 7a is joined to the first surface extension portion 3a2 of the first external electrode 3a by the circular weld portion 7a3.
  • the first external terminal 7a is joined to the first surface extending portion 3a2 of the first external electrode 3a only by the welded portion 7a3.
  • the second external terminal 7b is welded to the second external electrode 3b and the second electrode connection portion 7b2 by using, for example, spot welding.
  • a circular weld 7b3 is formed at the joint. Therefore, the second electrode connection portion 7b2 of the second external terminal 7b is joined to the first surface extension portion 3b2 of the second external electrode 3b by the circular weld portion 7b3.
  • the second external terminal 7b is joined to the first surface extending portion 3b2 of the second external electrode 3b only by the welded portion 7b3.
  • the external electrode 3 and the external terminal 7 are joined by the circular welded portion 7a3 and welded portion 7b3.
  • the multilayer capacitor 10 includes two welded portions 7a3 provided on the first electrode connecting portion 7a2 and two welded portions 7b3 provided on the second electrode connecting portion 7b2. Yes.
  • the number of the welds 7a3 and the welds 7b3 is not limited to these numbers, and may be one or three or more depending on the size of the multilayer capacitor 10 or the bonding strength.
  • the first external terminal 7a has a first board connecting portion 7a1 that is a rectangular plate-like body, and is provided substantially parallel to the first surface 4a.
  • the second external terminal 7b has a second board connection portion 7b1 that is a rectangular plate-like body, and is provided substantially parallel to the first surface 4a.
  • substrate connection part 7b1 is set suitably not only in a rectangular plate-shaped body.
  • a pair of external electrodes 3 and a pair of external terminals 7 are joined together by welding.
  • the joint portion between the first electrode connection portion 7a2 and the first surface extension portion 3a2 of the first external electrode 3a is in point contact and becomes a welded portion 7a3.
  • the joint portion between the second electrode connection portion 7b2 and the first surface extension portion 3b2 of the second external electrode 3b is in point contact and becomes a welded portion 7b3.
  • the point contact makes it difficult for the multilayer capacitor 10 to propagate vibrations to the pair of external terminals 7.
  • the point contact portion is a circular joint and has a diameter of 30 ( ⁇ m) to 50 ( ⁇ m).
  • the first external terminal 7a is joined to the first surface extending portion 3a2 of the first external electrode 3a by point contact, and is not easily restrained by the first external electrode 3a.
  • the second external terminal 7b is joined to the first surface extension 3b2 of the second external electrode 3b by point contact, and is not easily restrained by the second external electrode 3b. Therefore, in the multilayer capacitor 10, vibration due to strain is easily absorbed by the first external terminal 7a and the second external terminal 7b.
  • the external terminal 7 is joined to the external electrode 3 by welding, and the joining area of the welded portion 7a3 and the welded portion 7b3 can be reduced. Therefore, in the multilayer capacitor 10, the external terminal 7 is not easily restrained by the external electrode 3, and vibration due to distortion is easily absorbed.
  • the sizes of the welded portion 7a3 and the welded portion 7b3 can be adjusted by, for example, the beam diameter of laser light to be irradiated or the output of laser light emission when laser spot welding is used.
  • the material of the external terminal 7 is, for example, a metal material such as iron (Fe), nickel (Ni), chromium (Cr), copper (Cu), silver (Ag), or cobalt (Co).
  • the material of the external terminal 7 is an alloy material including one or more of these metal materials, such as a stainless alloy or a copper alloy.
  • the first external terminal 7a and the second external terminal 7b may use the same metal material or alloy material.
  • the pair of external terminals 7 has a plating layer formed on the surface for solder bonding to the substrate electrode 9a and the substrate electrode 9b, and includes a plating layer formed on the surface. Further, the plating layer is formed, for example, by performing a masking process on a region of the pair of external terminals 7 where the plating layer is unnecessary.
  • the masking treatment can be performed using, for example, a low hardness rubber sheet.
  • the plating layer is formed in a region including the first substrate connection portion 7a1 and the second substrate connection portion 7b1 by using, for example, an electrolytic plating method.
  • the first substrate connection portion 7a1 and the second substrate connection portion 7b1 are provided with a plating layer at least on the substrate electrode 9a (substrate electrode 9b) side.
  • the external terminal 7 is provided with plating layers for the entire first substrate connection portion 7a1 and the first electrode connection portion 7a2, and the second substrate connection portion 7b1 and the second electrode connection portion 7b2. It may be provided for the whole. Note that the plating layer may be provided not only on both surfaces of the external terminal 7 but also on the side surface located between both surfaces.
  • the plating layer has a first plating layer and a second plating layer formed on the surface of the first plating layer.
  • the first plating layer covers the surfaces of the first external terminal 7a and the second external terminal 7b.
  • the second plating layer is formed on the surface of the first plating layer and covers the surface of the first plating layer.
  • Each of the first plating layer and the second plating layer may be composed of a plurality of plating layers.
  • the first plating layer and the second plating layer are, for example, metal materials such as nickel (Ni), silver (Ag), or tin (Sn).
  • the first plating layer and the second plating layer are alloy materials including one or more of these metal materials, for example, Sn—Ag alloy.
  • the first plating layer is, for example, a nickel (Ni) metal material or an alloy material containing nickel (Ni) as a main component.
  • the thickness of the first plating layer is, for example, 1 ( ⁇ m) to 2 ( ⁇ m).
  • the second plating layer is, for example, a tin (Sn) metal material or an alloy material containing tin (Sn) as a main component.
  • the thickness of the second plating layer is, for example, 1 ( ⁇ m) to 2 ( ⁇ m).
  • the thickness of the external terminal 7 is, for example, 0.1 (mm) to 0.15 (mm).
  • the thickness is appropriately set according to the size or application of the multilayer capacitor 10 so that vibration noise is reduced.
  • the thickness of the external terminal 7 is thinner than 0.1 (mm), the rigidity is reduced and vibration due to distortion generated in the multilayer capacitor body is easily absorbed. Mounting stability is deteriorated. In the external terminal 7, a portion not joined to the external electrode 3 absorbs vibration due to distortion.
  • the thickness of the external terminal 7 is greater than 0.15 (mm)
  • the rigidity is increased and it is difficult to absorb vibration due to distortion generated in the multilayer capacitor body.
  • the thickness of the external terminal 7 is set in consideration of reduction of vibration noise and mounting stability.
  • FIG. 5A shows a state in which the multilayer capacitor 10 is mounted on the substrate 9, and FIG. 5B is a side view of the state in which the multilayer capacitor 10 is mounted on the substrate 9, as viewed from the side. .
  • the multilayer capacitor 10 is mounted on a circuit board (hereinafter, referred to as a board 9) via a conductive bonding material, for example, a solder 11.
  • substrate 9 is used for a notebook personal computer, a smart phone, a mobile phone, etc., for example.
  • the substrate 9 has, for example, an electric circuit on the surface where the multilayer capacitor 10 is electrically connected.
  • the substrate 9 is shown with the insulating layer on the surface omitted.
  • the substrate 9 is provided with, for example, a substrate electrode 9a and a substrate electrode 9b on the mounting surface of the multilayer capacitor 10, and wiring (not shown) extends from the substrate electrode 9a. Further, wiring (not shown) extends from the substrate electrode 9b.
  • the first external terminal 7 a is soldered to the substrate electrode 9 a, for example, via solder 11
  • the second external terminal 7 b is connected to the substrate electrode 9 b, for example, via solder 11.
  • Soldered is arranged such that the first surface 4 a faces the mounting surface of the substrate 9. Solder joining is performed by, for example, a solder material printed on the substrate electrode 9a and the substrate electrode 9b.
  • the first external terminal 7a and the substrate electrode 9a are joined via the solder 11 disposed on the lower surface of the first substrate connection portion 7a1, and the second external terminal 7b
  • the substrate electrode 9b is joined via the solder 11 disposed on the lower surface of the second substrate connection portion 7b1.
  • solder material to be used is not particularly limited as long as it has good wettability with the external terminal 7.
  • solder material for example, Sn—Ag—Cu-based or Sn—Sb-based solder can be used.
  • a multilayer capacitor uses barium titanate (BaTiO 3 ) or the like as a main component as a dielectric layer.
  • a dielectric is formed according to the magnitude of the AC voltage due to an electrostrictive effect.
  • the layer is distorted and vibrates.
  • vibration propagates to the substrate, and vibration noise is generated by the propagated vibration.
  • the vibration frequency of the substrate is in an audible frequency band, an audible sound is generated from the substrate.
  • a conventional multilayer capacitor has a pair of external electrodes on a pair of end faces.
  • substrate is arrange
  • a pair of external electrodes may be provided at the center of a pair of side surfaces of the multilayer body in order to reduce vibration noise.
  • the substrate electrode is aligned with the pair of external electrodes and the short side of the multilayer capacitor multilayer body.
  • the arrangement of the substrate electrodes must be changed to the position in the short direction of the multilayer capacitor multilayer body in accordance with the pair of external electrodes.
  • the multilayer capacitor 10 is provided with a pair of external electrodes 3 on a pair of side surfaces.
  • the first substrate connecting portion 7a1 is disposed on the first end surface 4c side in the longitudinal direction of the multilayer body 1 so as to face the first surface 4a via a gap.
  • the second external terminal 7 b is arranged such that the second substrate connecting portion 7 b 1 is opposed to the first surface 4 a with a gap on the second end surface 4 d side in the longitudinal direction of the multilayer body 1.
  • the multilayer capacitor 10 can employ the same substrate electrode arrangement as a conventional multilayer capacitor having a pair of external electrodes on a pair of end faces.
  • the multilayer capacitor 10 can reduce noise without changing the arrangement of the substrate electrodes of the substrate.
  • the first ceramic green sheet forms the first internal electrode 2a.
  • the second ceramic green sheet forms the second internal electrode 2b.
  • the plurality of first ceramic green sheets are formed on the ceramic green sheet by using the conductive paste layer for the first internal electrode 2a as the conductive paste layer for the first internal electrode 2a.
  • the first ceramic green sheet in order to obtain a large number of multilayer capacitor bodies, a plurality of first internal electrodes 2a are formed in one ceramic green sheet.
  • the plurality of second ceramic green sheets are formed on the ceramic green sheet by using the conductive paste layer for the second internal electrode 2b using the conductive paste for the second internal electrode 2b.
  • the second ceramic green sheet in order to obtain a large number of multilayer capacitor bodies, a plurality of second internal electrodes 2b are formed in one ceramic green sheet.
  • the conductive paste layers of the first internal electrode 2a and the second internal electrode 2b described above are formed on the ceramic green sheet, for example, using a screen printing method or the like in a predetermined pattern shape for each conductive paste.
  • the material of the ceramic green sheet is mainly composed of dielectric ceramics such as barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium zirconate (CaZrO 3 ).
  • dielectric ceramics such as barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium zirconate (CaZrO 3 ).
  • a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound may be added as the accessory component.
  • the first and second ceramic green sheets are produced by adding a suitable organic solvent or the like to the dielectric ceramic raw material powder and the organic binder and mixing them, and using a doctor blade method or the like. Obtained by forming a ceramic slurry.
  • the conductive paste for the first internal electrode 2a and the second internal electrode 2b is formed by adding an additive (dielectric material), binder, solvent, dispersion to the above-described conductive material (metal material) powder of the internal electrode 2. It is prepared by adding an agent and kneading.
  • the laminated body 1 of ceramic materials is formed by alternately laminating first ceramic green sheets and second ceramic green sheets, and laminating ceramic green sheets not forming the internal electrodes 2 on the outermost layer in the laminating direction. To make.
  • a laminated body in which a plurality of first and second ceramic green sheets are laminated becomes a large-sized raw laminated body including a large number of raw laminated bodies by pressing and integrating them.
  • a green laminate that becomes the multilayer body 1 of the multilayer capacitor body shown in FIG. 1 can be obtained.
  • the large green laminate can be cut using, for example, a dicing blade.
  • the laminate 1 can be obtained by firing the green laminate at, for example, 800 (° C.) to 1300 (° C.). By firing, the plurality of first and second ceramic green sheets become the dielectric layer 1a.
  • the conductor paste layer of the first internal electrode 2a becomes the first internal electrode 2a.
  • the conductor paste layer of the second internal electrode 2b becomes the second internal electrode 2b.
  • the laminated body 1 is rounded a corner
  • the laminated body 1 is less likely to lack corners or sides by rounding the corners or sides.
  • the conductive paste to be the base electrode 5 is provided on the first side surface 4e (second side surface 4f), the first surface 4a, and the second surface 4b, respectively.
  • the conductive paste to be the base electrode 5 is transferred to the first side face 4e and the second side face 4f by using a roller transfer method.
  • the conductive paste is provided on the first side surface 4e (second side surface 4f) and is provided so as to extend to the first surface 4a and the second surface 4b.
  • the first surface extension portion 3a2 (first surface extension portion 3b2) and the second surface extension portion 3b3 (second surface extension portion 3b3) have the shape of the transferred base electrode 5 Will be reflected.
  • the transferred conductive paste becomes the base electrode 5 by sintering.
  • the plating layer 6 is provided on the surface of the base electrode 5 so as to cover the base electrode 5.
  • the plating layer 6 is formed on the surface of the base electrode 5 using, for example, an electrolytic plating method.
  • the conductive paste for the base electrode 5 is prepared by adding a binder, a solvent, a dispersant and the like to the powder of the metal material of the base electrode 5 described above and kneading.
  • the external terminal 7 is manufactured using a strip metal plate.
  • the thickness of the band-shaped metal plate is, for example, 0.1 (mm) to 0.15 (mm), and the length is 100 (mm) to 250 (mm).
  • the strip metal plate is, for example, a stainless alloy.
  • the first external terminal 7aa to be the first external terminal 7a and the second external terminal 7bb to be the second external terminal 7b are formed on the belt-shaped metal plate so as to face each other. Be placed.
  • the first external terminal 7aa and the second external terminal 7bb are punched by using, for example, a press punching method in accordance with the pattern shape of the band-shaped metal plate.
  • a plurality of external terminal pairs 12a of the first external terminal 7aa and the second external terminal 7bb are provided on the belt-shaped metal plate by press punching.
  • the lead frame 12 is a strip-shaped metal plate provided with a plurality of external terminal pairs 12a.
  • the multilayer capacitor 10 can be efficiently manufactured by using the lead frame 12.
  • the lead frame 12 forms a plating layer on the plurality of external terminal pairs 12a using, for example, a plating method.
  • the lead frame 12 is plated after being punched.
  • the lead frame 12 may be punched after plating.
  • the processing order is appropriately set in consideration of the shape of the pair of external terminals 7 and the like.
  • the multilayer capacitor body is mounted on the first external terminal 7aa and the second external terminal 7bb using, for example, an automatic mounting machine equipped with a suction nozzle.
  • the first external terminal 7aa is joined to the first external electrode 3a by using, for example, laser spot welding
  • the external terminal 7bb is joined to the second external electrode 3b.
  • the multilayer capacitor 10 is mounted on the substrate 9 via solder.
  • the joint between the external electrode 3 and the external terminal 7 is soldered. It is less susceptible to the temperature applied. Therefore, in the multilayer capacitor 10, the reliability of the joint is improved.
  • the multilayer capacitor 10 for example, when the first electrode connection portion 7a2 and the second electrode connection portion 7b2 are joined to the pair of external electrodes 3 via solder, the solder easily flows downward, It becomes easy to fall.
  • the multilayer capacitor 10 can improve the bondability between the external electrode 3 and the external terminal 7.
  • spot welding such as arc spot welding or laser spot welding
  • an energy beam such as a YAG laser is spot-irradiated to the first electrode connection portion 7a2 and the second electrode connection portion 7b2.
  • the first electrode connection portion 7a2 is joined to the first external electrode 3a by laser spot welding.
  • the second electrode connection portion 7b2 is joined to the second external electrode 3b.
  • the first electrode connecting portion 7a2 and the second electrode connecting portion 7b2 are locally heated when the energy beam is applied in a spot manner. For example, when the melting temperature of the stainless alloy of the external terminal 7 reaches 1400 (° C.) to 1450 (° C.), the first electrode connecting portion 7a2 and the second electrode connecting portion 7b2 are partially melted, It joins with the external electrode 3.
  • the multilayer capacitor 10 when a nickel (Ni) plating layer formed by an electrolytic plating method is used for the plating layer 6 and a stainless alloy is used for the external terminal 7, the nickel (Ni) plating layer and the stainless alloy are melted. The temperatures are similar, and the bondability between the external terminal 7 and the external electrode 3 can be improved. As described above, the multilayer capacitor 10 uses the material having a similar melting temperature to the plating layer 6 and the external terminal 7 in joining the external electrode 3 and the external terminal 7, so that the welded portion 7 a 3 and the welded portion 7 are welded. It becomes easy to control the joining region of the portion 7b3.
  • the multilayer capacitor body has the first external terminal 7aa attached to the first external electrode 3a and the second external terminal 7bb attached to the second external electrode 3b by welding.
  • the lead frame 12 sets the first cutting line S1 and the second cutting line S2, and with respect to the first cutting line S1 and the second cutting line S2. Cutting.
  • the external terminal pair 12a is separated from the lead frame 12 using, for example, a cutting die.
  • a plurality of multilayer capacitors 10 are obtained from the lead frame 12 as shown in FIG.
  • the first cutting line S1 and the second cutting line S2 are indicated by dotted lines.
  • the multilayer capacitor 10 can be efficiently manufactured by using the lead frame 12.
  • the external terminals 7 are joined to the external electrodes 3 by welding. Even if the external terminals 7 are soldered onto the substrate 9, the external terminals 7 are externally connected by heating of the soldering. Difficult to leave 3
  • the multilayer capacitor 10 ⁇ / b> B has a protruding portion 8 that protrudes toward the first surface 4 a side (positive side in the Z direction) on the first substrate connecting portion 7 a 1.
  • the second substrate connecting portion 7b1 has a protruding portion 8 that protrudes toward the first surface 4a side (the positive side in the Z direction).
  • the end portion of the first surface 4a may be inclined toward the first substrate connecting portion 7a1 and come into contact with the first substrate connecting portion 7a1.
  • the first board connecting portion 7a1 may be inclined toward the first surface 4a and come into contact with the first surface 4a.
  • the end portion of the first surface 4a may be inclined toward the second substrate connection portion 7b1 and come into contact with the second substrate connection portion 7b1.
  • the second board connecting portion 7b1 may be inclined toward the first surface 4a and come into contact with the first surface 4a.
  • the multilayer capacitor is The vibration is directly transmitted to the substrate 9 and it is easy for noise to occur.
  • the multilayer capacitor 10 does not protrude.
  • the first surface 4a is in point contact with the first substrate connecting portion 7a1, and the contact area with the first substrate connecting portion 7a1 is small.
  • the multilayer capacitor 10 does not protrude.
  • the first surface 4a is in point contact with the second substrate connecting portion 7b1, and the contact area with the second substrate connecting portion 7b1 is small. Therefore, the multilayer capacitor 10B is less likely to transmit vibration directly to the substrate 9.
  • the number of the protrusions 8 may be one or three or more according to the size of the first substrate connection portion 7a1 and the second substrate connection portion 7b1.
  • the present disclosure is not limited to the multilayer capacitor 10 and the multilayer capacitor 10B described above, and various modifications and improvements can be made without departing from the gist of the present disclosure. Other embodiments will be described below. Note that, among the multilayer capacitors according to other embodiments, the same portions as those of the multilayer capacitor 10 according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • a pair of external terminals 70 includes a first external terminal 7A and a second external terminal 7B. Although the shape is different from the pair of external terminals 7 of the multilayer capacitor 10, the materials and the like are The same thing is used.
  • the multilayer capacitor 10A is the same as the multilayer capacitor 10 except for the shape of the pair of external terminals 70.
  • the first external terminal 7A includes a first substrate connecting portion 7A1 and a first electrode connecting portion 7A2.
  • the first substrate connection portion 7A1 is a rectangular shape disposed on the first end surface 4c side (negative side in the X direction) in the longitudinal direction of the multilayer body 1 so as to face the first surface 4a via a gap. It is a plate-like body.
  • the first electrode connection portion 7A2 extends from the first substrate connection portion 7A1 along the longitudinal direction of the multilayer body 1 toward the first surface extension portion 3a2 of the first external electrode 3a. The end of the portion is joined to the first surface extension 3a2 of the first external electrode 3a.
  • the first electrode connection portion 7A2 extends toward the second end surface 4d so as to overlap the first surface extension portion 3a2 of the first external electrode 3a, and the first external electrode 3a.
  • the first surface extending portion 3a2 is joined.
  • the second external terminal 7B includes a second substrate connecting portion 7B1 and a second electrode connecting portion 7B2.
  • the second substrate connection portion 7B1 is disposed on the second end face 4d side in the longitudinal direction (positive side in the X direction) of the multilayer body 1 of the multilayer capacitor 10A so as to face the first face 4a via a gap.
  • the second electrode connection portion 7B2 extends from the second substrate connection portion 7B1 along the longitudinal direction of the stacked body 1 toward the first surface extension portion 3b2 of the second external electrode 3b. The end of the portion is joined to the first surface extension 3b2 of the second external electrode 3b.
  • the second electrode connection portion 7B2 extends toward the first end surface 4c so as to overlap the first surface extension portion 3b2 of the second external electrode 3b, and the second external electrode 3b.
  • the first surface extending portion 3b2 is joined.
  • the first electrode connecting portion 7A2 is a first surface extending portion of the first external electrode 3a whose bonding portion is bonded to the first surface extending portion 3a2 at the end. It protrudes upward (the positive side in the Z direction) from the surface on the first surface 4a side of the first substrate connecting portion 7A1 toward the 3a2 side. Furthermore, the first electrode connection portion 7A2 has a space portion 7A4 in a lower portion opposite to the first surface extension portion 3a2. Further, as shown in FIGS. 9 and 10, the second electrode connection portion 7B2 is formed such that the joint portion joined to the first surface extension portion 3b2 at the end is the first surface extension of the second external electrode 3b.
  • the second electrode connection portion 7B2 has a space portion 7B4 in a lower portion opposite to the first surface extension portion 3b2.
  • the first external terminal 7A is connected to the first external electrode 3a at the first electrode connection portion 7A2 by using, for example, soldering or welding. 1 surface extension part 3a2.
  • the second external terminal 7B is joined to the first surface extension portion 3b2 of the second external electrode 3b by the second electrode connection portion 7B2 by using, for example, solder joining or welding.
  • the first external terminal 7A and the second external terminal 7B are joined to the first external electrode 3a and the second external electrode 3b by welding.
  • the first electrode connection portion 7A2 is provided with a protruding portion and a space portion 7A4 in a region corresponding to the joint portion with the first surface extension portion 3a2, for example, by deep drawing using press working. be able to.
  • the second electrode connection portion 7B2 is a portion that protrudes into a region corresponding to a joint portion with the first surface extension portion 3b2 and a space portion 7B4 by deep drawing using, for example, pressing. Can be provided.
  • the space portion 7A4 and the space portion 7B4 are formed by the side wall portion 7A5 and the side wall portion 7B5.
  • the first substrate connecting portion 7A1 is bonded to the substrate electrode 9a
  • the second substrate connecting portion 7B1 is bonded to the substrate electrode 9b.
  • the first electrode connection portion 7A2 extends from the longitudinal end portion of the first substrate connection portion 7A1 toward the first surface extension portion 3a2 of the first external electrode 3a.
  • the second electrode connection portion 7B2 extends from the longitudinal end portion of the second substrate connection portion 7B1 toward the first surface extension portion 3b2 of the second external electrode 3b.
  • the joint part where the first surface extension part 3a2 and the first electrode connection part 7A2 are joined and the joint part where the first surface extension part 3b2 and the second electrode connection part 7B2 are joined are the first part.
  • the board connecting portion 7A1 and the second board connecting portion 7B1 are joined to the board electrode 9a and the board electrode 9b, respectively, and stress toward the inside of the first surface 4a is likely to occur. That is, a stress that rotates around the central portion of the first surface 4a is likely to occur in the welded portion 7A3 and the welded portion 7B3.
  • the first electrode connection portion 7A2 is such that the joint portion that joins the first surface extension portion 3a2 faces the first surface extension portion 3a2, and the first surface connection portion 7A1 has the first surface 4a side. And a space 7A4 on the side opposite to the first surface extension 3a2.
  • the second electrode connection portion 7B2 is such that the joint portion that joins the first surface extension portion 3b2 faces the first surface extension portion 3b2 and the first surface 4a side of the second substrate connection portion 7B1. And a space 7B4 on the side opposite to the first surface extension 3b2.
  • the multilayer capacitor 10A can relieve the stress that rotates around the central portion of the first surface 4a at the drawn side wall portions 7A5 and 7B5.
  • twisting stress is less likely to occur with respect to the welded portion 7A3 and the welded portion 7B3, and the reliability of the joint portion is improved.
  • the multilayer capacitor 10 ⁇ / b> A can be manufactured in the same manner as the multilayer capacitor 10.
  • the first external terminal 7Aa to be the first external terminal 7A and the second external terminal 7Bb to be the second external terminal 7B are formed on the band-shaped metal plate so as to face each other. Be placed.
  • the first external terminal 7Aa and the second external terminal 7Bb are punched using, for example, a press punching method in accordance with the pattern shape of the band-shaped metal plate.
  • the first electrode connection portion 7A2 can be provided with a space portion 7A4 below by projecting the joint portion with the first surface extension portion 3a2.
  • the second electrode connection portion 7B2 can be provided with a space portion 7B4 below by projecting a joint portion with the first surface extension portion 3b2.
  • a plurality of pairs of external terminals 12A of the first external terminals 7Aa and the second external terminals 7Bb are provided on the belt-shaped metal plate by punching and pressing.
  • the lead frame 12 forms a plating layer on the plurality of external terminal pairs 12A using, for example, a plating method.
  • the lead frame 12 is subjected to plating after punching and pressing. Without being limited thereto, the lead frame 12 may be punched and pressed after plating. In the lead frame 12, the processing order is appropriately set in consideration of the shape of the pair of external terminals 7 and the like.
  • the multilayer capacitor body is mounted on the first external terminal 7Aa and the second external terminal 7Bb by using, for example, an automatic mounting machine having a suction nozzle.
  • the first external terminal 7Aa is joined to the first external electrode 3a by using, for example, laser spot welding,
  • the external terminal 7Bb is joined to the second external electrode 3b.
  • the lead frame 12 sets the first cutting line S1 and the second cutting line S2, and with respect to the first cutting line S1 and the second cutting line S2. Cutting.
  • the external terminal pair 12A is separated from the lead frame 12 using, for example, a cutting die.
  • FIG. 11 (d) a plurality of multilayer capacitors 10 A are obtained from the lead frame 12.
  • the multilayer capacitor 10C has a protruding portion 8A protruding toward the first surface 4a side (positive side in the Z direction) in the region of the first substrate connecting portion 7a1. Moreover, you may have the protrusion part 8A which protrudes toward the 1st surface 4a side (positive side of a Z direction) in the area
  • the multilayer capacitor 10C is The first surface 4a is in point contact with the first substrate connecting portion 7A1, and the contact area with the first substrate connecting portion 7A1 is small.
  • the multilayer capacitor 10C is protruded.
  • the first surface 4a is in point contact with the second substrate connecting portion 7B1, and the contact area with the second substrate connecting portion 7B1 is small.
  • the multilayer capacitor 10 ⁇ / b> C is less likely to transmit vibration directly to the substrate 9.
  • the present disclosure is not limited to the above-described multilayer capacitors 10 to 10C, and various changes and improvements can be made without departing from the gist of the present disclosure.

Abstract

This multilayer capacitor is provided with: a laminate which has first and second surfaces, first and second end faces, and first and second lateral surfaces; a plurality of internal electrodes; first and second external electrodes which are respectively arranged on the pair of lateral surfaces; and a first external terminal connected to the first external electrode and a second external terminal connected to the second external electrode. The first external terminal comprises: a plate-like first substrate connection part that is arranged above the first surface with a space therebetween; and a first electrode connection part which extends from the first substrate connection part toward the second end face and has a front end portion that is connected to the first external electrode. The second external terminal comprises: a plate-like second substrate connection part that is arranged above the first surface with a space therebetween; and a second electrode connection part which extends from the second substrate connection part toward the first end face and has a front end portion that is connected to the second external electrode.

Description

積層型コンデンサおよびその実装構造体Multilayer capacitor and its mounting structure
 本発明は、複数の誘電体層と内部電極とが交互に積層された積層体に一対の外部電極を設けた積層型コンデンサおよびその実装構造体に関するものである。 The present invention relates to a multilayer capacitor in which a pair of external electrodes are provided on a multilayer body in which a plurality of dielectric layers and internal electrodes are alternately stacked, and a mounting structure thereof.
 積層型コンデンサは、誘電体層と内部電極とが交互に積層されており、誘電体層を構成するセラミック材料としては、誘電率が比較的高いチタン酸バリウム等の強誘電体材料が一般的に用いられている。例えば、このような積層型コンデンサは、交流電圧が印加されると、電圧による電歪効果によって誘電体層に歪みが発生して振動する。積層型コンデンサは、はんだ等を介して基板に実装されており、はんだ接合部を介して振動を基板に伝播させる。さらに、積層型コンデンサは、振動によって基板を共鳴させるとともに振動を増幅させて、基板に振動音を発生させる。したがって、基板は、可聴域の共振周波数で共振した際に、可聴音を発生し、いわゆる、音鳴きという現象を生じる。このように、積層型コンデンサは、一対の外部電極と基板電極とがはんだを介して実装されており、振動がはんだ接合部を介して基板を変形させるので、基板において振動音を発生させることになる。例えば、特許文献1には、積層体の長手方向に沿った一対の側面の中央部に一対の外部電極を設けた積層型コンデンサが開示されている。 In a multilayer capacitor, dielectric layers and internal electrodes are alternately laminated. As a ceramic material constituting the dielectric layer, a ferroelectric material such as barium titanate having a relatively high dielectric constant is generally used. It is used. For example, when an AC voltage is applied to such a multilayer capacitor, the dielectric layer is distorted by an electrostrictive effect caused by the voltage and vibrates. The multilayer capacitor is mounted on the substrate via solder or the like, and propagates vibration to the substrate via the solder joint. Furthermore, the multilayer capacitor resonates the substrate by vibration and amplifies the vibration to generate vibration sound on the substrate. Therefore, the substrate generates an audible sound when resonating at a resonance frequency in the audible range, and a so-called sounding phenomenon occurs. Thus, in the multilayer capacitor, the pair of external electrodes and the substrate electrode are mounted via the solder, and the vibration causes the substrate to be deformed via the solder joint. Become. For example, Patent Document 1 discloses a multilayer capacitor in which a pair of external electrodes is provided at the center of a pair of side surfaces along the longitudinal direction of a multilayer body.
特開2007-194312号公報JP 2007-194312 A
 本開示の積層型コンデンサは、複数の誘電体層が積層された、一対の第1の面および第2の面と、一対の第1の端面および第2の端面と、一対の第1の側面および第2の側面とを有する直方体状の積層体と、前記複数の誘電体層の層間に積層方向に間隔をおいて配置された複数の内部電極と、前記第1の側面および前記第2の側面にそれぞれ配置された、互いに異なる前記内部電極に電気的に接続された第1の外部電極および第2の外部電極と、前記第1の外部電極に接合された第1の外部端子および前記第2の外部電極に接合された第2の外部端子と、を備えている。前記第1の外部電極および前記第2の外部電極は、前記側面の中央部を含むように配置された側面部と、該側面部から前記第1の面に延在する第1の面延在部および前記第2の面に延在する第2の面延在部とを有している。前記第1の外部端子は、前記第1の端面に近接する前記第1の面の部分に隙間を介して対向して配置された板状体の第1の基板接続部および該第1の基板接続部から前記積層体の長手方向に沿って前記第2の端面の方向に向かって延び、延びた部分の端部が前記第1の外部電極の前記第1の面延在部に接合された第1の電極接続部を有している。前記第2の外部端子は、前記第2の端面に近接する前記第1の面の部分に隙間を介して対向して配置された板状体の第2の基板接続部および該第2の基板接続部から前記積層体の長手方向に沿って前記第1の端面の方向に向かって延び、延びた部分の端部が前記第2の外部電極の第1の面延在部に接合された第2の電極接続部を有している。 The multilayer capacitor of the present disclosure includes a pair of first surfaces and second surfaces, a pair of first end surfaces and second end surfaces, and a pair of first side surfaces on which a plurality of dielectric layers are stacked. And a rectangular parallelepiped laminate having a second side surface, a plurality of internal electrodes arranged in the stacking direction between the plurality of dielectric layers, the first side surface and the second side surface A first external electrode and a second external electrode electrically connected to the different internal electrodes, which are respectively disposed on the side surfaces; a first external terminal joined to the first external electrode; and the first external electrode And a second external terminal joined to the two external electrodes. The first external electrode and the second external electrode include a side surface portion disposed so as to include a central portion of the side surface, and a first surface extension extending from the side surface portion to the first surface. And a second surface extending portion extending on the second surface. The first external terminal includes a first substrate connecting portion of a plate-like body and the first substrate which are arranged to face each other with a gap between the first surface adjacent to the first end surface. It extended toward the direction of the said 2nd end surface from the connection part along the longitudinal direction of the said laminated body, and the edge part of the extended part was joined to the said 1st surface extension part of the said 1st external electrode. The first electrode connection portion is included. The second external terminal includes a second substrate connecting portion of the plate-like body and the second substrate, which are arranged to face each other with a gap between the first surface adjacent to the second end surface. Extending from the connecting portion along the longitudinal direction of the laminate toward the first end surface, the end of the extended portion is joined to the first surface extending portion of the second external electrode. 2 electrode connections.
実施の形態1に係る積層型コンデンサを示す概略の斜視図であって、(a)は、上面側から視た概略の斜視図であり、(b)は、下面側から視た概略の斜視図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic perspective view showing a multilayer capacitor according to a first embodiment, where (a) is a schematic perspective view seen from the upper surface side, and (b) is a schematic perspective view seen from the lower surface side. It is. (a)は、図1に示す積層型コンデンサを上面側から平面視した平面図であり、(b)は、図1に示す積層型コンデンサを下面側から平面視した平面図である。1A is a plan view of the multilayer capacitor shown in FIG. 1 as viewed from above, and FIG. 1B is a plan view of the multilayer capacitor shown in FIG. 1 as viewed from below. (a)は、図2(a)に示す積層型コンデンサのA-A線で切断した切断部端面図であり、(b)は、図2(a)に示す積層型コンデンサのB-B線で切断した切断部端面図である。FIG. 2 (a) is an end view of a cut portion taken along line AA of the multilayer capacitor shown in FIG. 2 (a), and FIG. 2 (b) is a BB line of the multilayer capacitor shown in FIG. 2 (a). FIG. (a)~(c)は内部電極を説明するための平面図である。(A)-(c) is a top view for demonstrating an internal electrode. (a)は、図1に示す積層型コンデンサを基板上に実装した状態を示す概略の斜視図であり、(b)は、図1に示す積層型コンデンサを基板上に実装した状態で積層型コンデンサの長手方向に垂直な方向から視た概略の側面図である。(A) is a schematic perspective view showing a state in which the multilayer capacitor shown in FIG. 1 is mounted on a substrate, and (b) is a multilayer type in a state where the multilayer capacitor shown in FIG. 1 is mounted on a substrate. It is the schematic side view seen from the direction perpendicular | vertical to the longitudinal direction of a capacitor | condenser. (a)~(d)は、図1に示す積層型コンデンサの製造方法を説明するための説明図である。(A)-(d) is explanatory drawing for demonstrating the manufacturing method of the multilayer capacitor shown in FIG. 実施の形態2に係る積層型コンデンサを示す概略の斜視図であって、(a)は、上面側から視た概略の斜視図であり、(b)は、下面側から視た概略の斜視図である。FIG. 3 is a schematic perspective view illustrating a multilayer capacitor according to a second embodiment, where (a) is a schematic perspective view viewed from the upper surface side, and (b) is a schematic perspective view viewed from the lower surface side. It is. (a)は、図7に示す積層型コンデンサを上面側から平面視した平面図であり、(b)は、図7に示す積層型コンデンサを下面側から平面視した平面図である。(A) is the top view which planarly viewed the multilayer capacitor shown in FIG. 7 from the upper surface side, (b) is the top view which planarly viewed the multilayer capacitor shown in FIG. (a)は、図8(a)に示す積層型コンデンサのA-A線で切断した切断部端面図であり、(b)は、図8(a)に示す積層型コンデンサのB-B線で切断した切断部端面図である。FIG. 8A is an end view of the multilayer capacitor shown in FIG. 8A cut along line AA. FIG. 8B is a cross-sectional view taken along line BB of the multilayer capacitor shown in FIG. FIG. (a)は、図7に示す積層型コンデンサを基板上に実装した状態を示す概略の斜視図であり、(b)は、図7に示す積層型コンデンサを基板上に実装した状態で積層型コンデンサの長手方向に垂直な方向から視た概略の側面図である。(A) is a schematic perspective view showing a state in which the multilayer capacitor shown in FIG. 7 is mounted on a substrate, and (b) is a multilayer type in a state where the multilayer capacitor shown in FIG. 7 is mounted on a substrate. It is the schematic side view seen from the direction perpendicular | vertical to the longitudinal direction of a capacitor | condenser. (a)~(d)は、図7に示す積層型コンデンサの製造方法を説明するための説明図である。FIGS. 8A to 8D are explanatory views for explaining a method of manufacturing the multilayer capacitor shown in FIG. 図1に示す積層型コンデンサの他の例であって、積層型コンデンサの長手方向に垂直な方向から視た側面図である。FIG. 6 is another example of the multilayer capacitor shown in FIG. 1, and is a side view seen from a direction perpendicular to the longitudinal direction of the multilayer capacitor. 図12に示す積層型コンデンサに用いられている外部端子を説明するための説明図であって、(a)は、図12に示す積層型コンデンサを上面側から平面視した平面図であり、(b)は、図12に示す積層型コンデンサに用いられる外部端子を上面側から視た平面図であり、(c)は、(b)に示す外部端子のE-E線で切断した切断部端面図である。It is explanatory drawing for demonstrating the external terminal used for the multilayer capacitor | condenser shown in FIG. 12, Comprising: (a) is the top view which planarly viewed the multilayer capacitor | condenser shown in FIG. FIG. 13B is a plan view of the external terminal used in the multilayer capacitor shown in FIG. 12 as viewed from the upper surface side, and FIG. 10C is a cut end surface cut along the line EE of the external terminal shown in FIG. FIG. 図7に示す積層型コンデンサの他の例であって、積層型コンデンサの長手方向に垂直な方向から視た側面図である。FIG. 8 is another example of the multilayer capacitor shown in FIG. 7, and is a side view seen from a direction perpendicular to the longitudinal direction of the multilayer capacitor.
 従来の積層型コンデンサは、一対の外部電極が一対の端面に設けられている。また、基板電極は、一対の端面に設けられた一対の外部電極に合わせて基板に設けられており、積層型コンデンサの積層体の長手方向の位置に配置されている。特許文献1に開示された積層型コンデンサは、一対の外部電極が一対の側面の中央部に設けられており、長手方向の位置に配置された基板電極を採用することができない。その結果、特許文献1に開示された積層型コンデンサは、一対の側面に設けられた一対の外部電極に合わせて積層型コンデンサの積層体の短手方向の位置に基板電極の配置を変更しなければならない。 A conventional multilayer capacitor has a pair of external electrodes on a pair of end faces. The substrate electrode is provided on the substrate in alignment with the pair of external electrodes provided on the pair of end faces, and is disposed at a position in the longitudinal direction of the multilayer body of the multilayer capacitor. In the multilayer capacitor disclosed in Patent Document 1, a pair of external electrodes is provided at the center of a pair of side surfaces, and a substrate electrode disposed at a position in the longitudinal direction cannot be employed. As a result, in the multilayer capacitor disclosed in Patent Document 1, the arrangement of the substrate electrodes must be changed to the position in the short direction of the multilayer capacitor multilayer body in accordance with the pair of external electrodes provided on the pair of side surfaces. I must.
 本開示の積層型コンデンサにおいては、一対の外部電極に一対の外部端子を設けることによって、一対の外部電極に合わせて基板電極の配置を変更しなくてもよい。以下、本開示の積層型コンデンサについて、詳細に説明する。 In the multilayer capacitor of the present disclosure, it is not necessary to change the arrangement of the substrate electrodes in accordance with the pair of external electrodes by providing the pair of external terminals on the pair of external electrodes. Hereinafter, the multilayer capacitor of the present disclosure will be described in detail.
 <実施の形態1>
 本開示の実施の形態1に係る積層型コンデンサ10について図面を参照しながら説明する。また、積層型コンデンサ10は、便宜的に、直交座標系XYZを定義するとともに、Z方向の正側を上方として、上面もしくは下面の用語を用いるものとする。本実施の形態では、一対の面のうちの下面が第1の面4aとなり、上面が第2の面4bとなる。なお、各図面において、同じ部材および同じ部分に関しては共通の符号を用いて、重複する説明は省略する。また、便宜的に、積層型コンデンサ10のうち一対の外部端子7を除いたものを積層型コンデンサ本体という用語を用いることがある。
<Embodiment 1>
The multilayer capacitor 10 according to the first embodiment of the present disclosure will be described with reference to the drawings. In addition, for convenience, the multilayer capacitor 10 defines an orthogonal coordinate system XYZ, and uses the terms “upper surface” or “lower surface” with the positive side in the Z direction as the upper side. In the present embodiment, the lower surface of the pair of surfaces is the first surface 4a, and the upper surface is the second surface 4b. In addition, in each drawing, the same code | symbol is used about the same member and the same part, and the overlapping description is abbreviate | omitted. For convenience, the term “multilayer capacitor body” may be used for the multilayer capacitor 10 excluding the pair of external terminals 7.
 図1(a)は、本開示の実施の形態1に係る積層型コンデンサ10の上面を上側にした状態の概略の斜視図であり、また、図1(b)は、積層型コンデンサ10の下面を上側にした状態の概略の斜視図である。 FIG. 1A is a schematic perspective view of the multilayer capacitor 10 according to the first embodiment of the present disclosure with the top surface thereof facing upward, and FIG. 1B is the bottom surface of the multilayer capacitor 10. FIG.
 積層型コンデンサ10は、積層体1と、一対の外部電極3と、一対の外部端子7とを備えている。積層体1は、直方体状であり、一対の第1の面4aおよび第2の面4bと、一対の第1の端面4cおよび第2の端面4dと、一対の第1の側面4eおよび第2の側面4fを有している。積層体1は、第1の内部電極2aと第2の内部電極2bとが交互に誘電体層1aを介して積層されている。一対の外部電極3(第1の外部電極3aおよび第2の外部電極3b)は、積層体1の一対の側面(第1の側面4eおよび第2の側面4f)の中央部を含むように設けられ、互いに異なる内部電極2にそれぞれ電気的に接続されている。一対の外部端子7(第1の外部端子7aおよび第2の外部端子7b)は、一対の外部電極3(第1の外部電極3aおよび第2の外部電極3b)に接合されている。 The multilayer capacitor 10 includes a multilayer body 1, a pair of external electrodes 3, and a pair of external terminals 7. The laminated body 1 has a rectangular parallelepiped shape, a pair of first surfaces 4a and second surfaces 4b, a pair of first end surfaces 4c and second end surfaces 4d, a pair of first side surfaces 4e and second. Side surface 4f. In the multilayer body 1, first internal electrodes 2a and second internal electrodes 2b are alternately stacked via dielectric layers 1a. The pair of external electrodes 3 (the first external electrode 3a and the second external electrode 3b) are provided so as to include the central part of the pair of side surfaces (the first side surface 4e and the second side surface 4f) of the multilayer body 1. Are electrically connected to different internal electrodes 2. The pair of external terminals 7 (first external terminal 7a and second external terminal 7b) are joined to the pair of external electrodes 3 (first external electrode 3a and second external electrode 3b).
 積層体1は、互いに対向する長方形状の第1の面4aおよび第2の面4bが積層方向に位置している。互いに対向する一対の端面(第1の端面4cおよび第2の端面4d)は、第1の面4aと第2の面4bとの間に位置するとともに第1の面4aおよび第2の面4bの短辺側に隣接している。また、互いに対向する一対の側面(第1の側面4eおよび第2の側面4f)は、第1の面4aと第2の面4bとの間に位置するとともに第1の面4aおよび第2の面4bの長辺側に隣接している。なお、一対の側面(第1の側面4eおよび第2の側面4f)は、積層体1の長手方向(X方向)に沿って位置している。また、一対の端面(第1の端面4cおよび第2の端面4d)は、積層体1の短手方向(Y方向)に沿って位置している。 The laminated body 1 has a rectangular first surface 4a and a second surface 4b facing each other positioned in the stacking direction. A pair of end surfaces (a first end surface 4c and a second end surface 4d) facing each other are located between the first surface 4a and the second surface 4b, and the first surface 4a and the second surface 4b. Adjacent to the short side. A pair of side surfaces (the first side surface 4e and the second side surface 4f) facing each other are located between the first surface 4a and the second surface 4b, and the first surface 4a and the second surface 4b. Adjacent to the long side of the surface 4b. The pair of side surfaces (the first side surface 4e and the second side surface 4f) are positioned along the longitudinal direction (X direction) of the stacked body 1. Further, the pair of end faces (first end face 4 c and second end face 4 d) are located along the short direction (Y direction) of the stacked body 1.
 このように、積層体1は、一対の端面が一対の面間に位置するとともに一対の面に直交している。また、積層体1は、一対の側面が一対の面間に位置するとともに一対の面に直交している。さらに、積層体1は、一対の端面と一対の側面とが直交している。直方体状とは、立方体形状または直方体形状のみならず、例えば、立方体または直方体の稜線部分に面取りが施されて、稜線部分がR形状になっているものを含んでいる。 Thus, in the laminated body 1, the pair of end faces are positioned between the pair of faces and are orthogonal to the pair of faces. Moreover, as for the laminated body 1, a pair of side surface is located between a pair of surface, and is orthogonal to a pair of surface. Furthermore, as for the laminated body 1, a pair of end surface and a pair of side surface are orthogonally crossed. The rectangular parallelepiped shape includes not only a cubic shape or a rectangular parallelepiped shape, but also includes, for example, a shape in which a ridge line portion of a cube or a rectangular parallelepiped is chamfered and the ridge line portion has an R shape.
 積層体1は、誘電体層1aの表面に内部電極2が形成されたセラミックグリーンシートを複数枚積層して焼成することで得られる焼結体である。また、積層型コンデンサ10は、積層体1の各稜線部が丸みを有していてもよい。 The laminate 1 is a sintered body obtained by laminating and firing a plurality of ceramic green sheets in which the internal electrode 2 is formed on the surface of the dielectric layer 1a. In the multilayer capacitor 10, each ridge line portion of the multilayer body 1 may be rounded.
 一対の外部電極3は、図1および図2に示すように、一対の側面に設けられ、第1の外部電極3aと第2の外部電極3bとを含んでいる。 As shown in FIGS. 1 and 2, the pair of external electrodes 3 is provided on a pair of side surfaces, and includes a first external electrode 3a and a second external electrode 3b.
 第1の外部電極3aは、図3に示すように、側面部3a1と第1の面延在部3a2と第2の面延在部3a3とを有している。側面部3a1は、第1の側面4eの中央部を含むように第1の側面4eに設けられている。第1の面延在部3a2は、側面部3a1から積層体1の短手方向(Y方向)の中央部に向かって第1の面4a上に延在している。第2の面延在部3a3は、側面部3a1から積層体1の短手方向(Y方向)の中央部に向かって第2の面4b上に延在している。 As shown in FIG. 3, the first external electrode 3a has a side surface portion 3a1, a first surface extension portion 3a2, and a second surface extension portion 3a3. The side surface portion 3a1 is provided on the first side surface 4e so as to include the central portion of the first side surface 4e. The first surface extending portion 3a2 extends on the first surface 4a from the side surface portion 3a1 toward the center portion in the short side direction (Y direction) of the multilayer body 1. The second surface extending portion 3a3 extends on the second surface 4b from the side surface portion 3a1 toward the center portion in the short direction (Y direction) of the stacked body 1.
 また、第2の外部電極3bは、図3に示すように、側面部3b1と第1の面延在部3b2と第2の面延在部3b3とを有している。側面部3b1は、第2の側面4fの中央部を含むように第2の側面4fに設けられている。第1の面延在部3b2は、側面部3b1から積層体1の短手方向(Y方向)の中央部に向かって第1の面4a上に延在している。第2の面延在部3b3は、側面部3b1から積層体1の短手方向(Y方向)の中央部に向かって第2の面4b上に延在している。 Further, as shown in FIG. 3, the second external electrode 3b has a side surface portion 3b1, a first surface extension portion 3b2, and a second surface extension portion 3b3. The side surface portion 3b1 is provided on the second side surface 4f so as to include the central portion of the second side surface 4f. The first surface extending portion 3b2 extends on the first surface 4a from the side surface portion 3b1 toward the center portion in the short direction (Y direction) of the stacked body 1. The second surface extension portion 3b3 extends on the second surface 4b from the side surface portion 3b1 toward the central portion in the short side direction (Y direction) of the stacked body 1.
 図1に示すように、第1の面延在部3a2(第1の面延在部3b2)および第2の面延在部3a3(第2の面延在部3b3)は、第1の面4aおよび第2の面4bの中央部に向かって凸状に湾曲し、例えば、中央部に向かって円弧状に設けられている。このように、第1の面延在部3a2(第1の面延在部3b2)および第2の面延在部3a3(第2の面延在部3b3)は、中央部側に向かって凸状に湾曲する湾曲部を有している。湾曲部は、例えば、凸状に湾曲する円弧状、半円形状または半楕円形状等である。積層型コンデンサ10は、第1の面延在部3a2(第1の面延在部3b2)および第2の面延在部3a3(第2の面延在部3b3)が第1の面4aおよび第2の面4bの中央部に向かって凸状に湾曲して延在しているので、外部電極3が積層体1から剥離しにくい。 As shown in FIG. 1, the first surface extension portion 3a2 (first surface extension portion 3b2) and the second surface extension portion 3a3 (second surface extension portion 3b3) are formed on the first surface. 4a and the 2nd surface 4b are convexly curved toward the center part, for example, are provided in circular arc shape toward the center part. Thus, the 1st surface extension part 3a2 (1st surface extension part 3b2) and the 2nd surface extension part 3a3 (2nd surface extension part 3b3) protrude toward the center part side. A curved portion that curves in a shape. The bending portion has, for example, an arc shape, a semicircular shape, or a semi-elliptical shape that is curved in a convex shape. The multilayer capacitor 10 includes a first surface extension portion 3a2 (first surface extension portion 3b2) and a second surface extension portion 3a3 (second surface extension portion 3b3). Since it extends in a convex shape toward the center of the second surface 4 b, the external electrode 3 is difficult to peel off from the laminate 1.
 内部電極2は、図3に示すように、第1の内部電極2aおよび第2の内部電極2bを含んでいる。第1の内部電極2aおよび第2の内部電極2bは、複数の誘電体層1aの層間に積層方向に所定の間隔をおいて互いに対向して配置されている。また、内部電極2は、積層体1の第1の面4aおよび第2の面4bに略平行になるように設けられている。 The internal electrode 2 includes a first internal electrode 2a and a second internal electrode 2b as shown in FIG. The first internal electrode 2a and the second internal electrode 2b are arranged opposite to each other with a predetermined interval in the stacking direction between the plurality of dielectric layers 1a. The internal electrode 2 is provided so as to be substantially parallel to the first surface 4 a and the second surface 4 b of the multilayer body 1.
 第1の外部電極3aは、図1乃至図4に示すように、側面部3a1が第1の側面4eの中央部を含むように配置されており、第1の側面4eに引き出された第1の内部電極2aに電気的に接続されている。また、第2の外部電極3bは、側面部3b1が第2の側面4fの中央部を含むように配置されており、第2の側面4fに引き出された第2の内部電極2bに電気的に接続されている。 As shown in FIGS. 1 to 4, the first external electrode 3a is arranged such that the side surface portion 3a1 includes the central portion of the first side surface 4e, and the first external electrode 3a is drawn to the first side surface 4e. The internal electrode 2a is electrically connected. The second external electrode 3b is disposed such that the side surface portion 3b1 includes the central portion of the second side surface 4f, and electrically connected to the second internal electrode 2b drawn out to the second side surface 4f. It is connected.
 第1の内部電極2aは、図4(b)に示すように、第1の側面4e側の中央部に第1の側面4eへの引出部2aaを有している。引出部2aaは、第1の側面4eに引き出され、第1の側面4eに露出するように配置されている。また、第2の内部電極2bは、図4(c)に示すように、第2の側面4f側の中央部に第2の側面4fへの引出部2baを有している。引出部2baは、第1の側面4eに対向する第2の側面4fに引き出され、第2の側面4fに露出するように配置されている。なお、第1の内部電極2aおよび第2の内部電極2bは、第1の端面4cおよび第2の端面4dには露出していない。図4(a)は、第1の側面4eに露出する第1の内部電極2aを実線で示し、第2の側面4fに露出する第2の内部電極2bを破線で示している。 As shown in FIG. 4B, the first internal electrode 2a has a lead-out portion 2aa to the first side surface 4e at the center on the first side surface 4e side. The lead-out portion 2aa is arranged so as to be drawn out to the first side surface 4e and exposed to the first side surface 4e. Further, as shown in FIG. 4C, the second internal electrode 2b has a lead-out portion 2ba to the second side surface 4f at the central portion on the second side surface 4f side. The lead-out portion 2ba is arranged so as to be drawn out to the second side face 4f facing the first side face 4e and exposed to the second side face 4f. The first internal electrode 2a and the second internal electrode 2b are not exposed on the first end surface 4c and the second end surface 4d. In FIG. 4A, the first internal electrode 2a exposed on the first side face 4e is shown by a solid line, and the second internal electrode 2b exposed on the second side face 4f is shown by a broken line.
 第1の外部電極3aは、図4(b)に示すように、側面部3a1が第1の側面4eに引き出された第1の内部電極2aの引出部2aaを覆うように設けられ、第1の内部電極2aに電気的に接続されている。また、第2の外部電極3bは、図4(c)に示すように、側面部3b1が第2の側面4fに引き出された第2の内部電極2bの引出部2baを覆うように設けられ、第2の内部電極2bに電気的に接続されている。 As shown in FIG. 4B, the first external electrode 3a is provided so that the side surface portion 3a1 covers the extraction portion 2aa of the first internal electrode 2a extracted to the first side surface 4e. The internal electrode 2a is electrically connected. Further, as shown in FIG. 4C, the second external electrode 3b is provided so that the side surface portion 3b1 covers the extraction portion 2ba of the second internal electrode 2b extracted to the second side surface 4f. It is electrically connected to the second internal electrode 2b.
 なお、第1の側面4eの中央部とは、第1の側面4eを垂直に2等分する2等分線Lを含む領域であり、第1の外部電極3aは側面部3a1がこの領域を含んで設けられている。また、第2の側面4fの中央部とは、第2の側面4fを垂直に2等分する2等分線Lを含む領域であり、第2の外部電極3bは側面部3b1がこの領域を含んで設けられている。図4は、2等分線Lを長鎖線で示している。 The central portion of the first side surface 4e is a region including a bisector L that bisects the first side surface 4e vertically, and the side portion 3a1 of the first external electrode 3a has this region. It is provided including. Further, the central portion of the second side surface 4f is a region including a bisector L that bisects the second side surface 4f vertically, and the side portion 3b1 of the second external electrode 3b is defined by this region. It is provided including. FIG. 4 shows the bisector L as a long chain line.
 このように、積層型コンデンサ10は、内部電極2が1層毎に異なる外部電極3に電気的に接続されており、一対の外部電極3に電圧が印加されると、第1の内部電極2aと第2の内部電極2bに挟まれた誘電体層1aにおいて静電容量が発生する。 Thus, in the multilayer capacitor 10, the internal electrodes 2 are electrically connected to different external electrodes 3 for each layer, and when a voltage is applied to the pair of external electrodes 3, the first internal electrodes 2a And a capacitance is generated in the dielectric layer 1a sandwiched between the second internal electrodes 2b.
 積層型コンデンサ本体の長手方向(X方向)の長さは、例えば、0.6(mm)~2.2(mm)であり、短手方向(Y方向)の長さは、例えば、0.3(mm)~1.5(mm)であり、高さ方向(Z方向)の長さは、例えば、0.3(mm)~1.2(mm)である。 The length of the multilayer capacitor body in the longitudinal direction (X direction) is, for example, 0.6 (mm) to 2.2 (mm), and the length in the lateral direction (Y direction) is, for example, 0. 3 (mm) to 1.5 (mm), and the length in the height direction (Z direction) is, for example, 0.3 (mm) to 1.2 (mm).
 誘電体層1aは、積層方向(Z方向)からの平面視において長方形状であり、1層当たりの厚みが、例えば、0.2(μm)~3(μm)である。積層体1は、例えば、10(層)~1000(層)の複数の誘電体層1aと複数の内部電極2とがZ方向に積層されている。また、積層体1内の内部電極2の積層数は、積層型コンデンサ10の特性等に応じて適宜に設定される。 The dielectric layer 1a is rectangular in a plan view from the stacking direction (Z direction), and the thickness per layer is, for example, 0.2 (μm) to 3 (μm). In the laminated body 1, for example, a plurality of dielectric layers 1a of 10 (layers) to 1000 (layers) and a plurality of internal electrodes 2 are laminated in the Z direction. Further, the number of internal electrodes 2 in the multilayer body 1 is appropriately set according to the characteristics of the multilayer capacitor 10.
 誘電体層1aは、例えば、チタン酸バリウム(BaTiO)、チタン酸カルシウム(CaTiO)、チタン酸ストロンチウム(SrTiO)またはジルコン酸カルシウム(CaZrO)等である。また、誘電体層1aは、高い誘電率の点から、特に、誘電率の高い強誘電体材料としてチタン酸バリウムを用いてもよい。 The dielectric layer 1a is, for example, barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium zirconate (CaZrO 3 ). In addition, the dielectric layer 1a may use barium titanate as a ferroelectric material having a high dielectric constant from the viewpoint of a high dielectric constant.
 図4に示すように、引出部2aaおよび引出部2baは、積層体1の長手方向(X方向)に沿った長さがほぼ同じ長さになるように設けられている。これに限らず、引出部2aaおよび引出部2baは、積層体1の長手方向(X方向)に沿った長さが互いに異なっていてもよい。 As shown in FIG. 4, the lead-out part 2aa and the lead-out part 2ba are provided so that the lengths along the longitudinal direction (X direction) of the laminate 1 are substantially the same. Not only this but the drawer part 2aa and the drawer part 2ba may mutually differ in the length along the longitudinal direction (X direction) of the laminated body 1. FIG.
 また、引出部2aa(引出部2ba)は、振動の対称性を保ち、基板9を振動させる要素を低減するために、第1の側面4e(第2の側面4f)における露出部が第1の側面4e(第2の側面4f)の2等分線Lを含むように設けてもよい。 In addition, in the drawing portion 2aa (drawing portion 2ba), the exposed portion on the first side face 4e (second side face 4f) is the first in order to maintain the symmetry of vibration and reduce elements that vibrate the substrate 9. You may provide so that the bisector L of the side surface 4e (2nd side surface 4f) may be included.
 内部電極2の導電材料は、例えば、ニッケル(Ni)、銅(Cu)、銀(Ag)、パラジウム(Pd)または金(Au)等の金属材料である。または、内部電極2の導電材料は、これらの金属材料の一種以上を含む、例えば、Ag-Pd合金等の合金材料である。第1の内部電極2aおよび第2の内部電極2bの電極の厚みは、例えば、0.2(μm)~2(μm)であり、用途に応じて適宜に設定すればよい。また、第1の内部電極2aおよび第2の内部電極2bは、同一の金属材料または合金材料を用いてもよい。 The conductive material of the internal electrode 2 is a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au). Alternatively, the conductive material of the internal electrode 2 is an alloy material such as an Ag—Pd alloy including one or more of these metal materials. The thicknesses of the first internal electrode 2a and the second internal electrode 2b are, for example, 0.2 (μm) to 2 (μm), and may be set appropriately depending on the application. The first internal electrode 2a and the second internal electrode 2b may use the same metal material or alloy material.
 一対の外部電極3は、図3に示すように、下地電極5とめっき層6とを含んでいる。一対の下地電極5は、第1の側面4eまたは第2の側面4fに引き出された内部電極2に電気的に接続されている。めっき層6は、下地電極5を覆うように下地電極5の表面上に設けられている。めっき層6は、下地電極5を保護するために設けられている。また、めっき層6は、一対の外部端子7との接合に溶接を用いる場合、外部電極3と外部端子7との接合性を向上させることができる。なお、外部電極3は、めっき層6に限らず、外部端子7に対して接合可能な金属層が下地電極5を覆うように設けられていればよい。特に、外部電極3は、下地電極5を覆うように外部端子7に対して溶接でもって接合可能な金属層が設けられていればよい。 The pair of external electrodes 3 includes a base electrode 5 and a plating layer 6 as shown in FIG. The pair of base electrodes 5 is electrically connected to the internal electrode 2 drawn out to the first side face 4e or the second side face 4f. The plating layer 6 is provided on the surface of the base electrode 5 so as to cover the base electrode 5. The plating layer 6 is provided to protect the base electrode 5. In addition, the plating layer 6 can improve the bondability between the external electrode 3 and the external terminal 7 when welding is used for bonding the pair of external terminals 7. The external electrode 3 is not limited to the plating layer 6, and any metal layer that can be bonded to the external terminal 7 may be provided so as to cover the base electrode 5. In particular, the external electrode 3 only needs to be provided with a metal layer that can be joined to the external terminal 7 by welding so as to cover the base electrode 5.
 下地電極5の導電材料は、例えば、ニッケル(Ni)、銅(Cu)、銀(Ag)、パラジウム(Pd)または金(Au)等の金属材料である。または、下地電極5の導電材料は、これらの金属材料の一種以上を含む、例えば、Ag-Pd合金等の合金材料である。また、一対の下地電極5は、同一の金属材料または合金材料を用いてもよい。 The conductive material of the base electrode 5 is a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au). Alternatively, the conductive material of the base electrode 5 is an alloy material such as an Ag—Pd alloy including one or more of these metal materials. The pair of base electrodes 5 may use the same metal material or alloy material.
 下地電極5は、第1の面4aおよび第2の面4bにおける厚みが、例えば、4(μm)~10(μm)であり、第1の側面4eおよび第2の側面4fにおける厚みが、例えば、10(μm)~25(μm)である。 The base electrode 5 has a thickness on the first surface 4a and the second surface 4b of, for example, 4 (μm) to 10 (μm), and a thickness on the first side surface 4e and the second side surface 4f, for example. 10 (μm) to 25 (μm).
 また、下地電極5は、第1の下地電極が第1の側面4eから第1の面4aおよび第2の面4bに延在するように設けられ、また、第2の下地電極が第2の側面4fから第1の面4aおよび第2の面4bに延在するように設けられている。めっき層6は、積層体1の表面に形成された下地電極5を覆うように下地電極5の表面上に設けられている。めっき層6は、例えば、ニッケル(Ni)めっき層、銅(Cu)めっき層、金(Au)めっき層またはスズ(Sn)めっき層等である。また、めっき層6は、例えば、電解めっき法を用いて形成される。 The base electrode 5 is provided so that the first base electrode extends from the first side surface 4e to the first surface 4a and the second surface 4b, and the second base electrode is the second base electrode. It is provided to extend from the side surface 4f to the first surface 4a and the second surface 4b. The plating layer 6 is provided on the surface of the base electrode 5 so as to cover the base electrode 5 formed on the surface of the multilayer body 1. The plating layer 6 is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like. The plating layer 6 is formed using, for example, an electrolytic plating method.
 めっき層6は、下地電極5の表面上に単一のめっき層で設けてもよい。積層型コンデンサ10は、図3に示すように、めっき層6が複数層であり、第1のめっき層6aと第2のめっき層6bを有している。このように、めっき層6は、第1のめっき層6aおよび第1のめっき層6aの表面に形成された第2のめっき層6bの積層体である。めっき層6は、例えば、ニッケル(Ni)めっき層、銅(Cu)めっき層、金(Au)めっき層または錫(Sn)めっき層等である。 The plating layer 6 may be provided as a single plating layer on the surface of the base electrode 5. As shown in FIG. 3, the multilayer capacitor 10 includes a plurality of plating layers 6 and includes a first plating layer 6a and a second plating layer 6b. Thus, the plating layer 6 is a laminated body of the first plating layer 6a and the second plating layer 6b formed on the surfaces of the first plating layer 6a. The plating layer 6 is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like.
 積層型コンデンサ10は、例えば、第1のめっき層6aがニッケル(Ni)めっき層であり、第2のめっき層6bが錫(Sn)めっき層であり、第2のめっき層6bが第1のめっき層6aを覆うように設けられている。第1のめっき層6aは、めっき層の厚みが、例えば、5(μm)~10(μm)であり、第2のめっき層6bは、めっき層の厚みが、例えば、3(μm)~5(μm)である。 In the multilayer capacitor 10, for example, the first plating layer 6a is a nickel (Ni) plating layer, the second plating layer 6b is a tin (Sn) plating layer, and the second plating layer 6b is a first plating layer. It is provided so as to cover the plating layer 6a. The first plating layer 6a has a plating layer thickness of, for example, 5 (μm) to 10 (μm), and the second plating layer 6b has a plating layer thickness of, for example, 3 (μm) to 5 (μm). (Μm).
 ここで、一対の外部端子7(第1の外部端子7aおよび第2の外部端子7b)について図面を参照しながら説明する。 Here, the pair of external terminals 7 (first external terminal 7a and second external terminal 7b) will be described with reference to the drawings.
 一対の外部端子7は、図1および図2に示すように、第1の外部端子7aおよび第2の外部端子7bを含んでいる。第1の外部端子7aは、第1の外部電極3aの第1の面延在部3a2に接合されている。また、第2の外部端子7bは、第2の外部電極3bの第1の面延在部3b2に接合されている。 As shown in FIGS. 1 and 2, the pair of external terminals 7 includes a first external terminal 7a and a second external terminal 7b. The first external terminal 7a is joined to the first surface extending portion 3a2 of the first external electrode 3a. The second external terminal 7b is joined to the first surface extending portion 3b2 of the second external electrode 3b.
 第1の外部端子7aは、図1および図2に示すように、第1の基板接続部7a1と第1の電極接続部7a2とを含んでいる。第1の基板接続部7a1は、第1の端面4cに近接する第1の面4aの部分に対向しており、平面視して積層体1の第1の端面4c側の端部と重なるように設けられている。このように、第1の基板接続部7a1は、積層体1の長手方向の第1の端面4c側(X方向の負側)に第1の面4aの部分に隙間を介して対向するように配置されており、矩形状の板状体である。第1の電極接続部7a2は、第1の基板接続部7a1から積層体1の長手方向に沿って第1の外部電極3aの第1の面延在部3a2に向かって延びており、延びた部分の端部が第1の外部電極3aの第1の面延在部3a2に接合されている。このように、第1の電極接続部7a2は、第1の外部電極3aの第1の面延在部3a2に重なるように第2の端面4dに向かって延びており、第1の外部電極3aの第1の面延在部3a2に接合されている。 The first external terminal 7a includes a first substrate connection portion 7a1 and a first electrode connection portion 7a2 as shown in FIGS. The first substrate connection portion 7a1 is opposed to the portion of the first surface 4a that is close to the first end surface 4c, and overlaps the end portion on the first end surface 4c side of the stacked body 1 in plan view. Is provided. In this way, the first substrate connection portion 7a1 is opposed to the first end surface 4c side (negative side in the X direction) in the longitudinal direction of the multilayer body 1 with the gap of the first surface 4a. It is a rectangular plate-shaped body. The first electrode connection portion 7a2 extends from the first substrate connection portion 7a1 along the longitudinal direction of the multilayer body 1 toward the first surface extension portion 3a2 of the first external electrode 3a. The end of the portion is joined to the first surface extension 3a2 of the first external electrode 3a. Thus, the first electrode connection portion 7a2 extends toward the second end face 4d so as to overlap the first surface extension portion 3a2 of the first external electrode 3a, and the first external electrode 3a. The first surface extending portion 3a2 is joined.
 また、第2の外部端子7bは、図1および図2に示すように、第2の基板接続部7b1と第2の電極接続部7b2とを含んでいる。第2の基板接続部7b1は、第2の端面4dに近接する第1の面4aの部分に対向しており、平面視して積層体1の第2の端面4d側の端部と重なるように設けられている。このように、第2の基板接続部7b1は、積層体1の長手方向の第2の端面4d側(X方向の正側)に第1の面4aの部分に隙間を介して対向するように配置されており、矩形状の板状体である。第2の電極接続部7b2は、第2の基板接続部7b1から積層体1の長手方向に沿って第2の外部電極3bの第1の面延在部3b2に向かって延びており、延びた部分の端部が第2の外部電極3bの第1の面延在部3b2に接合されている。このように、第2の電極接続部7b2は、第2の外部電極3bの第1の面延在部3b2に重なるように第1の端面4cに向かって延びており、第2の外部電極3bの第1の面延在部3b2に接合されている。 The second external terminal 7b includes a second substrate connection portion 7b1 and a second electrode connection portion 7b2, as shown in FIGS. The second substrate connection portion 7b1 faces the portion of the first surface 4a that is close to the second end surface 4d, and overlaps the end portion of the stacked body 1 on the second end surface 4d side in plan view. Is provided. In this way, the second substrate connection portion 7b1 is opposed to the portion of the first surface 4a on the second end surface 4d side (the positive side in the X direction) in the longitudinal direction of the multilayer body 1 via the gap. It is a rectangular plate-shaped body. The second electrode connection portion 7b2 extends from the second substrate connection portion 7b1 along the longitudinal direction of the stacked body 1 toward the first surface extension portion 3b2 of the second external electrode 3b. The end of the portion is joined to the first surface extension 3b2 of the second external electrode 3b. Thus, the second electrode connection portion 7b2 extends toward the first end surface 4c so as to overlap the first surface extension portion 3b2 of the second external electrode 3b, and the second external electrode 3b. The first surface extending portion 3b2 is joined.
 第1の外部端子7aは、例えば、はんだ接合または溶接等を用いて、第1の電極接続部7a2が第1の外部電極3aの第1の面延在部3a2に接合される。また、第2の外部端子7bは、例えば、はんだ接合または溶接等を用いて、第2の電極接続部7b2が第2の外部電極3bの第1の面延在部3b2に接合される。本実施の形態においては、第1の外部端子7aおよび第2の外部端子7bは、溶接を用いて第1の外部電極3aおよび第2の外部電極3bに接合されている。 In the first external terminal 7a, the first electrode connection portion 7a2 is joined to the first surface extension portion 3a2 of the first external electrode 3a by using, for example, soldering or welding. In the second external terminal 7b, for example, the second electrode connection portion 7b2 is joined to the first surface extension portion 3b2 of the second external electrode 3b by soldering or welding. In the present embodiment, the first external terminal 7a and the second external terminal 7b are joined to the first external electrode 3a and the second external electrode 3b by welding.
 第1の外部端子7aは、図1乃至図3に示すように、例えば、スポット溶接等を用いて、第1の外部電極3aと第1の電極接続部7a2とを溶接することによって、接合部に円形状の溶接部7a3が形成される。したがって、第1の外部端子7aの第1の電極接続部7a2は、円形状の溶接部7a3で第1の外部電極3aの第1の面延在部3a2に接合されることになる。また、第1の外部端子7aは、溶接部7a3のみで第1の外部電極3aの第1の面延在部3a2に接合されている。 As shown in FIG. 1 to FIG. 3, the first external terminal 7a is welded to the first external electrode 3a and the first electrode connecting portion 7a2 by using, for example, spot welding. A circular weld 7a3 is formed. Accordingly, the first electrode connection portion 7a2 of the first external terminal 7a is joined to the first surface extension portion 3a2 of the first external electrode 3a by the circular weld portion 7a3. The first external terminal 7a is joined to the first surface extending portion 3a2 of the first external electrode 3a only by the welded portion 7a3.
 また、第2の外部端子7bは、図1乃至図3に示すように、例えば、スポット溶接等を用いて、第2の外部電極3bと第2の電極接続部7b2とを溶接することによって、接合部に円形状の溶接部7b3が形成される。したがって、第2の外部端子7bの第2の電極接続部7b2は、円形状の溶接部7b3で第2の外部電極3bの第1の面延在部3b2に接合されることになる。また、第2の外部端子7bは、溶接部7b3のみで第2の外部電極3bの第1の面延在部3b2に接合されている。このように、積層型コンデンサ10は、外部電極3と外部端子7とが円形状の溶接部7a3および溶接部7b3で接合される。 Further, as shown in FIGS. 1 to 3, the second external terminal 7b is welded to the second external electrode 3b and the second electrode connection portion 7b2 by using, for example, spot welding. A circular weld 7b3 is formed at the joint. Therefore, the second electrode connection portion 7b2 of the second external terminal 7b is joined to the first surface extension portion 3b2 of the second external electrode 3b by the circular weld portion 7b3. The second external terminal 7b is joined to the first surface extending portion 3b2 of the second external electrode 3b only by the welded portion 7b3. Thus, in the multilayer capacitor 10, the external electrode 3 and the external terminal 7 are joined by the circular welded portion 7a3 and welded portion 7b3.
 積層型コンデンサ10は、図1および図2に示すように、溶接部7a3が第1の電極接続部7a2に2個設けられ、溶接部7b3が第2の電極接続部7b2に2個設けられている。溶接部7a3および溶接部7b3の個数は、これらの個数に限らず、積層型コンデンサ10の大きさまたは接合の強度等に応じて1個または3個以上であってもよい。 As shown in FIGS. 1 and 2, the multilayer capacitor 10 includes two welded portions 7a3 provided on the first electrode connecting portion 7a2 and two welded portions 7b3 provided on the second electrode connecting portion 7b2. Yes. The number of the welds 7a3 and the welds 7b3 is not limited to these numbers, and may be one or three or more depending on the size of the multilayer capacitor 10 or the bonding strength.
 第1の外部端子7aは、図1および図2に示すように、第1の基板接続部7a1が矩形状の板状体であり、第1の面4aに略平行に設けられている。また、第2の外部端子7bは、図1および図2に示すように、第2の基板接続部7b1が矩形状の板状体であり、第1の面4aに略平行に設けられている。また、第1の基板接続部7a1および第2の基板接続部7b1の形状は、矩形の板状体に限らず、適宜に設定される。 As shown in FIG. 1 and FIG. 2, the first external terminal 7a has a first board connecting portion 7a1 that is a rectangular plate-like body, and is provided substantially parallel to the first surface 4a. Further, as shown in FIGS. 1 and 2, the second external terminal 7b has a second board connection portion 7b1 that is a rectangular plate-like body, and is provided substantially parallel to the first surface 4a. . Moreover, the shape of the 1st board | substrate connection part 7a1 and the 2nd board | substrate connection part 7b1 is set suitably not only in a rectangular plate-shaped body.
 積層型コンデンサ10は、例えば、一対の外部電極3と一対の外部端子7とが溶接を用いて接合される。第1の電極接続部7a2と第1の外部電極3aの第1の面延在部3a2との接合部は、点接触になり、溶接部7a3となる。また、第2の電極接続部7b2と第2の外部電極3bの第1の面延在部3b2との接合部は、点接触になり、溶接部7b3となる。点接触によって、積層型コンデンサ10は、振動が一対の外部端子7に伝播しにくくなる。なお、ここでは、点接触部は、円形状の接合部であり、30(μm)~50(μm)の直径を有している。 In the multilayer capacitor 10, for example, a pair of external electrodes 3 and a pair of external terminals 7 are joined together by welding. The joint portion between the first electrode connection portion 7a2 and the first surface extension portion 3a2 of the first external electrode 3a is in point contact and becomes a welded portion 7a3. Further, the joint portion between the second electrode connection portion 7b2 and the first surface extension portion 3b2 of the second external electrode 3b is in point contact and becomes a welded portion 7b3. The point contact makes it difficult for the multilayer capacitor 10 to propagate vibrations to the pair of external terminals 7. In this case, the point contact portion is a circular joint and has a diameter of 30 (μm) to 50 (μm).
 このように、第1の外部端子7aは、第1の外部電極3aの第1の面延在部3a2に点接触で接合されており、第1の外部電極3aに拘束されにくい。また、第2の外部端子7bは、第2の外部電極3bの第1の面延在部3b2に点接触で接合されており、第2の外部電極3bに拘束されにくい。したがって、積層型コンデンサ10は、歪による振動が第1の外部端子7aおよび第2の外部端子7bで吸収されやすくなる。 Thus, the first external terminal 7a is joined to the first surface extending portion 3a2 of the first external electrode 3a by point contact, and is not easily restrained by the first external electrode 3a. The second external terminal 7b is joined to the first surface extension 3b2 of the second external electrode 3b by point contact, and is not easily restrained by the second external electrode 3b. Therefore, in the multilayer capacitor 10, vibration due to strain is easily absorbed by the first external terminal 7a and the second external terminal 7b.
 また、外部端子7は、外部電極3に溶接を用いて接合されており、溶接部7a3および溶接部7b3の接合領域を小さくすることできる。したがって、積層型コンデンサ10は、外部端子7が外部電極3に拘束されにくく、歪みによる振動が吸収されやすくなる。なお、溶接部7a3および溶接部7b3の大きさは、例えば、レーザスポット溶接を用いる場合には、照射するレーザ光のビーム径またはレーザ光の射出の出力等で調整することができる。 Moreover, the external terminal 7 is joined to the external electrode 3 by welding, and the joining area of the welded portion 7a3 and the welded portion 7b3 can be reduced. Therefore, in the multilayer capacitor 10, the external terminal 7 is not easily restrained by the external electrode 3, and vibration due to distortion is easily absorbed. Note that the sizes of the welded portion 7a3 and the welded portion 7b3 can be adjusted by, for example, the beam diameter of laser light to be irradiated or the output of laser light emission when laser spot welding is used.
 外部端子7の材料は、例えば、鉄(Fe)、ニッケル(Ni)、クロム(Cr)、銅(Cu)、銀(Ag)またはコバルト(Co)等の金属材料である。または、外部端子7の材料は、これらの金属材料の一種以上を含む、例えば、ステンレス合金または銅合金等の合金材料である。また、第1の外部端子7aおよび第2の外部端子7bは、同一の金属材料または合金材料を用いてもよい。 The material of the external terminal 7 is, for example, a metal material such as iron (Fe), nickel (Ni), chromium (Cr), copper (Cu), silver (Ag), or cobalt (Co). Alternatively, the material of the external terminal 7 is an alloy material including one or more of these metal materials, such as a stainless alloy or a copper alloy. The first external terminal 7a and the second external terminal 7b may use the same metal material or alloy material.
 一対の外部端子7は、基板電極9aおよび基板電極9bにはんだ接合するために表面にめっき層が形成されており、表面に形成されためっき層を含むものである。また、めっき層は、例えば、一対の外部端子7のうちめっき層が不要な領域にはマスキング処理等を行なって形成される。なお、マスキング処理は、例えば、低硬度ゴムシート等を用いて行なうことができる。 The pair of external terminals 7 has a plating layer formed on the surface for solder bonding to the substrate electrode 9a and the substrate electrode 9b, and includes a plating layer formed on the surface. Further, the plating layer is formed, for example, by performing a masking process on a region of the pair of external terminals 7 where the plating layer is unnecessary. The masking treatment can be performed using, for example, a low hardness rubber sheet.
 めっき層は、例えば、電解めっき法等を用いて、第1の基板接続部7a1および第2の基板接続部7b1を含む領域に形成される。第1の基板接続部7a1および第2の基板接続部7b1は、めっき層が少なくとも基板電極9a(基板電極9b)側には設けられている。また、外部端子7は、めっき層が第1の基板接続部7a1および第1の電極接続部7a2の全体に対して設けられ、また、第2の基板接続部7b1および第2の電極接続部7b2の全体に対して設けられていてもよい。なお、めっき層は、外部端子7の両面だけでなく、両面間に位置する側面に設けられていてもよい。 The plating layer is formed in a region including the first substrate connection portion 7a1 and the second substrate connection portion 7b1 by using, for example, an electrolytic plating method. The first substrate connection portion 7a1 and the second substrate connection portion 7b1 are provided with a plating layer at least on the substrate electrode 9a (substrate electrode 9b) side. The external terminal 7 is provided with plating layers for the entire first substrate connection portion 7a1 and the first electrode connection portion 7a2, and the second substrate connection portion 7b1 and the second electrode connection portion 7b2. It may be provided for the whole. Note that the plating layer may be provided not only on both surfaces of the external terminal 7 but also on the side surface located between both surfaces.
 また、外部端子7において、例えば、めっき層は、第1のめっき層および第1のめっき層の表面に形成される第2のめっき層を有している。第1のめっき層は、第1の外部端子7aおよび第2の外部端子7bの表面を覆うものである。第2のめっき層は、第1のめっき層の表面に形成されて第1のめっき層の表面を覆うものである。なお、第1のめっき層および第2のめっき層は、それぞれ複数のめっき層で構成されていてもよい。 Further, in the external terminal 7, for example, the plating layer has a first plating layer and a second plating layer formed on the surface of the first plating layer. The first plating layer covers the surfaces of the first external terminal 7a and the second external terminal 7b. The second plating layer is formed on the surface of the first plating layer and covers the surface of the first plating layer. Each of the first plating layer and the second plating layer may be composed of a plurality of plating layers.
 第1のめっき層および第2のめっき層は、例えば、ニッケル(Ni)、銀(Ag)または錫(Sn)等の金属材料である。または、第1のめっき層および第2のめっき層は、これらの金属材料の一種以上を含む、例えば、Sn-Ag合金等の合金材料である。第1のめっき層は、例えば、ニッケル(Ni)の金属材料またはニッケル(Ni)を主成分として含む合金材料である。第1のめっき層の厚みは、例えば、1(μm)~2(μm)である。また、第2のめっき層は、例えば、錫(Sn)の金属材料またはスズ(Sn)を主成分として含む合金材料である。第2のめっき層の厚みは、例えば、1(μm)~2(μm)である。 The first plating layer and the second plating layer are, for example, metal materials such as nickel (Ni), silver (Ag), or tin (Sn). Alternatively, the first plating layer and the second plating layer are alloy materials including one or more of these metal materials, for example, Sn—Ag alloy. The first plating layer is, for example, a nickel (Ni) metal material or an alloy material containing nickel (Ni) as a main component. The thickness of the first plating layer is, for example, 1 (μm) to 2 (μm). Further, the second plating layer is, for example, a tin (Sn) metal material or an alloy material containing tin (Sn) as a main component. The thickness of the second plating layer is, for example, 1 (μm) to 2 (μm).
 外部端子7の厚みは、例えば、0.1(mm)~0.15(mm)である。厚みは、積層型コンデンサ10の大きさまたは用途等に応じて振動音が低減するように適宜に設定される。 The thickness of the external terminal 7 is, for example, 0.1 (mm) to 0.15 (mm). The thickness is appropriately set according to the size or application of the multilayer capacitor 10 so that vibration noise is reduced.
 例えば、外部端子7は、厚みが、0.1(mm)よりも薄くなると、剛性が小さくなり、積層型コンデンサ本体で発生した歪みによる振動を吸収しやすくなるが、基板9に実装した場合に実装安定性が悪くなる。なお、外部端子7は、外部電極3に接合されていない部分が歪みによる振動を吸収することになる。 For example, if the thickness of the external terminal 7 is thinner than 0.1 (mm), the rigidity is reduced and vibration due to distortion generated in the multilayer capacitor body is easily absorbed. Mounting stability is deteriorated. In the external terminal 7, a portion not joined to the external electrode 3 absorbs vibration due to distortion.
 逆に、外部端子7は、厚みが、0.15(mm)よりも厚くなると、剛性が大きくなり、積層型コンデンサ本体で発生した歪みによる振動を吸収しにくくなる。このように、積層型コンデンサ10は、外部端子7の厚みが振動音の低減と実装安定性とを考慮して設定される。 Conversely, when the thickness of the external terminal 7 is greater than 0.15 (mm), the rigidity is increased and it is difficult to absorb vibration due to distortion generated in the multilayer capacitor body. As described above, in the multilayer capacitor 10, the thickness of the external terminal 7 is set in consideration of reduction of vibration noise and mounting stability.
 ここで、本実施の形態に係る積層型コンデンサ10の実装構造体について説明する。 Here, the mounting structure of the multilayer capacitor 10 according to the present embodiment will be described.
 図5(a)は、積層型コンデンサ10を基板9に実装した状態を示しており、図5(b)は、積層型コンデンサ10を基板9に実装した状態を側面から視た側面図である。 5A shows a state in which the multilayer capacitor 10 is mounted on the substrate 9, and FIG. 5B is a side view of the state in which the multilayer capacitor 10 is mounted on the substrate 9, as viewed from the side. .
 積層型コンデンサ10は、導電性接合材、例えば、はんだ11を介して回路基板(以下、基板9という)上に実装される。基板9は、例えば、ノートパソコン、スマートフォンまたは携帯電話等に用いられるものである。基板9は、例えば、表面には積層型コンデンサ10が電気的に接続される電気回路が形成されている。なお、基板9は、表面の絶縁層を省略して示している。 The multilayer capacitor 10 is mounted on a circuit board (hereinafter, referred to as a board 9) via a conductive bonding material, for example, a solder 11. The board | substrate 9 is used for a notebook personal computer, a smart phone, a mobile phone, etc., for example. The substrate 9 has, for example, an electric circuit on the surface where the multilayer capacitor 10 is electrically connected. The substrate 9 is shown with the insulating layer on the surface omitted.
 また、基板9は、図5に示すように、例えば、積層型コンデンサ10の実装面には基板電極9aおよび基板電極9bが設けられており、基板電極9aから配線(図示せず)が延び、また、基板電極9bから配線(図示せず)が延びている。 In addition, as shown in FIG. 5, the substrate 9 is provided with, for example, a substrate electrode 9a and a substrate electrode 9b on the mounting surface of the multilayer capacitor 10, and wiring (not shown) extends from the substrate electrode 9a. Further, wiring (not shown) extends from the substrate electrode 9b.
 積層型コンデンサ10は、第1の外部端子7aが基板電極9aに、例えば、はんだ11を介してはんだ接合され、また、第2の外部端子7bが基板電極9bに、例えば、はんだ11を介してはんだ接合されている。積層型コンデンサ10は、第1の面4aが基板9の実装面に対向して配置されている。はんだ接合は、例えば、基板電極9aおよび基板電極9b上に印刷したはんだ材料によって行なう。 In the multilayer capacitor 10, the first external terminal 7 a is soldered to the substrate electrode 9 a, for example, via solder 11, and the second external terminal 7 b is connected to the substrate electrode 9 b, for example, via solder 11. Soldered. The multilayer capacitor 10 is arranged such that the first surface 4 a faces the mounting surface of the substrate 9. Solder joining is performed by, for example, a solder material printed on the substrate electrode 9a and the substrate electrode 9b.
 図5に示すように、第1の外部端子7aと基板電極9aとは、第1の基板接続部7a1の下面に配置されたはんだ11を介して接合され、また、第2の外部端子7bと基板電極9bとは、第2の基板接続部7b1の下面に配置されたはんだ11を介して接合される。 As shown in FIG. 5, the first external terminal 7a and the substrate electrode 9a are joined via the solder 11 disposed on the lower surface of the first substrate connection portion 7a1, and the second external terminal 7b The substrate electrode 9b is joined via the solder 11 disposed on the lower surface of the second substrate connection portion 7b1.
 また、使用するはんだ材料は、外部端子7との濡れ性がよいものであれば特に限定されない。はんだ材料は、例えば、Sn-Ag-Cu系またはSn-Sb系のはんだ等を用いることができる。 Also, the solder material to be used is not particularly limited as long as it has good wettability with the external terminal 7. As the solder material, for example, Sn—Ag—Cu-based or Sn—Sb-based solder can be used.
 例えば、積層型コンデンサは、誘電体層としてチタン酸バリウム(BaTiO)、等を主成分として用いており、交流電圧が印加されると、電歪効果により交流電圧の大きさに応じて誘電体層に歪みが発生して振動する。積層型コンデンサは、振動が基板に伝播し、伝播した振動によって振動音を発生させる。基板の振動周波数が可聴周波数帯域である場合には、可聴音が基板から発生する。 For example, a multilayer capacitor uses barium titanate (BaTiO 3 ) or the like as a main component as a dielectric layer. When an AC voltage is applied, a dielectric is formed according to the magnitude of the AC voltage due to an electrostrictive effect. The layer is distorted and vibrates. In the multilayer capacitor, vibration propagates to the substrate, and vibration noise is generated by the propagated vibration. When the vibration frequency of the substrate is in an audible frequency band, an audible sound is generated from the substrate.
 従来の積層型コンデンサは、一対の外部電極が一対の端面に設けられている。また、従来の基板の基板電極は、一対の端面に設けられた一対の外部電極に合わせて積層型コンデンサの積層体の長手方向の位置に配置されている。一方、積層型コンデンサは、振動音を低減するために、一対の外部電極が積層体の一対の側面の中央部に設けられることがある。このような積層型コンデンサは、一対の外部電極を一対の側面の中央部に設けて音鳴きを低減しているものの、一対の外部電極に合わせて基板電極を積層型コンデンサの積層体の短手方向の位置に配置しなければならず、従来の基板の基板電極の配置を採用することができない。したがって、基板電極は、一対の外部電極に合わせて積層型コンデンサの積層体の短手方向の位置に配置を変更しなければならない。 A conventional multilayer capacitor has a pair of external electrodes on a pair of end faces. Moreover, the substrate electrode of the conventional board | substrate is arrange | positioned in the position of the longitudinal direction of the laminated body of a multilayer capacitor according to a pair of external electrode provided in a pair of end surface. On the other hand, in the multilayer capacitor, a pair of external electrodes may be provided at the center of a pair of side surfaces of the multilayer body in order to reduce vibration noise. In such a multilayer capacitor, although a pair of external electrodes are provided at the center of a pair of side surfaces to reduce noise, the substrate electrode is aligned with the pair of external electrodes and the short side of the multilayer capacitor multilayer body. It must be arranged at a position in the direction, and the conventional arrangement of the substrate electrode of the substrate cannot be adopted. Therefore, the arrangement of the substrate electrodes must be changed to the position in the short direction of the multilayer capacitor multilayer body in accordance with the pair of external electrodes.
 しかしながら、積層型コンデンサ10は、一対の外部電極3が一対の側面に設けられている。そして、第1の外部端子7aは、第1の基板接続部7a1が積層体1の長手方向の第1の端面4c側に第1の面4aに隙間を介して対向して配置されている。また、第2の外部端子7bは、第2の基板接続部7b1が積層体1の長手方向の第2の端面4d側に第1の面4aに隙間を介して対向して配置されている。 However, the multilayer capacitor 10 is provided with a pair of external electrodes 3 on a pair of side surfaces. In the first external terminal 7a, the first substrate connecting portion 7a1 is disposed on the first end surface 4c side in the longitudinal direction of the multilayer body 1 so as to face the first surface 4a via a gap. In addition, the second external terminal 7 b is arranged such that the second substrate connecting portion 7 b 1 is opposed to the first surface 4 a with a gap on the second end surface 4 d side in the longitudinal direction of the multilayer body 1.
 このように、積層型コンデンサ10は、第1の基板接続部7a1および第2の基板接続部7b1がそれぞれ積層体1の長手方向に配置され、基板電極9aと第1の基板接続部7a1が接合され、基板電極9bと第2の基板接続部7b1が接合されることになる。したがって、積層型コンデンサ10は、従来の一対の端面に一対の外部電極を有する積層型コンデンサと同じ基板電極の配置を採用することができる。このように、積層型コンデンサ10は、基板の基板電極の配置を変えることなく、音鳴きを低減することができる。 As described above, in the multilayer capacitor 10, the first substrate connection portion 7a1 and the second substrate connection portion 7b1 are arranged in the longitudinal direction of the multilayer body 1, and the substrate electrode 9a and the first substrate connection portion 7a1 are joined. Then, the substrate electrode 9b and the second substrate connecting portion 7b1 are joined. Therefore, the multilayer capacitor 10 can employ the same substrate electrode arrangement as a conventional multilayer capacitor having a pair of external electrodes on a pair of end faces. Thus, the multilayer capacitor 10 can reduce noise without changing the arrangement of the substrate electrodes of the substrate.
 ここで、図1に示す積層型コンデンサ10の製造方法の一例を説明する。 Here, an example of a method for manufacturing the multilayer capacitor 10 shown in FIG. 1 will be described.
 複数の第1および第2のセラミックグリーンシートを準備する。第1のセラミックグリーンシートは、第1の内部電極2aを形成するものである。また、第2のセラミックグリーンシートは第2の内部電極2bを形成するものである。 Prepare a plurality of first and second ceramic green sheets. The first ceramic green sheet forms the first internal electrode 2a. The second ceramic green sheet forms the second internal electrode 2b.
 複数の第1のセラミックグリーンシートは、セラミックグリーンシート上に、第1の内部電極2aの導体ペースト層を第1の内部電極2a用の導体ペーストを用いて形成する。なお、第1のセラミックグリーンシートは、多数個の積層型コンデンサ本体を得るために、1枚のセラミックグリーンシート内に第1の内部電極2aが複数個形成される。 The plurality of first ceramic green sheets are formed on the ceramic green sheet by using the conductive paste layer for the first internal electrode 2a as the conductive paste layer for the first internal electrode 2a. In the first ceramic green sheet, in order to obtain a large number of multilayer capacitor bodies, a plurality of first internal electrodes 2a are formed in one ceramic green sheet.
 また、複数の第2のセラミックグリーンシートは、セラミックグリーンシート上に、第2の内部電極2bの導体ペースト層を第2の内部電極2b用の導体ペーストを用いて形成する。なお、第2のセラミックグリーンシートには、多数個の積層型コンデンサ本体を得るために、1枚のセラミックグリーンシート内に第2の内部電極2bが複数個形成される。 Further, the plurality of second ceramic green sheets are formed on the ceramic green sheet by using the conductive paste layer for the second internal electrode 2b using the conductive paste for the second internal electrode 2b. In the second ceramic green sheet, in order to obtain a large number of multilayer capacitor bodies, a plurality of second internal electrodes 2b are formed in one ceramic green sheet.
 上述の第1の内部電極2aおよび第2の内部電極2bの導体ペースト層は、セラミックグリーンシート上に、例えば、それぞれの導体ペーストを所定のパターン形状でスクリーン印刷法等を用いて形成される。 The conductive paste layers of the first internal electrode 2a and the second internal electrode 2b described above are formed on the ceramic green sheet, for example, using a screen printing method or the like in a predetermined pattern shape for each conductive paste.
 セラミックグリーンシートの材料は、例えば、チタン酸バリウム(BaTiO)、チタン酸カルシウム(CaTiO)、チタン酸ストロンチウム(SrTiO)またはジルコン酸カルシム(CaZrO)等の誘電体セラミックスを主成分とするものである。副成分として、例えば、Mn化合物、Fe化合物、Cr化合物、Co化合物またはNi化合物等が添加されたものであってもよい。 The material of the ceramic green sheet is mainly composed of dielectric ceramics such as barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium zirconate (CaZrO 3 ). Is. For example, a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound may be added as the accessory component.
 第1および第2のセラミックグリーンシートは、誘電体セラミックスの原料粉末および有機バインダに適当な有機溶剤等を添加して混合することによって泥漿状のセラミックスラリーを作製して、ドクターブレード法等を用いてセラミックスラリーを成形することによって得られる。 The first and second ceramic green sheets are produced by adding a suitable organic solvent or the like to the dielectric ceramic raw material powder and the organic binder and mixing them, and using a doctor blade method or the like. Obtained by forming a ceramic slurry.
 第1の内部電極2a用および第2の内部電極2b用の導体ペーストは、上述したそれぞれの内部電極2の導体材料(金属材料)の粉末に添加剤(誘電体材料)、バインダ、溶剤、分散剤等を加えて混練することで作製される。 The conductive paste for the first internal electrode 2a and the second internal electrode 2b is formed by adding an additive (dielectric material), binder, solvent, dispersion to the above-described conductive material (metal material) powder of the internal electrode 2. It is prepared by adding an agent and kneading.
 セラミック材料の積層体1は、第1のセラミックグリーンシートと第2のセラミックグリーンシートとを交互に積層して、内部電極2を形成していないセラミックグリーンシートを積層方向の最外層にそれぞれ積層することによって作製する。 The laminated body 1 of ceramic materials is formed by alternately laminating first ceramic green sheets and second ceramic green sheets, and laminating ceramic green sheets not forming the internal electrodes 2 on the outermost layer in the laminating direction. To make.
 このように、複数の第1および第2のセラミックグリーンシートが積層された積層体は、プレスして一体化することによって、多数個の生積層体を含む大型の生積層体となる。この大型の生積層体を切断することによって、図1に示す積層型コンデンサ本体の積層体1となる生積層体を得ることができる。大型の生積層体の切断は、例えば、ダイシングブレード等を用いて行なうことができる。 As described above, a laminated body in which a plurality of first and second ceramic green sheets are laminated becomes a large-sized raw laminated body including a large number of raw laminated bodies by pressing and integrating them. By cutting this large green laminate, a green laminate that becomes the multilayer body 1 of the multilayer capacitor body shown in FIG. 1 can be obtained. The large green laminate can be cut using, for example, a dicing blade.
 そして、積層体1は、生積層体を、例えば、800(℃)~1300(℃)で焼成することによって得ることができる。焼成することによって、複数の第1および第2のセラミックグリーンシートが誘電体層1aとなる。第1の内部電極2aの導体ペースト層は、第1の内部電極2aとなる。第2の内部電極2bの導体ペースト層は、第2の内部電極2bとなる。また、積層体1は、例えば、バレル研磨等の研磨手段を用いて角部または辺部(稜線部)を丸められる。積層体1は、角部または辺部を丸めることによって角部または辺部が欠けにくいものになる。 The laminate 1 can be obtained by firing the green laminate at, for example, 800 (° C.) to 1300 (° C.). By firing, the plurality of first and second ceramic green sheets become the dielectric layer 1a. The conductor paste layer of the first internal electrode 2a becomes the first internal electrode 2a. The conductor paste layer of the second internal electrode 2b becomes the second internal electrode 2b. Moreover, the laminated body 1 is rounded a corner | angular part or a side part (ridgeline part) using grinding | polishing means, such as barrel grinding | polishing, for example. The laminated body 1 is less likely to lack corners or sides by rounding the corners or sides.
 ここで、一対の外部電極3(第1の外部電極3aおよび第2の外部電極3b)の製造方法についての一例を説明する。 Here, an example of a method for manufacturing the pair of external electrodes 3 (the first external electrode 3a and the second external electrode 3b) will be described.
 一対の下地電極5は、下地電極5となる導電性ペーストが第1の側面4e(第2の側面4f)、第1の面4aおよび第2の面4bにそれぞれ設けられる。 In the pair of base electrodes 5, the conductive paste to be the base electrode 5 is provided on the first side surface 4e (second side surface 4f), the first surface 4a, and the second surface 4b, respectively.
 具体的には、下地電極5となる導電性ペーストは、ローラ転写法を用いて、第1の側面4eおよび第2の側面4fに転写される。導電性ペーストは、第1の側面4e(第2の側面4f)に設けられるとともに、第1の面4aおよび第2の面4bに延在するように設けられる。なお、第1の面延在部3a2(第1の面延在部3b2)および第2の面延在部3b3(第2の面延在部3b3)は、転写された下地電極5の形状が反映されることになる。 Specifically, the conductive paste to be the base electrode 5 is transferred to the first side face 4e and the second side face 4f by using a roller transfer method. The conductive paste is provided on the first side surface 4e (second side surface 4f) and is provided so as to extend to the first surface 4a and the second surface 4b. The first surface extension portion 3a2 (first surface extension portion 3b2) and the second surface extension portion 3b3 (second surface extension portion 3b3) have the shape of the transferred base electrode 5 Will be reflected.
 転写された導電性ペーストは、焼結することによって下地電極5になる。さらに、めっき層6は、下地電極5を覆うように下地電極5の表面に設けられる。めっき層6は、例えば、電解めっき法等を用いて、下地電極5の表面に形成される。また、下地電極5用の導電ペーストは、上述した下地電極5の金属材料の粉末にバインダ、溶剤、分散剤等を加えて混練することで作製される。 The transferred conductive paste becomes the base electrode 5 by sintering. Further, the plating layer 6 is provided on the surface of the base electrode 5 so as to cover the base electrode 5. The plating layer 6 is formed on the surface of the base electrode 5 using, for example, an electrolytic plating method. In addition, the conductive paste for the base electrode 5 is prepared by adding a binder, a solvent, a dispersant and the like to the powder of the metal material of the base electrode 5 described above and kneading.
 次に、一対の外部端子7(第1の外部端子7aおよび第2の外部端子7b)の製造方法の一例を説明する。 Next, an example of a manufacturing method of the pair of external terminals 7 (first external terminal 7a and second external terminal 7b) will be described.
 外部端子7は、帯状金属板を用いて製造する。帯状金属板の厚みは、例えば、0.1(mm)~0.15(mm)であり、長さは、100(mm)~250(mm)である。帯状金属板は、例えば、ステンレス合金である。 The external terminal 7 is manufactured using a strip metal plate. The thickness of the band-shaped metal plate is, for example, 0.1 (mm) to 0.15 (mm), and the length is 100 (mm) to 250 (mm). The strip metal plate is, for example, a stainless alloy.
 図6(a)に示すように、第1の外部端子7aとなる第1の外部端子7aaおよび第2の外部端子7bとなる第2の外部端子7bbは、互いに対向するように帯状金属板に配置される。第1の外部端子7aaおよび第2の外部端子7bbは、帯状金属板に対して、それぞれのパターン形状に合わせて、例えば、プレス打ち抜き加工法を用いて打ち抜き加工される。 As shown in FIG. 6A, the first external terminal 7aa to be the first external terminal 7a and the second external terminal 7bb to be the second external terminal 7b are formed on the belt-shaped metal plate so as to face each other. Be placed. The first external terminal 7aa and the second external terminal 7bb are punched by using, for example, a press punching method in accordance with the pattern shape of the band-shaped metal plate.
 プレス打ち抜き加工によって、図6(a)に示すように、第1の外部端子7aaと第2の外部端子7bbの外部端子対12aが帯状金属板に複数個設けられる。リードフレーム12は、帯状金属板に複数の外部端子対12aが設けられたものである。このように、積層型コンデンサ10は、リードフレーム12を用いることによって効率よく作製することができる。 As shown in FIG. 6A, a plurality of external terminal pairs 12a of the first external terminal 7aa and the second external terminal 7bb are provided on the belt-shaped metal plate by press punching. The lead frame 12 is a strip-shaped metal plate provided with a plurality of external terminal pairs 12a. Thus, the multilayer capacitor 10 can be efficiently manufactured by using the lead frame 12.
 リードフレーム12は、例えば、めっき加工法を用いて複数個の外部端子対12aにめっき層を形成する。 The lead frame 12 forms a plating layer on the plurality of external terminal pairs 12a using, for example, a plating method.
 また、上述のように、リードフレーム12は、打ち抜き加工を行なった後にめっき加工を行なっている。これに限定されず、リードフレーム12は、めっき加工を行なった後に打ち抜き加工を行なってもよい。リードフレーム12は、加工の順番が一対の外部端子7の形状等を考慮して適宜に設定される。 Further, as described above, the lead frame 12 is plated after being punched. However, the lead frame 12 may be punched after plating. In the lead frame 12, the processing order is appropriately set in consideration of the shape of the pair of external terminals 7 and the like.
 次に、図6(b)に示すように、積層型コンデンサ本体は、例えば、吸引ノズルを備えた自動実装機を用いて、第1の外部端子7aaおよび第2の外部端子7bb上に搭載される。 Next, as shown in FIG. 6B, the multilayer capacitor body is mounted on the first external terminal 7aa and the second external terminal 7bb using, for example, an automatic mounting machine equipped with a suction nozzle. The
 そして、積層型コンデンサ本体を搭載した後、図6(c)に示すように、例えば、レーザスポット溶接を用いて、第1の外部端子7aaは第1の外部電極3aに接合され、第2の外部端子7bbは第2の外部電極3bに接合される。このように、一対の外部電極3と一対の外部端子7との接合に溶接を用いることによって、接合工程は非常に簡略化され、量産性に優れた工程になる。 After mounting the multilayer capacitor body, as shown in FIG. 6C, the first external terminal 7aa is joined to the first external electrode 3a by using, for example, laser spot welding, The external terminal 7bb is joined to the second external electrode 3b. Thus, by using welding for joining the pair of external electrodes 3 and the pair of external terminals 7, the joining process is greatly simplified and the process is excellent in mass productivity.
 また、積層型コンデンサ10は、はんだを介して基板9に実装されるが、外部電極3と外部端子7とを溶接を用いて接合すると、外部電極3と外部端子7との接合部は、はんだ付け温度の影響を受けにくくなる。したがって、積層型コンデンサ10は、接合部の信頼性が向上する。 The multilayer capacitor 10 is mounted on the substrate 9 via solder. When the external electrode 3 and the external terminal 7 are joined together by welding, the joint between the external electrode 3 and the external terminal 7 is soldered. It is less susceptible to the temperature applied. Therefore, in the multilayer capacitor 10, the reliability of the joint is improved.
 積層型コンデンサ10は、例えば、第1の電極接続部7a2および第2の電極接続部7b2と一対の外部電極3とをはんだを介して接合する場合には、はんだが下方に流動しやすく、接合性が低下しやすくなる。一方、第1の電極接続部7a2と第1の外部電極3aとを溶接を用いて接合し、第2の電極接続部7b2と第2の外部電極3bとを溶接を用いて接合することによって、積層型コンデンサ10は、外部電極3と外部端子7との接合性を高めることができる。 In the multilayer capacitor 10, for example, when the first electrode connection portion 7a2 and the second electrode connection portion 7b2 are joined to the pair of external electrodes 3 via solder, the solder easily flows downward, It becomes easy to fall. On the other hand, by joining the first electrode connecting portion 7a2 and the first external electrode 3a using welding, and joining the second electrode connecting portion 7b2 and the second external electrode 3b using welding, The multilayer capacitor 10 can improve the bondability between the external electrode 3 and the external terminal 7.
 また、溶接を用いる接合は、例えば、アークスポット溶接またはレーザスポット溶接等のスポット溶接を用いることができる。レーザスポット溶接は、例えば、第1の電極接続部7a2および第2の電極接続部7b2に対してYAGレーザ等のエネルギービームをスポット的に照射するものである。レーザスポット溶接によって、第1の電極接続部7a2は、第1の外部電極3aに接合される。また、第2の電極接続部7b2は、第2の外部電極3bに接合される。第1の電極接続部7a2および第2の電極接続部7b2は、エネルギービームがスポット的に照射されると、局所的に昇温する。例えば、外部端子7のステンレス合金の溶融温度の1400(℃)~1450(℃)になると、第1の電極接続部7a2および第2の電極接続部7b2は、一部が溶融して、一対の外部電極3と接合することになる。 Further, for the joining using welding, for example, spot welding such as arc spot welding or laser spot welding can be used. In laser spot welding, for example, an energy beam such as a YAG laser is spot-irradiated to the first electrode connection portion 7a2 and the second electrode connection portion 7b2. The first electrode connection portion 7a2 is joined to the first external electrode 3a by laser spot welding. The second electrode connection portion 7b2 is joined to the second external electrode 3b. The first electrode connecting portion 7a2 and the second electrode connecting portion 7b2 are locally heated when the energy beam is applied in a spot manner. For example, when the melting temperature of the stainless alloy of the external terminal 7 reaches 1400 (° C.) to 1450 (° C.), the first electrode connecting portion 7a2 and the second electrode connecting portion 7b2 are partially melted, It joins with the external electrode 3.
 また、積層型コンデンサ10は、めっき層6に電解めっき法で形成したニッケル(Ni)めっき層を用い、また、外部端子7にステンレス合金を用いると、ニッケル(Ni)めっき層およびステンレス合金の溶融温度が類似しており、外部端子7と外部電極3との接合性を向上させることができる。このように、積層型コンデンサ10は、外部電極3と外部端子7との接合において、めっき層6および外部端子7に対して互いの溶融温度が類似した材料を用いることによって、溶接部7a3および溶接部7b3の接合領域が制御しやすくなる。 In the multilayer capacitor 10, when a nickel (Ni) plating layer formed by an electrolytic plating method is used for the plating layer 6 and a stainless alloy is used for the external terminal 7, the nickel (Ni) plating layer and the stainless alloy are melted. The temperatures are similar, and the bondability between the external terminal 7 and the external electrode 3 can be improved. As described above, the multilayer capacitor 10 uses the material having a similar melting temperature to the plating layer 6 and the external terminal 7 in joining the external electrode 3 and the external terminal 7, so that the welded portion 7 a 3 and the welded portion 7 are welded. It becomes easy to control the joining region of the portion 7b3.
 積層型コンデンサ本体は、溶接を用いて、第1の外部電極3aに第1の外部端子7aaを取り付け、また、第2の外部電極3bに第2の外部端子7bbを取り付ける。 The multilayer capacitor body has the first external terminal 7aa attached to the first external electrode 3a and the second external terminal 7bb attached to the second external electrode 3b by welding.
 次に、図6(c)に示すように、リードフレーム12は、第1の切断線S1および第2の切断線S2を設定し、第1の切断線S1および第2の切断線S2に対して切断加工を行なう。外部端子対12aは、例えば、切断金型を用いて、リードフレーム12から切り離される。これによって、図6(d)に示すように、積層型コンデンサ10は、リードフレーム12から複数個得られる。なお、図6(c)において、第1の切断線S1および第2の切断線S2は、点線によって示している。 Next, as shown in FIG. 6C, the lead frame 12 sets the first cutting line S1 and the second cutting line S2, and with respect to the first cutting line S1 and the second cutting line S2. Cutting. The external terminal pair 12a is separated from the lead frame 12 using, for example, a cutting die. As a result, a plurality of multilayer capacitors 10 are obtained from the lead frame 12 as shown in FIG. In FIG. 6C, the first cutting line S1 and the second cutting line S2 are indicated by dotted lines.
 上述のように、積層型コンデンサ10は、リードフレーム12を用いることによって、効率よく作製することができる。 As described above, the multilayer capacitor 10 can be efficiently manufactured by using the lead frame 12.
 また、積層型コンデンサ10は、外部端子7が溶接を用いて外部電極3に接合されており、外部端子7を基板9上にはんだ付けしても、はんだ付けの加熱によって外部端子7が外部電極3から離脱しにくい。 In the multilayer capacitor 10, the external terminals 7 are joined to the external electrodes 3 by welding. Even if the external terminals 7 are soldered onto the substrate 9, the external terminals 7 are externally connected by heating of the soldering. Difficult to leave 3
 また、積層型コンデンサ10Bは、図12および図13に示すように、第1の基板接続部7a1に第1の面4a側(Z方向の正側)に向かって突出する突出部8を有し、第2の基板接続部7b1に第1の面4a側(Z方向の正側)に向かって突出する突出部8を有している。 In addition, as shown in FIGS. 12 and 13, the multilayer capacitor 10 </ b> B has a protruding portion 8 that protrudes toward the first surface 4 a side (positive side in the Z direction) on the first substrate connecting portion 7 a 1. The second substrate connecting portion 7b1 has a protruding portion 8 that protrudes toward the first surface 4a side (the positive side in the Z direction).
 例えば、第1の面4aの端部は、第1の基板接続部7a1側に傾いて第1の基板接続部7a1に接触する虞がある。また、第1の基板接続部7a1は、第1の面4a側に傾いて第1の面4aに接触する虞がある。第1の面4aの端部は、第2の基板接続部7b1側に傾いて第2の基板接続部7b1に接触する虞がある。また、第2の基板接続部7b1は、第1の面4a側に傾いて第1の面4aに接触する虞がある。このように、第1の面4aと第1の基板接続部7a1とが接触した状態、あるいは、第1の面4aと第2の基板接続部7b1とが接触した状態なると、積層型コンデンサは、振動が基板9に直接伝わり、音鳴きが発生しやすくなる。 For example, the end portion of the first surface 4a may be inclined toward the first substrate connecting portion 7a1 and come into contact with the first substrate connecting portion 7a1. Further, the first board connecting portion 7a1 may be inclined toward the first surface 4a and come into contact with the first surface 4a. The end portion of the first surface 4a may be inclined toward the second substrate connection portion 7b1 and come into contact with the second substrate connection portion 7b1. Further, the second board connecting portion 7b1 may be inclined toward the first surface 4a and come into contact with the first surface 4a. As described above, when the first surface 4a and the first substrate connecting portion 7a1 are in contact with each other, or when the first surface 4a and the second substrate connecting portion 7b1 are in contact with each other, the multilayer capacitor is The vibration is directly transmitted to the substrate 9 and it is easy for noise to occur.
 しかしながら、第1の面4aの端部が第1の基板接続部7a1側に、あるいは、第1の基板接続部7a1が第1の面4a側に傾いたとしても、積層型コンデンサ10は、突出部8を有しており、第1の面4aが第1の基板接続部7a1に点接触し、第1の基板接続部7a1との接触面積が小さい。また、第1の面4aの端部が第2の基板接続部7b1側に、あるいは、第2の基板接続部7b1が第1の面4a側に傾いたとしても、積層型コンデンサ10は、突出部8を有しており、第1の面4aが第2の基板接続部7b1に点接触し、第2の基板接続部7b1との接触面積が小さい。したがって、積層型コンデンサ10Bは、振動が基板9に直接伝わりにくくなる。 However, even if the end portion of the first surface 4a is inclined toward the first substrate connection portion 7a1 or the first substrate connection portion 7a1 is inclined toward the first surface 4a, the multilayer capacitor 10 does not protrude. The first surface 4a is in point contact with the first substrate connecting portion 7a1, and the contact area with the first substrate connecting portion 7a1 is small. Further, even if the end of the first surface 4a is inclined toward the second substrate connecting portion 7b1 or the second substrate connecting portion 7b1 is inclined toward the first surface 4a, the multilayer capacitor 10 does not protrude. The first surface 4a is in point contact with the second substrate connecting portion 7b1, and the contact area with the second substrate connecting portion 7b1 is small. Therefore, the multilayer capacitor 10B is less likely to transmit vibration directly to the substrate 9.
 積層型コンデンサ10Bは、突出部8が第1の基板接続部7a1および第2の基板接続部7b1にそれぞれ2個ずつ設けられている。これに限定されず、突出部8の個数は、第1の基板接続部7a1および第2の基板接続部7b1の大きさ等に応じて1個または3個以上であってもよい。 In the multilayer capacitor 10B, two protruding portions 8 are provided on each of the first substrate connecting portion 7a1 and the second substrate connecting portion 7b1. However, the number of the protrusions 8 may be one or three or more according to the size of the first substrate connection portion 7a1 and the second substrate connection portion 7b1.
 本開示は、上述の積層型コンデンサ10および積層型コンデンサ10Bに限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更および改良等が可能である。他の実施の形態について以下に説明する。なお、他の実施の形態に係る積層型コンデンサのうち、実施の形態1に係る積層型コンデンサ10と同じ部分については、同一の符号を付して適宜説明を省略する。 The present disclosure is not limited to the multilayer capacitor 10 and the multilayer capacitor 10B described above, and various modifications and improvements can be made without departing from the gist of the present disclosure. Other embodiments will be described below. Note that, among the multilayer capacitors according to other embodiments, the same portions as those of the multilayer capacitor 10 according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
 <実施の形態2>
 本開示の実施の形態2に係る積層型コンデンサ10Aについて図面を参照しながら説明する。
<Embodiment 2>
A multilayer capacitor 10A according to Embodiment 2 of the present disclosure will be described with reference to the drawings.
 積層型コンデンサ10Aは、一対の外部端子70が第1の外部端子7Aおよび第2の外部端子7Bを含んでおり、積層型コンデンサ10の一対の外部端子7とは形状が異なるものの、材料等は同じものを用いている。なお、積層型コンデンサ10Aは、一対の外部端子70の形状以外の構成については積層型コンデンサ10と同じである。 In the multilayer capacitor 10A, a pair of external terminals 70 includes a first external terminal 7A and a second external terminal 7B. Although the shape is different from the pair of external terminals 7 of the multilayer capacitor 10, the materials and the like are The same thing is used. The multilayer capacitor 10A is the same as the multilayer capacitor 10 except for the shape of the pair of external terminals 70.
 第1の外部端子7Aは、図7および図8に示すように、第1の基板接続部7A1と第1の電極接続部7A2とを含んでいる。第1の基板接続部7A1は、積層体1の長手方向の第1の端面4c側(X方向の負側)に第1の面4aに隙間を介して対向するように配置された矩形状の板状体である。第1の電極接続部7A2は、第1の基板接続部7A1から積層体1の長手方向に沿って第1の外部電極3aの第1の面延在部3a2に向かって延びており、延びた部分の端部が第1の外部電極3aの第1の面延在部3a2に接合されている。このように、第1の電極接続部7A2は、第1の外部電極3aの第1の面延在部3a2に重なるように第2の端面4dに向かって延びており、第1の外部電極3aの第1の面延在部3a2に接合されている。 As shown in FIGS. 7 and 8, the first external terminal 7A includes a first substrate connecting portion 7A1 and a first electrode connecting portion 7A2. The first substrate connection portion 7A1 is a rectangular shape disposed on the first end surface 4c side (negative side in the X direction) in the longitudinal direction of the multilayer body 1 so as to face the first surface 4a via a gap. It is a plate-like body. The first electrode connection portion 7A2 extends from the first substrate connection portion 7A1 along the longitudinal direction of the multilayer body 1 toward the first surface extension portion 3a2 of the first external electrode 3a. The end of the portion is joined to the first surface extension 3a2 of the first external electrode 3a. Thus, the first electrode connection portion 7A2 extends toward the second end surface 4d so as to overlap the first surface extension portion 3a2 of the first external electrode 3a, and the first external electrode 3a. The first surface extending portion 3a2 is joined.
 また、第2の外部端子7Bは、図7および図8に示すように、第2の基板接続部7B1と第2の電極接続部7B2とを含んでいる。第2の基板接続部7B1は、積層型コンデンサ10Aの積層体1の長手方向の第2の端面4d側(X方向の正側)に第1の面4aに隙間を介して対向するように配置された矩形状の板状体である。第2の電極接続部7B2は、第2の基板接続部7B1から積層体1の長手方向に沿って第2の外部電極3bの第1の面延在部3b2に向かって延びており、延びた部分の端部が第2の外部電極3bの第1の面延在部3b2に接合されている。このように、第2の電極接続部7B2は、第2の外部電極3bの第1の面延在部3b2に重なるように第1の端面4cに向かって延びており、第2の外部電極3bの第1の面延在部3b2に接合されている。 Further, as shown in FIGS. 7 and 8, the second external terminal 7B includes a second substrate connecting portion 7B1 and a second electrode connecting portion 7B2. The second substrate connection portion 7B1 is disposed on the second end face 4d side in the longitudinal direction (positive side in the X direction) of the multilayer body 1 of the multilayer capacitor 10A so as to face the first face 4a via a gap. A rectangular plate-shaped body. The second electrode connection portion 7B2 extends from the second substrate connection portion 7B1 along the longitudinal direction of the stacked body 1 toward the first surface extension portion 3b2 of the second external electrode 3b. The end of the portion is joined to the first surface extension 3b2 of the second external electrode 3b. Thus, the second electrode connection portion 7B2 extends toward the first end surface 4c so as to overlap the first surface extension portion 3b2 of the second external electrode 3b, and the second external electrode 3b. The first surface extending portion 3b2 is joined.
 第1の電極接続部7A2は、図9および図10に示すように、端部の第1の面延在部3a2に接合する接合部が第1の外部電極3aの第1の面延在部3a2側に向かって第1の基板接続部7A1の第1の面4a側の面よりも上方(Z方向の正側)に突出している。さらに、第1の電極接続部7A2は、第1の面延在部3a2とは反対の下方の部分に空間部7A4を有している。また、第2の電極接続部7B2は、図9および図10に示すように、端部の第1の面延在部3b2に接合する接合部が第2の外部電極3bの第1の面延在部3b2側に向かって第2の基板接続部7B1の第1の面4a側の面よりも上方(Z方向の正側)に突出している。さらに、第2の電極接続部7B2は、第1の面延在部3b2とは反対の下方の部分に空間部7B4を有している。 As shown in FIGS. 9 and 10, the first electrode connecting portion 7A2 is a first surface extending portion of the first external electrode 3a whose bonding portion is bonded to the first surface extending portion 3a2 at the end. It protrudes upward (the positive side in the Z direction) from the surface on the first surface 4a side of the first substrate connecting portion 7A1 toward the 3a2 side. Furthermore, the first electrode connection portion 7A2 has a space portion 7A4 in a lower portion opposite to the first surface extension portion 3a2. Further, as shown in FIGS. 9 and 10, the second electrode connection portion 7B2 is formed such that the joint portion joined to the first surface extension portion 3b2 at the end is the first surface extension of the second external electrode 3b. It protrudes upward (the positive side in the Z direction) from the surface on the first surface 4a side of the second substrate connection portion 7B1 toward the existing portion 3b2. Further, the second electrode connection portion 7B2 has a space portion 7B4 in a lower portion opposite to the first surface extension portion 3b2.
 積層型コンデンサ10Aにおいて、積層型コンデンサ10と同じように、第1の外部端子7Aは、例えば、はんだ接合または溶接等を用いて、第1の電極接続部7A2で第1の外部電極3aの第1の面延在部3a2に接合される。また、第2の外部端子7Bは、例えば、はんだ接合または溶接等を用いて、第2の電極接続部7B2で第2の外部電極3bの第1の面延在部3b2に接合される。本実施の形態においては、第1の外部端子7Aおよび第2の外部端子7Bは、溶接を用いて第1の外部電極3aおよび第2の外部電極3bに接合されている。 In the multilayer capacitor 10A, as in the multilayer capacitor 10, the first external terminal 7A is connected to the first external electrode 3a at the first electrode connection portion 7A2 by using, for example, soldering or welding. 1 surface extension part 3a2. The second external terminal 7B is joined to the first surface extension portion 3b2 of the second external electrode 3b by the second electrode connection portion 7B2 by using, for example, solder joining or welding. In the present embodiment, the first external terminal 7A and the second external terminal 7B are joined to the first external electrode 3a and the second external electrode 3b by welding.
 第1の電極接続部7A2は、例えば、プレス加工を用いて、深絞りすることによって、第1の面延在部3a2との接合部に対応する領域に、突出する部分および空間部7A4を設けることができる。また、第2の電極接続部7B2は、例えば、プレス加工を用いて、深絞りすることによって、第1の面延在部3b2との接合部に対応する領域に、突出する部分および空間部7B4を設けることができる。 The first electrode connection portion 7A2 is provided with a protruding portion and a space portion 7A4 in a region corresponding to the joint portion with the first surface extension portion 3a2, for example, by deep drawing using press working. be able to. Further, the second electrode connection portion 7B2 is a portion that protrudes into a region corresponding to a joint portion with the first surface extension portion 3b2 and a space portion 7B4 by deep drawing using, for example, pressing. Can be provided.
 このように、第1の電極接続部7A2および第2の電極接続部7B2は、空間部7A4および空間部7B4が側壁部7A5および側壁部7B5で形成されることになる。 Thus, in the first electrode connection portion 7A2 and the second electrode connection portion 7B2, the space portion 7A4 and the space portion 7B4 are formed by the side wall portion 7A5 and the side wall portion 7B5.
 積層型コンデンサ10Aは、図10に示すように、第1の基板接続部7A1が基板電極9aに接合され、第2の基板接続部7B1が基板電極9bに接合されている。また、第1の電極接続部7A2は、第1の基板接続部7A1の長手方向の端部から第1の外部電極3aの第1の面延在部3a2に向かって延びている。また、第2の電極接続部7B2は、第2の基板接続部7B1の長手方向の端部から第2の外部電極3bの第1の面延在部3b2に向かって延びている。 In the multilayer capacitor 10A, as shown in FIG. 10, the first substrate connecting portion 7A1 is bonded to the substrate electrode 9a, and the second substrate connecting portion 7B1 is bonded to the substrate electrode 9b. The first electrode connection portion 7A2 extends from the longitudinal end portion of the first substrate connection portion 7A1 toward the first surface extension portion 3a2 of the first external electrode 3a. The second electrode connection portion 7B2 extends from the longitudinal end portion of the second substrate connection portion 7B1 toward the first surface extension portion 3b2 of the second external electrode 3b.
 第1の面延在部3a2と第1の電極接続部7A2とが接合する接合部および第1の面延在部3b2と第2の電極接続部7B2とが接合する接合部は、第1の基板接続部7A1および第2の基板接続部7B1が基板電極9aおよび基板電極9bにそれぞれ接合されており、第1の面4aの内側に向かう応力が発生しやすい。すなわち、第1の面4aの中央部を中心に回転する応力が溶接部7A3および溶接部7B3に発生しやすくなる。 The joint part where the first surface extension part 3a2 and the first electrode connection part 7A2 are joined and the joint part where the first surface extension part 3b2 and the second electrode connection part 7B2 are joined are the first part. The board connecting portion 7A1 and the second board connecting portion 7B1 are joined to the board electrode 9a and the board electrode 9b, respectively, and stress toward the inside of the first surface 4a is likely to occur. That is, a stress that rotates around the central portion of the first surface 4a is likely to occur in the welded portion 7A3 and the welded portion 7B3.
 しかしながら、第1の電極接続部7A2は、第1の面延在部3a2に接合する接合部が第1の面延在部3a2に向かって第1の基板接続部7A1の第1の面4a側の面よりも上方に突出するとともに第1の面延在部3a2とは反対側に空間部7A4を有している。また、第2の電極接続部7B2は、第1の面延在部3b2に接合する接合部が第1の面延在部3b2に向かって第2の基板接続部7B1の第1の面4a側の面よりも上方に突出するとともに第1の面延在部3b2とは反対側に空間部7B4を有している。 However, the first electrode connection portion 7A2 is such that the joint portion that joins the first surface extension portion 3a2 faces the first surface extension portion 3a2, and the first surface connection portion 7A1 has the first surface 4a side. And a space 7A4 on the side opposite to the first surface extension 3a2. In addition, the second electrode connection portion 7B2 is such that the joint portion that joins the first surface extension portion 3b2 faces the first surface extension portion 3b2 and the first surface 4a side of the second substrate connection portion 7B1. And a space 7B4 on the side opposite to the first surface extension 3b2.
 したがって、積層型コンデンサ10Aは、図7に示すように、絞り加工された部分の側壁部7A5および側壁部7B5で第1の面4aの中央部を中心に回転する応力を緩和することができる。このように、積層型コンデンサ10Aは、溶接部7A3および溶接部7B3に対して捻じれ応力が発生しにくくなり、接合部の信頼性が向上する。 Therefore, as shown in FIG. 7, the multilayer capacitor 10A can relieve the stress that rotates around the central portion of the first surface 4a at the drawn side wall portions 7A5 and 7B5. Thus, in the multilayer capacitor 10A, twisting stress is less likely to occur with respect to the welded portion 7A3 and the welded portion 7B3, and the reliability of the joint portion is improved.
 積層型コンデンサ10Aは、積層型コンデンサ10と同じようにして製造することができる。図11(a)に示すように、第1の外部端子7Aとなる第1の外部端子7Aaおよび第2の外部端子7Bとなる第2の外部端子7Bbは、互いに対向するように帯状金属板に配置される。第1の外部端子7Aaおよび第2の外部端子7Bbは、帯状金属板に対して、それぞれのパターン形状に合わせて、例えば、プレス打ち抜き加工法を用いて打ち抜き加工される。 The multilayer capacitor 10 </ b> A can be manufactured in the same manner as the multilayer capacitor 10. As shown in FIG. 11A, the first external terminal 7Aa to be the first external terminal 7A and the second external terminal 7Bb to be the second external terminal 7B are formed on the band-shaped metal plate so as to face each other. Be placed. The first external terminal 7Aa and the second external terminal 7Bb are punched using, for example, a press punching method in accordance with the pattern shape of the band-shaped metal plate.
 例えば、プレス加工を用いて、深絞りすることによって、第1の電極接続部7A2は、第1の面延在部3a2との接合部を突出させて下方に空間部7A4を設けることができ、また、第2の電極接続部7B2は、第1の面延在部3b2との接合部を突出させて下方に空間部7B4を設けることができる。 For example, by deep drawing using press processing, the first electrode connection portion 7A2 can be provided with a space portion 7A4 below by projecting the joint portion with the first surface extension portion 3a2. In addition, the second electrode connection portion 7B2 can be provided with a space portion 7B4 below by projecting a joint portion with the first surface extension portion 3b2.
 打ち抜き加工およびプレス加工によって、図11(a)に示すように、第1の外部端子7Aaと第2の外部端子7Bbの外部端子対12Aは帯状金属板に複数個設けられる。 As shown in FIG. 11A, a plurality of pairs of external terminals 12A of the first external terminals 7Aa and the second external terminals 7Bb are provided on the belt-shaped metal plate by punching and pressing.
 リードフレーム12は、例えば、めっき加工法を用いて複数個の外部端子対12Aにめっき層を形成する。 The lead frame 12 forms a plating layer on the plurality of external terminal pairs 12A using, for example, a plating method.
 また、上述のように、リードフレーム12は、打ち抜き加工およびプレス加工を行なった後にめっき加工を行なっている。これに限定されず、リードフレーム12は、めっき加工を行なった後に打ち抜き加工およびプレス加工を行なってもよい。リードフレーム12は、加工の順番が一対の外部端子7の形状等を考慮して適宜に設定される。 Further, as described above, the lead frame 12 is subjected to plating after punching and pressing. Without being limited thereto, the lead frame 12 may be punched and pressed after plating. In the lead frame 12, the processing order is appropriately set in consideration of the shape of the pair of external terminals 7 and the like.
 次に、図11(b)に示すように、積層型コンデンサ本体は、例えば、吸引ノズルを備えた自動実装機を用いて、第1の外部端子7Aaおよび第2の外部端子7Bb上に搭載される。 Next, as shown in FIG. 11B, the multilayer capacitor body is mounted on the first external terminal 7Aa and the second external terminal 7Bb by using, for example, an automatic mounting machine having a suction nozzle. The
 そして、積層型コンデンサ本体を搭載した後、図11(c)に示すように、例えば、レーザスポット溶接を用いて、第1の外部端子7Aaは第1の外部電極3aに接合され、第2の外部端子7Bbは第2の外部電極3bに接合される。 After mounting the multilayer capacitor main body, as shown in FIG. 11C, the first external terminal 7Aa is joined to the first external electrode 3a by using, for example, laser spot welding, The external terminal 7Bb is joined to the second external electrode 3b.
 次に、図11(c)に示すように、リードフレーム12は、第1の切断線S1および第2の切断線S2を設定し、第1の切断線S1および第2の切断線S2に対して切断加工を行なう。外部端子対12Aは、例えば、切断金型を用いて、リードフレーム12から切り離される。これによって、図11(d)に示すように、積層型コンデンサ10Aは、リードフレーム12から複数個得られる。 Next, as shown in FIG. 11C, the lead frame 12 sets the first cutting line S1 and the second cutting line S2, and with respect to the first cutting line S1 and the second cutting line S2. Cutting. The external terminal pair 12A is separated from the lead frame 12 using, for example, a cutting die. As a result, as shown in FIG. 11 (d), a plurality of multilayer capacitors 10 A are obtained from the lead frame 12.
 また、積層型コンデンサ10Cは、図14に示すように、第1の基板接続部7a1の領域に第1の面4a側(Z方向の正側)に向かって突出する突出部8Aを有し、また、第2の基板接続部7b1の領域に第1の面4a側(Z方向の正側)に向かって突出する突出部8Aを有していてもよい。 Further, as shown in FIG. 14, the multilayer capacitor 10C has a protruding portion 8A protruding toward the first surface 4a side (positive side in the Z direction) in the region of the first substrate connecting portion 7a1. Moreover, you may have the protrusion part 8A which protrudes toward the 1st surface 4a side (positive side of a Z direction) in the area | region of the 2nd board | substrate connection part 7b1.
 このように、第1の面4aの端部が第1の基板接続部7A1側に、あるいは、第1の基板接続部7A1が第1の面4a側に傾いたとしても、積層型コンデンサ10Cは、突出部8Aを有しており、第1の面4aが第1の基板接続部7A1に点接触し、第1の基板接続部7A1との接触面積が小さい。 As described above, even when the end of the first surface 4a is inclined toward the first substrate connecting portion 7A1 or the first substrate connecting portion 7A1 is inclined toward the first surface 4a, the multilayer capacitor 10C is The first surface 4a is in point contact with the first substrate connecting portion 7A1, and the contact area with the first substrate connecting portion 7A1 is small.
 また、第1の面4aの端部が第2の基板接続部7B1側に、あるいは、第2の基板接続部7B1が第1の面4a側に傾いたとしても、積層型コンデンサ10Cは、突出部8Aを有しており、第1の面4aが第2の基板接続部7B1に点接触し、第2の基板接続部7B1との接触面積が小さい。これによって、積層型コンデンサ10Cは、振動が基板9に直接伝わりにくくなる。 Further, even if the end portion of the first surface 4a is inclined toward the second substrate connecting portion 7B1 or the second substrate connecting portion 7B1 is inclined toward the first surface 4a, the multilayer capacitor 10C is protruded. The first surface 4a is in point contact with the second substrate connecting portion 7B1, and the contact area with the second substrate connecting portion 7B1 is small. As a result, the multilayer capacitor 10 </ b> C is less likely to transmit vibration directly to the substrate 9.
 本開示は、上述の積層型コンデンサ10~10Cに限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更、改良等が可能である。 The present disclosure is not limited to the above-described multilayer capacitors 10 to 10C, and various changes and improvements can be made without departing from the gist of the present disclosure.
1 積層体
1a 誘電体層
2 内部電極
2a 第1の内部電極
2b 第2の内部電極
3 外部電極
3a 第1の外部電極
3b 第2の外部電極
4a 第1の面
4b 第2の面
4c 第1の端面
4d 第2の端面
4e 第1の側面
4f 第2の側面
5 下地電極
6 めっき層
6a 第1のめっき層
6b 第2のめっき層
7、70 外部端子
7a、7A 第1の外部端子
7b、7B 第2の外部端子
7a1、7A1 第1の基板接続部
7a2、7A2 第1の電極接続部
7b1、7B1 第2の基板接続部
7b2、7B2 第2の電極接続部
7a3、7b3、7A3、7B3 溶接部
7A4、7B4 空間部
7A5、7B5 側壁部
8、8A 突出部
9 基板
9a、9b 基板電極
10~10C 積層型コンデンサ
11 はんだ
12 リードフレーム
12a、12A 外部端子対
S1、S2 切断線
DESCRIPTION OF SYMBOLS 1 Laminated body 1a Dielectric layer 2 Internal electrode 2a 1st internal electrode 2b 2nd internal electrode 3 External electrode 3a 1st external electrode 3b 2nd external electrode 4a 1st surface 4b 2nd surface 4c 1st End face 4d second end face 4e first side face 4f second side face 5 ground electrode 6 plating layer 6a first plating layer 6b second plating layer 7, 70 external terminal 7a, 7A first external terminal 7b, 7B Second external terminals 7a1, 7A1 First substrate connecting portions 7a2, 7A2 First electrode connecting portions 7b1, 7B1 Second substrate connecting portions 7b2, 7B2 Second electrode connecting portions 7a3, 7b3, 7A3, 7B3 Welding Part 7A4, 7B4 Space part 7A5, 7B5 Side wall part 8, 8A Projection part 9 Substrate 9a, 9b Substrate electrode 10-10C Multilayer capacitor 11 Solder 12 Lead frame 12a, 12A External terminal pair S1, S2 Cutting line

Claims (5)

  1.  複数の誘電体層が積層された、一対の第1の面および第2の面と、一対の第1の端面および第2の端面と、一対の第1の側面および第2の側面とを有する直方体状の積層体と、前記複数の誘電体層の層間に積層方向に間隔をおいて配置された複数の内部電極と、前記第1の側面および前記第2の側面にそれぞれ配置された、互いに異なる前記内部電極に電気的に接続された第1の外部電極および第2の外部電極と、前記第1の外部電極に接合された第1の外部端子および前記第2の外部電極に接合された第2の外部端子とを備えており、
     前記第1の外部電極および前記第2の外部電極は、前記側面の中央部を含むように配置された側面部と、該側面部から前記第1の面に延在する第1の面延在部および前記第2の面に延在する第2の面延在部とを有し、
     前記第1の外部端子は、前記第1の端面に近接する前記第1の面の部分に隙間を介して対向して配置された板状体の第1の基板接続部および該第1の基板接続部から前記積層体の長手方向に沿って前記第2の端面の方向に向かって延び、延びた部分の端部が前記第1の外部電極の前記第1の面延在部に接合された第1の電極接続部を有し、
     前記第2の外部端子は、前記第2の端面に近接する前記第1の面の部分に隙間を介して対向して配置された板状体の第2の基板接続部および該第2の基板接続部から前記積層体の長手方向に沿って前記第1の端面の方向に向かって延び、延びた部分の端部が前記第2の外部電極の第1の面延在部に接合された第2の電極接続部を有していることを特徴とする積層型コンデンサ。
    A pair of first and second surfaces, a pair of first end surfaces and second end surfaces, and a pair of first side surfaces and second side surfaces on which a plurality of dielectric layers are stacked. A rectangular parallelepiped laminate, a plurality of internal electrodes arranged in the stacking direction between the plurality of dielectric layers, and the first side surface and the second side surface, respectively. The first external electrode and the second external electrode that are electrically connected to the different internal electrodes, and the first external terminal and the second external electrode that are bonded to the first external electrode A second external terminal,
    The first external electrode and the second external electrode include a side surface portion disposed so as to include a central portion of the side surface, and a first surface extension extending from the side surface portion to the first surface. And a second surface extending portion extending to the second surface,
    The first external terminal includes a first substrate connecting portion of a plate-like body and the first substrate which are arranged to face each other with a gap between the first surface adjacent to the first end surface. It extended toward the direction of the said 2nd end surface from the connection part along the longitudinal direction of the said laminated body, and the edge part of the extended part was joined to the said 1st surface extension part of the said 1st external electrode. Having a first electrode connection;
    The second external terminal includes a second substrate connecting portion of the plate-like body and the second substrate, which are arranged to face each other with a gap between the first surface adjacent to the second end surface. Extending from the connecting portion along the longitudinal direction of the laminate toward the first end surface, the end of the extended portion is joined to the first surface extending portion of the second external electrode. 2. A multilayer capacitor comprising two electrode connection portions.
  2.  前記第1の電極接続部は、前記第1の外部電極の前記第1の面延在部とは反対の部分に空間部を有し、前記第2の電極接続部は、前記第2の外部電極の前記第1の面延在部とは反対の部分に空間部を有していることを特徴とする請求項1に記載の積層型コンデンサ。 The first electrode connection portion has a space in a portion opposite to the first surface extension portion of the first external electrode, and the second electrode connection portion is formed of the second external electrode. The multilayer capacitor according to claim 1, wherein a space portion is provided in a portion opposite to the first surface extending portion of the electrode.
  3.  前記第1の基板接続部および前記第2の基板接続部は、前記第1の面に向かって突出する突出部を有していることを特徴とする請求項1または請求項2に記載の積層型コンデンサ。 3. The stack according to claim 1, wherein each of the first substrate connecting portion and the second substrate connecting portion has a protruding portion that protrudes toward the first surface. Type capacitor.
  4.  前記第1の電極接続部は、前記第1の外部電極の前記第1の面延在部と溶接部によって接合され、前記第2の電極接続部は、前記第2の外部電極の前記第1の面延在部と溶接部によって接合されていることを特徴とする請求項1乃至請求項3のいずれかに記載の積層型コンデンサ。 The first electrode connection portion is joined to the first surface extension portion of the first external electrode by a welding portion, and the second electrode connection portion is the first electrode of the second external electrode. The multilayer capacitor according to claim 1, wherein the multilayer capacitor is joined by a surface extension portion and a welding portion.
  5.  請求項1乃至請求項4のいずれかに記載の積層型コンデンサと該積層型コンデンサが実装される基板電極を備えた基板とが、前記第1の面と前記基板電極とを対向させて配置され、前記第1の基板接続部および前記第2の基板接続部と前記基板電極とが導電性接合材を介して接合されていることを特徴とする実装構造体。
     
     
     
     
     
     
     
     
     
     
     
    5. The multilayer capacitor according to claim 1 and a substrate including a substrate electrode on which the multilayer capacitor is mounted are disposed with the first surface and the substrate electrode facing each other. The mounting structure, wherein the first substrate connecting portion, the second substrate connecting portion, and the substrate electrode are bonded via a conductive bonding material.










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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000235931A (en) * 1998-12-15 2000-08-29 Murata Mfg Co Ltd Multilayer ceramic capacitor
JP2010123614A (en) * 2008-11-17 2010-06-03 Murata Mfg Co Ltd Ceramic capacitor and electronic component equipped with the same
JP2010171061A (en) * 2009-01-20 2010-08-05 Tdk Corp Multilayer capacitor
JP2014207428A (en) * 2013-03-19 2014-10-30 株式会社村田製作所 Laminated electronic component and mounting structure thereof
JP2015019037A (en) * 2013-07-09 2015-01-29 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor and mounting substrate of the same
JP2015220451A (en) * 2014-05-19 2015-12-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor, multilayer ceramic capacitor assembly, and board for mounting the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000235931A (en) * 1998-12-15 2000-08-29 Murata Mfg Co Ltd Multilayer ceramic capacitor
JP2010123614A (en) * 2008-11-17 2010-06-03 Murata Mfg Co Ltd Ceramic capacitor and electronic component equipped with the same
JP2010171061A (en) * 2009-01-20 2010-08-05 Tdk Corp Multilayer capacitor
JP2014207428A (en) * 2013-03-19 2014-10-30 株式会社村田製作所 Laminated electronic component and mounting structure thereof
JP2015019037A (en) * 2013-07-09 2015-01-29 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor and mounting substrate of the same
JP2015220451A (en) * 2014-05-19 2015-12-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor, multilayer ceramic capacitor assembly, and board for mounting the same

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