WO2017107282A1

WO2017107282A1 - Pixel circuit structure and fingerprint recognition system

Info

Publication number: WO2017107282A1
Application number: PCT/CN2016/072272
Authority: WO
Inventors: 刘毅成; 杨孟达
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2015-12-25
Filing date: 2016-01-27
Publication date: 2017-06-29
Also published as: CN106778458A

Abstract

Disclosed is a pixel circuit structure (20), comprising: a substrate (SS); a to-be-contacted portion (200) provided at a first side (S1) of the substrate (SS) and used for accepting a contact of a finger; and a capacitance detection circuit (CS) provided on a second side (S2) of the substrate, coupled to the to-be-contacted portion (200), and used for detecting a capacitance between the to-be-contacted portion (200) and the finger. A capacitance detection circuit (CS) and a to-be-contacted portion (200) are provided on different sides of a substrate (SS) by a pixel circuit structure (20), so that the parasitic capacitance (CP2) can be effectively reduced, and a fingerprint signal is relatively significant, thereby enhancing the accuracy of fingerprint recognition.

Description

Pixel circuit structure and fingerprint identification system

Technical field

The invention belongs to the technical field of fingerprint recognition, and in particular relates to a pixel circuit structure and a fingerprint identification system for reducing parasitic capacitance.

Background technique

With the rapid development of technology, more and more portable electronic devices such as mobile phones, digital cameras, tablet computers, and notebook computers have become essential tools in people's lives. Since portable electronic devices are generally used by individuals and have a certain degree of privacy, their internally stored data, such as phone books, photos, personal information, and the like, are privately owned. If the electronic device is lost, the data may be used by others and cause unnecessary losses. Although password protection has been used to prevent electronic devices from being used by others, passwords are easily leaked or cracked, and have low security. Moreover, the user needs to remember the password in order to use the electronic device, and if the password is forgotten, it will bring a lot of inconvenience. Therefore, the use of personal fingerprint identification systems to achieve identity authentication has been developed to improve data security.

In general, a fingerprint identification system includes a plurality of pixel circuits arranged in an array, each pixel circuit including a top electrode and a capacitance detecting circuit. The top electrode is used to accept finger contact and form a contact capacitance with the finger. The fingerprint identification system charges the contact capacitance and transmits the charge stored in the contact capacitance through charge sharing (Charge Sharing) or charge transfer (Charge Transferring) is converted into a fingerprint signal. The capacitance detecting circuit determines the magnitude of the contact capacitance based on the fingerprint signal. However, the top electrode will form a parasitic capacitance, and the parasitic capacitance is usually much larger than the contact capacitance, making the contact charge appear rather small, which is not conducive to the interpretation of the fingerprint signal, and even reduces the accuracy of fingerprint recognition. In view of this, how to improve the accuracy of fingerprint recognition has become one of the goals of the industry.

technical problem

A first technical problem to be solved by embodiments of the present invention is to provide a pixel circuit structure capable of reducing parasitic capacitance to improve the disadvantages of the prior art.

Technical solution

The embodiment of the present invention is implemented as follows. A pixel circuit structure includes:

Substrate

a contact portion disposed on the first side of the substrate for receiving contact with a finger;

The capacitance detecting circuit is disposed on the second side of the substrate and coupled to the contact portion for detecting a capacitance between the contact portion and the finger.

Further, a through hole (Via) is formed in the substrate, and the capacitance detecting circuit is coupled to the contact portion through the through hole.

Further, the substrate is a silicon substrate (Silicon Substrate).

Further, the through holes are formed by a through silicon via (TSV) process.

Further, the contact portion includes a top electrode, and the top electrode is coupled to the capacitance detecting circuit.

Further, the contact portion further includes a passivation layer covering the top electrode.

Further, an insulating layer is disposed between the top electrode and the substrate.

Further, the capacitance detecting circuit includes a conductive layer, and the top electrode is coupled to the conductive layer.

A second technical problem to be solved by embodiments of the present invention is to provide a fingerprint identification system including the pixel circuit structure as described above.

Beneficial effect

The pixel circuit structure of the invention has the capacitance detecting circuit and the contacted portion connected to different sides of the substrate, thereby effectively reducing the parasitic capacitance, so that the fingerprint signal is more significant, thereby improving the accuracy of the fingerprint identification.

DRAWINGS

1 is a schematic diagram of a pixel circuit structure provided by the prior art;

2 is a schematic diagram of a structure of a pixel circuit according to an embodiment of the present invention.

Embodiments of the invention

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an existing pixel circuit structure 10 in an integrated circuit layout. The pixel circuit structure 10 is applied to a fingerprint identification system. The pixel circuit structure 10 includes a substrate SS, a capacitance detecting circuit CS, and a contact portion 100. The substrate SS is a silicon substrate (Silicon The contact portion 100 includes a first metal layer M1 (corresponding to the top electrode) and a passivation layer PV for receiving the contact of the finger; and the capacitance detecting circuit CS is disposed on the substrate SS and includes the second metal Layer M2 (corresponding to the conductive layer). The passivation layer PV covers the first metal layer M1, and the contact capacitance CF (not shown) is formed between the first metal layer M1 and the finger, and the first metal layer M1 and the second metal layer M2 are A parasitic capacitance CP1 is formed therebetween. It should be noted that in the pixel circuit structure 10, since the capacitance detecting circuit CS and the contact portion 100 are disposed on the same side of the substrate SS, the parasitic capacitance CP1 formed by the first metal layer M1 and the second metal layer M2 is generally much larger than The contact capacitance CF is not conducive to fingerprint recognition, and even reduces the accuracy of fingerprint recognition.

In order to improve the accuracy of fingerprint recognition, the first metal layer M1 and the passivation layer PV may be disposed on the other side of the substrate SS, so that the capacitance value of the parasitic capacitance can be effectively reduced. Specifically, please refer to FIG. 2. FIG. 2 is a schematic diagram of a pixel circuit structure 20 provided in an embodiment of the present invention (in an integrated circuit layout).

The pixel circuit structure 20 can be applied to a fingerprint recognition system. Similar to the pixel circuit structure 10, the pixel circuit structure 20 includes a substrate SS, a capacitance detecting circuit CS, and a contact portion 200. The substrate SS may be a silicon substrate, and the contact portion 200 includes a first metal layer M1 and a passivation layer PV. The contact portion 200 is used to receive contact with a finger, and a contact capacitance CF is formed between the first metal layer M1 and the finger. Not shown in the figure). The fingerprint identification system charges the contact capacitance CF and forms a fingerprint signal, and the capacitance detection circuit CS can determine the size of the contact capacitance CF according to the fingerprint signal. The capacitance detecting circuit CS may include a capacitor component such as a (transistor) switch, a capacitor, an operational amplifier, etc. The circuit structure of the capacitance detecting circuit CS is well known to those skilled in the art, and thus will not be described herein. Different from the pixel circuit structure 10, in the pixel circuit structure 20, the contact portion 200 and the capacitance detecting circuit CS are respectively disposed on different sides of the substrate SS, in other words, the contact portion 200 is disposed on the first side of the substrate SS. S1, and the capacitance detecting circuit CS is disposed on the second side S2 of the substrate SS. Setting the contact portion 200 and the capacitance detecting circuit CS on different sides of the substrate SS can effectively reduce the parasitic capacitance.

The capacitance detecting circuit CS is coupled to the contact portion 200 via the via Via. More specifically, the second metal layer M2 of the capacitance detecting circuit CS is coupled to the first metal layer M1 of the contact portion 200 through the via Via. The through hole Via is directly coupled between the first metal layer M1 and the second metal layer M2 through the substrate SS, and the through hole Via can be perforated (Through) Silicon Via, TSV) process is formed. In addition, an insulating layer IL is disposed between the first metal layer M1 and the first side S1 of the substrate SS. The via hole Via is also coupled between the first metal layer M1 and the second metal layer M2 through the insulating layer IL.

As a result, the parasitic capacitance CP2 formed between the first metal layer M1 and the second metal layer M2 can be effectively reduced. The parasitic capacitance CP2 can be reduced to half of the parasitic capacitance CP1 or even one tenth of the parasitic capacitance CP1 compared to the parasitic capacitance CP1. For example, assuming parasitic capacitance CP1 is 100 picofarad (pF), parasitic capacitance CP2 can be reduced to 10 to 50 pF. In the case of reducing the parasitic capacitance CP2, the fingerprint signal formed by the fingerprint identification system charging the contact capacitance CF is more significant, and the fingerprint identification is more accurate.

In the existing pixel circuit structure, since the capacitance detecting circuit and the contacted portion are disposed on the same side of the substrate, a large parasitic capacitance is formed, which is disadvantageous for fingerprint recognition and even reduces the accuracy of fingerprint recognition. In contrast, the pixel circuit structure of the present invention connects the capacitance detecting circuit and the contacted portion to different sides of the substrate, effectively reducing parasitic capacitance, making the fingerprint signal more significant, thereby improving the accuracy of fingerprint recognition.

It should be noted that the foregoing embodiments are used to explain the concept of the present invention, and those skilled in the art can make various modifications, and are not limited thereto. For example, the passivation layer can be made of sapphire or glass material, and is not limited thereto. In addition, the first metal layer may be a conductive layer made of a metal electrode or other materials, and is not limited thereto.

In summary, the pixel circuit structure of the present invention connects the capacitance detecting circuit and the contacted portion to different sides of the substrate, thereby effectively reducing the parasitic capacitance, so that the fingerprint signal is more significant, thereby improving the accuracy of fingerprint recognition.

The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalents, and improvements made within the spirit and scope of the present invention should be included in the scope of the present invention. Inside.

Claims

A pixel circuit structure characterized by comprising:

Substrate

a contact portion disposed on the first side of the substrate for receiving contact with a finger;

The capacitance detecting circuit is disposed on the second side of the substrate and coupled to the contact portion for detecting a capacitance between the contact portion and the finger.
The pixel circuit structure of claim 1 , wherein a via is formed in the substrate, and the capacitance detecting circuit is coupled to the contact portion through the through hole.
The pixel circuit structure according to claim 2, wherein said substrate is a silicon substrate (Silicon Substrate).
The pixel circuit structure of claim 3, wherein the via is made of through silicon (Through Silicon Via, TSV) process is formed.
The pixel circuit structure of claim 1 , wherein the contact portion comprises a top electrode, and the top electrode is coupled to the capacitance detecting circuit.
The pixel circuit structure of claim 5, wherein the contact portion further comprises a passivation layer, the passivation layer covering the top electrode.
The pixel circuit structure according to claim 5, wherein an insulating layer is disposed between the top electrode and the substrate.
The pixel circuit structure of claim 5, wherein the capacitance detecting circuit comprises a conductive layer, and the top electrode is coupled to the conductive layer.
A fingerprint identification system comprising the pixel circuit structure according to any one of claims 1 to 8.