WO2017104169A1 - Electronic component, method for manufacturing same, and electronic component manufacturing device - Google Patents

Electronic component, method for manufacturing same, and electronic component manufacturing device Download PDF

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Publication number
WO2017104169A1
WO2017104169A1 PCT/JP2016/073389 JP2016073389W WO2017104169A1 WO 2017104169 A1 WO2017104169 A1 WO 2017104169A1 JP 2016073389 W JP2016073389 W JP 2016073389W WO 2017104169 A1 WO2017104169 A1 WO 2017104169A1
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WO
WIPO (PCT)
Prior art keywords
resin
substrate
electronic component
semiconductor chip
sealing
Prior art date
Application number
PCT/JP2016/073389
Other languages
French (fr)
Japanese (ja)
Inventor
勝則 傳藤
山本　雅之
幹司 石橋
Original Assignee
Ｔｏｗａ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ｔｏｗａ株式会社 filed Critical Ｔｏｗａ株式会社
Priority to KR1020187017784A priority Critical patent/KR102261309B1/en
Priority to CN201680072617.1A priority patent/CN108431933B/en
Publication of WO2017104169A1 publication Critical patent/WO2017104169A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to an electronic component, a manufacturing method thereof, and an electronic component manufacturing apparatus.
  • a technique is known in which the back surface of a semiconductor wafer (having an integrated circuit pattern formed on the front surface side) before being singulated to form a semiconductor chip is ground (back grind).
  • the thickness of the semiconductor wafer is below a certain level (for example, about 100 ⁇ m or less), cracking or chipping is likely to occur during grinding of the back surface of the wafer, separation into pieces, or conveyance due to insufficient strength.
  • a certain level for example, about 100 ⁇ m or less
  • cracking or chipping is likely to occur during grinding of the back surface of the wafer, separation into pieces, or conveyance due to insufficient strength.
  • the semiconductor wafer is set to a certain thickness or less, processing becomes difficult, and the yield of semiconductor chips deteriorates.
  • an independent manufacturing apparatus used in each process for manufacturing an electronic component includes a workpiece carry-in portion and a carry-out portion. Providing manufacturing apparatuses used for each process separately increases the area occupied by the apparatus in the electronic component manufacturing factory.
  • An object of the present invention is to provide an electronic component in which cracks and chips of a semiconductor wafer are suppressed and yield is improved, and a method for manufacturing the same.
  • another object of the present invention is to provide an electronic component manufacturing apparatus having a reduced occupation area in an electronic component manufacturing factory.
  • the electronic component manufacturing method includes a step of mounting a plurality of semiconductor chips on a substrate, a step of resin-sealing the plurality of semiconductor chips mounted on the substrate, and the resin sealing. Grinding the upper surface of the resin used for stopping and reducing the thickness of the resin.
  • the semiconductor chip is mounted on the substrate by flip chip bonding, and the upper surface of the resin is ground so that the semiconductor chip is exposed.
  • the method of manufacturing the electronic component includes a step of reducing the thickness of the resin and the thickness of the semiconductor chip by grinding the upper surface of the resin and the upper surface of the semiconductor chip.
  • the method for manufacturing an electronic component according to the present invention includes a step of mounting a plurality of semiconductor chips on a substrate, and a step of grinding the upper surface of the semiconductor chip to reduce the thickness of the semiconductor chip.
  • an electronic component manufacturing apparatus includes a first specific mechanism having a first function and a grinding mechanism for grinding an upper surface of a resin that seals a plurality of functional elements provided on a substrate.
  • the first function is a function of resin-sealing the plurality of functional elements provided on the substrate.
  • the electronic component manufacturing apparatus includes a grinding mechanism for grinding an upper surface of a resin that seals a plurality of functional elements provided on a substrate, and a second specific mechanism having a second function.
  • the second function is a function of cutting the substrate and the resin to produce individual electronic parts.
  • the electronic component manufacturing apparatus is configured to grind the upper surface of the resin that seals the first specific mechanism having the first function and the plurality of functional elements provided on the substrate.
  • the function is a function of cutting the substrate and the resin to produce individualized electronic components.
  • the electronic component manufacturing apparatus includes a grinding mechanism for grinding an upper surface of a resin that seals a plurality of functional elements provided on a substrate, and a third specification having a third function.
  • the third function is a function of marking at least the upper surface of the resin.
  • the first to third specific mechanisms and the grinding mechanism are detachable from each other.
  • an electronic component includes a substrate, a plurality of functional elements provided on the substrate, a sealing resin that seals the plurality of functional elements, and an upper surface of the sealing resin. And a continuous groove.
  • an electronic component according to the present invention includes a substrate, a plurality of functional elements provided on the substrate, and a seal that seals the plurality of functional elements while exposing the top surfaces of the plurality of functional elements.
  • a stop resin, and a groove continuous over the upper surface of the sealing resin and the upper surfaces of the plurality of functional elements are provided.
  • an electronic component according to the present invention includes a substrate, a semiconductor chip mounted on the substrate, a sealing resin that seals the semiconductor chip, and a groove that is continuous on the top surface of the sealing resin.
  • an electronic component includes a substrate, a semiconductor chip mounted on the substrate, a sealing resin that seals the semiconductor chip while exposing an upper surface of the semiconductor chip, and A groove that is continuous over the upper surface of the sealing resin and the upper surface of the semiconductor chip is provided.
  • the present invention after the semiconductor chip is mounted on the substrate, a grinding process for reducing the thickness of the resin or the semiconductor chip is performed. As a result, the yield can be improved by suppressing the occurrence of cracks and chips in the semiconductor chip.
  • FIG. 10 is a top view corresponding to the state of FIG. 9. It is a top view which shows the further modification of the example shown in FIG. 9, FIG.
  • FIG. 1 is a flowchart showing a method for manufacturing an electronic component according to the present embodiment.
  • the method of manufacturing an electronic component according to the present embodiment includes a step of forming a semiconductor chip by separating a wafer (S10), and a step of mounting a semiconductor chip on a substrate (S20).
  • the step of mounting the semiconductor chip on the substrate (S20) includes a step of mounting the semiconductor chip on the substrate (eg, die bonding) and a step of electrically connecting the terminals of the semiconductor chip and the terminals of the substrate ( Example: wire bonding). Flip chip bonding is also included in the step of mounting the semiconductor chip on the substrate (S20).
  • FIG. 2 is a flowchart showing a method for manufacturing an electronic component according to a comparative example.
  • the method of manufacturing an electronic component according to the comparative example also includes a wafer singulation step (S10A), a semiconductor chip mounting step (S20A), a resin sealing step (S30A), and polishing ( A grinding) step (S40A), a resin-encapsulated product singulation step (S50A), and an inspection / test step (S60A).
  • the wafer back surface polishing (grinding) step (S40A) is performed before the wafer singulation step (S10A).
  • the thickness of a semiconductor chip is reduced before being mounted on a substrate, cracking or chipping is likely to occur during polishing (grinding), wafer singulation, or semiconductor chip transport, and the yield of semiconductor chips. Gets worse.
  • the semiconductor wafer manufactured in the previous process is cut while maintaining a predetermined thickness in the subsequent process (assembly process). It becomes a semiconductor chip.
  • the semiconductor chip is resin-sealed after being mounted on the circuit board. Thereafter, the resin-encapsulated portion and the semiconductor chip are ground and thinned sequentially. By doing in this way, a crack and a chip
  • tip of a semiconductor chip can be suppressed and the yield of a semiconductor chip can be improved.
  • FIG. 3 is a diagram showing a state in which the resin sealing step (S30) in the electronic component manufacturing method according to the present embodiment is performed.
  • a plurality of semiconductor chips 20 are mounted on the substrate 10 and are sealed with a sealing resin 30.
  • the sealing resin 30 for example, an epoxy resin is used.
  • Each semiconductor chip 20 has functions such as calculation, control, and data storage.
  • the plurality of semiconductor chips 20 mounted on the substrate 10 correspond to a plurality of functional elements provided on the substrate 10.
  • FIG. 4 is a diagram showing a polishing (grinding) step (S40) in the method of manufacturing an electronic component according to the present embodiment.
  • the substrate 10 on which the semiconductor chip 20 is mounted is attracted to the table 40 (arrow DR40).
  • the substrate 10 may be fixed to the table 40 using a jig.
  • a solder ball 10 ⁇ / b> A as a back electrode is formed on the back surface of the substrate 10.
  • the table 40 has a recess 40A that can accommodate the solder ball 10A.
  • the sealing resin 30 and the semiconductor chip 20 are polished by the grinder 50 that moves in the direction of the arrow DR50 at a constant moving speed while rotating.
  • the area to be polished is increased as compared with the case of polishing only the back surface of the semiconductor chip 20, but before the semiconductor chip 20 is mounted on the substrate 10. Therefore, it is possible to suppress the occurrence of cracks and chips in the semiconductor chip 20 and improve the yield.
  • FIG. 4 shows a step of simultaneously polishing (grinding) the entire thickness of the sealing resin 30 and the thickness of a part of the semiconductor chip 20 as a step of polishing (grinding) (S40).
  • the rotational speed of the grinder 50 (referred to as the rotational speed per unit time; hereinafter the same) is limited by the semiconductor chip 20 having hard and brittleness.
  • the thickness of a part of the semiconductor chip 20 is polished (ground) at a small rotational speed. May be.
  • the thickness of a part of the semiconductor chip 20 may be polished (ground) at a low moving speed.
  • the moving speed may be a relative moving speed between the table 40 and the grinder 50.
  • FIG. 5 is a diagram showing a cutting step (S50) in the electronic component manufacturing method according to the present embodiment. As shown in FIG. 5, the substrate 10 and the sealing resin 30 are cut by the rotating blade 60, and the resin-sealed electronic component is cut (divided into pieces) according to the product size.
  • FIG. 6 shows an example in which the resin sealing mechanism and the grinding mechanism are incorporated in one apparatus
  • FIG. 7 shows an example in which the grinding mechanism and the cutting mechanism are incorporated in one apparatus.
  • the electronic component manufacturing apparatus includes first to fourth units A1 to A4.
  • the first unit A1 as a “carry-in unit” includes a carry-in unit 100 into which a workpiece is carried in, a workpiece conveyance mechanism 150, and a substrate platform 200.
  • the second unit A2 as the “resin sealing unit” includes a rotation mechanism 300 that rotates the workpiece and a resin sealing mechanism 400 that performs resin sealing of the semiconductor chip.
  • the third unit A3 as a “grinding unit” includes a rotation mechanism 300 that rotates the workpiece, and a grinding mechanism 500 that polishes (grinds) the workpiece.
  • the fourth unit A4 as the “inspection / unloading unit” includes an inspection table 600 and an unloading unit 700 for unloading the workpiece.
  • the first unit A1 and the second unit A2 are detachable from each other.
  • the second unit A2 and the third unit A3 are detachable from each other.
  • the third unit A3 and the fourth unit A4 are detachable from each other.
  • the same type of units for example, two or more second units as “resin sealing units” may be provided as in the second units A2a, A2b,. In this case, the second units A2a, A2b,... Can be attached to and detached from each other.
  • Two or more third units A3 as “grinding units” may be provided as the same type of unit. In this case, the third units A3a, A3b,... Can be attached to and detached from each other.
  • the electronic component manufacturing apparatus includes first to fourth units B1 to B4.
  • the first unit B1 as a “carry-in unit” includes a carry-in unit 100 into which a workpiece is carried in, a workpiece conveyance mechanism 150, and a substrate platform 200.
  • the second unit B2 as the “grinding unit” includes a rotation mechanism 300 that rotates the workpiece and a grinding mechanism 500 that polishes (grinds) the workpiece.
  • the third unit B3 as the “cutting unit” includes a rotation mechanism 300 that rotates the workpiece and a cutting mechanism 800 that cuts the workpiece.
  • the fourth unit B4 as the “inspection / unloading unit” includes an inspection table 600 and an unloading unit 700 for unloading the workpiece.
  • the first unit B1 and the second unit B2 are detachable from each other.
  • the second unit B2 and the third unit B3 are detachable from each other.
  • the third unit B3 and the fourth unit B4 are detachable from each other. It is the same in the case of the example in FIG. 6 that two or more units of the same type may be provided.
  • the same type of unit is a second unit as a “grinding unit” and a third unit as a “cutting unit”.
  • a resin sealing unit (see the second unit A2 in FIG. 6) may be provided in front of the second unit B2 as a “grinding unit”.
  • the first unit B1 as the “carry-in unit” and the resin sealing unit are detachable from each other, and the resin sealing unit and the grinding unit are detachable from each other.
  • the grinding unit and the marking unit can be attached to and detached from each other.
  • the grinding unit for grinding the upper surface of the resin that seals the semiconductor chip is incorporated afterwards into a common apparatus including the resin sealing unit, the singulation unit, and the marking unit. It is removed from the device afterwards. Therefore, if necessary, it is possible to provide an electronic component manufacturing apparatus in which the grinding unit is incorporated afterwards and the grinding unit is removed afterward. In addition, it is possible to provide an electronic component manufacturing apparatus in which a resin sealing unit is added afterwards and a resin sealing unit is removed afterward as needed. Therefore, according to these electronic component manufacturing apparatuses, it is possible to respond to an increase or decrease in demand for electronic components and a request for thinning of electronic components afterwards.
  • a resin sealing mechanism, a grinding mechanism, and a cutting mechanism may be incorporated into one device.
  • FIG. 8A and 8B are cross-sectional views of an electronic component as a workpiece to be processed by the above-described electronic component manufacturing apparatus.
  • an electronic component in which the semiconductor chip 20 is wire-bonded on the substrate 10 may be used, and as shown in FIG. 8B, an electronic component in which the semiconductor chip 20 is flip-chip mounted on the substrate 10. It may be.
  • the grinding range needs to be above the wire 20A, and therefore, for example, is above the “A” line in the figure.
  • the semiconductor chip 20 is not exposed, but a cooling plate mounted on the semiconductor chip 20 may be exposed. After grinding, a continuous polishing mark is formed on the upper surface of the sealing resin 30.
  • an underfill 20B is provided below the semiconductor chip 20.
  • MEMS can be cited in addition to an electronic component including a semiconductor element.
  • only the underfill 20B may be provided as the sealing resin. In this case, continuous polishing marks are formed on the upper surface of the semiconductor chip.
  • a plurality of semiconductor chips 20 may be included in one electronic component.
  • a plurality of semiconductor chips 20 included in one electronic component may be stacked.
  • the sealing resin 30 on the uppermost semiconductor chip 20 is polished.
  • the obtained electronic component becomes a stack-type electronic component.
  • the sealing resin 30 on the uppermost semiconductor chip 20 is polished.
  • the sealing resin 30 on the uppermost semiconductor chip 20 and the uppermost semiconductor chip 20 are polished.
  • a chip other than a semiconductor chip may be included in a plurality of chips included in one electronic component.
  • the plurality of chips shown in FIG. 4 may be control ICs, power devices, passive elements, and the like. In this case, dimensions such as thickness and the number of terminals in a plurality of chips are different.
  • the part after the grinding process shown in FIG. 4 is completed may correspond to one electronic part (for example, an electronic module for power control).
  • the continuous polishing mark is composed of continuous fine grooves arranged in parallel to each other.
  • a plurality of fine ridges and valleys are formed in parallel on the upper surface of the electronic component.
  • a plurality of fine concave portions and convex portions are formed side by side.
  • the term “groove” includes “concave portion”.
  • the surface area on the top surface of the sealing resin, the surface area on the top surface of the semiconductor chip, or the top surface of the sealing resin and the top surface of the semiconductor chip by a plurality of fine grooves formed side by side or a plurality of concave and convex portions formed side by side The surface area on the top surface increases. Therefore, first, heat dissipation from the upper surface of the sealing resin and heat dissipation from the upper surface of the semiconductor chip are improved. Second, in the case where a heat sink is attached to at least the upper surface of the semiconductor chip, the adhesion and heat dissipation between the upper surface of the semiconductor chip and the lower surface of the heat sink are improved.
  • FIG. 9 is a cross-sectional view showing one step of a modified example of the electronic component manufacturing method according to the present embodiment.
  • grooves 30A (30A1, 30A2) are formed in the sealing resin 30 before the grinding process.
  • the molded substrate after resin sealing may be warped due to the difference in thermal expansion coefficient between the resin and the substrate, the warpage can be reduced by forming the groove 30A.
  • the groove 30A is formed shallower than the grinding line (C).
  • the step of forming the groove 30A is incorporated between a plurality of steps, for example, the groove 30A is formed by a cutting mechanism after resin sealing, the resin surface is ground by the grinding mechanism, and completely cut again by the cutting mechanism. Can do. Thereby, the conveyance time of a workpiece can be reduced.
  • the arrangement of the grooves 30A may be as shown in FIG. 10 or as shown in FIG.
  • the groove shapes shown in FIGS. 10 and 11 are examples and can be arbitrarily changed.
  • FIG. 8A and FIG. 8B the example of wire bonding and flip-chip mounting was shown as a process which electrically connects the terminal which each of the some semiconductor chip 20 has, and the terminal which the board
  • the method of mounting the semiconductor chip 20 on the upper surface of the substrate 10 is arbitrary, and the types of electronic components are not limited to the examples of FIGS. 8A and 8B.
  • FIGS. 3 to 5 are merely examples for schematically explaining the invention.
  • an after-curing process and a marking process after resin sealing there are an after-curing process and a marking process after resin sealing.
  • the present invention appropriately employs a manufacturing process corresponding to the type of electronic component, and is not limited to the above-described manufacturing process.
  • the semiconductor chip 20 and the sealing resin 30 are not necessarily ground together. Depending on the product type, only the semiconductor chip 20 or only the sealing resin 30 may be ground. When grinding only the semiconductor chip 20, for example, after underfilling (filling a resin between the semiconductor chip 20 and the substrate 10) is performed on the semiconductor chip 20 that is flip-chip mounted, the semiconductor chip 20 is then ground. Can be ground.
  • the order of the manufacturing process of the electronic component according to the present invention is appropriately changed depending on the manufacturing type.
  • an example in which the resin sealing mechanism or the cutting mechanism and the grinding mechanism are incorporated (built-in) in one apparatus has been described.
  • the process of combining with the grinding mechanism can be appropriately changed according to the type of manufacture. .
  • a grinding process is performed to reduce at least one of the thickness of the sealing resin 30 or the thickness of the semiconductor chip 20.
  • This makes it possible to omit the step of grinding the semiconductor wafer before mounting the semiconductor chip 20 on the substrate 10.
  • the amount (thickness) of grinding the semiconductor wafer can be reduced. Therefore, first, the yield can be improved by making the thickness of the semiconductor wafer easy to handle during transportation. Secondly, the number of steps for grinding the semiconductor wafer can be reduced.
  • the grinding mechanism 500 for grinding the upper surface of the sealing resin 30 for sealing the semiconductor chip 20 into the mechanism for performing the preceding and following processes, the occupation area in the electronic component manufacturing factory is reduced, and the factory floor area is reduced. There is room.
  • the electronic component according to the present invention is not limited to an electronic component including a semiconductor chip.
  • a first example of the electronic component is a surface acoustic wave filter.
  • One surface of a substrate having a piezoelectric function (having a piezoelectric effect) is divided into a plurality of regions, and opposing comb-like metal electrodes are formed in each region.
  • One surface of the substrate is resin-sealed, the upper surface of the sealing resin is polished, and the substrate is separated into each region.
  • a plurality of surface acoustic wave filters corresponding to a plurality of regions can be manufactured.
  • the comb-like metal electrode in each region corresponds to a functional element that functions as a surface acoustic wave filter.
  • a first example of an electronic component is a micromirror array.
  • One surface of a substrate made of silicon, glass, ceramics, or the like is divided into a plurality of regions.
  • a metal thin film is formed on one surface of the substrate by vapor deposition, sputtering, or the like.
  • a plurality of minute columnar metals are formed on the metal thin film by combining processes such as photolithography and electroforming. After resin-sealing one surface of the substrate, the upper surface of the sealing resin is polished to expose the cross-sections of the plurality of columnar metals in a mirror shape. Thereafter, the substrate is divided into each region. Light such as laser light is reflected by the exposed surface of the columnar metal.
  • a plurality of micromirror arrays corresponding to a plurality of regions can be manufactured.
  • the plurality of columnar metals in each region correspond to functional elements that function as a micromirror array.
  • the substrate between the plurality of columnar metals may be removed by an appropriate thickness by etching or the like.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A method for manufacturing an electronic component is provided with a step for preparing a semiconductor wafer, a step for dicing the semiconductor wafer and fabricating a plurality of semiconductor chips (20), a step for mounting the plurality of semiconductor chips (20) on a substrate (10), and a step for reducing the thickness of the semiconductor chips (20) by grinding the upper surface of the semiconductor chips (20).

Description

電子部品およびその製造方法ならびに電子部品製造装置Electronic component, method for manufacturing the same, and electronic component manufacturing apparatus
　本発明は、電子部品およびその製造方法ならびに電子部品製造装置に関する。 The present invention relates to an electronic component, a manufacturing method thereof, and an electronic component manufacturing apparatus.
　電子部品の厚みを薄くしたい（電子部品の薄肉化）という市場の要請に応じて、半導体チップの厚みを薄くする技術が開発されている。 In response to market demands for reducing the thickness of electronic components (thinning electronic components), technologies for reducing the thickness of semiconductor chips have been developed.
　たとえば、個片化して半導体チップを形成する前の半導体ウエハ（表面側に集積回路のパターンが形成されているもの）の裏面を研削（バックグラインド）する技術が知られている。 For example, a technique is known in which the back surface of a semiconductor wafer (having an integrated circuit pattern formed on the front surface side) before being singulated to form a semiconductor chip is ground (back grind).
特開平４－２９７０５６号公報JP-A-4-297056
　半導体ウエハの厚みが一定以下（たとえば１００μｍ以下程度）になると、強度不足によってウエハの裏面研削時、個片化時、搬送時に割れまたは欠けが生じやすくなる。このように、半導体ウエハを一定厚み以下にすると加工が困難になり、半導体チップの歩留まりが悪化する。 When the thickness of the semiconductor wafer is below a certain level (for example, about 100 μm or less), cracking or chipping is likely to occur during grinding of the back surface of the wafer, separation into pieces, or conveyance due to insufficient strength. As described above, when the semiconductor wafer is set to a certain thickness or less, processing becomes difficult, and the yield of semiconductor chips deteriorates.
　また、上記とは異なる観点では、電子部品を製造する各工程において使用される独立した製造装置は、被加工物の搬入部と搬出部とを含む。各工程に用いる製造装置を別々に設けることにより、電子部品の製造工場において装置の占有面積が大きくなる。 Also, from a viewpoint different from the above, an independent manufacturing apparatus used in each process for manufacturing an electronic component includes a workpiece carry-in portion and a carry-out portion. Providing manufacturing apparatuses used for each process separately increases the area occupied by the apparatus in the electronic component manufacturing factory.
　本発明の１つの目的は、半導体ウエハの割れや欠けなどが抑制され、歩留まりが改善された電子部品およびその製造方法を提供することにある。 An object of the present invention is to provide an electronic component in which cracks and chips of a semiconductor wafer are suppressed and yield is improved, and a method for manufacturing the same.
　また、上記とは異なる観点では、本発明の他の目的は、電子部品の製造工場において占有面積が低減された電子部品製造装置を提供することにある。 In another aspect different from the above, another object of the present invention is to provide an electronic component manufacturing apparatus having a reduced occupation area in an electronic component manufacturing factory.
　１つの局面では、複数の機能要素を基板に設ける工程と、上記基板に形成された上記複数の機能要素を樹脂封止する工程と、上記樹脂封止に用いた樹脂の上面を研削して上記樹脂の厚みを減じる工程とを備える。 In one aspect, the step of providing a plurality of functional elements on the substrate, the step of resin-sealing the plurality of functional elements formed on the substrate, and grinding the upper surface of the resin used for the resin sealing described above And a step of reducing the thickness of the resin.
　他の局面では、本発明に係る電子部品の製造方法は、複数の半導体チップを基板に実装する工程と、上記基板に実装された上記複数の半導体チップを樹脂封止する工程と、上記樹脂封止に用いた樹脂の上面を研削して上記樹脂の厚みを減じる工程とを備える。 In another aspect, the electronic component manufacturing method according to the present invention includes a step of mounting a plurality of semiconductor chips on a substrate, a step of resin-sealing the plurality of semiconductor chips mounted on the substrate, and the resin sealing. Grinding the upper surface of the resin used for stopping and reducing the thickness of the resin.
　１つの実施態様では、上記電子部品の製造方法において、上記半導体チップはフリップチップボンディングにより上記基板に実装され、上記半導体チップが露出するように上記樹脂の上面が研削される。 In one embodiment, in the electronic component manufacturing method, the semiconductor chip is mounted on the substrate by flip chip bonding, and the upper surface of the resin is ground so that the semiconductor chip is exposed.
　１つの実施態様では、上記電子部品の製造方法は、上記樹脂の上面と上記半導体チップの上面とを研削することによって上記樹脂の厚みと上記半導体チップの厚みとを減じる工程を備える。 In one embodiment, the method of manufacturing the electronic component includes a step of reducing the thickness of the resin and the thickness of the semiconductor chip by grinding the upper surface of the resin and the upper surface of the semiconductor chip.
　他の局面では、本発明に係る電子部品の製造方法は、複数の半導体チップを基板に実装する工程と、上記半導体チップの上面を研削して上記半導体チップの厚みを減じる工程とを備える。 In another aspect, the method for manufacturing an electronic component according to the present invention includes a step of mounting a plurality of semiconductor chips on a substrate, and a step of grinding the upper surface of the semiconductor chip to reduce the thickness of the semiconductor chip.
　１つの局面では、本発明に係る電子部品製造装置は、第１の機能を有する第１の特定機構と、基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構とを備え、上記第１の機能は、上記基板上に設けられた上記複数の機能要素を樹脂封止する機能である。 In one aspect, an electronic component manufacturing apparatus according to the present invention includes a first specific mechanism having a first function and a grinding mechanism for grinding an upper surface of a resin that seals a plurality of functional elements provided on a substrate. The first function is a function of resin-sealing the plurality of functional elements provided on the substrate.
　他の局面では、本発明に係る電子部品製造装置は、基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構と、第２の機能を有する第２の特定機構とを備え、上記第２の機能は、上記基板および上記樹脂を切断して個片化された電子部品を作製する機能である。 In another aspect, the electronic component manufacturing apparatus according to the present invention includes a grinding mechanism for grinding an upper surface of a resin that seals a plurality of functional elements provided on a substrate, and a second specific mechanism having a second function. The second function is a function of cutting the substrate and the resin to produce individual electronic parts.
　さらに他の局面では、本発明に係る電子部品製造装置は、第１の機能を有する第１の特定機構と、基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構と、第２の機能を有する第２の特定機構とを備え、上記第１の機能は、上記基板上に設けられた上記複数の機能要素を樹脂封止する機能であり、上記第２の機能は、上記基板および上記樹脂を切断して個片化された電子部品を作製する機能である。 In still another aspect, the electronic component manufacturing apparatus according to the present invention is configured to grind the upper surface of the resin that seals the first specific mechanism having the first function and the plurality of functional elements provided on the substrate. A mechanism and a second specific mechanism having a second function, wherein the first function is a function of resin-sealing the plurality of functional elements provided on the substrate. The function is a function of cutting the substrate and the resin to produce individualized electronic components.
　さらに他の局面では、本発明に係る電子部品製造装置は、基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構と、第３の機能を有する第３の特定機構とを備え、上記第３の機能は、少なくとも上記樹脂の上面にマークを付ける機能である。 In still another aspect, the electronic component manufacturing apparatus according to the present invention includes a grinding mechanism for grinding an upper surface of a resin that seals a plurality of functional elements provided on a substrate, and a third specification having a third function. And the third function is a function of marking at least the upper surface of the resin.
　１つの実施態様では、上記電子部品製造装置において、上記第１ないし第３の特定機構と上記研削機構とは互いに着脱可能である。 In one embodiment, in the electronic component manufacturing apparatus, the first to third specific mechanisms and the grinding mechanism are detachable from each other.
　１つの局面では、本発明に係る電子部品は、基板と、上記基板上に設けられた複数の機能要素と、上記複数の機能要素を封止する封止樹脂と、上記封止樹脂の上面において連続する溝とを備える。 In one aspect, an electronic component according to the present invention includes a substrate, a plurality of functional elements provided on the substrate, a sealing resin that seals the plurality of functional elements, and an upper surface of the sealing resin. And a continuous groove.
　他の局面では、本発明に係る電子部品は、基板と、上記基板上に設けられた複数の機能要素と、上記複数の機能要素の上面を露出させながら上記複数の機能要素を封止する封止樹脂と、上記封止樹脂の上面と上記複数の機能要素の上面とにわたって連続する溝とを備える。 In another aspect, an electronic component according to the present invention includes a substrate, a plurality of functional elements provided on the substrate, and a seal that seals the plurality of functional elements while exposing the top surfaces of the plurality of functional elements. A stop resin, and a groove continuous over the upper surface of the sealing resin and the upper surfaces of the plurality of functional elements are provided.
　さらに他の局面では、本発明に係る電子部品は、基板と、上記基板上に実装された半導体チップと、上記半導体チップを封止する封止樹脂と、上記封止樹脂の上面において連続する溝とを備える。 In still another aspect, an electronic component according to the present invention includes a substrate, a semiconductor chip mounted on the substrate, a sealing resin that seals the semiconductor chip, and a groove that is continuous on the top surface of the sealing resin. With.
　さらに他の局面では、本発明に係る電子部品は、基板と、上記基板上に実装された半導体チップと、上記半導体チップの上面を露出させながら上記半導体チップを封止する封止樹脂と、上記封止樹脂の上面と上記半導体チップの上面とにわたって連続する溝とを備える。 In still another aspect, an electronic component according to the present invention includes a substrate, a semiconductor chip mounted on the substrate, a sealing resin that seals the semiconductor chip while exposing an upper surface of the semiconductor chip, and A groove that is continuous over the upper surface of the sealing resin and the upper surface of the semiconductor chip is provided.
　１つの効果として、本発明によれば、半導体チップを基板に実装した後に樹脂ないし半導体チップの厚みを減じる研削工程を行なう。この結果、半導体チップに割れや欠けが生じることを抑制して、歩留まりを向上させることができる。 As one effect, according to the present invention, after the semiconductor chip is mounted on the substrate, a grinding process for reducing the thickness of the resin or the semiconductor chip is performed. As a result, the yield can be improved by suppressing the occurrence of cracks and chips in the semiconductor chip.
　他の効果として、本発明によれば、半導体チップを封止する樹脂の上面を研削する研削機構を樹脂封止機構、個片化機構やマーキング機構と共通の装置に組み込むことにより、電子部品の製造工場において占有面積が低減された電子部品製造装置を提供することができる。 As another effect, according to the present invention, by incorporating a grinding mechanism for grinding the upper surface of the resin that seals the semiconductor chip into the same device as the resin sealing mechanism, the singulation mechanism, and the marking mechanism, An electronic component manufacturing apparatus having a reduced occupation area in a manufacturing factory can be provided.
本発明の１つの実施の形態に係る電子部品の製造方法を示すフロー図である。It is a flowchart which shows the manufacturing method of the electronic component which concerns on one embodiment of this invention. 比較例に係る電子部品の製造方法を示すフロー図である。It is a flowchart which shows the manufacturing method of the electronic component which concerns on a comparative example. 本発明の１つの実施の形態に係る電子部品の製造方法における樹脂封止工程を行なった状態を示す図である。It is a figure which shows the state which performed the resin sealing process in the manufacturing method of the electronic component which concerns on one embodiment of this invention. 本発明の１つの実施の形態に係る電子部品の製造方法における研削工程を示す図である。It is a figure which shows the grinding process in the manufacturing method of the electronic component which concerns on one embodiment of this invention. 本発明の１つの実施の形態に係る電子部品の製造方法における切断工程を示す図である。It is a figure which shows the cutting process in the manufacturing method of the electronic component which concerns on one embodiment of this invention. 本発明の１つの実施の形態に係る電子部品製造装置を示す図である。It is a figure which shows the electronic component manufacturing apparatus which concerns on one embodiment of this invention. 本発明の他の実施の形態に係る電子部品製造装置を示す図である。It is a figure which shows the electronic component manufacturing apparatus which concerns on other embodiment of this invention. 図６，図７に示す電子部品製造装置により加工される被加工物としての電子部品の例を示す断面図である。It is sectional drawing which shows the example of the electronic component as a workpiece processed by the electronic component manufacturing apparatus shown in FIG. 6, FIG. 図６，図７に示す電子部品製造装置により加工される被加工物としての電子部品の例を示す断面図である。It is sectional drawing which shows the example of the electronic component as a workpiece processed by the electronic component manufacturing apparatus shown in FIG. 6, FIG. 本発明の１つの実施の形態に係る電子部品の製造方法の変形例の一工程を示す断面図である。It is sectional drawing which shows 1 process of the modification of the manufacturing method of the electronic component which concerns on one embodiment of this invention. 図９の状態に対応する上面図である。FIG. 10 is a top view corresponding to the state of FIG. 9. 図９，図１０に示す例のさらなる変形例を示す上面図である。It is a top view which shows the further modification of the example shown in FIG. 9, FIG.
　以下に、本発明の実施の形態について説明する。なお、同一または相当する部分に同一の参照符号を付し、その説明を繰返さない場合がある。 Hereinafter, embodiments of the present invention will be described. Note that the same or corresponding portions are denoted by the same reference numerals, and the description thereof may not be repeated.
　なお、以下に説明する実施の形態において、個数、量などに言及する場合、特に記載がある場合を除き、本発明の範囲は必ずしもその個数、量などに限定されない。また、以下の実施の形態において、各々の構成要素は、特に記載がある場合を除き、本発明にとって必ずしも必須のものではない。 In the embodiment described below, when referring to the number, amount, etc., the scope of the present invention is not necessarily limited to the number, amount, etc. unless otherwise specified. In the following embodiments, each component is not necessarily essential for the present invention unless otherwise specified.
　図１は、本実施の形態に係る電子部品の製造方法を示すフロー図である。図１に示すように、本実施の形態に係る電子部品の製造方法は、ウエハを個片化して半導体チップを形成する工程（Ｓ１０）と、基板上に半導体チップを実装する工程（Ｓ２０）と、基板上に実装された半導体チップを樹脂封止する工程（Ｓ３０）と、樹脂の上面を研磨（研削）する工程（Ｓ４０）と、樹脂封止品を個片化する工程（Ｓ５０）と、検査・試験を行なう工程（Ｓ６０）とを含む。基板上に半導体チップを実装する工程（Ｓ２０）は、基板上に半導体チップを装着する工程（例：ダイボンディング）と、半導体チップが有する端子と基板が有する端子とを電気的に接続する工程（例：ワイヤボンディング）とを含む。フリップチップボンディングも、基板上に半導体チップを実装する工程（Ｓ２０）に含まれる。 FIG. 1 is a flowchart showing a method for manufacturing an electronic component according to the present embodiment. As shown in FIG. 1, the method of manufacturing an electronic component according to the present embodiment includes a step of forming a semiconductor chip by separating a wafer (S10), and a step of mounting a semiconductor chip on a substrate (S20). A step of resin-sealing the semiconductor chip mounted on the substrate (S30), a step of polishing (grinding) the upper surface of the resin (S40), a step of separating the resin-sealed product into pieces (S50), And a step of performing an inspection / test (S60). The step of mounting the semiconductor chip on the substrate (S20) includes a step of mounting the semiconductor chip on the substrate (eg, die bonding) and a step of electrically connecting the terminals of the semiconductor chip and the terminals of the substrate ( Example: wire bonding). Flip chip bonding is also included in the step of mounting the semiconductor chip on the substrate (S20).
　図２は、比較例に係る電子部品の製造方法を示すフロー図である。図２に示すように、比較例に係る電子部品の製造方法も、ウエハの個片化工程（Ｓ１０Ａ）と、半導体チップの実装工程（Ｓ２０Ａ）と、樹脂封止工程（Ｓ３０Ａ）と、研磨（研削）工程（Ｓ４０Ａ）と、樹脂封止品の個片化工程（Ｓ５０Ａ）と、検査・試験工程（Ｓ６０Ａ）とを含む。ただし、比較例においては、ウエハの個片化工程（Ｓ１０Ａ）の前にウエハ裏面を研磨（研削）する工程（Ｓ４０Ａ）を行なっている。このように、半導体チップを基板に実装する前にその厚みを減じる場合、その研磨（研削）時、ウエハの個片化時、半導体チップの搬送時に割れまたは欠けが生じやすくなり、半導体チップの歩留まりが悪化する。 FIG. 2 is a flowchart showing a method for manufacturing an electronic component according to a comparative example. As shown in FIG. 2, the method of manufacturing an electronic component according to the comparative example also includes a wafer singulation step (S10A), a semiconductor chip mounting step (S20A), a resin sealing step (S30A), and polishing ( A grinding) step (S40A), a resin-encapsulated product singulation step (S50A), and an inspection / test step (S60A). However, in the comparative example, the wafer back surface polishing (grinding) step (S40A) is performed before the wafer singulation step (S10A). As described above, when the thickness of a semiconductor chip is reduced before being mounted on a substrate, cracking or chipping is likely to occur during polishing (grinding), wafer singulation, or semiconductor chip transport, and the yield of semiconductor chips. Gets worse.
　これに対し、本実施の形態に係る電子部品の製造方法においては、前工程（ウエハの製造工程）で製造された半導体ウエハは、後工程（組立て工程）において、所定の厚みを維持したまま切断されて半導体チップとなる。半導体チップは、回路基板に実装された後、樹脂封止される。その後、樹脂封止部分と半導体チップとが順次研削されて薄くなる。このようにすることで、半導体チップの割れや欠けを抑制し、半導体チップの歩留まりを向上させることができる。 On the other hand, in the electronic component manufacturing method according to the present embodiment, the semiconductor wafer manufactured in the previous process (wafer manufacturing process) is cut while maintaining a predetermined thickness in the subsequent process (assembly process). It becomes a semiconductor chip. The semiconductor chip is resin-sealed after being mounted on the circuit board. Thereafter, the resin-encapsulated portion and the semiconductor chip are ground and thinned sequentially. By doing in this way, a crack and a chip | tip of a semiconductor chip can be suppressed and the yield of a semiconductor chip can be improved.
　図３は、本実施の形態に係る電子部品の製造方法における樹脂封止工程（Ｓ３０）を行なった状態を示す図である。図３に示すように、基板１０上に複数の半導体チップ２０が実装され、封止樹脂３０により樹脂封止される。封止樹脂３０としては、たとえばエポキシ樹脂が用いられる。各半導体チップ２０は、演算、制御、データの記憶などの機能を有する。基板１０上に実装された複数の半導体チップ２０は、基板１０上に設けられた複数の機能要素に相当する。 FIG. 3 is a diagram showing a state in which the resin sealing step (S30) in the electronic component manufacturing method according to the present embodiment is performed. As shown in FIG. 3, a plurality of semiconductor chips 20 are mounted on the substrate 10 and are sealed with a sealing resin 30. As the sealing resin 30, for example, an epoxy resin is used. Each semiconductor chip 20 has functions such as calculation, control, and data storage. The plurality of semiconductor chips 20 mounted on the substrate 10 correspond to a plurality of functional elements provided on the substrate 10.
　図４は、本実施の形態に係る電子部品の製造方法における研磨（研削）工程（Ｓ４０）を示す図である。図４に示すように、半導体チップ２０が実装された基板１０は、テーブル４０に吸着される（矢印ＤＲ４０）。なお、治具を用いて基板１０をテーブル４０に固定してもよい。基板１０の裏面には裏面電極としてのはんだボール１０Ａが形成されている。テーブル４０は、はんだボール１０Ａを収納可能な凹部４０Ａを有している。回転しながら一定の移動速度で矢印ＤＲ５０方向に移動するグラインダ５０により、封止樹脂３０および半導体チップ２０が研磨される。半導体チップ２０に加えて封止樹脂３０を研磨することにより、半導体チップ２０の裏面のみを研磨する場合と比較して、研磨すべき面積は増大するものの、半導体チップ２０を基板１０に実装する前に研磨する必要がないため、半導体チップ２０に割れや欠けが生じることを抑制して、歩留まりを向上させることができる。 FIG. 4 is a diagram showing a polishing (grinding) step (S40) in the method of manufacturing an electronic component according to the present embodiment. As shown in FIG. 4, the substrate 10 on which the semiconductor chip 20 is mounted is attracted to the table 40 (arrow DR40). The substrate 10 may be fixed to the table 40 using a jig. A solder ball 10 </ b> A as a back electrode is formed on the back surface of the substrate 10. The table 40 has a recess 40A that can accommodate the solder ball 10A. The sealing resin 30 and the semiconductor chip 20 are polished by the grinder 50 that moves in the direction of the arrow DR50 at a constant moving speed while rotating. By polishing the sealing resin 30 in addition to the semiconductor chip 20, the area to be polished is increased as compared with the case of polishing only the back surface of the semiconductor chip 20, but before the semiconductor chip 20 is mounted on the substrate 10. Therefore, it is possible to suppress the occurrence of cracks and chips in the semiconductor chip 20 and improve the yield.
　図４は、研磨（研削）する工程（Ｓ４０）として、封止樹脂３０のすべての厚みと半導体チップ２０の一部分の厚みとを同時に研磨（研削）する工程を示す。この場合には、グラインダ５０の回転数（単位時間当りの回転数をいう。以下同じ。）が、硬脆性を有する半導体チップ２０によって制約を受ける。研磨（研削）する効率を高めることを目的として、封止樹脂３０のすべての厚みを大きい回転数によって研磨（研削）した後に、半導体チップ２０の一部分の厚みを小さい回転数によって研磨（研削）してもよい。封止樹脂３０のすべての厚みを大きい移動速度によって研磨（研削）した後に、半導体チップ２０の一部分の厚みを小さい移動速度によって研磨（研削）してもよい。移動速度は、テーブル４０とグラインダ５０との間の相対的な移動の速度であってもよい。 FIG. 4 shows a step of simultaneously polishing (grinding) the entire thickness of the sealing resin 30 and the thickness of a part of the semiconductor chip 20 as a step of polishing (grinding) (S40). In this case, the rotational speed of the grinder 50 (referred to as the rotational speed per unit time; hereinafter the same) is limited by the semiconductor chip 20 having hard and brittleness. For the purpose of increasing the efficiency of polishing (grinding), after polishing (grinding) all the thickness of the sealing resin 30 at a large rotational speed, the thickness of a part of the semiconductor chip 20 is polished (ground) at a small rotational speed. May be. After polishing (grinding) all the thickness of the sealing resin 30 at a high moving speed, the thickness of a part of the semiconductor chip 20 may be polished (ground) at a low moving speed. The moving speed may be a relative moving speed between the table 40 and the grinder 50.
　図５は、本実施の形態に係る電子部品の製造方法における切断工程（Ｓ５０）を示す図である。図５に示すように、回転するブレート６０によって基板１０および封止樹脂３０に切り込みを入れ、樹脂封止された電子部品を製品サイズに合わせて切断（個片化）する。 FIG. 5 is a diagram showing a cutting step (S50) in the electronic component manufacturing method according to the present embodiment. As shown in FIG. 5, the substrate 10 and the sealing resin 30 are cut by the rotating blade 60, and the resin-sealed electronic component is cut (divided into pieces) according to the product size.
　次に、図６、図７を用いて、本実施の形態に係る電子部品製造装置について説明する。
　図６は、樹脂封止機構と研削機構とを１つの装置に組み込んだ例を示し、図７は、研削機構と切断機構とを１つの装置に組み込んだ例を示す。 Next, the electronic component manufacturing apparatus according to the present embodiment will be described with reference to FIGS.
FIG. 6 shows an example in which the resin sealing mechanism and the grinding mechanism are incorporated in one apparatus, and FIG. 7 shows an example in which the grinding mechanism and the cutting mechanism are incorporated in one apparatus.
　図６の例では、電子部品製造装置は、第１ないし第４ユニットＡ１～Ａ４を含む。「搬入ユニット」としての第１ユニットＡ１は、被加工物が搬入される搬入部１００と、被加工物の搬送機構１５０と、基板載置部２００とを含む。「樹脂封止ユニット」としての第２ユニットＡ２は、被加工物を回転させる回転機構３００と、半導体チップの樹脂封止を行なう樹脂封止機構４００とを含む。「研削ユニット」としての第３ユニットＡ３は、被加工物を回転させる回転機構３００と、被加工物に研磨（研削）を施す研削機構５００とを含む。「検査・搬出ユニット」としての第４ユニットＡ４は、検査用テーブル６００と、被加工物を搬出するための搬出部７００とを含む。 In the example of FIG. 6, the electronic component manufacturing apparatus includes first to fourth units A1 to A4. The first unit A1 as a “carry-in unit” includes a carry-in unit 100 into which a workpiece is carried in, a workpiece conveyance mechanism 150, and a substrate platform 200. The second unit A2 as the “resin sealing unit” includes a rotation mechanism 300 that rotates the workpiece and a resin sealing mechanism 400 that performs resin sealing of the semiconductor chip. The third unit A3 as a “grinding unit” includes a rotation mechanism 300 that rotates the workpiece, and a grinding mechanism 500 that polishes (grinds) the workpiece. The fourth unit A4 as the “inspection / unloading unit” includes an inspection table 600 and an unloading unit 700 for unloading the workpiece.
　図６において、第１ユニットＡ１と第２ユニットＡ２とは互いに着脱可能である。第２ユニットＡ２と第３ユニットＡ３とは互いに着脱可能である。第３ユニットＡ３と第４ユニットＡ４とは互いに着脱可能である。加えて、同種のユニット、例えば、「樹脂封止ユニット」としての第２ユニットを、第２ユニットＡ２ａ、Ａ２ｂ、・・・にように２個以上設けてもよい。この場合には、第２ユニットＡ２ａ、Ａ２ｂ、・・・同士が互いに着脱可能である。同種のユニットとして、「研削ユニット」としての第３ユニットＡ３を２個以上設けてもよい。この場合には、第３ユニットＡ３ａ、Ａ３ｂ、・・・同士が互いに着脱可能である。 In FIG. 6, the first unit A1 and the second unit A2 are detachable from each other. The second unit A2 and the third unit A3 are detachable from each other. The third unit A3 and the fourth unit A4 are detachable from each other. In addition, the same type of units, for example, two or more second units as “resin sealing units” may be provided as in the second units A2a, A2b,. In this case, the second units A2a, A2b,... Can be attached to and detached from each other. Two or more third units A3 as “grinding units” may be provided as the same type of unit. In this case, the third units A3a, A3b,... Can be attached to and detached from each other.
　図７の例では、電子部品製造装置は、第１ないし第４ユニットＢ１～Ｂ４を含む。「搬入ユニット」としての第１ユニットＢ１は、被加工物が搬入される搬入部１００と、被加工物の搬送機構１５０と、基板載置部２００とを含む。「研削ユニット」としての第２ユニットＢ２は、被加工物を回転させる回転機構３００と、被加工物に研磨（研削）を施す研削機構５００とを含む。「切断ユニット」としての第３ユニットＢ３は、被加工物を回転させる回転機構３００と、被加工物を切断する切断機構８００とを含む。「検査・搬出ユニット」としての第４ユニットＢ４は、検査用テーブル６００と、被加工物を搬出するための搬出部７００とを含む。 In the example of FIG. 7, the electronic component manufacturing apparatus includes first to fourth units B1 to B4. The first unit B1 as a “carry-in unit” includes a carry-in unit 100 into which a workpiece is carried in, a workpiece conveyance mechanism 150, and a substrate platform 200. The second unit B2 as the “grinding unit” includes a rotation mechanism 300 that rotates the workpiece and a grinding mechanism 500 that polishes (grinds) the workpiece. The third unit B3 as the “cutting unit” includes a rotation mechanism 300 that rotates the workpiece and a cutting mechanism 800 that cuts the workpiece. The fourth unit B4 as the “inspection / unloading unit” includes an inspection table 600 and an unloading unit 700 for unloading the workpiece.
　図７において、第１ユニットＢ１と第２ユニットＢ２とは互いに着脱可能である。第２ユニットＢ２と第３ユニットＢ３とは互いに着脱可能である。第３ユニットＢ３と第４ユニットＢ４とは互いに着脱可能である。同種のユニットを２個以上設けてもよいことは、図６の例の場合に同じである。図７の例では、同種のユニットは、「研削ユニット」としての第２ユニット、「切断ユニット」としての第３ユニットである。 In FIG. 7, the first unit B1 and the second unit B2 are detachable from each other. The second unit B2 and the third unit B3 are detachable from each other. The third unit B3 and the fourth unit B4 are detachable from each other. It is the same in the case of the example in FIG. 6 that two or more units of the same type may be provided. In the example of FIG. 7, the same type of unit is a second unit as a “grinding unit” and a third unit as a “cutting unit”.
　図７の例において、「研削ユニット」としての第２ユニットＢ２の前に、樹脂封止ユニット（図６における第２ユニットＡ２参照）を設けてもよい。この場合には、「搬入ユニット」としての第１ユニットＢ１と樹脂封止ユニットとが互いに着脱可能であり、樹脂封止ユニットと研削ユニットとが互いに着脱可能である。 In the example of FIG. 7, a resin sealing unit (see the second unit A2 in FIG. 6) may be provided in front of the second unit B2 as a “grinding unit”. In this case, the first unit B1 as the “carry-in unit” and the resin sealing unit are detachable from each other, and the resin sealing unit and the grinding unit are detachable from each other.
　図６および図７の例においては、「研削ユニット」としての第３ユニットＡ３（図６参照）または第２ユニットＢ２（図７参照）の後に、少なくとも樹脂封止に用いた封止樹脂の上面にマークを付けるマーキングユニットを設けてもよい。この場合には、研削ユニットとマーキングユニットとが互いに着脱可能である。 6 and FIG. 7, after the third unit A3 (see FIG. 6) or the second unit B2 (see FIG. 7) as a “grinding unit”, at least the top surface of the sealing resin used for resin sealing A marking unit for marking a mark may be provided. In this case, the grinding unit and the marking unit can be attached to and detached from each other.
　本実施の形態によれば、半導体チップを封止する樹脂の上面を研削する研削ユニットが、樹脂封止ユニット、個片化ユニットやマーキングユニットを含む共通の装置に事後的に組み込まれ、共通の装置から事後的に取り外される。したがって、必要に応じて、研削ユニットが事後的に組み込まれ、研削ユニットが事後的に取り外される、電子部品製造装置を提供することができる。加えて、必要に応じて、樹脂封止ユニットが事後的に増設され、樹脂封止ユニットが事後的に減設される、電子部品製造装置を提供することができる。したがって、これらの電子部品製造装置によれば、電子部品に関する需要の増減および電子部品の薄肉化の要請に事後的に対応することができる。 According to this embodiment, the grinding unit for grinding the upper surface of the resin that seals the semiconductor chip is incorporated afterwards into a common apparatus including the resin sealing unit, the singulation unit, and the marking unit. It is removed from the device afterwards. Therefore, if necessary, it is possible to provide an electronic component manufacturing apparatus in which the grinding unit is incorporated afterwards and the grinding unit is removed afterward. In addition, it is possible to provide an electronic component manufacturing apparatus in which a resin sealing unit is added afterwards and a resin sealing unit is removed afterward as needed. Therefore, according to these electronic component manufacturing apparatuses, it is possible to respond to an increase or decrease in demand for electronic components and a request for thinning of electronic components afterwards.
　なお、上記の変形例として、たとえば、樹脂封止機構と研削機構と切断機構とを１つの装置に組み込んでもよい。 Note that as a modification of the above, for example, a resin sealing mechanism, a grinding mechanism, and a cutting mechanism may be incorporated into one device.
　図８Ａ、図８Ｂは、上述の電子部品製造装置により加工される被加工物としての電子部品の断面図である。図８Ａに示すように、基板１０上に半導体チップ２０がワイヤボンディングされた電子部品であってもよいし、図８Ｂに示すように、基板１０上に半導体チップ２０がフリップチップ実装された電子部品であってもよい。 8A and 8B are cross-sectional views of an electronic component as a workpiece to be processed by the above-described electronic component manufacturing apparatus. As shown in FIG. 8A, an electronic component in which the semiconductor chip 20 is wire-bonded on the substrate 10 may be used, and as shown in FIG. 8B, an electronic component in which the semiconductor chip 20 is flip-chip mounted on the substrate 10. It may be.
　図８Ａの構造の場合、研削範囲はワイヤ２０Ａよりも上方とする必要があるため、たとえば図中「Ａ」線よりも上方となる。この場合、半導体チップ２０は露出しないが、半導体チップ２０上に搭載した冷却板などが露出する場合がある。研削後においては、封止樹脂３０の上面において連続した研磨痕が形成される。 In the case of the structure shown in FIG. 8A, the grinding range needs to be above the wire 20A, and therefore, for example, is above the “A” line in the figure. In this case, the semiconductor chip 20 is not exposed, but a cooling plate mounted on the semiconductor chip 20 may be exposed. After grinding, a continuous polishing mark is formed on the upper surface of the sealing resin 30.
　図８Ｂの構造の場合、半導体チップ２０の下方にはアンダーフィル２０Ｂが設けられる。この構造の場合、研削範囲を図中「Ｂ」よりも上方として、封止樹脂３０とともに半導体チップ２０の裏面を研削することも可能である。これにより、封止樹脂３０から半導体チップ２０の裏面が露出する。また、研削後においては、封止樹脂３０の上面と半導体チップ２０の上面とにわたって連続した研磨痕が形成される。図８Ｂの構造を適用した電子部品として、半導体素子を含む電子部品の他に、たとえばＭＥＭＳなどが挙げられる。 8B, an underfill 20B is provided below the semiconductor chip 20. In the case of this structure, it is also possible to grind the back surface of the semiconductor chip 20 together with the sealing resin 30 with the grinding range being higher than “B” in the drawing. Thereby, the back surface of the semiconductor chip 20 is exposed from the sealing resin 30. Further, after grinding, a continuous polishing mark is formed over the upper surface of the sealing resin 30 and the upper surface of the semiconductor chip 20. As an electronic component to which the structure of FIG. 8B is applied, for example, MEMS can be cited in addition to an electronic component including a semiconductor element.
　図８Ｂにおいて、アンダーフィル２０Ｂのみを封止樹脂として設けてもよい。この場合には、半導体チップの上面において連続した研磨痕が形成される。 In FIG. 8B, only the underfill 20B may be provided as the sealing resin. In this case, continuous polishing marks are formed on the upper surface of the semiconductor chip.
　１個の電子部品に複数の半導体チップ２０が含まれていてもよい。たとえば、１個の電子部品に含まれる複数の半導体チップ２０が積層されていてもよい。この場合には、最上段の半導体チップ２０上の封止樹脂３０が研磨される。得られた電子部品は、スタック型の電子部品になる。 A plurality of semiconductor chips 20 may be included in one electronic component. For example, a plurality of semiconductor chips 20 included in one electronic component may be stacked. In this case, the sealing resin 30 on the uppermost semiconductor chip 20 is polished. The obtained electronic component becomes a stack-type electronic component.
　ＰｏＰ（Ｐａｃｋａｇｅ　ｏｎ　Ｐａｃｋａｇｅ）型の電子部品においては、最上段の半導体チップ２０上の封止樹脂３０が研磨される。最上段の半導体チップ２０がフリップチップである場合には、最上段の半導体チップ２０上の封止樹脂３０と最上段の半導体チップ２０とが研磨される。 In a PoP (Package on Package) type electronic component, the sealing resin 30 on the uppermost semiconductor chip 20 is polished. When the uppermost semiconductor chip 20 is a flip chip, the sealing resin 30 on the uppermost semiconductor chip 20 and the uppermost semiconductor chip 20 are polished.
　１個の電子部品に含まれる複数のチップに半導体チップ以外のチップが含まれていてもよい。たとえば、図４に示された複数のチップが、制御用ＩＣ、パワー系デバイス、受動素子などであってもよい。この場合には、複数のチップにおける厚さなどの寸法、端子数などが異なる。図４に示された研削工程が完了した後の部品が１個の電子部品（例：パワー制御用の電子モジュール）に相当する場合がある。 A chip other than a semiconductor chip may be included in a plurality of chips included in one electronic component. For example, the plurality of chips shown in FIG. 4 may be control ICs, power devices, passive elements, and the like. In this case, dimensions such as thickness and the number of terminals in a plurality of chips are different. The part after the grinding process shown in FIG. 4 is completed may correspond to one electronic part (for example, an electronic module for power control).
　図８Ａの構造および図８Ｂの構造の場合のいずれの場合においても、連続した研磨痕は、平行に複数本並んだ連続する微細溝によって構成される。言い換えれば、電子部品の上面にいずれも微細な尾根部と谷部とが平行に複数本並んで形成される。研磨の方法によっては、いずれも微細な凹部と凸部とが複数個並んで形成される。本出願書類においては、「溝」という文言は「凹部」を含むものとする。 8A and 8B, the continuous polishing mark is composed of continuous fine grooves arranged in parallel to each other. In other words, a plurality of fine ridges and valleys are formed in parallel on the upper surface of the electronic component. Depending on the polishing method, a plurality of fine concave portions and convex portions are formed side by side. In the present application documents, the term “groove” includes “concave portion”.
　複数本並んで形成された微細溝または複数個並んで形成された凹部と凸部とによって、封止樹脂の上面における表面積、半導体チップの上面における表面積、または、封止樹脂の上面と半導体チップの上面とにおける表面積が増加する。したがって、第１に、封止樹脂の上面からの放熱性と半導体チップの上面からの放熱性とが向上する。第２に、少なくとも半導体チップの上面に放熱板を取り付ける場合において、半導体チップの上面と放熱板の下面との間の密着性および放熱性が向上する。第３に、捺印によって電子部品にマーキングする場合において、インクと封止樹脂または半導体チップとの間の密着性が向上する。第４に、プリント基板などに電子部品をマウントする工程において、電子部品を位置決めするための画像認識が反射光によって妨げられることが抑制される。 The surface area on the top surface of the sealing resin, the surface area on the top surface of the semiconductor chip, or the top surface of the sealing resin and the top surface of the semiconductor chip by a plurality of fine grooves formed side by side or a plurality of concave and convex portions formed side by side The surface area on the top surface increases. Therefore, first, heat dissipation from the upper surface of the sealing resin and heat dissipation from the upper surface of the semiconductor chip are improved. Second, in the case where a heat sink is attached to at least the upper surface of the semiconductor chip, the adhesion and heat dissipation between the upper surface of the semiconductor chip and the lower surface of the heat sink are improved. Thirdly, when marking an electronic component by stamping, the adhesion between the ink and the sealing resin or semiconductor chip is improved. Fourth, in the step of mounting the electronic component on a printed circuit board or the like, it is suppressed that the image recognition for positioning the electronic component is hindered by the reflected light.
　図９は、本実施の形態に係る電子部品の製造方法の変形例の一工程を示す断面図である。図９の変形例では、研削工程前に封止樹脂３０に溝３０Ａ（３０Ａ１，３０Ａ２）を形成している。樹脂封止した後の成形済基板は、樹脂と基板との熱膨張係数の違いから反りを生ずる場合があるが、溝３０Ａを形成することにより、上記の反りを低減させることができる。ただし、溝３０Ａは研削ライン（Ｃ）よりも浅く形成する。 FIG. 9 is a cross-sectional view showing one step of a modified example of the electronic component manufacturing method according to the present embodiment. In the modification of FIG. 9, grooves 30A (30A1, 30A2) are formed in the sealing resin 30 before the grinding process. Although the molded substrate after resin sealing may be warped due to the difference in thermal expansion coefficient between the resin and the substrate, the warpage can be reduced by forming the groove 30A. However, the groove 30A is formed shallower than the grinding line (C).
　なお、溝３０Ａの形成工程は、たとえば樹脂封止後に溝３０Ａを切断機構において形成し、研削機構で樹脂面を研削し、再び切断機構において完全に切断するなど、複数の工程の間に組み込むことができる。これにより、被加工物の搬送時間を低減することができる。 The step of forming the groove 30A is incorporated between a plurality of steps, for example, the groove 30A is formed by a cutting mechanism after resin sealing, the resin surface is ground by the grinding mechanism, and completely cut again by the cutting mechanism. Can do. Thereby, the conveyance time of a workpiece can be reduced.
　溝３０Ａの配置は、図１０に示すようなものであってもよいし、図１１に示すようなものであってもよい。図１０，図１１に示す溝形状は例示であって任意に変更可能である。 The arrangement of the grooves 30A may be as shown in FIG. 10 or as shown in FIG. The groove shapes shown in FIGS. 10 and 11 are examples and can be arbitrarily changed.
　ところで、図８Ａ、図８Ｂにおいては、複数の半導体チップ２０がそれぞれ有する端子と基板１０が有する端子とを電気的に接続する工程として、ワイヤボンディングおよびフリップチップ実装の例を示した。基板１０の上面に半導体チップ２０を実装する方法は任意であり、電子部品の品種は図８Ａ、図８Ｂの例に限定されない。 By the way, in FIG. 8A and FIG. 8B, the example of wire bonding and flip-chip mounting was shown as a process which electrically connects the terminal which each of the some semiconductor chip 20 has, and the terminal which the board | substrate 10 has. The method of mounting the semiconductor chip 20 on the upper surface of the substrate 10 is arbitrary, and the types of electronic components are not limited to the examples of FIGS. 8A and 8B.
　また、図３～図５に示す製造工程は、発明を概略的に説明するための一例にすぎない。たとえば、上述した工程の他に、樹脂封止後のアフターキュア工程やマーキング工程等が存在する。本発明は、電子部品の品種に相応する製造工程を適宜採用するものであり、上述した製造工程に係るものに限定されない。 Further, the manufacturing processes shown in FIGS. 3 to 5 are merely examples for schematically explaining the invention. For example, in addition to the processes described above, there are an after-curing process and a marking process after resin sealing. The present invention appropriately employs a manufacturing process corresponding to the type of electronic component, and is not limited to the above-described manufacturing process.
　また、半導体チップ２０と封止樹脂３０とは必ずしも一括して研削されない。製造品種によっては、半導体チップ２０のみまたは封止樹脂３０のみが研削されることもある。半導体チップ２０のみを研削する場合は、たとえば、フリップチップ実装された半導体チップ２０を対象にアンダーフィル（半導体チップ２０と基板１０との間に樹脂を充填させること）を施した後、半導体チップ２０を研削可能である。 Further, the semiconductor chip 20 and the sealing resin 30 are not necessarily ground together. Depending on the product type, only the semiconductor chip 20 or only the sealing resin 30 may be ground. When grinding only the semiconductor chip 20, for example, after underfilling (filling a resin between the semiconductor chip 20 and the substrate 10) is performed on the semiconductor chip 20 that is flip-chip mounted, the semiconductor chip 20 is then ground. Can be ground.
　本発明に係る電子部品の製造工程の順序は、製造品種によって適宜変更される。本実施の形態では、樹脂封止機構または切断機構と研削機構とを１つの装置に組み込んだ（ビルドインした）例を示したが、研削機構と組み合わせる工程は製造品種に応じて適宜変更可能である。 The order of the manufacturing process of the electronic component according to the present invention is appropriately changed depending on the manufacturing type. In the present embodiment, an example in which the resin sealing mechanism or the cutting mechanism and the grinding mechanism are incorporated (built-in) in one apparatus has been described. However, the process of combining with the grinding mechanism can be appropriately changed according to the type of manufacture. .
　本実施の形態に係る電子部品の製造方法によれば、半導体チップ２０を基板１０に実装した後に、封止樹脂３０の厚みまたは半導体チップ２０の厚みのうち少なくとも一方を減じる研削工程を行なう。このことにより、半導体チップ２０を基板１０に実装する前に半導体ウエハを研削する工程を省略することが可能となる。この結果、半導体チップ２０に割れや欠けが生じることを抑制して、歩留まりを向上させることができる。半導体ウエハを個片化する前に半導体ウエハを研削する工程を残す場合においても、半導体ウエハを研削する量（厚み）を低減できる。したがって、第１に、半導体ウエハの厚みを搬送時などにおいて取り扱いやすい厚みにすることによって、歩留まりを向上させることができる。第２に、半導体ウエハを研削する工数を低減することができる。 According to the method of manufacturing an electronic component according to the present embodiment, after the semiconductor chip 20 is mounted on the substrate 10, a grinding process is performed to reduce at least one of the thickness of the sealing resin 30 or the thickness of the semiconductor chip 20. This makes it possible to omit the step of grinding the semiconductor wafer before mounting the semiconductor chip 20 on the substrate 10. As a result, it is possible to suppress the occurrence of cracks and chips in the semiconductor chip 20 and improve the yield. Even when the step of grinding the semiconductor wafer is left before the semiconductor wafer is singulated, the amount (thickness) of grinding the semiconductor wafer can be reduced. Therefore, first, the yield can be improved by making the thickness of the semiconductor wafer easy to handle during transportation. Secondly, the number of steps for grinding the semiconductor wafer can be reduced.
　また、半導体チップ２０を封止する封止樹脂３０の上面を研削する研削機構５００を前後の工程を実施する機構に組み込むことにより、電子部品の製造工場において占有面積が低減され、工場床面積に余裕が生じる。 Further, by incorporating the grinding mechanism 500 for grinding the upper surface of the sealing resin 30 for sealing the semiconductor chip 20 into the mechanism for performing the preceding and following processes, the occupation area in the electronic component manufacturing factory is reduced, and the factory floor area is reduced. There is room.
　本発明に係る電子部品は、半導体チップを含む電子部品に限定されない。電子部品の第１の例として、表面弾性波フィルタが挙げられる。圧電機能を有する（圧電効果を奏する）基板の一面を複数の領域に区分し、相対向する櫛歯状の金属電極を各領域に形成する。基板の一面を樹脂封止し、封止樹脂の上面を研磨し、基板を各領域に個片化する。複数の領域にそれぞれ相当する複数の表面弾性波フィルタを製造することができる。この場合には、各領域における櫛歯状の金属電極が、表面弾性波フィルタとして機能する機能要素に相当する。 The electronic component according to the present invention is not limited to an electronic component including a semiconductor chip. A first example of the electronic component is a surface acoustic wave filter. One surface of a substrate having a piezoelectric function (having a piezoelectric effect) is divided into a plurality of regions, and opposing comb-like metal electrodes are formed in each region. One surface of the substrate is resin-sealed, the upper surface of the sealing resin is polished, and the substrate is separated into each region. A plurality of surface acoustic wave filters corresponding to a plurality of regions can be manufactured. In this case, the comb-like metal electrode in each region corresponds to a functional element that functions as a surface acoustic wave filter.
　電子部品の第１の例として、マイクロミラーアレイが挙げられる。シリコン、ガラス、セラミックス等からなる基板の一面を複数の領域に区分する。基板の一面に、蒸着、スパッタリングなどによって金属薄膜を形成する。その金属薄膜上に、フォトリソグラフィー、電鋳などの工程を組み合わせることによって、微小な複数の柱状金属を形成する。基板の一面を樹脂封止した後に、封止樹脂の上面を研磨して複数の柱状金属の断面を鏡面状に露出させる。その後に基板を各領域に個片化する。柱状金属の露出面によってレーザ光などの光を反射する。複数の領域にそれぞれ相当する複数のマイクロミラーアレイを製造することができる。この場合には、各領域における複数の柱状金属が、マイクロミラーアレイとして機能する機能要素に相当する。複数の柱状金属同士の間における基板を、エッチングなどによって適当な厚みだけ除去してもよい。 A first example of an electronic component is a micromirror array. One surface of a substrate made of silicon, glass, ceramics, or the like is divided into a plurality of regions. A metal thin film is formed on one surface of the substrate by vapor deposition, sputtering, or the like. A plurality of minute columnar metals are formed on the metal thin film by combining processes such as photolithography and electroforming. After resin-sealing one surface of the substrate, the upper surface of the sealing resin is polished to expose the cross-sections of the plurality of columnar metals in a mirror shape. Thereafter, the substrate is divided into each region. Light such as laser light is reflected by the exposed surface of the columnar metal. A plurality of micromirror arrays corresponding to a plurality of regions can be manufactured. In this case, the plurality of columnar metals in each region correspond to functional elements that function as a micromirror array. The substrate between the plurality of columnar metals may be removed by an appropriate thickness by etching or the like.
　以上、本発明の実施の形態について説明したが、今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　１０　基板、１０Ａ　はんだボール、２０　半導体チップ、２０Ａ　ワイヤ、２０Ｂ　アンダーフィル、３０　封止樹脂、３０Ａ，３０Ａ１，３０Ａ２　溝部、４０　テーブル、４０Ａ　凹部、５０　グラインダ、６０　ブレード、１００　搬入部、１５０　搬送機構、２００　基板載置部、３００　回転機構、４００　樹脂封止機構、５００　研削機構、６００　検査用テーブル、７００　搬出部、８００　切断機構。 10 substrate, 10A solder ball, 20 semiconductor chip, 20A wire, 20B underfill, 30 sealing resin, 30A, 30A1, 30A2 groove, 40 table, 40A recess, 50 grinder, 60 blade, 100 carry-in part, 150 transport mechanism, 200 substrate mounting part, 300 rotation mechanism, 400 resin sealing mechanism, 500 grinding mechanism, 600 inspection table, 700 unloading part, 800 cutting mechanism.

Claims (14)

  1. 　複数の機能要素を基板に設ける工程と、
    　前記基板に形成された前記複数の機能要素を樹脂封止する工程と、
    　前記樹脂封止に用いた樹脂の上面を研削して前記樹脂の厚みを減じる工程とを備えた、電子部品の製造方法。     Providing a plurality of functional elements on the substrate;
    A step of resin-sealing the plurality of functional elements formed on the substrate;
    And a step of grinding the upper surface of the resin used for the resin sealing to reduce the thickness of the resin.
  2. 　複数の半導体チップを基板に実装する工程と、
    　前記基板に実装された前記複数の半導体チップを樹脂封止する工程と、
    　前記樹脂封止に用いた樹脂の上面を研削して前記樹脂の厚みを減じる工程とを備えた、電子部品の製造方法。     Mounting a plurality of semiconductor chips on a substrate;
    A step of resin-sealing the plurality of semiconductor chips mounted on the substrate;
    And a step of grinding the upper surface of the resin used for the resin sealing to reduce the thickness of the resin.
  3. 　前記半導体チップはフリップチップボンディングにより前記基板に実装され、
    　前記半導体チップが露出するように前記樹脂の上面が研削される、請求項２に記載の電子部品の製造方法。     The semiconductor chip is mounted on the substrate by flip chip bonding,
    The method of manufacturing an electronic component according to claim 2, wherein an upper surface of the resin is ground so that the semiconductor chip is exposed.
  4. 　前記樹脂の上面と前記半導体チップの上面とを研削することによって前記樹脂の厚みと前記半導体チップの厚みとを減じる工程を備えた、請求項３に記載の電子部品の製造方法。 4. The method of manufacturing an electronic component according to claim 3, further comprising a step of reducing the thickness of the resin and the thickness of the semiconductor chip by grinding the upper surface of the resin and the upper surface of the semiconductor chip.
  5. 　複数の半導体チップを基板に実装する工程と、
    　前記半導体チップの上面を研削して前記半導体チップの厚みを減じる工程とを備えた、電子部品の製造方法。     Mounting a plurality of semiconductor chips on a substrate;
    And a step of grinding the upper surface of the semiconductor chip to reduce the thickness of the semiconductor chip.
  6. 　第１の機能を有する第１の特定機構と、
    　基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構とを備え、
    　前記第１の機能は、前記基板上に設けられた前記複数の機能要素を樹脂封止する機能である、電子部品製造装置。     A first specific mechanism having a first function;
    A grinding mechanism for grinding the upper surface of the resin that seals a plurality of functional elements provided on the substrate,
    The electronic component manufacturing apparatus, wherein the first function is a function of resin-sealing the plurality of functional elements provided on the substrate.
  7. 　基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構と、
    　第２の機能を有する第２の特定機構とを備え、
    　前記第２の機能は、前記基板および前記樹脂を切断して個片化された電子部品を作製する機能である、電子部品製造装置。     A grinding mechanism for grinding the upper surface of the resin sealing a plurality of functional elements provided on the substrate;
    A second specific mechanism having a second function,
    The second function is an electronic component manufacturing apparatus that is a function of cutting the substrate and the resin to produce an individual electronic component.
  8. 　第１の機能を有する第１の特定機構と、
    　基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構と、
    　第２の機能を有する第２の特定機構とを備え、
    　前記第１の機能は、前記基板上に設けられた前記複数の機能要素を樹脂封止する機能であり、
    　前記第２の機能は、前記基板および前記樹脂を切断して個片化された電子部品を作製する機能である、電子部品製造装置。     A first specific mechanism having a first function;
    A grinding mechanism for grinding the upper surface of the resin sealing a plurality of functional elements provided on the substrate;
    A second specific mechanism having a second function,
    The first function is a function of resin-sealing the plurality of functional elements provided on the substrate,
    The second function is an electronic component manufacturing apparatus that is a function of cutting the substrate and the resin to produce an individual electronic component.
  9. 　基板上に設けられた複数の機能要素を封止する樹脂の上面を研削する研削機構と、
    　第３の機能を有する第３の特定機構とを備え、
    　前記第３の機能は、少なくとも前記樹脂の上面にマークを付ける機能である、電子部品製造装置。     A grinding mechanism for grinding the upper surface of the resin sealing a plurality of functional elements provided on the substrate;
    A third specific mechanism having a third function,
    The third function is an electronic component manufacturing apparatus that is a function of marking at least an upper surface of the resin.
  10. 　前記第１ないし第３の特定機構と前記研削機構とは互いに着脱可能である、請求項６～９のいずれか１項に記載の電子部品製造装置。 10. The electronic component manufacturing apparatus according to claim 6, wherein the first to third specific mechanisms and the grinding mechanism are detachable from each other.
  11. 　基板と、
    　前記基板上に設けられた複数の機能要素と、
    　前記複数の機能要素を封止する封止樹脂と、
    　前記封止樹脂の上面において連続する溝とを備えた、電子部品。     A substrate,
    A plurality of functional elements provided on the substrate;
    A sealing resin for sealing the plurality of functional elements;
    An electronic component comprising a continuous groove on the upper surface of the sealing resin.
  12. 　基板と、
    　前記基板上に設けられた複数の機能要素と、
    　前記複数の機能要素の上面を露出させながら前記複数の機能要素を封止する封止樹脂と、
    　前記封止樹脂の上面と前記複数の機能要素の上面とにわたって連続する溝とを備えた、電子部品。     A substrate,
    A plurality of functional elements provided on the substrate;
    A sealing resin that seals the plurality of functional elements while exposing the top surfaces of the plurality of functional elements;
    An electronic component comprising a groove continuous over the top surface of the sealing resin and the top surfaces of the plurality of functional elements.
  13. 　基板と、
    　前記基板上に実装された半導体チップと、
    　前記半導体チップを封止する封止樹脂と、
    　前記封止樹脂の上面において連続する溝とを備えた、電子部品。     A substrate,
    A semiconductor chip mounted on the substrate;
    A sealing resin for sealing the semiconductor chip;
    An electronic component comprising a continuous groove on the upper surface of the sealing resin.
  14. 　基板と、
    　前記基板上に実装された半導体チップと、
    　前記半導体チップの上面を露出させながら前記半導体チップを封止する封止樹脂と、
    　前記封止樹脂の上面と前記半導体チップの上面とにわたって連続する溝とを備えた、電子部品。     A substrate,
    A semiconductor chip mounted on the substrate;
    A sealing resin for sealing the semiconductor chip while exposing an upper surface of the semiconductor chip;
    An electronic component comprising a groove continuous over the upper surface of the sealing resin and the upper surface of the semiconductor chip.
PCT/JP2016/073389 2015-12-18 2016-08-09 Electronic component, method for manufacturing same, and electronic component manufacturing device WO2017104169A1 (en)

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