WO2017084229A1 - 通用串行输入输出的数据传输方法 - Google Patents

通用串行输入输出的数据传输方法 Download PDF

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Publication number
WO2017084229A1
WO2017084229A1 PCT/CN2016/077346 CN2016077346W WO2017084229A1 WO 2017084229 A1 WO2017084229 A1 WO 2017084229A1 CN 2016077346 W CN2016077346 W CN 2016077346W WO 2017084229 A1 WO2017084229 A1 WO 2017084229A1
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Prior art keywords
data
expander
page
output
universal serial
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PCT/CN2016/077346
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English (en)
French (fr)
Inventor
卢俊杰
胡翔竣
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英业达科技有限公司
英业达股份有限公司
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Priority to US15/743,611 priority Critical patent/US20180246835A1/en
Publication of WO2017084229A1 publication Critical patent/WO2017084229A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0036—Small computer system interface [SCSI]

Definitions

  • the present invention relates to a data transmission method for universal serial input and output, and more particularly to a data transmission method between an expander and a target device connected by a universal serial input/output bus.
  • the current technology generally uses a Universal Serial Input/Output (SGPIO) bus or an Inter-Integrated Circuit (I2C), Universal Asynchronous A data transmission between an expander or an initiator and a target device is performed by a Universal Asynchronous Receiver Transmitter (UART).
  • SGPIO Serial Input/Output
  • I2C Inter-Integrated Circuit
  • UART Universal Asynchronous Receiver Transmitter
  • the target device when the data is transmitted between the expander and the target device by using the universal serial input/output bus, in the existing universal serial input/output bus architecture, a certain number of time slots are usually allocated and defined in advance.
  • the target device the target device transmits the corresponding data content from the defined time slot to the expander according to the defined time slot.
  • the number of pre-allocated and defined time slots limits the amount of data that the target device transmits to the expander. For example, if 60 time slots are defined in advance for the target device to transmit data to the expander, the target device can only transmit 60 different data contents to the expander, and no more data can be added.
  • the present invention provides a data transmission method for universal serial input and output, thereby solving the problem that the amount of data transmitted by the target device in the prior art is limited.
  • the data transmission method of the universal serial input and output disclosed by the present invention is applicable to an expander and a target device connected by a universal serial input/output bus.
  • the universal serial input/output bus has at least a data output line and a data read line.
  • the expander outputs a page indication signal to the target device via the data output line, and the page indication signal indicates the page address.
  • the target device searches for the paging data indicated by the paging address according to the paging instruction signal.
  • the target device outputs the page address and the page data to the expander via the data read line.
  • the expander reads the content transmitted via the data read line.
  • the expander receives the paged data when the expander determines that the content transmitted by the data read line has a paged address.
  • the spreader actively outputs the paging indication signal to the target device, and the target device further divides the paging under the paging address according to the paging address indicated by the paging indication signal.
  • the data is transmitted to the spreader to increase the amount of data that the target device transmits to the expander via the universal serial input/output bus.
  • the communication can be realized by the universal serial input/output bus between the expander and the target device.
  • FIG. 1 is a schematic diagram of a universal serial input/output bus electrical connection expander and a target device according to an embodiment of the invention.
  • FIG. 2 is a schematic diagram of a slot assignment of a universal serial input/output bus according to an embodiment of the invention.
  • FIG. 3 is a flow chart showing the steps of a data transmission method for universal serial input and output according to an embodiment of the invention.
  • FIG. 4 is a flow chart showing the steps of a data transmission method for universal serial input and output according to another embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a universal serial input/output bus electrical connection expander and a target device according to an embodiment of the invention.
  • FIG. 2 is a schematic diagram of a universal string according to an embodiment of the invention.
  • FIG. 3 is a flow chart showing the steps of a data transmission method for universal serial input and output according to an embodiment of the invention.
  • the data transmission method of the universal serial input and output of the present invention is applicable to an expander 20 and a target device connected by a Serial General Purpose Input Output (SGPIO) bus 10.
  • SGPIO Serial General Purpose Input Output
  • the expander 20 is, for example, a serial small computer system interface expander, a microprocessor, an embedded controller, a baseboard management controller (BMC), or other suitable device.
  • BMC baseboard management controller
  • the target device 30, such as a backplane module and a disk array device, includes a hard disk, a backup battery, a control unit and a fan, and a simple disk bundle (JBOD, also known as a disk cluster or a simple drive bundle).
  • JBOD also known as a disk cluster or a simple drive bundle.
  • Redundant Array of Independent Disks (RAID) large disk array group Programmable Logic Device (PLD), Complex PLD (CPLD), field programmable Field-programmable gate array (FPGA) or other suitable device.
  • PLD Programmable Logic Device
  • CPLD Complex PLD
  • FPGA field programmable Field-programmable gate array
  • the universal serial input/output bus 10 has a data output line SDataOut, a data read line SDataIn, a frequency signal line SClock, and a load signal line SLoad.
  • the expander 20 and the target device 30 respectively have corresponding frequency pins, load pins, data input pins and data output pins, and the pins corresponding to the expander 20 and the target device 30 are respectively passed through the universal serial input/output bus 10
  • the data output line SDataOut, the data read line SDataIn, the frequency signal line SClock, and the load signal line SLoad are electrically connected.
  • the expander 20 is defined as the SGPIO initiator of the universal serial input/output bus 10
  • the target device 30 is defined as the target of the universal serial input/output bus 10 (SGPIO Target).
  • SGPIO Target the target of the universal serial input/output bus 10
  • the frequency signal line SClock of the universal serial input/output bus 10 is used to provide the expander 20 to transmit the frequency signal to the target device 30, and the load signal line SLoad provides the expander 20 to transmit the load signal to the target device 30, and the data output line SDataOut provides the expander. 20 sends a signal to the target device 30, and the data read line SDataIn provides the target device 30 to send a signal to the expander 20.
  • the frequency signal is used to define the transmission frequency of the universal serial input/output bus 10.
  • the load signal is a frame that defines the data output line SDataOut or the data read line SDataIn to transmit data. For example, a transmission frame is a load signal that is triggered for 8 clock cycles to the falling edge of the frequency waveform after the rising edge of the frequency waveform.
  • step S401 the expander 20 outputs a page indication signal to the target device 30 via the data output line SDataOut, which is indicated by the page indication signal.
  • a paged address In step S403, the target device 30 searches for the page data indicated by the page address according to the page indication signal.
  • step S405 the target device 30 outputs the page address and the page data to the expander 20 via the data read line SDataIn.
  • step S407 the expander 20 reads the content transmitted via the data read line SDataIn.
  • step S409 when the expander 20 judges that the content transmitted by the data read line SDataIn has a page break address, the expander 20 receives the page data.
  • the universal serial input/output bus 10 first allocates a plurality of time slots of the data output line SDataOut and the data read line SDataIn. For example, eight time slots in the data output line SDataOut are allocated to transmit the page break instruction signal, and eight time slots in the data read line SDataIn are allocated to transfer the page address, and the other eight time slots are used to transfer the page data under the page address.
  • the expander 20 is a microprocessor and the target device is a CPLD. When data is to be transferred between the microprocessor and the CPLD, the microprocessor first transmits 8 data output lines SDataOut.
  • the time slot transmits a paging indication signal to the CPLD to instruct the CPLD to provide the data content required by the microprocessor.
  • the CPLD receives the paging instruction signal, the CPLD switches to the paging under the paging address according to the paging address indicated by the paging instruction signal, and transmits the paging data under the paging address and the paging address to the micro through the data reading line SDataIn. processor.
  • the paging instruction signal is an 8-bit signal, so 8 time slots are allocated for transmission.
  • the data read line SDataIn cooperates with the 8 bits of the page pointer signal, and also allocates 8 time slots to the CPLD to transmit the page address, and the other 8 time slots are provided to the CPLD to transmit the page data.
  • the microprocessor actively requests data from the CPLD and specifies the required data content through the paging instruction signal, instead of the way the CPLD directly transmits data to the microprocessor, the CPLD and the microprocessor can
  • the data content transmitted is more diverse. For example, when the CPLD transmits data to the microprocessor through the 16 time slots of the data read line SDataIn, only 16 data can be transmitted to the microprocessor.
  • the microprocessor actively requests data from the CPLD, and transmits the paging instruction signal and the eight time slots of the data read line SDataIn through the eight time slots of the data output line SDataOut to transmit the paged data.
  • the CPLD can provide 8 ways. ⁇ 2 8 pens or more of data to the microprocessor.
  • the 8 ⁇ 28 CPLD data each pen 8 to 28 classified pagination addresses when the microprocessor CPLD receives paging data in the active claim 28 wherein pagination addresses in a paged address
  • the CPLD transmits the paging address required by the microprocessor and the eight data under the paging address to the microprocessor from the 16 time slots of the data reading line SDataIn.
  • the CPLD may have more or less data under each page address, for example, when the CPLD has 16 page data under one page address, when the microprocessor requests the CPLD to provide the page address.
  • CPLD batches 16 paged data to the microprocessor. In other words, the CPLD can transfer 16 paged data under the page address to the microprocessor through two transfers.
  • the CPLD can output all the paging data under the paging address to the microprocessor once or in batches according to the paging indication signal output by the microprocessor.
  • the microprocessor can also pass through the microprocessor.
  • the paging data of the lower portion of the CPLD output page is specified, for example, the other time slot transmission request signal is assigned to be specified, which is not limited in this embodiment.
  • the embodiment does not limit the data having the same number of pens under each paging address. Those skilled in the art can configure the number of paging data under the paging address according to actual needs.
  • the number of time slots for transmitting the page indication signal by the data output line SDataOut and the number of time slots for transmitting the page address and the page data in the data read line SDataIn are for convenience of description, and are not intended to limit the present invention. Other possible implementations.
  • FIG. 4 is a general string according to another embodiment of the present invention.
  • the expander 20 outputs a page indication signal to the target device 30 via the data output line SDataOut according to the frequency signal and the load signal.
  • the expander 20 depends on the period of the frequency signal and the signal of the load signal.
  • the frame transmits a paging indicator signal.
  • the paging indicator signal is 8 bits
  • the expander 20 outputs the first bit at the rising edge of the load signal and transmits one bit in each of the eight periods of the frequency signal.
  • step S503 the target device 30 determines the paging address indicated by the paging instruction signal, and in step S405, searches for the paging data indicated by the paging address according to the paging instruction signal.
  • step S507 the target device 30 outputs the page address and the page data to the expander 20 via the time slot allocated by the data read line SDataIn.
  • step S509 the expander 20 reads the page address of the content transmitted via the data read line SDataIn, and in step S511, determines whether the page address of the content of the data read line SDataIn matches the page break instruction output to the target device 30.
  • the paging address indicated by the signal is the paging address indicated by the signal.
  • the expander 20 receives the page data transferred by the data read line SDataIn in step S513. That is, after the target device 30 transmits the page address and the page data to the expander 20, the expander 20 further judges the time slot in the data read line SDataIn for transmitting the page address, and whether the paged address transmitted is For the requested paging address, if the paging address matches, the expander 20 receives the paging data transmitted by the data reading line SDataIn.
  • the expander 20 ignores the content transmitted by the data read line SDataIn in step S515.
  • the embodiments of the present invention provide a data transmission method for universal serial input and output, which is suitable for use in an extension machine and a target device connected by a universal serial input/output bus.
  • the pager indication signal is actively outputted to the target device by the expander, so that the target device searches for the paged data under the paged address according to the page address indicated by the page indication signal, and transmits the paged data to the expander. According to this, the amount of data that the target device can transmit to the expander via the universal serial input/output bus is increased.
  • the expander can output the paged data under the paged address to the expander once or batch, and when the expander or the target device does not support the transport interface such as I 2 C or UART,
  • the data communication between the expander and the target device can be realized not only through the universal serial input/output bus, but also the universal serial input/output bus can transmit a variety of different data contents.

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Abstract

本发明提供一种通用串行输入输出的数据传输方法，适用于以通用串行输入输出总线连接的扩展器和目标装置。通用串行输入输出总线至少具有数据输出线及数据读取线。扩展器经由数据输出线输出分页指示信号至目标装置，分页指示信号指示分页地址。目标装置依据分页指示信号，查找分页地址指示的分页数据。目标装置经由数据读取线将分页地址和分页数据输出至扩展器。扩展器读取经由数据读取线传送的内容。当扩展器判断数据读取线传送的内容具有分页地址时，扩展器接收分页数据。

Description

通用串行输入输出的数据传输方法 技术领域
本发明关于一种通用串行输入输出的数据传输方法，特别是涉及一种以通用串行输入输出总线连接的扩展器和目标装置之间的数据传输方法。
背景技术
随着科技的发展，电子装置之间的数据传输速度与数据量的需求也随之成长。为了因应大量的数据快速地在电子装置之间传输，目前技术上多会采用通用串行输入输出(Serial General Purpose Input Output，SGPIO)总线或内部整合电路(Inter-Integrated Circuit，I2C)、通用异步收发传输器(Universal Asynchronous Receiver Transmitter，UART)等进行扩展器(Expander)或启动装置(Initiator)与目标装置(Target)之间的数据传输。
然而，当以通用串行输入输出总线进行扩展器与目标设备之间的数据传输时，现有的通用串行输入输出总线架构中，通常会预先分配与定义一定数量的时槽(timeslot)给目标设备，目标设备再根据定义好的时槽，将对应的数据内容从定义的时槽传送到扩展器。如此一来，预先分配和定义好的时槽数量就限制了目标设备传输到扩展器的数据数量。例如事先定义60个时槽让目标设备传送数据到扩展器，目标设备就只能传送60个不同的数据内容到扩展器，而无法再增加更多的数据量。
发明内容
鉴于以上所述现有技术的缺点，本发明在于提供一种通用串行输入输出的数据传输方法，藉以解决先前技术中目标设备传输数据量受到限制的问题。
为实现上述目的及其他相关目的，本发明所揭露的通用串行输入输出的数据传输方法，适用于以通用串行输入输出总线连接的扩展器和目标装置。通用串行输入输出总线至少具有数据输出线及数据读取线。扩展器经由数据输出线输出分页指示信号至目标装置，分页指示信号指示分页地址。目标装置依据分页指示信号，查找分页地址指示的分页数据。目标装置经由数据读取线将分页地址和分页数据输出至扩展器。扩展器读取经由数据读取线传送的内容。当扩展器判断数据读取线传送的内容具有分页地址时，扩展器接收分页数据。
根据上述本发明所揭露的通用串行输入输出的数据传输方法，藉由扩展器主动输出分页指示信号给目标装置，目标装置再依据分页指示信号指示的分页地址，将分页地址下的分页 数据传输给扩暂器，据以增加目标装置藉由通用串行输入输出总线传输给扩展器的数据量。当部分扩展器或目标装置不支持如I2C或UART的传输接口时，扩展器和目标装置之间仍可利用通用串行输入输出总线来实现的通讯。
以上有关于本发明揭露的内容说明及以下的之实施方式的说明用以示范与解释本发明的精神与原理，并且提供本发明的专利权利要求主张的范围更进一步之解释。
附图说明
图1为根据本发明一实施例所绘示的通用串行输入输出总线电性连接扩展器和目标装置的示意图。
图2为根据本发明一实施例所绘示的通用串行输入输出总线时槽分配的示意图。
图3为根据本发明一实施例所绘示的通用串行输入输出的数据传输方法的步骤流程图。
图4为根据本发明另一实施例所绘示的通用串行输入输出的数据传输方法的步骤流程图。
组件标号说明
10 通用串行输入输出总线
20 扩展器
30 目标装置
SClock 频率信号线
SLoad 负载信号线
SDataOut 数据输出线
SDataIn 数据读取线
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图 式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参照图1，图1为根据本发明一实施例所绘示的通用串行输入输出总线电性连接扩展器和目标装置的示意图，图2为根据本发明一实施例所绘示的通用串行输入输出总线时槽分配的示意图，图3为根据本发明一实施例所绘示的通用串行输入输出的数据传输方法的步骤流程图。如图所示，本发明通用串行输入输出的数据传输方法，适用于以通用串行输入输出(Serial General Purpose Input Output，SGPIO)总线10连接的扩展器(expander)20和目标装置(target)30。扩展器20例如序列式小型计算机系统接口扩展器、微处理器(microcontroller)、嵌入式处理器(embedded controller)、基板管理控制器(baseboard management controller，BMC)或其他合适的装置。目标装置30例如背板模块(backplane module)、磁盘阵列装置包括硬盘、备用电池、控制单元及风扇、简单磁盘捆绑(Just Bundle Of Disks，JBOD，亦称磁盘簇或简单驱动捆绑)大型硬盘阵列组、独立硬盘冗余阵列(RAID,Redundant Array of Independent Disks，RAID)大型硬盘阵列组、可编程逻辑器件(Programmable Logic Device，PLD)、复杂式可编程逻辑器件(Complex PLD，CPLD)、现场可编程门阵列(Field-programmable gate array，FPGA)或其他合适的装置。
通用串行输入输出总线10具有数据输出线SDataOut、数据读取线SDataIn、频率信号线SClock及负载信号线SLoad。扩展器20和目标装置30分别具有对应的频率脚位、负载脚位、数据输入脚位及数据输出脚位，扩展器20和目标装置30对应的脚位分别藉由通用串行输入输出总线10的数据输出线SDataOut、数据读取线SDataIn、频率信号线SClock及负载信号线SLoad电性连接。扩展器20定义为通用串行输入输出总线10的起始者(SGPIO initiator)，而目标装置30定义为通用串行输入输出总线10的目标者(SGPIO Target)。于所属技术领域具有通常知识者应可理解通用串行输入输出总线10、扩展器20和目标装置30之间的连接方式，于此不再加以赘述。
通用串行输入输出总线10的频率信号线SClock用以提供扩展器20传送频率信号至目标装置30，而负载信号线SLoad提供扩展器20传送负载信号至目标装置30，数据输出线SDataOut提供扩展器20发送信号至目标装置30，数据读取线SDataIn提供目标装置30发送信号至扩展器20。频率信号用以定义通用串行输入输出总线10的传输频率。负载信号是定义数据输出线SDataOut或数据读取线SDataIn传输数据的框架，例如一个传输框架是负载信号在频率波形的上升边缘后触发8个时钟周期至频率波形的下降边缘。
当扩展器20和目标装置30透过通用串行输入输出总线10进行数据传输时，于步骤S401中，扩展器20经由数据输出线SDataOut输出分页指示信号至目标装置30，藉由分页指示信号指示一个分页地址。于步骤S403中，目标装置30依据分页指示信号，查找分页地址指示的分页数据。于步骤S405中，目标装置30经由数据读取线SDataIn将分页地址和分页数据输出至扩展器20。于步骤S407中，扩展器20读取经由数据读取线SDataIn传送的内容。于步骤S409中，当扩展器20判断数据读取线SDataIn传送的内容具有分页地址时，扩展器20接收分页数据。
更详细来说，通用串行输入输出总线10会先分配数据输出线SDataOut和数据读取线SDataIn的多个时槽。例如分配数据输出线SDataOut中的8个时槽来传输分页指示信号，而分配数据读取线SDataIn中的8个时槽来传输分页地址，另8个时槽来传输分页地址下的分页数据。在实际的例子中，以扩展器20为微处理器，目标装置为CPLD来说，当微处理器和CPLD之间要进行数据传输时，微处理器会先透过数据输出线SDataOut的8个时槽传输分页指示信号给CPLD，以指示CPLD提供微处理器所需要的数据内容。当CPLD接收到分页指示信号时，CPLD依据分页指示信号指示的分页地址，切换到分页地址下的分页，并将分页地址和分页地址下的分页数据一并藉由数据读取线SDataIn传送给微处理器。
于本实施例中，分页指示信号为8位元的信号，因此分配8个时槽来传送。而数据读取线SDataIn配合分页指示信号的8个位元，亦分配了8个时槽给CPLD来传送分页地址，而另外的8个时槽提供给CPLD来传送分页数据。
据此，微处理器透过主动地向CPLD要求数据，并透过分页指示信号来指定所需要的数据内容，取代以往CPLD直接传送数据给微处理器的方式，CPLD和微处理器之间可以传输的数据内容更为多元。举例来说，以往CPLD透过数据读取线SDataIn的16个时槽传输数据给微处理器时，只能传送16笔数据给微处理器。而微处理器主动地向CPLD要求数据，并透过数据输出线SDataOut的8个时槽来传送分页指示信号和数据读取线SDataIn的8个时槽来传送分页数据的方式，CPLD可提供8×28笔或更多的数据给微处理器。
也就是说，CPLD将8×28个数据，每8笔数据分类至28个分页地址中，当CPLD收到微处理器主动要求28个分页地址中的其中一个分页地址下的分页数据时，CPLD将微处理器要求的该分页地址和该分页地址下的8笔数据一并从数据读取线SDataIn的16个时槽传输数据给微处理器。于其他实施例中，CPLD的每个分页地址下亦可以有更多或更少笔的数据，例如CPLD的一个分页地址下具有16笔分页数据时，当微处理器要求CPLD提供该分页地址下的分页数据时，CPLD批次地将16笔分页数据输出至微处理器，换言之，CPLD可以透过两 次的传送，将分页地址下的16笔分页数据传送给微处理器。
于本实施例中，CPLD可以依据微处理器输出的分页指示信号将分页地址下的所有分页数据一次地或分批地输出给微处理器，于其他实施例中，微处理器亦可以透过其他合适的方式，指定CPLD输出分页下部分的分页数据，例如分配其他时槽传送要求信号来指定，本实施例不予限制。再者，本实施例亦不限制每个分页地址下具有相同数量笔的数据，于所属技术领域具有通常知识者可以依据实际的需求而配置分页地址下的分页数据数量。此外，前述实施例中，数据输出线SDataOut传输分页指示信号的时槽数量和数据读取线SDataIn中用以传输分页地址和分页数据的时槽数量仅为方便说明之用，并非加以限制本发明其他可行的实施方式。
为了更清楚说明本发明通用串行输入输出的数据传输方法，兹举另一实施例说明，请一并参照图1和图4，图4为根据本发明另一实施例所绘示的通用串行输入输出的数据传输方法的步骤流程图。如图4所示，于步骤S501中，扩展器20依据频率信号及负载信号，经由数据输出线SDataOut输出分页指示信号至目标装置30，换言之，扩展器20依据频率信号的周期以及负载信号的信号框架，传送分页指示信号，当分页指示信号为8位元时，扩展器20在负载信号上升边缘输出第一个位元，并在频率信号的八个周期各别传输一个位元。
于步骤S503中，目标装置30判断分页指示信号指示的分页地址，并于步骤S405中，依据分页指示信号，查找分页地址指示的分页数据。接着，于步骤S507中，目标装置30将分页地址和分页数据经由数据读取线SDataIn分配的时槽输出至扩展器20。于步骤S509中，扩展器20读取经由数据读取线SDataIn传送的内容的分页地址，并于步骤S511中，判断数据读取线SDataIn传送内容的分页地址是否符合输出给目标装置30的分页指示信号所指示的分页地址。当数据读取线SDataIn传送内容的分页地址符合输出给目标装置30的分页地址时，于步骤S513中，扩展器20接收数据读取线SDataIn传送的分页数据。也就是说，当目标装置30将分页地址和分页数据传送给扩展器20后，扩展器20会更进一步判断数据读取线SDataIn中用以传输分页地址的时槽，其所传输的分页地址是否为要求的分页地址，若分页地址符合时，扩展器20才接收数据读取线SDataIn传输的分页数据。
此外，当数据读取线SDataIn传送内容的分页地址不符合输出给目标装置30的分页地址时，于步骤S515中，扩展器20忽略数据读取线SDataIn传送的内容。
综合以上所述，本发明实施例提供一种通用串行输入输出的数据传输方法，适用于以通用串行输入输出总线连接的扩展机和目标装置中。于本发明实施例中，藉由扩展器主动地输出分页指示信号给目标装置，使目标装置依据分页指示信号指示的分页地址，来查找分页地 址下的分页数据，并将分页数据传输给扩展器，据以增加目标装置可以经由通用串行输入输出总线传输给扩展器的数据量。于一个实施例中，扩展器可以一次性地或批次性当将分页地址下的分页数据输出至扩展器中，并当扩展器或目标装置不支持如I2C或UART的传输接口时，扩展器和目标装置之间不仅可透过通用串行输入输出总线来实现的数据通讯，通用串行输入输出总线还可以传输多种不同的数据内容。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

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  1. 一种通用串行输入输出的数据传输方法，适用于以一通用串行输入输出总线连接的一扩展器和一目标装置，所述通用串行输入输出总线至少具有一数据输出线及一数据读取线，其特征在于，所述通用串行输入输出的数据传输方法包括：
    所述扩展器经由所述数据输出线输出一分页指示信号至所述目标装置，所述分页指示信号指示一分页地址；
    所述目标装置依据所述分页指示信号，查找所述分页地址指示的至少一分页数据；
    所述目标装置经由所述数据读取线将所述分页地址和所述至少一分页数据输出至所述扩展器；
    所述扩展器读取经由所述数据读取线传送的内容；以及
    当所述扩展器判断所述数据读取线传送的内容包含所述分页地址时，所述扩展器接收所述至少一分页数据。
  2. 如权利要求1所述的通用串行输入输出的数据传输方法，其特征在于，还包括分配所述数据输出线的多个时槽，以所述多个时槽中的部分时槽传输所述分页指示信号。
  3. 如权利要求1所述的通用串行输入输出的数据传输方法，其特征在于，还包括分配所述数据读取线的多个时槽，以所述数据读取线的所述多个时槽中的部分时槽传输所述分页地址，所述多个时槽中的另一部分时槽传输所述至少一分页数据。
  4. 如权利要求3所述的通用串行输入输出的数据传输方法，其特征在于，所述目标装置批次地将所述分页地址下的所述致少一分页数据输出至所述扩展器。
  5. 如权利要求4所述的通用串行输入输出的数据传输方法，其特征在于，于所述目标装置经由所述数据读取线将所述分页地址和所述至少一分页数据输出至所述扩展器的步骤中，还包括所述目标装置将所述分页地址下的所有分页数据输出至所述扩展器。
  6. 如权利要求1所述的通用串行输入输出的数据传输方法，其特征在于，所述通用串行输入输出总线还具有一频率信号线及一负载信号线，所述频率信号线传送一频率信号，所述负载信号线传送一负载信号，于所述扩展器经由所述数据输出线输出所述分页指示信号至所述目标装置的步骤中还包括依据所述频率信号及所述负载信号输出所述分页指示信号。
  7. 如权利要求1所述的通用串行输入输出的数据传输方法，其特征在于，于所述扩展器读取经由所述数据读取线传送的内容的步骤中，还包括读取所述数据读取线传送的内容中的所述分页地址。
  8. 如权利要求7所述的通用串行输入输出的数据传输方法，其特征在于，还包括所述扩展器判断读取到的所述分页地址是否符合输出给所述目标装置的所述分页指示信号所指示的所述分页地址。
  9. 如权利要求8所述的通用串行输入输出的数据传输方法，其特征在于，当所述扩展器判断读取到的所述分页地址不符合所述分页指示信号所指示的所述分页地址时，所述扩展器忽略所述数据读取线传送的内容。
  10. 如权利要求1所述的通用串行输入输出的数据传输方法，其特征在于，还包括所述目标装置判断所述分页指示信号指示的所述分页地址。
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