WO2017084123A1 - 一种液晶显示面板 - Google Patents

一种液晶显示面板 Download PDF

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Publication number
WO2017084123A1
WO2017084123A1 PCT/CN2015/096545 CN2015096545W WO2017084123A1 WO 2017084123 A1 WO2017084123 A1 WO 2017084123A1 CN 2015096545 W CN2015096545 W CN 2015096545W WO 2017084123 A1 WO2017084123 A1 WO 2017084123A1
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Prior art keywords
liquid crystal
display panel
crystal display
thin film
film transistor
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PCT/CN2015/096545
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English (en)
French (fr)
Inventor
王聪
杜鹏
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/907,886 priority Critical patent/US20180157071A1/en
Publication of WO2017084123A1 publication Critical patent/WO2017084123A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel.
  • Figure 1 shows a prior art liquid crystal display panel.
  • a light shielding structure 2 Light Shield, LS
  • a buffer layer 3 is covered on the light shielding structure 2.
  • a low temperature polysilicon layer 4 is disposed over the buffer layer 3.
  • the low temperature polysilicon layer 4 acts as a semiconductor channel in the transistor.
  • the buffer layer 3 serves to block electrical communication between the light shielding structure 2 and the low temperature polysilicon layer 4.
  • the low temperature polysilicon layer 4 is divided into a plurality of regions of different degrees of doping, such as highly doped regions, low doped regions, and undoped regions.
  • a low temperature polysilicon (LTPS) 4 is connected to the source 8 and the drain 9 of the thin film transistor.
  • a gate insulating layer (GI) 5 is disposed on the low temperature polysilicon layer 4, and a gate electrode 6 of the thin film transistor is disposed on the gate insulating layer (Gate Insulator (GI) 5.
  • a Gate Insulator (GI) 5 is used to prevent electrical connection between the gate 6 and the low temperature polysilicon layer 4.
  • An interlayer dielectric (ILD) 7 is disposed between the gate electrode 6 and the source electrode 8 and the drain electrode 9 of the thin film transistor.
  • the PLN insulating layer 10 is covered on the source 8 and the drain 9 of the thin film transistor. In the region of the array substrate of the liquid crystal display panel shown in FIG.
  • the first glass substrate 1 is covered with the buffer layer 3.
  • a first insulating layer 5 located in the same layer as the gate insulating layer (GI) 5 is provided over the buffer layer 3.
  • a second insulating layer 7 is provided in the same layer as the interlayer dielectric (ILD) 7.
  • ILD interlayer dielectric
  • a third insulating layer 10 is disposed in the same layer as the PLN insulating layer 10.
  • a common electrode layer 11 is disposed over the third insulating layer 10.
  • An electrode insulating layer 12 is provided on top of 11.
  • a pixel electrode layer 13 connected to the drain electrode 9 of the thin film transistor is disposed over the electrode insulating layer 12.
  • the electrode insulating layer 12 serves to block electrical communication between the common electrode layer 11 and the pixel electrode layer 13.
  • the pixel electrode layer 13 is connected to the drain electrode 9 of the thin film transistor through the via hole 19.
  • a black matrix 17 is disposed at a specific position on the second glass substrate 18 for blocking light leakage.
  • a color resist layer 16 is covered on the outside of the black matrix 17 and the second glass substrate 18.
  • a protective layer 15 is provided outside the color group layer 16.
  • a spacer 14 is provided at a specific position of the color filter substrate. The spacer 14 serves to maintain the distance between the two substrates of the liquid crystal cell.
  • a columnar spacer (Photo Spacer, PS) 14 is deposited on the substrate on the side of the color filter for supporting the upper substrate.
  • a certain thickness ie, a liquid crystal gap
  • the location of the spacers 14 is typically placed at the lateral and longitudinal boundaries of the black matrix (BM) of the panel viewable area (AA) to avoid loss of pixel aperture ratio.
  • the PLN holes 19 for turning on the drain electrode 9 and the pixel electrode 13 are large.
  • the spacer 14 easily slides into the PLN hole 19. This causes unevenness in the thickness of the substrate at the center of the substrate, and display abnormality occurs.
  • the number of pixels per inch Pixel Per Inch, PPI
  • the smaller the distance between the spacer 14 and the PLN hole 19 the greater the probability that the spacer 14 slides into the PLN hole 19.
  • the present invention proposes An improved liquid crystal display panel.
  • the present invention provides a liquid crystal display panel
  • the array substrate of the liquid crystal display panel includes at least two pixel units, each of the pixel units including: a scan line extending in a first direction; a data line extending in two directions; and a thin film transistor in which at least a portion of adjacent two pixel units are arranged in mirror symmetry with each other.
  • the thin film transistor is disposed between the pixel electrode and the data line in a functional connection manner, that is, the thin film transistor controls whether the source and the drain are turned on or not through the gate switch, thereby timely injecting the signal of the data line into the pixel electrode.
  • the invention provides a novel panel wiring design, so that the spacer can avoid the PLN via, The effect prevents the panel from slipping into the PLN via in the pair of cells or during the bending test.
  • two pixel units adjacent in the second direction are arranged in mirror symmetry with each other in a manner that the scan lines are adjacent to each other in parallel, the plane of symmetry being perpendicular to the surface of the array substrate and parallel to the Scan line.
  • the nth scan line and the n+1th scan line of the two adjacent pixel units are adjacent to the wiring, and the two adjacent parallel extending scan lines respectively control the pixels of the upper line and the lower line.
  • a row of pixels Compared with the liquid crystal display panel of the prior art, the position of the spacer does not change, so that the limitation of the first via hole can be well avoided.
  • a source of the thin film transistor is connected to the data line
  • a drain of the thin film transistor is connected to the pixel electrode through a first via
  • the first via is located at the An insulating layer and a common electrode layer between the drain and the pixel electrode, the source and the drain being connected by a channel structure, the channel structure spanning the scan line.
  • the extending paths of the channel structures of two adjacent two pixel units are mirror-symmetrical to each other, communicate with each other, and together form an H-shaped pattern, and in the H-shaped pattern
  • the four opposite sides of the four sides span the scan line.
  • the first vias of the two adjacent two pixel units are merged into one via to complete, so that the first via crosses the two adjacent two when viewed in a top view.
  • the drain of each pixel unit In this way, process complexity and error risk are greatly reduced.
  • the color filter substrate of the liquid crystal display panel is provided with a spacer for maintaining a liquid crystal gap, and the position of the spacer corresponds to a distance of the pixel unit of the array substrate in the second direction.
  • the end of the symmetry plane In this way, it is ensured that the position of the spacer does not change with respect to the liquid crystal display panel of the prior art.
  • two pixel units adjacent in the first direction are arranged in mirror symmetry with each other in parallel adjacent to each other, the plane of symmetry being perpendicular to the surface of the array substrate and parallel to the Data line.
  • the data lines of the two columns of pixel cells adjacent to each other are adjacent to the wiring. At this time, the distance between the two data lines which are far apart is 2p (p is the pixel unit size in the first direction).
  • a source of the thin film transistor is connected to the data line, the thin film crystal A drain of the body tube is connected to the pixel electrode through a first via, and the source and the drain are connected by a channel structure, the channel structure spanning the scan line. In this way, the switching action of the thin film transistor can be ensured.
  • the color filter substrate of the liquid crystal display panel is provided with a spacer for maintaining a liquid crystal gap, and the position of the spacer corresponds to a distance of the pixel unit of the array substrate in a first direction. The end of the symmetry plane. In this way, it is ensured that the position of the spacer does not change with respect to the liquid crystal display panel of the prior art.
  • the distance between the first via and the end of the pixel unit remote from the plane of symmetry is greater than the cell-to-group accuracy in the first direction.
  • the distance between the spacers and the first vias on both sides is d2.
  • the uniformity of the thickness of the box can be effectively ensured, and the display performance of the panel can be improved.
  • the introduction of the PLN negative photoresist material can be realized, and the cost reduction effect can be achieved.
  • FIG. 1 is a longitudinal cross-sectional view showing a liquid crystal display panel of the prior art
  • FIG. 2 is a plan view showing a partial structure of a liquid crystal display panel in the prior art
  • Figure 3 shows an enlarged view of the circled portion in Figure 2;
  • FIG. 4 is a plan view showing a partial structure of a first embodiment of a liquid crystal display panel proposed by the present invention
  • Figure 5 is a partial enlarged view of Figure 4.
  • Figure 6 is a plan view showing a partial structure of a second embodiment of the liquid crystal display panel proposed by the present invention.
  • Fig. 7 is a partial enlarged view of Fig. 6.
  • Fig. 2 is a plan view showing a part of the structure of a liquid crystal display panel in the prior art. 2 clearly shows that the array substrate of the prior art liquid crystal display panel includes a pixel unit 30 (not shown in FIG. 2).
  • Each of the pixel units 30 includes: a scan line 6 extending in a first direction (ie, a left-right direction in the drawing), a data line 102 extending in a second direction different from the first direction (ie, an up-and-down direction in the drawing), A selected pixel electrode (not shown); and a thin film transistor disposed between the data line 102 and the pixel electrode in a functionally connected manner.
  • a black matrix 17 is provided at a position corresponding to the scanning line 6 and the data line 102 for blocking light leakage.
  • the pixel electrode may be disposed in a region surrounded by the scan line 6 and the data line 102.
  • Fig. 3 shows an enlarged view of a circled portion in Fig. 2.
  • the source 8 of the thin film transistor is connected to the data line 102, and the drain 9 of the thin film transistor is connected to a pixel electrode (not shown).
  • the source 8 and the drain 9 are connected by a channel structure 4 which crosses the scan line 6.
  • the channel structure 4 spans the scan line 6 to constitute the gate of the thin film transistor, thereby performing on-off control of the thin film transistor.
  • the source electrode 8 of the thin film transistor is connected to the channel structure 4 through the second via hole 21 (internal insulating layer via, ILD hole).
  • the drain electrode 9 of the thin film transistor is connected to the channel structure 4 through a second via 22 (inter-insulator via, ILD hole).
  • the drain 9 of the thin film transistor is also connected to the pixel electrode through the first via 19 (PLN hole) and the PV via 20.
  • the first via 19 passes through a PVN insulating layer, a common electrode layer, and an electrode insulating layer between the drain electrode 9 and the pixel electrode (the electrode insulating layer is used to separate the common electrode layer and the pixel electrode layer to prevent breakdown) .
  • the size of the pixel unit 30 is p, and the width of the first via 19 is d.
  • the position of the spacer 14 of the upper plate (color film substrate) generally corresponds to the middle of the data line 102.
  • the spacer 14 of the size d3 in the first direction in the figure can easily slide into the first via 19 of the pixel unit 30 on the right side, resulting in uneven liquid crystal gap in the display screen, thereby affecting the display. effect.
  • the present application proposes an improved liquid crystal display panel.
  • Fig. 4 is a plan view showing a partial structure of a first embodiment of the liquid crystal display panel proposed by the present invention. 4 clearly shows that in the first embodiment, the array substrate of the liquid crystal display panel proposed by the present invention includes at least two pixel units 30.
  • the pixel unit 30 includes: a scanning line 6 extending in a first direction (ie, a left-right direction in the drawing), and a second direction different from the first direction (ie, an up-and-down direction in the drawing)
  • a black matrix 17 is provided at a position corresponding to the scanning line 6 and the data line 102 for blocking light leakage.
  • the pixel electrode may be disposed in a region surrounded by the scan line 6 and the data line 102.
  • Fig. 5 is an enlarged view showing a portion in the vicinity of the thin film transistor of Fig. 4.
  • the source 8 of the thin film transistor is connected to the data line 102
  • the drain 9 of the thin film transistor is connected to the pixel electrode (not shown) through the first via 19.
  • the source 8 and the drain 9 are connected by a channel structure 4 which straddles the scan line 6.
  • the material of the channel structure 4 can be, for example, low temperature polysilicon doped to varying degrees.
  • the channel structure 4 spans the scan line 6 to constitute the gate of the thin film transistor, thereby performing on-off control of the thin film transistor.
  • the source electrode 8 of the thin film transistor is connected to the low temperature polysilicon 4 through the second via hole 21 (the interlayer insulating via, ILD hole).
  • the drain electrode 9 of the thin film transistor is connected to the low temperature polysilicon 4 through a second via 22 (inter-insulator via, ILD hole).
  • the drain 9 of the thin film transistor is also connected to the pixel electrode through the first via 19 (PLN hole) and the PV via 20.
  • two pixel units 30 adjacent to each other in the second direction are scanned lines.
  • the adjacent parallel extending manners are arranged mirror-symmetrically to each other, the plane of symmetry P being perpendicular to the surface of the array substrate and parallel to the scanning line 6.
  • the plane of symmetry is schematically represented by a broken line P.
  • the extending paths of the channel structures 4 of the two adjacent two pixel units 30 are mirror-symmetrical to each other, communicate with each other and form an H-shaped pattern together, and four strips in the H-shaped pattern.
  • the opposite sides of the two sides span the scan line 6.
  • a spacer 14 for holding a liquid crystal gap is provided on the color filter substrate of the liquid crystal display panel.
  • the position of the spacer 14 corresponds to the end of the pixel unit 30 of the array substrate which is away from the plane of symmetry P in the second direction.
  • the nth scan line and the n+1th scan line of the two adjacent pixel units 30 are adjacent to each other, for example, the first scan line and the second scan line are adjacent to the line.
  • the third scanning line and the fourth scanning line are adjacent to the wiring, and so on, and two adjacent parallel extending scanning lines respectively control the pixels of the previous row and the pixels of the next row.
  • the position of the spacer 14 is not changed, so that the limitation of the first via hole 19 (PLN hole) can be well avoided.
  • the spacer 14 is difficult to slide into the first via hole 19 (PLN hole), which ensures The uniformity of the liquid crystal gap.
  • the distance between the thin film transistors of the pixel units 30 adjacent to each other is reduced at this time, and two adjacent ones of the upper and lower sides are two
  • the first vias 19 (PLN holes) of the pixel unit 30 may also be combined into one via, such that the first vias span the drains of the two adjacent two pixel units as viewed in a top view.
  • PV vias 20 may also be combined into one via, such that the first vias span the drains of the two adjacent two pixel units as viewed in a top view.
  • Fig. 6 is a plan view showing a partial structure of a second embodiment of the liquid crystal display panel proposed by the present invention.
  • the array substrate of the liquid crystal display panel proposed by the present invention includes at least two pixel units 30.
  • the pixel unit 30 includes: a scan line 6 extending in a first direction (ie, a left-right direction in the drawing), a data line 102 extending in a second direction different from the first direction (ie, an up-and-down direction in the drawing), and a pixel An electrode (not shown); and a thin film transistor disposed between the data line 102 and the pixel electrode in a functionally connected manner.
  • a black matrix 17 is provided at a position corresponding to the scanning line 6 and the data line 102 for blocking light leakage.
  • the pixel electrode may be disposed in a region surrounded by the scan line 6 and the data line 102.
  • Fig. 7 is an enlarged view showing a portion in the vicinity of the thin film transistor of Fig. 6.
  • the source 8 of the thin film transistor is connected to the data line 102.
  • the drain electrode 9 of the thin film transistor is connected to a pixel electrode (not shown) through the first via hole 19.
  • the source 8 and the drain 9 are connected by a channel structure 4 which crosses the scan line 6.
  • the material of the channel structure 4 can be, for example, low temperature polysilicon doped to varying degrees.
  • the channel structure 4 spans the scan line 6 to constitute a gate, thereby performing on-off control of the thin film transistor.
  • the source electrode 8 of the thin film transistor is connected to the low temperature polysilicon 4 through the second via hole 21 (the interlayer insulating via, ILD hole).
  • the drain electrode 9 of the thin film transistor is connected to the low temperature polysilicon 4 through a second via 22 (inter-insulator via, ILD hole).
  • the drain 9 of the thin film transistor is also connected to the pixel electrode through the first via 19 (PLN hole) and the PV via 20.
  • the two adjacent pixel units 30 in the first direction are connected by the data line 102.
  • the adjacent parallel extending manners are arranged mirror-symmetrically to each other, the plane of symmetry Q being perpendicular to the surface of the array substrate and parallel to the data line 102.
  • the plane of symmetry is indicated by a broken line Q.
  • a spacer 14 for holding a liquid crystal gap is provided on the color filter substrate of the liquid crystal display panel. As can be clearly seen in FIG. 7, the position of the spacer 14 corresponds to the end of the pixel unit 30 of the array substrate which is away from the plane of symmetry Q in the first direction.
  • the drain electrode 9 of the thin film transistor is connected to the pixel electrode through the first via hole 19.
  • the size of the pixel unit 30 is p, and the distance d2 between the first via 19 and the end of the pixel unit 30 away from the plane of symmetry Q is preferably greater than the cell-to-group precision. In this way, when the liquid crystal cell is paired, the spacer 14 does not easily slide into the first via 19 which is closest thereto.
  • the extended path of the channel structure 4 of the pixel unit 30 constitutes a U-shaped pattern and spans the scan line 6 at two opposite sides of the U-shaped pattern.
  • the gate of the thin film transistor is formed to control its on and off.
  • the data lines of the two columns of pixel cells adjacent to each other are adjacent to the wiring.
  • the first data line and the second data line are routed close to each other, the third data line and the fourth data line are brought close to the wiring, and so on.
  • the distance between the second data line and the third data line is 2p.
  • the position of the spacer 14 is unchanged, and the distance between the spacer 14 and the first via 19 (PLN hole) on both sides is D2
  • the pixel design only need to ensure that the value of d2 is greater than the accuracy value of the liquid crystal cell pair. This ensures that the spacers 14 do not slip into the first vias 19 (PLN holes) when the cells are paired.

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Abstract

提供了一种液晶显示面板，液晶显示面板的阵列基板包括至少两个像素单元（30），像素单元（30）包括：沿第一方向延伸的扫描线（6）；沿不同于第一方向的第二方向延伸的数据线（102）；像素电极；以及以功能性连接的方式布置在数据线（102）和像素电极之间的薄膜晶体管，其中，至少一部分的相邻的两个像素单元（30）彼此镜像对称地布置。提供了一种新型的面板走线设计，使得隔离子（14）能够避开PLN过孔（19），有效防止了面板在液晶盒对组或者在弯曲测试时出现隔离子（14）滑入PLN过孔（19）的现象。

Description

一种液晶显示面板
相关申请的交叉引用
本申请要求享有于2015年11月19日提交的名称为“一种液晶显示面板”的中国专利申请CN201510812472.1的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，尤其涉及一种液晶显示面板。
背景技术
图1显示了一种现有技术中的液晶显示面板。参照图1，在液晶显示面板的阵列基板的设置有薄膜晶体管的区域中：在第一玻璃基板1上设置有用于阻挡漏光的遮光结构2(Light Shield, LS)。在遮光结构2之上覆盖有缓冲层3。在缓冲层3之上设置有低温多晶硅层4。低温多晶硅层4作为晶体管中的半导体沟道。缓冲层3用于阻挡遮光结构2和低温多晶硅层4之间的电连通。低温多晶硅层4划分为多个不同程度掺杂的区域，例如高掺杂区域、低掺杂区域和无掺杂区域。低温多晶硅层(Low Temperature Poly Silicon,LTPS)4与薄膜晶体管的源极8和漏极9相连。在低温多晶硅层4之上设置有栅极绝缘层(Gate Insulator,GI)5，栅极绝缘层(Gate Insulator,GI)5上设置有薄膜晶体管的栅极6。栅极绝缘层(Gate Insulator,GI)5用于阻止栅极6和低温多晶硅层4之间的电接通。在栅极6和薄膜晶体管的源极8、漏极9之间布置有间绝缘层(Interlayer Dielectric,ILD)7。在薄膜晶体管的源极8、漏极9之上覆盖有PLN绝缘层10。在图1所示的液晶显示面板的阵列基板的未设置有薄膜晶体管的区域中：在第一玻璃基板1上覆盖有缓冲层3。在缓冲层3之上设置有与栅极绝缘层(Gate Insulator,GI)5位于同一层中的第一绝缘层5。在第一绝缘层5上，设置有与间绝缘层(Interlayer Dielectric,ILD)7位于同一层中的第二绝缘层7。在第二绝缘层7之上，设置有与PLN绝缘层10位于同一层中的第三绝缘层10。在第三绝缘层10之上设置有公共电极层11。在公共电极层 11之上设置有电极绝缘层12。在电极绝缘层12之上设置有与薄膜晶体管的漏极9相连的像素电极层13。电极绝缘层12用于阻止公共电极层11和像素电极层13之间的电连通。像素电极层13通过过孔19与薄膜晶体管的漏极9相连。
另一侧，在该液晶显示面板的彩膜基板上：在第二玻璃基板18上的特定位置处设置有黑色矩阵17，用于阻挡漏光。在黑色矩阵17和第二玻璃基板18之外覆盖有色阻层16。在色组层16之外设置有保护层15。在保护层15之外，在彩膜基板的特定位置处，设置有隔离子14。隔离子14用于保持液晶盒的两个基板之间的距离。
可见，在传统的低温多晶硅(Low Temperature Poly Silicon,LTPS)面板制程中，彩色滤光片一侧的基板上会沉积一层柱状的隔离子(Photo Spacer,PS)14，以用于支撑上基板，使得上下基板之间形成一定的盒厚(即液晶间隙)。隔离子14的位置一般放置于面板可视区(AA)的黑色矩阵(BM)的横向与纵向的交界处，避免损失像素的开口率。
在薄膜晶体管阵列的基板的像素中，用于导通漏极9与像素电极13的PLN孔19较大。在进行液晶盒对组或者弯曲时，由于隔离子14到PLN孔19的距离较小，隔离子14很容易滑入PLN孔19中。这样会形成基板中央的盒厚不均，出现显示异常。当每英寸的像素数(Pixel Per Inch,PPI)越大时，隔离子14到PLN孔19距离越小，隔离子14滑入到PLN孔19中的几率就越大。
发明内容
针对上述现有技术中的问题，即由于隔离子到PLN孔的距离较小，隔离子很容易滑入PLN孔中，这样会形成基板中央的盒厚不均以及因此造成显示不良，本发明提出了一种改进的液晶显示面板。
本发明提出了一种液晶显示面板，所述液晶显示面板的阵列基板包括至少两个像素单元，每一所述像素单元包括：沿第一方向延伸的扫描线；沿不同于第一方向的第二方向延伸的数据线；以及薄膜晶体管，其中，至少一部分的相邻的两个像素单元彼此镜像对称地布置。薄膜晶体管以功能性连接的方式布置在像素电极和数据线之间，即薄膜晶体管通过栅极开关控制源漏极导通与否、从而适时地将数据线的信号灌入像素电极中。
本发明提供了一种新型的面板走线设计，使得隔离子能够避开PLN过孔，有 效防止了面板在液晶盒对组或者在弯曲测试时出现隔离子滑入PLN过孔的现象。
在一个实施方案中，在第二方向上两两相邻的两个像素单元以扫描线相邻平行延伸的方式彼此镜像对称地布置，对称面垂直于所述阵列基板的表面且平行于所述扫描线。在本实施例中，将上下相邻的两个像素单元中的第n条扫描线与第n+1条扫描线靠近布线，两条相邻平行延伸的扫描线分别控制上一行的像素与下一行的像素。相对于现有技术中的液晶显示面板，隔离子的位置不发生改变，这样能很好地避开第一过孔的限制。
在一个实施方案中，所述薄膜晶体管的源极与所述数据线相连，所述薄膜晶体管的漏极通过第一过孔与所述像素电极相连，所述第一过孔穿过位于所述漏极和所述像素电极之间的绝缘层和公共电极层，所述源极和所述漏极通过沟道结构相连，所述沟道结构跨越过所述扫描线。以此方式，可以保证薄膜晶体管的开关作用。
在一个实施方案中，在第二方向上，两两相邻的两个像素单元的所述沟道结构的延伸路径彼此镜像对称、彼此连通且一起构成H形图案，并在所述H形图案的四条两两相对的侧边处跨越所述扫描线。以此方式，简化了整个走线布局的复杂程度，可有效降低工艺耗时和材料成本。
在一个实施方案中，所述两两相邻的两个像素单元的第一过孔合并成一个过孔来完成，使得沿俯视视角观测时第一过孔跨越过所述两两相邻的两个像素单元的漏极。以此方式，大大降低了工艺复杂度和误差风险。
在一个实施方案中，所述液晶显示面板的彩膜基板上设置有用于保持液晶间隙的隔离子，所述隔离子的位置对应于所述阵列基板的像素单元的在第二方向上的远离所述对称面的端部。以此方式，可以保证相对于现有技术中的液晶显示面板，隔离子的位置不变。在进行液晶盒的对组时，隔离子很难滑入到第一过孔中，保证了液晶间隙的均一性。
在一个实施方案中，在第一方向上两两相邻的两个像素单元以数据线相邻平行延伸的方式彼此镜像对称地布置，对称面垂直于所述阵列基板的表面且平行于所述数据线。在本实施例中，将左右两两相邻的两列像素单元的数据线靠近布线。此时相隔较远的两条数据线之间的间距为2p(p为在第一方向上的像素单元尺寸)。
在一个实施方案中，所述薄膜晶体管的源极与所述数据线相连，所述薄膜晶 体管的漏极通过第一过孔与所述像素电极相连，所述源极和所述漏极通过沟道结构相连，所述沟道结构跨越过所述扫描线。以此方式，可以保证薄膜晶体管的开关作用。
在一个实施方案中，所述液晶显示面板的彩膜基板上设置有用于保持液晶间隙的隔离子，所述隔离子的位置对应于所述阵列基板的像素单元的在第一方向上的远离所述对称面的端部。以此方式，可以保证相对于现有技术中的液晶显示面板，隔离子的位置不变。
在一个实施方案中，在第一方向上，所述第一过孔与所述像素单元的远离所述对称面的端部之间的距离大于液晶盒对组精度。此时隔离子距离两边的第一过孔的距离都为d2，在像素设计时，则只需保证d2的值大于液晶盒对组的精度值。这样就能保证隔离子在液晶盒对组时不会滑入第一过孔中。
通过本发明所提出的方案，可有效保证盒厚的均一性，提升面板的显示性能。同时可以实现PLN负性化光阻材料的导入，实现降低成本的效果。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1显示了现有技术中的液晶显示面板的纵向剖视图；
图2显示了现有技术中的液晶显示面板的部分结构的俯视图；
图3显示了图2中圆圈部分的放大图；
图4显示了本发明所提出的液晶显示面板的第一实施例的部分结构的俯视图；
图5为图4的局部放大图；
图6显示了本发明所提出的液晶显示面板的第二实施例的部分结构的俯视图；以及
图7为图6的局部放大图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
下面将结合附图对本发明作进一步说明。
图2显示了现有技术中的液晶显示面板的部分结构的俯视图。图2清楚地显示了，现有技术中的液晶显示面板的阵列基板包括像素单元30(图2中未标示)。每一像素单元30包括：沿第一方向(即图中的左右方向)延伸的扫描线6、沿不同于第一方向的第二方向(即图中的上下方向)延伸的数据线102、可选的像素电极(图中未示出)；以及以功能性连接的方式布置在数据线102和像素电极之间的薄膜晶体管。在与扫描线6和数据线102相对应的位置处设置有黑色矩阵17，用于阻挡漏光。像素电极可设置在扫描线6和数据线102所包围的区域中。
图3显示了图2中圆圈部分的放大图。在图3中可看出，薄膜晶体管的源极8与所述数据线102相连，薄膜晶体管的漏极9与像素电极(图中未示出)相连。源极8和漏极9通过沟道结构4相连，沟道结构4跨越过扫描线6。沟道结构4跨越过扫描线6以构成薄膜晶体管的栅极，从而进行对薄膜晶体管的通断控制。
在像素单元30中，薄膜晶体管的源极8通过第二过孔21(间绝缘层过孔，ILD hole)与沟道结构4相连。薄膜晶体管的漏极9通过第二过孔22(间绝缘层过孔，ILD hole)与沟道结构4相连。而薄膜晶体管的漏极9还通过第一过孔19(PLN hole)以及PV过孔20与像素电极相连。所述第一过孔19穿过位于漏极9和像素电极之间的PVN绝缘层、公共电极层以及电极绝缘层(电极绝缘层用于隔开公共电极层和像素电极层以防止击穿)。
在图2和图3所示的现有技术中的液晶显示面板中，假设在第一方向(图中的左右方向)上，像素单元30的尺寸为p，第一过孔19的宽度为d，而第一过孔19距离像素单元30在第一方向上的两个端部的距离分别为d1和d2，则从距离上可以得出p＝d1+d+d2。上板(彩膜基板)的隔离子14的位置一般对应于数据线102的正中间。假设d2≥d1，则图中的在第一方向上尺寸为d3的隔离子14很容易滑入右边的像素单元30的第一过孔19中，导致显示画面中液晶间隙不均，从而影响显示效果。
针对上述问题，本申请提出了改进的液晶显示面板。
图4显示了本发明所提出的液晶显示面板的第一实施例的部分结构的俯视图。图4清楚地显示了，在第一实施例中，本发明所提出的液晶显示面板的阵列基板包括至少两个像素单元30。像素单元30包括：沿第一方向(即附图中的左右方向)延伸的扫描线6、沿不同于第一方向的第二方向(即附图中的上下方向) 延伸的数据线102、像素电极(图中未示出)；以及以功能性连接的方式布置在数据线102和像素电极之间的薄膜晶体管。在与扫描线6和数据线102相对应的位置处设置有黑色矩阵17，用于阻挡漏光。像素电极可设置在扫描线6和数据线102所包围的区域中。
图5显示了图4中薄膜晶体管附近的部分的放大图。在图5中可看出，薄膜晶体管的源极8与数据线102相连，薄膜晶体管的漏极9通过第一过孔19与像素电极(图中未示出)相连。源极8和漏极9通过沟道结构4相连，沟道结构4跨过扫描线6。沟道结构4的材料例如可为不同程度掺杂的低温多晶硅。沟道结构4跨越过扫描线6以构成薄膜晶体管的栅极，从而进行对薄膜晶体管的通断控制。
在像素单元30中，薄膜晶体管的源极8通过第二过孔21(间绝缘层过孔，ILD hole)与低温多晶硅4相连。薄膜晶体管的漏极9通过第二过孔22(间绝缘层过孔，ILD hole)与低温多晶硅4相连。而薄膜晶体管的漏极9还通过第一过孔19(PLN hole)以及PV过孔20与像素电极相连。
在图4和图5所示的本发明所提出的液晶面板的第一实施例中，在第二方向(即附图中的上下方向)上两两相邻的两个像素单元30以扫描线6相邻平行延伸的方式彼此镜像对称地布置，对称面P垂直于阵列基板的表面且平行于扫描线6。在图4和图5中，对称面用虚线P来示意性表示。
如图5所示，在第二方向上，两两相邻的两个像素单元30的沟道结构4的延伸路径彼此镜像对称、彼此连通且一起构成H形图案，并在H形图案的四条两两相对的侧边处跨越扫描线6。
另一方面，在液晶显示面板的彩膜基板上设置有用于保持液晶间隙的隔离子14。在图4中可清楚看出，隔离子14的位置对应于阵列基板的像素单元30的在第二方向上的远离对称面P的端部。
在本实施例中，将上下相邻的两个像素单元30中的第n条扫描线与第n+1条扫描线靠近布线，例如将第1条扫描线和第2条扫描线靠近布线，将第3条扫描线和第4条扫描线靠近布线，以此类推，两条相邻平行延伸的扫描线分别控制上一行的像素与下一行的像素。相对于图2所示的现有技术中的液晶显示面板，隔离子14的位置不发生改变，这样能很好地避开第一过孔19(PLN hole)的限制。在进行液晶盒的对组时，隔离子14很难滑入到第一过孔19(PLN hole)中，保证了 液晶间隙的均一性。另一方面，相比于图2所示的现有技术中的液晶显示面板，此时上下两两相邻的像素单元30的薄膜晶体管之间的距离减小，上下两两相邻的两个像素单元30的第一过孔19(PLN hole)也可以合并成一个过孔来完成，使得沿俯视视角观测时第一过孔跨越过所述两两相邻的两个像素单元的漏极9和PV过孔20。
图6显示了本发明所提出的液晶显示面板的第二实施例的部分结构的俯视图。图6清楚地显示了，在第二实施例中，本发明所提出的液晶显示面板的阵列基板包括至少两个像素单元30。像素单元30包括：沿第一方向(即附图中的左右方向)延伸的扫描线6、沿不同于第一方向的第二方向(即附图中的上下方向)延伸的数据线102、像素电极(图中未示出)；以及以功能性连接的方式布置在数据线102和像素电极之间的薄膜晶体管。在与扫描线6和数据线102相对应的位置处设置有黑色矩阵17，用于阻挡漏光。像素电极可设置在扫描线6和数据线102所包围的区域中。
图7显示了图6中薄膜晶体管附近的部分的放大图。在图7中可看出，薄膜晶体管的源极8与数据线102相连。薄膜晶体管的漏极9通过第一过孔19与像素电极(图中未示出)相连。源极8和漏极9通过沟道结构4相连，沟道结构4跨越过扫描线6。沟道结构4的材料例如可为不同程度掺杂的低温多晶硅。沟道结构4跨越过扫描线6以构成栅极，从而进行对薄膜晶体管的通断控制。
在像素单元30中，薄膜晶体管的源极8通过第二过孔21(间绝缘层过孔，ILD hole)与低温多晶硅4相连。薄膜晶体管的漏极9通过第二过孔22(间绝缘层过孔，ILD hole)与低温多晶硅4相连。而薄膜晶体管的漏极9还通过第一过孔19(PLN hole)以及PV过孔20与像素电极相连。
在图6和图7所示的本发明所提出的液晶面板的第二实施例中，在第一方向(即附图的左右方向)上两两相邻的两个像素单元30以数据线102相邻平行延伸的方式彼此镜像对称地布置，对称面Q垂直于阵列基板的表面且平行于数据线102。在图6和图7中，对称面通过虚线Q来表示。
液晶显示面板的彩膜基板上设置有用于保持液晶间隙的隔离子14。在图7中可清楚地看出，隔离子14的位置对应于阵列基板的像素单元30的在第一方向上的远离对称面Q的端部。
薄膜晶体管的漏极9通过第一过孔19与像素电极相连。如图所示，在第一方 向上，像素单元30的尺寸为p，第一过孔19与像素单元30的远离对称面Q的端部之间的距离d2优选大于液晶盒对组精度。以此方式，在液晶盒对组时，隔离子14不易滑入与其最为相近的第一过孔19中。
具体地，像素单元30的沟道结构4的延伸路径构成U形图案，并在所述U形图案的两条相对的侧边处跨越过所述扫描线6。以此方式，形成了薄膜晶体管的栅极，以对其通断进行控制。
在本实施例中，将左右两两相邻的两列像素单元的数据线靠近布线。例如，将第1条数据线和第2条数据线靠近布线，将第3条数据线和第4条数据线靠近布线，以此类推。此时第2条数据线与第3条数据线之间的间距为2p。另一方面，相对于图2所示的现有技术中的液晶显示面板，隔离子14的位置不变，则此时隔离子14距离两边的第一过孔19(PLN hole)的距离都为d2，在像素设计时，则只需保证d2的值大于液晶盒对组的精度值。这样就能保证隔离子14在液晶盒对组时不会滑入第一过孔19(PLN hole)中。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (10)

  1. 一种液晶显示面板，其中，所述液晶显示面板的阵列基板包括至少两个像素单元，每一所述像素单元包括：
    沿第一方向延伸的扫描线；
    沿不同于第一方向的第二方向延伸的数据线；以及
    薄膜晶体管，
    其中，至少一部分的相邻的两个像素单元彼此镜像对称地布置。
  2. 根据权利要求1所述的液晶显示面板，其中，在第二方向上两两相邻的两个像素单元以扫描线相邻平行延伸的方式彼此镜像对称地布置，对称面垂直于所述阵列基板的表面且平行于所述扫描线。
  3. 根据权利要求2所述的液晶显示面板，其中，所述薄膜晶体管的源极与所述数据线相连，所述薄膜晶体管的漏极通过第一过孔与所述像素电极相连，所述第一过孔穿过位于所述漏极和所述像素电极之间的绝缘层和公共电极层，所述源极和所述漏极通过沟道结构相连，所述沟道结构跨越过所述扫描线。
  4. 根据权利要求3所述的液晶显示面板，其中，在第二方向上，两两相邻的两个像素单元的所述沟道结构的延伸路径彼此镜像对称、彼此连通且一起构成H形图案，并在所述H形图案的四条两两相对的侧边处跨越所述扫描线。
  5. 根据权利要求4所述的液晶显示面板，其中，所述两两相邻的两个像素单元的第一过孔合并成一个过孔来完成，使得沿俯视视角观测时第一过孔跨越过所述两两相邻的两个像素单元的漏极。
  6. 根据权利要求2所述的液晶显示面板，其中，所述液晶显示面板的彩膜基板上设置有用于保持液晶间隙的隔离子，所述隔离子的位置对应于所述阵列基板的像素单元的在第二方向上的远离所述对称面的端部。
  7. 根据权利要求1所述的液晶显示面板，其中，在第一方向上两两相邻的两个像素单元以数据线相邻平行延伸的方式彼此镜像对称地布置，对称面垂直于所述阵列基板的表面且平行于所述数据线。
  8. 根据权利要求7所述的液晶显示面板，其中，所述薄膜晶体管的源极与所述数据线相连，所述薄膜晶体管的漏极通过第一过孔与所述像素电极相连，所述源极和所述漏极通过沟道结构相连，所述沟道结构跨越过所述扫描线。
  9. 根据权利要求8所述的液晶显示面板，其中，所述液晶显示面板的彩膜基板上设置有用于保持液晶间隙的隔离子，所述隔离子的位置对应于所述阵列基板的像素单元的在第一方向上的远离所述对称面的端部。
  10. 根据权利要求9所述的液晶显示面板，其中，在第一方向上，所述第一过孔与所述像素单元的远离所述对称面的端部之间的距离大于液晶盒对组精度。
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