WO2017063450A1 - 一种时间戳过滤的方法及装置 - Google Patents

一种时间戳过滤的方法及装置 Download PDF

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WO2017063450A1
WO2017063450A1 PCT/CN2016/096234 CN2016096234W WO2017063450A1 WO 2017063450 A1 WO2017063450 A1 WO 2017063450A1 CN 2016096234 W CN2016096234 W CN 2016096234W WO 2017063450 A1 WO2017063450 A1 WO 2017063450A1
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timestamp
time
compensation value
correction
read
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PCT/CN2016/096234
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English (en)
French (fr)
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吕明
李春华
钟涛
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

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  • This document relates to, but is not limited to, the field of communications, and in particular to a method and apparatus for time stamp filtering.
  • the 1588v2 clock is a high-precision clock using the IEEE1588V2 protocol. It is born in the background of the urgent need for high-precision timing.
  • the phase alignment is realized by the traditional physical clock method, and the time alignment is realized by 1588 message interaction.
  • the traditional ground time synchronization link is implemented by the Network Time Protocol (NTP) transmission mode. It has been developed to the v4 version.
  • NTP Network Time Protocol
  • SNTP Simple Network Time Protocol
  • the standard is RFC 2030 (SNTPv4).
  • the biggest disadvantage of this protocol is that it can only meet the time transfer accuracy of the millisecond (ms) level. For the nanosecond (ns) level required for high-precision time synchronization, the accuracy of time is not enough.
  • GPS Global Positioning System
  • the 1588v2 clock Compared with the traditional timing technology, the 1588v2 clock has obvious advantages. It adopts two-way channel, the accuracy is ns, the cost is low, and it can adapt to different access environments. In the context of the industry with increasing accuracy requirements, the 1588v2 clock has become an inevitable trend of development. However, when there is noise, clock jitter, network delay, or other reasons, the time stamp of the 1588v2 clock provided by the logic device is abnormal or the time stamp accuracy is poor, the time abnormal jump occurs, which affects the accuracy of the time calculation of the 1588v2 clock.
  • the embodiment of the invention provides a method and a device for time stamp filtering, which can improve the time synchronization precision of the 1588v2 clock.
  • a method for timestamp filtering includes:
  • the timestamp of the exception is filtered, and if the timestamp is normal, the compensation value is used for time correction.
  • the compensation value is calculated according to the read timestamp and the correction domain, and the compensation value is used for time correction, including:
  • the calculated compensation value is counted in the preset time period. If the accumulated sum of the compensation values exceeds the preset threshold within the preset time period, the compensation value is continuously calculated according to the read time stamp and the corresponding correction domain. The compensation value is used for time correction; if the accumulated value of the compensation value does not exceed the preset threshold within the preset time period, the phase locked loop is set to be locked, and the time stamp of the timing reading is determined to be filtered.
  • determining whether the timestamp is abnormal according to the result of the linear regression jitter vector estimation including:
  • the vector information of the frequency includes a slope of the vector, and the vector information according to the frequency determines whether the time stamp has a fixed frequency offset, including:
  • the periodically reading the timestamp and the correction domain corresponding to the timestamp including: reading the timestamp from a timestamp generator of a time synchronization message and corresponding to the timestamp The correction domain; the using the compensation value for time correction comprises: writing the compensation value to a timestamp generator, so that the timestamp generator uses the compensation value for time correction.
  • the filtering process includes: performing a median value average filtering process on the read timestamp.
  • an apparatus for timestamp filtering comprising:
  • a reading module configured to periodically read a timestamp of the time synchronization message and a correction domain corresponding to the timestamp
  • a calculation module configured to calculate a compensation value according to the read time stamp and the correction domain, and use the calculated compensation value for time correction
  • a filtering module configured to filter the read timestamp
  • the estimating module is configured to divide the filtered data into one or more time windows, and perform linear regression jitter vector estimation on the data in each time window;
  • Determining a module configured to determine whether the timestamp is abnormal according to a result of the linear regression jitter vector estimation
  • the filtering module is configured to filter the timestamp of the abnormality if the timestamp is abnormal; if the timestamp is normal, use the compensation value for time correction.
  • the calculating module is configured to: perform statistics on the calculated compensation value within a preset time period, and if the accumulated sum of the compensation values exceeds a preset threshold within a preset time period, continue to The read time stamp and the corresponding correction domain calculate the compensation value, and use the compensation value for time correction; if the accumulated value of the compensation value does not exceed a preset threshold within a preset time period Then, the phase locked loop is set to be in a locked state, and the time stamp read by the timing is determined to be filtered.
  • the determining module includes: a first estimating unit, configured to perform linear regression jitter vector estimation by using a least square method for data in each time window to obtain vector information of a frequency within a time window; a unit, configured to determine, according to vector information of the frequency, whether the timestamp has a fixed frequency offset; the second estimating unit is configured to estimate a residual of the read timestamp using a least squares method, and determine the time according to the residual Whether there is a jump in the stamp; the second determining unit, setting In the case where there is a fixed frequency offset and/or an abnormal jump in the time stamp, the time stamp is determined to be abnormal.
  • the vector information of the frequency includes a slope of the vector
  • the first determining unit is configured to: when the slope of the vector is a non-zero constant, determine that the time stamp has a fixed frequency offset.
  • the reading module is configured to: read the timestamp and a correction domain corresponding to the timestamp from a timestamp generator of a time synchronization message;
  • the filtering module uses the compensation value for time correction including:
  • the technical solution provided by the embodiment of the present invention includes: periodically reading a timestamp and a correction domain corresponding to the timestamp; calculating a compensation value according to the read timestamp and the correction domain, and using the compensation value Time correction; filtering the read timestamp; dividing the filtered data into one or more time windows, performing linear regression jitter vector estimation on the data in each time window; The result of the vector estimation determines whether the timestamp is abnormal; if the timestamp is abnormal, the timestamp of the exception is filtered, and if the timestamp is normal, the offset value is used for time correction.
  • the solution of the embodiment of the invention improves the time synchronization accuracy of 1588.
  • the solution provided by the embodiment of the present invention is applicable to the fluctuation of the time stamp of the 1588v2 clock provided by the logic device caused by noise, jitter, network delay, or other reasons, and can effectively filter out the existing fluctuations to avoid the network element time. Synchronous fluctuations increase the time synchronization accuracy of the 1588v2 clock.
  • Embodiment 1 is a flowchart of a method for timestamp filtering provided by Embodiment 1 of the present invention
  • Embodiment 2 is a schematic structural diagram of a system for time stamp filtering provided by Embodiment 2 of the present invention
  • Embodiment 3 is a schematic diagram of generating 1588 timestamp and packet interaction in Embodiment 2 of the present invention.
  • Embodiment 4 is a flowchart of a method for timestamp filtering provided by Embodiment 2 of the present invention.
  • FIG. 5 is a schematic diagram of distribution of timestamp data before filtering in Embodiment 2 of the present invention.
  • FIG. 6 is a schematic diagram of distribution of time-stamped data after filtering in Embodiment 2 of the present invention.
  • FIG. 7 is a structural block diagram of a time filtering apparatus according to Embodiment 3 of the present invention.
  • the present invention provides a timestamp filtering method and apparatus, in order to solve the problem that the time-stability jump of the 1588 protocol is caused by the timestamp abnormality or the timestamp precision of the 1588 protocol, which affects the accuracy of the time calculation of the 1588v2 clock.
  • the embodiments of the present invention are described below in conjunction with the accompanying drawings and embodiments. It is to be understood that the embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
  • This embodiment aims to propose an abnormal timestamp filtering method based on the 1588 precise time protocol.
  • the time stamp of the 1588v2 clock is a series of discrete points.
  • the debounce filtering process is performed on a timestamp with a small clock frequency offset and a small timestamp fluctuation; and a series of timestamps with a clock offset or a large timestamp fluctuation are filtered to remove the abnormal timestamp.
  • the accuracy of time synchronization can be improved, and the time synchronization between communication devices can be realized by the Precision Time Protocol (PTP).
  • PTP Precision Time Protocol
  • FIG. 1 is a flowchart of a method for timestamp filtering according to Embodiment 1 of the present invention. As shown in FIG. 1, the method includes:
  • Step 101 Time-reading a timestamp of the time synchronization message and a correction domain corresponding to the timestamp
  • a logic device may be used to generate a timestamp of the time synchronization message.
  • the logic device is referred to as a timestamp generator. Based on this, the timed read timestamp and the correction domain corresponding to the timestamp may be used.
  • the method includes: reading a timestamp from a timestamp generator of a time synchronization message and a correction domain corresponding to the timestamp.
  • Step 102 Calculate a compensation value according to the read time stamp and the correction domain, and use the compensation value for time correction;
  • the calculating the compensation value according to the read time stamp and the correction domain, and using the compensation value for the time correction may include:
  • the calculated compensation value is counted in the preset time period. If the accumulated sum of the compensation values exceeds the preset threshold within the preset time period, the compensation value is continuously calculated according to the read time stamp and the corresponding correction domain. And the compensation value is used for the time correction; if the accumulated value of the compensation value does not exceed the preset threshold within the preset time period, then the phase locked loop is set to the locked state, and then step 103 is performed.
  • the preset time period can be set to about 30 seconds, and can be adjusted according to actual conditions. If the accumulated value of the compensation value exceeds the preset threshold within the preset time period, the 1588v2 clock is considered to be out of lock.
  • the preset threshold value ranges from 0 to 300 nanoseconds. In the case where the clock time is stable, the accumulated sum of the compensation values within the preset time period should not exceed the preset threshold.
  • the compensation value includes: the value calculated according to the data such as the time stamp.
  • the embodiment of the present invention includes the calculation of the compensation value when the 1588v2 clock is not locked, and the data such as the time stamp used for calculating the compensation value is not filtered. In the case of 1588v2 clock lock, the data such as the time stamp is processed first, and then the compensation value is calculated.
  • Step 103 Perform filtering processing on the read timestamp; optionally, in the embodiment, the filtering process is a median value average filtering process.
  • Step 104 Divide the filtered data into one or more time windows, and perform linear regression jitter vector estimation on data in each time window;
  • a time window may be used.
  • a person skilled in the art may set a time window related parameter according to the clock lock condition and the fluctuation of the time stamp, and estimate the data in the time window to determine the clock. Locking conditions and fluctuations in timestamps; time windows work periodically. When two or more time windows are employed, one skilled in the art can make parameter settings for each time window based on the relevant parameters of a time window.
  • Step 105 Determine whether the timestamp is abnormal according to the result of the linear regression jitter vector estimation; when determining that the timestamp is abnormal, perform step 106; and when it is determined that the timestamp is normal, perform step 107.
  • determining whether the timestamp is abnormal according to the result of the linear regression jitter vector estimation may include:
  • the linear regression jitter vector estimation is performed on the data in each time window by using the least square method to obtain the vector information of the frequency in the time window; determining whether the time stamp has a fixed frequency offset according to the vector information of the frequency; reading using the least squares method
  • the obtained timestamp estimates the residual, determines whether the timestamp has a hop according to the residual, and determines the timestamp abnormality if the timestamp has a fixed frequency offset and/or an abnormal hop.
  • the vector information of the frequency may include a slope of the vector
  • determining whether the timestamp has a fixed frequency offset according to the vector information of the frequency may include: determining that the timestamp has a fixed frequency offset if the slope of the vector is a non-zero constant.
  • Step 106 Filter the timestamp of the exception
  • the method for filtering the abnormal timestamp may include: 1. directly discarding the abnormal timestamp; 2. using a software correction for the timestamp with the hopping (eg, wavelet denoising or low-pass filtering, etc.).
  • a software correction for the timestamp with the hopping eg, wavelet denoising or low-pass filtering, etc.
  • Step 107 Perform time correction using the compensation value.
  • Performing the time correction in this embodiment may include writing the compensation value to the time stamp generator such that the time stamp generator uses the compensation value for time correction.
  • filtering and time calculation in the embodiment of the present invention are mainly implemented by a CPU.
  • the time system is maintained by the FPGA, and the time offset calculated by the CPU needs to be written to the FPGA for time correction.
  • Embodiments of the invention may be implemented by hardware comprising a CPU and an FPGA.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the time stamp filtering method.
  • This embodiment describes the method of timestamp filtering provided by the embodiment of the present invention on the basis of the foregoing embodiment 1.
  • FIG. 2 is a schematic structural diagram of a timestamp filtering system according to Embodiment 2 of the present invention.
  • the system may include two or two network elements, and this embodiment includes a network element A and a network element B.
  • the invention relates to an Ethernet switching processing unit, a central processing unit (CPU) processing unit, and an FPGA (Field-Programmable Gate Array) processing unit (that is, the timestamp generator in the first embodiment).
  • the CPU processing unit is mainly responsible for packet grouping, message control enable, filtering of 1588v2 clock, time calculation, etc.
  • FPGA processing unit The element is mainly responsible for time stamping the message for the CPU to calculate, and the Ethernet switching processing unit is responsible for the exchange and forwarding of the message.
  • SSM clock mark
  • the best master clock (BMC) algorithm is used to determine the master-slave state of each network element in 1588, and the 1588 protocol is used to send 1588 messages between the primary network element and the secondary network element.
  • the software registers and maintains a 1-second timer, periodically reads the state of the FPGA, and obtains the timestamp of the time synchronization message, for example, t1, t2, t3, t4 timestamp and corresponding timestamps as shown in FIG.
  • Correction data filter the timestamp and correction domain to calculate the offset (Offset), and write the compensation to the FPGA completion time correction.
  • the method for timestamp filtering provided in this embodiment may include:
  • Step 401 Enable 1588v2 clock time synchronization, and determine the master-slave port; include: powering on the network element, configuring 1588 time synchronization, and determining the master-slave state of the network element according to the best master clock (BMC) algorithm; each network element is based on The master-slave state and the configuration information sent by the self-decision are sent corresponding messages;
  • BMC master clock
  • the configuration parameters include: a delay measurement method: a one-step method; a PTP protocol packet format: 1588 OverETH; a synchronization packet (sync, Synchronous Packet) message transmission frequency and a synchronization sent from a master to a slave (slave) direction.
  • the packet is: 16 packets can be sent per second; the delay request packet (delay_req, Delay Request Packet) message sending frequency and the delay_req message from the slave to the master direction are: 16 packets are sent every second; the CPU saves the PTP. Configuration data and status of the port (for the timestamp of the timer polling the PTP port).
  • the CPU determines the master-slave status of the port based on the received and received announcements, and enables the corresponding packets according to the port status to implement normal interaction of 1588 packets.
  • Step 402 Extract a packet and read a timestamp of the 1588v2 clock.
  • the method includes: a CPU processing unit. A 1 second (S) timer is implemented. If the network element is the primary network element, no processing is performed. If the network element is a secondary network element, the timestamps t1, t2, t3, and t4 are read from the FPGA. The correction field of the timestamp.
  • Step 403 Determine whether the phase locked loop of the 1588v2 clock is locked.
  • the method may include: the software calculates an offset value according to the extracted timestamp and the corresponding correction domain, and writes the offset to the FPGA for time correction. In the process, the offset is counted. If the accumulated sum of the offset exceeds the preset threshold within a specified time, the time of the 1588v2 clock is not locked, and the filtering process is not performed, and the above step 403 is continued; If the accumulated sum of the offset does not exceed the preset threshold, set the phase locked loop of the 1588v2 clock to the locked state, and enable the filtering algorithm to improve the synchronization precision. Go to step 404, for example, if the offset is accumulated within 30 seconds.
  • Step 403 If the time of the 1588v2 clock is lost, the time of the 1588v2 clock is lost, and no filtering is performed. Step 403 is continued. If the accumulated sum of the offset is less than 300 nanoseconds within 30 seconds, the 1588 phase-locked loop is set to the locked state and the filtering is enabled. The algorithm increases the synchronization accuracy and proceeds to step 404.
  • Delay [T2-T1-T2T1Correction+T4-T3-T4T3Correction]/2;
  • Offset [T2-T1-T2T1Correction-T4+T3+T4T3Correction]/2.
  • Step 404 Start a time filtering algorithm for the 1588v2 clock, and include: first performing a filtering process on the timestamp read by the 1 second timer to initially remove the jitter.
  • N timestamps can be read in one second (N can take 1, 2, 4 to 128), and the delays calculated from the i-th timestamp data are x(i) and y(i), respectively.
  • Step 405 Determine whether the timestamp is abnormal according to the result of the linear regression jitter vector estimation, and may include: taking a fixed length estimation time window (calculating the initial time window data to start calculation) for the filtered data, and performing linearity by using a least squares method Regression jitter vector estimation.
  • the least squares estimate that the slope can be expressed as freq represents the frequency vector information in the short time window. Since the time window is relatively short, if the fixed flow rate is locked, the estimation result is in accordance with the normal distribution, and the mean value is approximately 0. When there is a fixed frequency offset, the mean value is non-zero constant. When the delay changes, the slope estimated by the least squares method will have a large outlier in the same direction and continue until the transition occurs.
  • the least-squares method is used to estimate the residual value of the timestamp, which is used to represent the fluctuation of the timestamp.
  • timestamps there is solid In the case of fixed frequency offset or abnormal hopping, it is considered that there is an abnormality in the timestamp at this time, the system discards it and does not participate in the time correction, and at the same time clears the data in the time window and collects again. The time at this time is kept by the system clock. Otherwise, it is considered that the normal timestamp is collected, and the point on the fitted curve is used for time calculation. For example, for the filtered data, 16 seconds is taken as the estimated time window (the data is collected after 3 seconds), The data in the time window is estimated by linear regression using least squares.
  • FIG. 5 is a schematic diagram of distribution of timestamp data before filtering according to Embodiment 2 of the present invention. As shown in FIG. 5, the timestamp distribution before filtering, the timestamp uncertainty is large; FIG. 6 is filtering in Embodiment 2 of the present invention. After the timestamp data distribution diagram, as shown in FIG. 6, the timestamp distribution obtained after filtering is more stable than before filtering.
  • Step 406 When determining that the timestamp is abnormal, calculate a time offset of the 1588v2 clock, and correct the system time; where the time deviation is a compensation value;
  • the 1588 phase-locked loop is considered to be out of lock, and the above step 403 is continued; if the time stamp of the 1588v2 clock is normal, the filtered time is used. The stamp is subjected to an offset calculation, and the calculated offset is written to the FPGA for time correction, while the time window data in step 404 is updated.
  • the method of the embodiment of the present invention includes the following advantages:
  • the 1588 timestamp provided by the logic device fluctuates due to noise, jitter, network delay, or other reasons, it can be effectively filtered to avoid fluctuations in the time synchronization of the network element.
  • the vector estimation can be detected and filtered out in time to avoid the abnormal adjustment of the time caused by the abnormal jump.
  • the embodiment of the invention can effectively improve the time synchronization accuracy of the 1588v2 clock.
  • FIG. 7 is a structural block diagram of a time filtering device according to Embodiment 3 of the present invention. As shown in FIG. 7, the device 70 includes:
  • the reading module 71 is configured to periodically read the timestamp and the correction domain corresponding to the timestamp;
  • the calculating module 72 is configured to calculate a compensation value according to the read time stamp and the correction domain, and use the calculated compensation value for time correction;
  • the filtering module 73 is configured to filter the read timestamp
  • the estimating module 74 is configured to divide the filtered data into one or more time windows, and perform linear regression jitter vector estimation on the data in each time window;
  • a determining module 75 configured to determine whether the timestamp is abnormal according to a result of the linear regression jitter vector estimation
  • the filtering module 76 is configured to filter the timestamp of the abnormality if the timestamp is abnormal; if the timestamp is normal, use the compensation value for time correction.
  • the calculating module 74 is configured to: calculate the calculated compensation value within a preset time period, and if the accumulated sum of the compensation values exceeds the preset threshold within the preset time period, continue to be based on the read time stamp. And the corresponding correction domain calculates the compensation value, and uses the compensation value for the time correction; if the accumulated value of the compensation value does not exceed the preset threshold within the preset time period, the phase locked loop is set to the locked state, and the timing reading is determined. The timestamp is taken for filtering.
  • the determining module 75 may include: a first estimating unit configured to perform linear regression jitter vector estimation by using a least square method for data in each time window to obtain vector information of a frequency in a time window; And determining, according to the vector information of the frequency, whether the timestamp has a fixed frequency offset; the second estimating unit is configured to estimate a residual value of the read timestamp by using a least square method, and determine whether the timestamp has a jump according to the residual; The second determining unit is configured to determine that the timestamp is abnormal when the timestamp has a fixed frequency offset and/or an abnormal hop.
  • the vector information of the frequency includes a slope of the vector, and the first determining unit is configured to: when the slope of the existence vector is greater than a preset abnormal value in the same direction, determining that the time stamp has a fixed frequency offset.
  • each module/unit in the foregoing embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, being executed by a processor and stored in a memory. Programs/instructions to implement their respective functions.
  • the invention is not limited to any particular form of hardware and software Combination of.

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Abstract

一种时间戳过滤的方法及装置，包括：定时读取时间戳以及与时间戳对应的修正域；根据读取到的时间戳和修正域计算补偿值，将该补偿值用于时间修正；对读取到的时间戳进行滤波处理；将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；根据线性回归抖动矢量估算的结果确定时间戳是否异常；如果时间戳异常，则过滤异常的时间戳，如果时间戳正常，则使用补偿值进行时间修正。本发明实施例方案提高了1588v2时钟的时间同步精度。

Description

一种时间戳过滤的方法及装置 技术领域
本文涉及但不限于通讯领域，尤其涉及一种时间戳过滤的方法及装置。
背景技术
1588v2时钟是一种采用IEEE1588V2协议的高精度时钟，其在行业对高精度授时迫切需求的大背景下孕育而生，以传统的物理时钟方式实现相位对齐，通过1588报文交互实现时间校对。
传统的地面时间同步链路采用网络时间协议(NTP，Network Time Protocol)传送方式实现，目前已发展到v4版本，简单网络时间协议(SNTP)为NTP的简化版，标准为RFC 2030(SNTPv4)。该协议最大的缺点是只能满足毫秒(ms)级别的时间传递精度，这对于高精度时间同步所需纳秒(ns)级来说，时间的精度是远远不够的。采用单向信道的全球定位系统(GPS)时间同步系统，虽然同步信号的获得稳定可靠、精度高，但其价格高(设备、安装、维护成本)、施工难度大(基站放在地下室)、失效率也高，同时存在政治和安全风险。
与传统授时技术相比，1588v2时钟有着明显的优势，其采用双向信道、精度为ns级、费用低、能适应不同的接入环境等等。在对精度要求不断提高的行业背景下，1588v2时钟已成为一种发展的必然趋势。但是在存在噪声、时钟抖动、网络延时或其它原因造成逻辑器件提供的1588v2时钟的时间戳异常或时间戳精度差时，会出现时间异常跳变，影响了1588v2时钟进行时间计算的准确性。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供一种时间戳过滤的方法及装置，能够提高1588v2时钟的时间同步精度。
根据本发明实施例的一个方面，提供了一种时间戳过滤的方法，所述方法包括：
定时读取时间同步报文的时间戳以及与时间戳对应的修正域；
根据读取到的所述时间戳和所述修正域计算补偿值，将该补偿值用于时间修正；
对读取到的所述时间戳进行滤波处理；
将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；
根据线性回归抖动矢量估算的结果确定所述时间戳是否异常；
如果所述时间戳异常，则过滤异常的所述时间戳，如果所述时间戳正常，则使用所述补偿值进行时间修正。
可选的，根据读取到的时间戳和修正域计算补偿值，将该补偿值用于时间修正，包括：
在预设时间段内对计算出的补偿值进行统计，如果在预设时间段内补偿值的累加和超过预设阈值，则继续根据读取到的时间戳和相应的修正域计算补偿值，并将该补偿值用于时间修正；如果在预设时间段内补偿值的累加和未超过预设阈值，则设置锁相环为锁定状态，确定对定时读取的时间戳进行滤波处理。
可选的，根据线性回归抖动矢量估算的结果确定时间戳是否异常，包括：
对每一个时间窗内的数据利用最小二乘法进行线性回归抖动矢量估算，得到所述时间窗内的频率的向量信息；根据频率的向量信息确定所述时间戳是否具有固定频偏；使用最小二乘法对读取到的所述时间戳估算出残差，根据残差确定时间戳是否存在跳变；当所述时间戳存在固定频偏和/或异常跳变的情况下，确定所述时间戳异常。
可选的，频率的向量信息包括向量的斜率，所述根据频率的向量信息确定时间戳是否具有固定频偏，包括：
在向量的斜率为非零常量时，确定所述时间戳存在固定频偏。
其中，所述定时读取所述时间戳以及与所述时间戳对应的所述修正域，包括：从时间同步报文的时间戳生成器中读取所述时间戳以及与所述时间戳对应的所述修正域；所述将所述补偿值用于时间修正，包括：将所述补偿值写入时间戳生成器，以使时间戳生成器使用所述补偿值进行时间修正。
可选的，滤波处理包括：对读取到的时间戳进行中位值平均滤波处理。
根据本发明实施例的第二个方面，提供了一种时间戳过滤的装置，所述装置包括：
读取模块，设置为定时读取时间同步报文的时间戳以及与所述时间戳对应的修正域；
计算模块，设置为根据读取到的时间戳和所述修正域计算补偿值，将计算获得的该补偿值用于时间修正；
滤波模块，设置为对读取到的时间戳进行滤波处理；
估算模块，设置为将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；
确定模块，设置为根据线性回归抖动矢量估算的结果确定所述时间戳是否异常；
过滤模块，设置为如果所述时间戳异常，则过滤异常的时间戳；如果所述时间戳正常，则使用补偿值进行时间修正。
可选的，所述计算模块设置为：在预设时间段内对计算出的所述补偿值进行统计，如果在预设时间段内所述补偿值的累加和超过预设阈值，则继续根据读取到的所述时间戳和相应的所述修正域计算所述补偿值，并将该补偿值用于时间修正；如果在预设时间段内所述补偿值的累加和未超过预设阈值，则设置锁相环为锁定状态，确定对定时读取的所述时间戳进行滤波处理。
可选的，所述确定模块，包括：第一估算单元，设置为对每一个时间窗内的数据利用最小二乘法进行线性回归抖动矢量估算，得到时间窗内的频率的向量信息；第一确定单元，设置为根据频率的向量信息确定所述时间戳是否具有固定频偏；第二估算单元，设置为使用最小二乘法对读取到的时间戳估算出残差，根据残差确定所述时间戳是否存在跳变；第二确定单元，设置 为当所述时间戳存在固定频偏和/或异常跳变的情况下，确定所述时间戳异常。
可选的，频率的向量信息包括向量的斜率，所述第一确定单元是设置为：在向量的斜率为非零常量时，确定时间戳存在固定频偏。
可选的，所述读取模块设置为：从时间同步报文的时间戳生成器中读取所述时间戳以及所述时间戳对应的修正域；
所述过滤模块使用补偿值进行时间修正包括：
根据读取到的时间戳和所述修正域计算补偿值，将计算获得的所述补偿值写入所述时间戳生成器，以使所述时间戳生成器使用所述补偿值进行时间修正。
与相关技术相比，本发明实施例提供的技术方案，包括：定时读取时间戳以及与时间戳对应的修正域；根据读取到的时间戳和修正域计算补偿值，将该补偿值用于时间修正；对读取到的时间戳进行滤波处理；将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；根据线性回归抖动矢量估算的结果确定时间戳是否异常；如果时间戳异常，则过滤异常的时间戳，如果时间戳正常，则使用补偿值进行时间修正。本发明实施例方案提高了1588时间同步精度。
本发明实施例的有益效果包括：
本发明实施例提供的方案，针对由噪声、抖动、网络延时或其它原因造成逻辑器件提供的1588v2时钟的时间戳存在波动的情况，可对存在的波动进行有效的滤除，避免网元时间同步出现波动，提高了1588v2时钟的时间同步精度。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1是本发明实施例1提供的时间戳过滤的方法的流程图；
图2是发明实施例2提供的时间戳过滤的系统的结构示意图；
图3是本发明实施例2中关于1588时间戳的生成及报文交互示意图；
图4是本发明实施例2提供的时间戳过滤的方法的流程图；
图5本发明实施例2中滤波前的时间戳数据分布示意图；
图6本发明实施例2中滤波后的时间戳数据分布示意图；
图7是本发明实施例3提供的时间过滤的装置的结构框图。
本发明的实施方式
下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
为了解决现有技术基于1588协议的时间戳异常或时间戳精度差而导致时间异常跳变，影响1588v2时钟的时间计算的准确性的问题，本发明提供了一种时间戳过滤的方法及装置，以下结合附图以及实施例，对本发明实施例进行说明。应当理解，此处所描述的实施例仅仅用以解释本发明，并不限定本发明。
实施例1
本实施例旨在提出一种基于1588精确时间协议的异常时间戳过滤的方法，1588v2时钟的时间戳是一系列离散的点，通过对时间戳的处理，可以估算出时钟频偏的变化情况以及时间戳的波动情况。本实施例中，对于时钟频偏很小，时间戳波动较小的时间戳进行去抖滤波处理；对于时钟存在频偏或时间戳波动较大的一系列时间戳进行滤除，去除异常时间戳对1588v2时钟的时间计算带来的影响，基于此，可以提高时间同步的精度，通过精确时间协议(PTP)实现通讯设备之间的时间同步。
图1是本发明实施例1提供的时间戳过滤的方法的流程图，如图1所示，该方法包括：
步骤101：定时读取时间同步报文的时间戳以及与时间戳对应的修正域；
在本实施例中可以使用逻辑器件来产生时间同步报文的时间戳，本实施例中称该逻辑器件为时间戳生成器，基于此，定时读取时间戳以及与时间戳对应的修正域可以包括：从时间同步报文的时间戳生成器中读取时间戳以及时间戳对应的修正域。
步骤102：根据读取到的时间戳和修正域计算补偿值，将该补偿值用于时间修正；
其中，根据读取到的时间戳和修正域计算补偿值，并将该补偿值用于时间修正，可以包括：
在预设时间段内对计算出的补偿值进行统计，如果在预设时间段内补偿值的累加和超过预设阈值，则继续根据读取到的时间戳和相应的修正域计算补偿值，并将该补偿值用于时间修正；如果在预设时间段内补偿值的累加和未超过预设阈值，则设置锁相环为锁定状态，则执行步骤103。
需要说明的是，预设时间段可以设置为30秒左右，可以根据实际情况进行调整。补偿值的累加和在预设时间段内超过预设阈值，则认为1588v2时钟失锁，预设阈值的取值范围是0～300纳秒。在时钟时间稳定的情况下，预设时间段内补偿值的累加和不应超过预设阈值。补偿值包括：依据时间戳等数据计算出来的数值，本发明实施例包括1588v2时钟没有锁定情况下的补偿值计算，用于计算补偿值的时间戳等数据没有经过滤波处理。在1588v2时钟锁定情况下，先将时间戳等数据进行处理，再用其计算补偿值。
步骤103：对读取到的时间戳进行滤波处理；可选的，在本实施例中，该滤波处理为中位值平均滤波处理。
步骤104：将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；
本发明实施例，可以采用一个时间窗，本领域技术人员可以根据可以判断出时钟锁定情况以及时间戳的波动情况设定时间窗的相关参数，对时间窗内的数据进行估算，能判断出时钟锁定情况以及时间戳的波动情况；时间窗周期性地进行工作。采用两个或两个以上时间窗时，本领域技术人员可以基于一个时间窗的相关参数进行每一个时间窗的参数设置。
步骤105：根据线性回归抖动矢量估算的结果确定时间戳是否异常；确定时间戳异常时，执行步骤106；确定时间戳正常时，执行步骤107。
可选的，根据线性回归抖动矢量估算的结果确定时间戳是否异常可以包括：
对每一个时间窗内的数据利用最小二乘法进行线性回归抖动矢量估算，得到时间窗内的频率的向量信息；根据频率的向量信息确定时间戳是否具有固定频偏；使用最小二乘法对读取到的时间戳估算出残差，根据残差确定时间戳是否存在跳变；当时间戳存在固定频偏和/或异常跳变的情况下，确定时间戳异常。可选的，频率的向量信息可以包括向量的斜率，根据频率的向量信息确定时间戳是否具有固定频偏可以包括：在向量的斜率为非零常量的情况下，确定时间戳存在固定频偏。
步骤106：过滤异常的时间戳；
需要说明的是，过滤异常时间戳的方法可以包括：1、直接丢弃异常时间戳；2、对于存在跳变的时间戳可使用软件修正(如：小波降噪或低通滤波等)。
步骤107、使用补偿值进行时间修正。
在本实施例中进行时间修正可以包括：将补偿值写入时间戳生成器，以使时间戳生成器使用补偿值进行时间修正。
需要说明的是，本发明实施例过滤及时间计算等功能主要由CPU实现。时间系统由FPGA来维护，CPU计算出的时间偏差需写入FPGA来进行时间修正。本发明实施例可以通过包含CPU和FPGA的硬件执行。
本发明实施例还提供一种计算机存储介质，计算机存储介质中存储有计算机可执行指令，计算机可执行指令用于执行上述时间戳过滤的方法。
实施例2
本实施例在上述实施例1的基础上，对本发明实施例提供的时间戳过滤的方法进行阐述。
图2是本发明实施例2提供的时间戳过滤系统的结构示意图，如图2所示，该系统可以包括两个或两个以上网元，本实施例包括网元A和网元B；主要涉及以太网交换处理单元、中央处理器(CPU)处理单元及FPGA(Field－Programmable Gate Array，即现场可编程门阵列)处理单元(即上述实施例1中的时间戳生成器)等几个处理单元，其中CPU处理单元主要负责报文组包、报文控制使能、1588v2时钟的滤波以及时间计算等功能，FPGA处理单 元主要负责给报文打时间戳，供CPU进行计算，以太网交换处理单元则负责报文的交换转发等。
本实施例所涉及的时间同步功能的实现主要包含频率同步以及时间同步两个方面的内容：
对于频率同步，采用物理层同步实现，通过时钟标记(SSM)算法建立时钟的跟踪关系，从时钟利用锁定后的系统时钟实现时间计数，进而实现系统时间的相位跟踪。
对于时间同步，首先利用最佳主时钟(BMC)算法决策出1588每一个网元的主从状态，利用1588协议在主网元和从网元之间互发1588报文。同时软件注册并维护1秒定时器，定时读取FPGA的状态，获取时间同步报文的时间戳，例如，如图3中所示的t1、t2、t3、t4时间戳以及每一个时间戳对应的修正域(correction)数据，对时间戳和修正域进行滤波计算补偿值(Offset)，并将该补偿写入FPGA完成时间修正。
图4是本发明实施例2提供的时间戳过滤的方法的流程图，如图4所示，本实施例提供的时间戳过滤的方法可以包括：
步骤401，启用1588v2时钟时间同步，决策主从端口；包括：网元上电，配置1588时间同步，并根据最佳主时钟(BMC)算法决策出网元的主从状态；每一个网元根据自身决策出的主从状态以及配置信息发送相应的报文；
其中，配置参数包括：延迟测量方式为：一步法；PTP协议包格式为：1588OverETH；同步报文(sync，Synchronous Packet)消息发送频率和sync为主机(master)到从机(slave)方向发送的报文为：每秒可以发送16个包；延时请求报文(delay_req，Delay Request Packet)消息发送频率和delay_req为slave到master方向的报文为：每秒发送16个包；CPU保存该PTP端口的配置数据及状态(用于定时器轮询该PTP端口的时间戳)。构造需要发送的sync报文和delay_req报文格式，由CPU预先写FPGA寄存器。CPU根据收发的宣称(announce)报文决策端口主从状态，并根据端口状态使能相应的报文，实现1588报文的正常交互。
步骤402，提取报文，读取1588v2时钟的时间戳；包括：CPU处理单元 实现一个1秒(S)定时器，若本网元是主网元，不进行任何处理；若本网元是从网元，则从FPGA中读取时间戳t1、t2、t3、t4和相应时间戳的修正域(correction)。
步骤403，确定1588v2时钟的锁相环是否锁定；可以包括：软件根据提取到的时间戳和相应的修正域计算补偿值(offset)，并将offset写入FPGA进行时间修正。在该过程中，对offset进行统计，如果在规定的时间内，offset的累加和超过预设阈值，则认为1588v2时钟的时间没有锁定，不进行滤波处理，继续执行上述步骤403；如果在规定的时间内offset的累加和没有超过预设阈值，则设置1588v2时钟的锁相环为锁定状态，同时启用滤波算法提高同步精度，转至步骤404，例如，如果30秒的时间内，offset的累加和超过300纳秒，则认为1588v2时钟的时间失锁，不进行滤波处理，继续执行步骤403；如果30秒内offset的累加和小于300纳秒，则设置1588锁相环为锁定状态，同时启用滤波算法提高同步精度，转至步骤404。
其中，Delay＝[T2－T1－T2T1Correction+T4－T3－T4T3Correction]/2；
Offset＝[T2－T1－T2T1Correction－T4+T3+T4T3Correction]/2。
步骤404，启动1588v2时钟的时间滤波算法；可以包括：对1秒定时器读取到的时间戳首先进行一次滤波处理，初步去除抖动。假设1秒钟可读取到N个时间戳(N可取1、2、4～128)，根据第i个时间戳数据计算得到的时延分别为x(i)和y(i)，则x(i)＝delay+offset＝t2(i)–t1(i)–t2t1correction(i)，y(i)＝delay-offset＝t4(i)–t3(i)–t4t3correction(i)，再分别对两组数据进行中位值平均滤波得到平均时延。
步骤405，根据线性回归抖动矢量估算的结果确定时间戳是否异常；可以包括：对于滤波后的数据，取固定长度估算时间窗(集齐初始时间窗数据就开始计算)，利用最小二乘法进行线性回归抖动矢量估算。最小二乘估算出斜率可以表示为freq，代表短时间窗里频率向量信息。由于时间窗比较短，如果是在锁定固定流量，估算结果是符合正态分布的，均值近似为0，当存在固定频偏时，均值为非0常量。当时延发生变化时，最小二乘法估算出的斜率会出现同一方向的较大异常值，持续到跳变发生区间。同时使用最小二乘法对时间戳估算出残差，用来代表时间戳的波动情况。对于时间戳存在固 定频偏的情况或者存在异常跳变的情况，认为此时的时间戳存在异常，系统将其丢弃不参与时间修正，同时清空时间窗中的数据重新收集，此时的时间采用系统时钟保持计数；否则认为收集到正常的时间戳，并取拟合曲线上的点进行时间计算，例如，对于滤波后的数据，取16秒为估算时间窗(集齐3秒的数据就开始计算)，对时间窗中的数据利用最小二乘法进行线性回归估算。
图5为本发明实施例2中滤波前的时间戳数据分布示意图，如图5所示，滤波前的时间戳分布情况，时间戳不确定性较大；图6为本发明实施例2中滤波后的时间戳数据分布示意图，如图6所示，滤波后得到的时间戳分布情况较滤波前稳定。
步骤406，确定时间戳异常时，计算1588v2时钟的时间偏差，修正系统时间；这里，时间偏差为补偿值；
本发明实施例，如果1588v2时钟的时间戳持续异常(例如，连续3次)，则认为1588锁相环失锁，继续执行上述步骤403；如果1588v2时钟的时间戳正常，则用滤波后的时间戳进行offset计算，并将计算出的offset写入FPGA进行时间校正，同时更新步骤404中的时间窗数据。
采用本发明实施例方法，与相关技术相比，包括如下优势：
针对噪声、抖动、网络延时或其它原因造成逻辑器件提供的1588时间戳存在波动的情况，可对其进行有效的滤除，避免网元时间同步出现波动。对于现有缺陷造成时间戳突然出现较大跳变的情况，通过矢量估算可及时发现并滤除，避免异常跳变带来的时间非正常调整。本发明实施例可有效提高1588v2时钟的时间同步精度。
实施例3
本实施例提供了一种时间戳过滤的装置，图7是本发明实施例3提供的时间过滤装置的结构框图，如图7所示，该装置70包括：
读取模块71，设置为定时读取时间戳以及与时间戳对应的修正域；
计算模块72，设置为根据读取到的时间戳和修正域计算补偿值，并将计算获得的该补偿值用于时间修正；
滤波模块73，设置为对读取到的时间戳进行滤波处理；
估算模块74，设置为将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；
确定模块75，设置为根据线性回归抖动矢量估算的结果确定所述时间戳是否异常；
过滤模块76，设置为如果所述时间戳异常，则过滤异常的时间戳；如果所述时间戳正常，则使用补偿值进行时间修正。
其中，上述计算模块74设置为：在预设时间段内对计算出的补偿值进行统计，如果在预设时间段内补偿值的累加和超过预设阈值，则继续根据读取到的时间戳和相应的修正域计算补偿值，并将该补偿值用于时间修正；如果在预设时间段内补偿值的累加和未超过预设阈值，则设置锁相环为锁定状态，确定对定时读取的时间戳进行滤波处理。
其中，上述确定模块75可以包括：第一估算单元，设置为对每一个时间窗内的数据利用最小二乘法进行线性回归抖动矢量估算，得到时间窗内的频率的向量信息；第一确定单元，设置为根据频率的向量信息确定时间戳是否具有固定频偏；第二估算单元，设置为使用最小二乘法对读取到的时间戳估算出残差，根据残差确定时间戳是否存在跳变；第二确定单元，设置为当时间戳存在固定频偏和/或异常跳变的情况下，确定时间戳异常。
其中，频率的向量信息包括向量的斜率，第一确定单元是设置为：存在向量的斜率在同一方向大于预设的异常值时，确定时间戳存在固定频偏。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的每个模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本发明不限制于任何特定形式的硬件和软件 的结合。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请，如本发明实施方式中的具体的实现方法。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。
工业实用性
上述技术方案提高了1588v2时钟的时间同步精度。

Claims (11)

  1. 一种时间戳过滤的方法，所述方法包括：
    定时读取时间同步报文的时间戳以及与所述时间戳对应的修正域；
    根据读取到的所述时间戳和所述修正域计算补偿值，将该补偿值用于时间修正；
    对读取到的所述时间戳进行滤波处理；
    将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；
    根据线性回归抖动矢量估算的结果确定所述时间戳是否异常；
    如果所述时间戳异常，则过滤异常的所述时间戳；如果所述时间戳正常，则使用补偿值进行时间修正。
  2. 根据权利要求1所述的方法，其中，所述根据读取到的时间戳和所述修正域计算所述补偿值，并将该补偿值用于时间修正，包括：
    在预设时间段内对计算出的所述补偿值进行统计，如果在预设时间段内所述补偿值的累加和超过预设阈值，则继续根据读取到的所述时间戳和相应的所述修正域计算补偿值，并将所述补偿值用于时间修正；如果在预设时间段内所述补偿值的累加和未超过所述预设阈值，则设置锁相环为锁定状态，确定对定时读取的所述时间戳进行滤波处理。
  3. 根据权利要求1所述的方法，其中，所述根据所述线性回归抖动矢量估算的结果确定所述时间戳是否异常，包括：
    对每一个所述时间窗内的数据利用最小二乘法进行所述线性回归抖动矢量估算，得到所述时间窗内的频率的向量信息；
    根据所述频率的向量信息确定所述时间戳是否具有固定频偏；
    使用最小二乘法根据读取到的所述时间戳估算出残差，根据所述残差确定所述时间戳是否存在跳变；
    当所述时间戳存在固定频偏和/或异常跳变的情况下，确定所述时间戳异常。
  4. 根据权利要求3所述的方法，其中，所述频率的向量信息包括所述频率向量的斜率，所述根据所述频率的向量信息确定所述时间戳是否具有固定频偏，包括：
    在所述频率向量的斜率为非零常量时，确定所述时间戳存在固定频偏。
  5. 根据权利要求1～4任一项所述的方法，其中，
    所述定时读取时间同步报文的时间戳以及与所述时间戳对应的所述修正域，包括：从时间同步报文的时间戳生成器中读取所述时间戳以及所述时间戳对应的所述修正域；
    所述将所述补偿值用于时间修正，包括：将所述补偿值写入所述时间戳生成器，以使所述时间戳生成器使用所述补偿值进行时间修正。
  6. 根据权利要求1～4任一项所述的方法，其中，所述滤波处理包括：
    对读取到的所述时间戳进行中位值平均滤波处理。
  7. 一种时间戳过滤的装置，所述装置包括：
    读取模块，设置为定时读取时间同步报文的时间戳以及与所述时间戳对应的修正域；
    计算模块，设置为根据读取到的所述时间戳和所述修正域计算补偿值，将计算获得的该补偿值用于时间修正；
    滤波模块，设置为对读取到的所述时间戳进行滤波处理；
    估算模块，设置为将经过滤波处理后的数据划分为一个或一个以上时间窗，对每一个时间窗中的数据进行线性回归抖动矢量估算；
    确定模块，设置为根据线性回归抖动矢量估算的结果确定所述时间戳是否异常；
    过滤模块，设置为如果所述时间戳异常，则过滤异常的所述时间戳；如果所述时间戳正常，则使用补偿值进行时间修正。
  8. 根据权利要求7所述的装置，其中，所述计算模块设置为：
    在预设时间段内对计算出的所述补偿值进行统计，如果在预设时间段内所述补偿值的累加和超过预设阈值，则继续根据读取到的所述时间戳和相应 的所述修正域计算所述补偿值，并将该补偿值用于时间修正；如果在预设时间段内所述补偿值的累加和未超过所述预设阈值，则设置锁相环为锁定状态，确定对定时读取的所述时间戳进行滤波处理。
  9. 根据权利要求7所述的装置，其中，所述确定模块，包括：
    第一估算单元，设置为对每一个所述时间窗内的数据利用最小二乘法进行线性回归抖动矢量估算，得到所述时间窗内的频率的向量信息；
    第一确定单元，设置为根据所述频率的向量信息确定所述时间戳是否具有固定频偏；
    第二估算单元，设置为使用最小二乘法根据读取到的所述时间戳估算出残差，根据所述残差确定所述时间戳是否存在跳变；
    第二确定单元，设置为当所述时间戳存在固定频偏和/或异常跳变的情况下，确定所述时间戳异常。
  10. 根据权利要求9所述的装置，其中，所述频率的向量信息包括所述频率向量的斜率，所述第一确定单元是设置为：
    在所述频率向量的斜率为非零常量时，确定所述时间戳存在固定频偏。
  11. 根据权利要求7～9任一项所述的装置，其中，
    所述读取模块设置为：从时间同步报文的时间戳生成器中读取所述时间戳以及所述时间戳对应的修正域；
    所述过滤模块使用补偿值进行时间修正包括：
    根据读取到的时间戳和所述修正域计算补偿值，将计算获得的所述补偿值写入所述时间戳生成器，以使所述时间戳生成器使用所述补偿值进行时间修正。
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