WO2017032113A1 - 一种时间同步偏差检测方法和装置 - Google Patents

一种时间同步偏差检测方法和装置 Download PDF

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Publication number
WO2017032113A1
WO2017032113A1 PCT/CN2016/083671 CN2016083671W WO2017032113A1 WO 2017032113 A1 WO2017032113 A1 WO 2017032113A1 CN 2016083671 W CN2016083671 W CN 2016083671W WO 2017032113 A1 WO2017032113 A1 WO 2017032113A1
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time
deviation
timestamp data
nodes
frequency deviation
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PCT/CN2016/083671
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English (en)
French (fr)
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杨元永
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中兴通讯股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

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  • This document relates to but not limited to the field of network management, and in particular to a time synchronization deviation detection method and apparatus.
  • 1588V2 is a synchronization technology standard based on packet transmission. It uses timestamp mechanism and master-slave scheme to encode and transmit time, and realizes the symmetry and delay measurement technology of network link. Synchronization of the frequency and time of the master and slave clocks.
  • the frequency deviation performance and time deviation performance of the slave clock node relative to the master clock node is one of the most important detection indicators for the time synchronization of the packet network.
  • the least squares estimation model is used for the 1588V2 frequency recovery or frequency deviation estimation method, and the frequency or frequency offset is obtained after the least squares regression fitting. This method is more common, but it is more complicated to implement.
  • the least squares estimation model detects the failure if the input reference frequency is too large or the crystal is aged and the clock source cannot be locked.
  • This paper provides a time synchronization deviation detection method and device, which can solve the technical problem of failure of frequency deviation and time deviation detection between nodes when the input reference frequency is too large or the crystal oscillator is aging and the clock source cannot be locked.
  • a time synchronization deviation detection method provided by the present invention includes:
  • the frequency deviation and the time deviation between the nodes are calculated by a preset algorithm.
  • the method before the detecting the frequency deviation and the time deviation, the method further includes:
  • the method further includes:
  • the alarm information is output when any of the following conditions occurs:
  • the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold
  • the frequency deviation and/or the time deviation is less than a corresponding minimum threshold.
  • the method further includes:
  • the method further includes:
  • the timestamp data is deleted, and new timestamp data is stored;
  • the frequency deviation and the time deviation between the nodes are calculated by a preset algorithm.
  • the deleting the timestamp data and storing the new timestamp data includes:
  • the timestamp data is deleted, and new timestamp data is stored.
  • the calculating, by the preset algorithm, the frequency deviation between the nodes according to the timestamp data includes:
  • the frequency deviation between the nodes is calculated by a frequency deviation formula.
  • the calculating, by the preset algorithm, the time offset between the nodes according to the timestamp data includes:
  • the present invention also provides a time synchronization deviation detecting device, including:
  • a receiving module configured to receive a detection instruction of a frequency deviation and a time deviation
  • Obtaining a module configured to acquire timestamp data of the detection message between the nodes within a preset time according to the detection instruction
  • the calculating module is configured to calculate, according to the timestamp data, a frequency deviation and a time deviation between the nodes by using a preset algorithm.
  • the time synchronization deviation detecting device further includes:
  • a module configured to set the frequency deviation and the maximum threshold and the minimum threshold corresponding to the time deviation
  • the output module is set to output alarm information when any of the following conditions occurs:
  • the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold
  • the frequency deviation and/or the time deviation is less than a corresponding minimum threshold.
  • the time synchronization deviation detecting device further includes:
  • a storage module configured to store the timestamp data
  • Deleting the module setting to delete the timestamp data and storing the new timestamp data when the preset condition is met;
  • the calculating module is further configured to calculate by using a preset algorithm according to the new timestamp data. A frequency deviation and a time deviation between the nodes are obtained.
  • the deleting module includes:
  • Obtaining a unit configured to acquire a current time T1 and a time T2 for storing the timestamp data
  • the deleting unit is configured to delete the timestamp data and store the new timestamp data when the difference between the current time T1 minus the time T2 is greater than the preset time.
  • the calculating module includes:
  • a first calculating unit configured to calculate, according to the timestamp data, a phase sum corresponding to the timestamp data
  • the second calculating unit is configured to calculate a frequency deviation between the nodes by a frequency deviation formula according to the phase sum.
  • the calculating module further includes:
  • a third calculating unit configured to calculate a first time offset according to the timestamp data
  • the correcting unit is configured to correct the clock of the detection message according to the first time offset, compare the clock of the corrected detection message with the clock of the non-detection message, to obtain a second time deviation, and the second The time deviation is the time offset between the nodes.
  • a computer readable storage medium storing computer executable instructions for performing the above method.
  • the timestamp data of the detection message is obtained, and according to the timestamp data, the frequency deviation and the time deviation between the nodes are calculated by a preset algorithm. It is realized that when the input reference frequency is too large or the crystal oscillator is aged and the clock source cannot be locked, the frequency deviation and time deviation between the nodes can be effectively detected.
  • FIG. 1 is a schematic flow chart of a first embodiment of a time synchronization deviation detecting method provided herein;
  • FIG. 2 is a schematic flow chart of a second embodiment of a time synchronization deviation detecting method provided herein;
  • FIG. 3 is a schematic flow chart of a third embodiment of a time synchronization deviation detecting method provided herein;
  • FIG. 4 is a schematic diagram of functional modules of a first embodiment of a time synchronization deviation detecting apparatus provided herein;
  • FIG. 5 is a schematic diagram of functional modules of a second embodiment of a time synchronization deviation detecting apparatus provided herein;
  • FIG. 6 is a schematic diagram of functional modules of a third embodiment of the time synchronization deviation detecting apparatus provided herein.
  • Embodiments of the present invention provide a time synchronization deviation detecting method.
  • FIG. 1 is a schematic flowchart of a first embodiment of a time synchronization deviation detecting method provided herein.
  • the time synchronization deviation detecting method includes the following steps S10 to S30:
  • Step S10 receiving a detection instruction of a frequency deviation and a time deviation
  • Step S20 Acquire, according to the detection instruction, timestamp data of the detection message between the nodes in a preset time
  • the device where the slave clock port (slave clock node) is located communicates with the device where the master clock (master clock) node is located through the IEEE (Institute of Electrical and Electronics Engineers) 1588V2 protocol. That is, the slave clock node device communicates with the master clock node device through the IEEE 1588V2 protocol.
  • the IEEE 1588V2 is a master-slave synchronization system. During the synchronization process of the system, the master clock periodically issues a PTP (Precision Time Synchronization Protocol) time synchronization protocol and time information.
  • PTP Precision Time Synchronization Protocol
  • the slave clock node receives the timestamp data sent by the master clock node, and the system calculates the master-slave line time delay and the master-slave time difference, and uses the time difference to adjust the local time, so that the slave clock node device time and the master clock node device time are maintained. Consistent frequency and phase.
  • the slave clock node device sends a detection packet and a 1588V2 packet to the master clock node device through the salve clock node.
  • the detection packet and the 1588V2 message process corresponding timestamp data through different time counters.
  • the different time counters use the same clock, and the detection message is also a 1588V2 message, where the detection message and the 1588V2 message pass through different communication channels at the salve clock node device and the The master clock node device transmits between the devices.
  • the message of the 1588V2 message may be divided into an event message and a common message, where the event message includes a Sync message, a Delay_Req message, a Pdelay_Req message, and a Pdelay_Resp message; the common message includes an announce message, a Follow_Up message, a Delay_Resp message, a Pdelay_Resp_Follow_Up message, and a Management message. , Signaling news.
  • the slave clock node device when the slave clock node device receives the detection instruction of the start frequency deviation and the time deviation sent by the server, the first timer and the second timer are started, and the slave clock node is acquired within a preset time. Timestamp data of the detection message between the master clock node and the master clock node.
  • the detection instruction includes an enable identifier of the detection message, the frequency deviation, a reporting period of the time deviation, and the like.
  • the unit of the preset time is seconds, for example, set to 60 seconds
  • the slave clock node device acquires the first set of timestamp data and the last set of timestamp data in 60 seconds, where the A set of time stamp data is recorded as T1, T2, T3 and T4, and the last set of time stamp data is recorded as T1', T2', T3', T4'.
  • a set of timestamp data includes a time T1 at which the master clock node device sends a Sync message, and a time T2 at which the slave clock node device receives the Sync message, the slave clock node device after receiving the Sync message The time T3 at which the Delay_Req message is sent to the master clock node device, and the time T4 at which the master clock node device receives the Delay_Req message.
  • Step S30 Calculate, according to the timestamp data, a frequency deviation and a time deviation between the nodes by using a preset algorithm.
  • the slave clock node device calculates, according to the timestamp data, a frequency deviation and a time offset of the slave clock node relative to the master clock node by using a preset algorithm.
  • the slave clock node device calculates, according to the timestamp data, a first timer by using a first timer.
  • the phase sum corresponding to the time stamp data is calculated according to the phase sum, and the frequency deviation of the slave clock node relative to the master clock node is calculated by a frequency deviation formula.
  • offset2 [(T1'-T2')+(T3'-T4')]/2
  • the slave clock node device calculates, by using a first timer, a time deviation of the slave clock node from the master clock node: the slave clock node device passes the first timer, according to the The timestamp data is calculated to obtain a first time deviation, the first time deviation is offset1 or offset2, and the slave clock node device corrects the time counter of the detection message according to the calculated offset1 and/or offset2, and the detection is performed.
  • the time counter of the packet is compared with the time counter of the non-detection packet, that is, the clock of the detection packet is corrected, and the clock of the time counter of the detection packet is compared with the clock of the time counter of the 1588V2 packet. Calculating the difference, obtaining the time offset of the slave clock node relative to the master clock node.
  • the timestamp data of the detection packet is obtained, and according to the timestamp data, the frequency deviation and the time deviation between the nodes are calculated by using a preset algorithm. It is realized that when the input reference frequency is too large or the crystal oscillator is aged and the clock source cannot be locked, the frequency deviation and time deviation between the two nodes can be effectively detected. Moreover, in the process of calculating the frequency deviation and the time deviation between the two nodes, it is not necessary to change the physical characteristics of the device where the two nodes are located, and the calculation cost is reduced.
  • FIG. 2 is a schematic flowchart diagram of a second embodiment of a time synchronization deviation detecting method provided herein, and a second embodiment of a time synchronization deviation detecting method is proposed based on the first embodiment.
  • the method before step S10, the method further includes:
  • Step S40 respectively setting the frequency deviation and the maximum threshold value corresponding to the time deviation and Minimum threshold
  • the slave clock node device sets a maximum threshold value and a minimum threshold value of a frequency deviation of a slave clock node relative to a master clock node of the master clock node device, and sets the slave clock node relative to The maximum threshold and the minimum threshold of the time deviation of the master clock node, port information, etc., and store the information.
  • the method further includes:
  • step S50 the alarm information is output when any of the following conditions occurs:
  • the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold
  • the frequency deviation and/or the time deviation is less than a corresponding minimum threshold.
  • the slave clock node device detects, by using a second timer, whether the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold or less than a corresponding minimum gate at a certain time period. Limit.
  • the slave clock node device detects that the frequency deviation of the detection packet is greater than a maximum threshold value set by the slave timer or less than a minimum threshold value set by the slave timer, or detects the detection
  • the alarm information is output to prompt the user of the frequency deviation of the slave clock node relative to the master clock node and/or The time deviation is in an abnormal range.
  • the slave clock node device detects that the frequency deviation of the detection packet is between the minimum threshold value and the maximum threshold value set by the second timer, and the time deviation of the detection packet The alarm information is not output when it is between the minimum threshold and the maximum threshold set.
  • the slave clock node device detects, by the second timer, the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold or less than a corresponding minimum threshold every 15 minutes. .
  • the slave clock node device has calculated the frequency deviation and time deviation of 15 of the slave clock nodes relative to the master clock node by using the first timer, in the 15 frequency deviations and time deviations.
  • the second timer selects the maximum and minimum frequency deviation and time deviation, and selects the frequency deviation and the time deviation calculated by the current time to be compared with the corresponding minimum threshold and maximum threshold set.
  • the alarm information is output when the slave clock node device detects that the selected frequency offset and/or the time offset is not between the corresponding minimum threshold and the maximum threshold set by the second timer.
  • the alarm information corresponding to the frequency deviation and the time deviation may be the same or different, for example, when the frequency deviation is not between the minimum threshold and the maximum threshold, the first alarm sound is output; When the time deviation is not between its minimum threshold and the maximum threshold, the second alarm tone is output.
  • the alarm information includes, but is not limited to, an alarm sound, or a flashing form of an LED or the like.
  • the alarm information is output to prompt the user for the frequency deviation and time between the current two nodes.
  • the detection result of the deviation improves the efficiency of fault location between the two nodes, and improves the decision basis for the switching of the clock synchronization path.
  • FIG. 3 is a schematic flowchart diagram of a third embodiment of a time synchronization deviation detecting method provided herein, and a third embodiment of a time synchronization deviation detecting method is proposed based on the first embodiment.
  • the foregoing method may further include:
  • Step S60 storing the timestamp data
  • the timestamp data is stored after the slave clock node device obtains the timestamp data of the detection message of the slave clock node relative to the master clock node within a preset time.
  • the foregoing method may further include the following steps S70 and S80:
  • Step S70 when the preset condition is met, deleting the timestamp data and storing new timestamp data;
  • Step S80 Calculate, according to the new timestamp data, a frequency deviation and a time deviation between the nodes by using a preset algorithm.
  • the slave clock node device calculates, according to the timestamp data, a frequency deviation and a time deviation of the slave clock node from the master clock node by using a preset algorithm
  • the first timer is used to calculate The time at which the timestamp data is stored.
  • the algorithm that can be adopted is: the slave clock node device acquires the current time T1 and the time T2 storing the time stamp data by using the first timer, and subtracts the time T2 from the current time T1, when the current time When the difference between T1 minus the time T2 is greater than the preset time, the timestamp data is deleted, and new timestamp data is stored.
  • the salve clock node device calculates, by using a preset timer, the slave clock node according to the new timestamp data by using a first algorithm. The frequency deviation and time deviation of the master clock node.
  • the frequency deviation and the time deviation between the two nodes are calculated multiple times according to different time stamp data, and the accuracy of detecting the frequency deviation and the time deviation between the two nodes is improved.
  • a time synchronization deviation detecting device is also provided herein.
  • FIG. 4 is a schematic diagram of functional modules of a first embodiment of a time synchronization deviation detecting apparatus provided herein.
  • the time synchronization deviation detecting device includes the following modules:
  • the receiving module 10 is configured to receive a detection instruction of a frequency deviation and a time deviation
  • the obtaining module 20 is configured to acquire timestamp data of the detection message between the nodes within a preset time according to the detection instruction;
  • the device where the slave clock node is located and the device where the master clock node is located can communicate through the IEEE (Institute of Electrical and Electronics Engineers) 1588V2 protocol. That is, the slave clock node device and the master clock node device can communicate through the IEEE 1588V2 protocol.
  • the IEEE 1588V2 is a master-slave synchronization system. During the synchronization process of the system, the master clock (master clock) periodically issues PTP (Precision Time Synchronization Protocol) time synchronization protocol and time information, and the slave clock port.
  • PTP Precision Time Synchronization Protocol
  • slave clock node receives the timestamp data sent by the master clock port (master clock node), and the system can calculate the master-slave line time delay and the master-slave time difference, and use the time difference to adjust the local time to make the slave device (slave)
  • the clock node device keeps the frequency and phase consistent with the time of the master device (master clock node device).
  • the obtaining module 20 may send the detection packet and the 1588V2 packet to the master clock node device by using the salve clock node.
  • the detection packet and the 1588V2 message process corresponding timestamp data through different time counters.
  • the different time counters use the same clock, and the detection packet is also a 1588V2 packet, the detection packet and the 1588V2
  • the message is transmitted between the salve clock node device and the master clock node device through different communication channels.
  • the message of the 1588V2 message may be divided into an event message and a common message, where the event message includes a Sync message, a Delay_Req message, a Pdelay_Req message, and a Pdelay_Resp message; the common message includes an announce message, a Follow_Up message, a Delay_Resp message, a Pdelay_Resp_Follow_Up message, and a Management message. , Signaling news.
  • the acquiring module 20 starts the first timer and the second timer when the receiving module 10 receives the detection instruction of the start frequency deviation and the time deviation sent by the server, and acquires the slave within a preset time. Timestamp data of the detection message between the clock node and the master clock node.
  • the detection instruction includes an enable identifier of the detection message, the frequency deviation, a reporting period of the time deviation, and the like.
  • the unit of the preset time is seconds.
  • a set of timestamp data includes a time T1 at which the master clock node device sends a Sync message, and the slave clock node device receives a time T2 of the Sync message, and the slave clock node device sends the Sync message after receiving the Sync message.
  • the calculating module 30 is configured to calculate, according to the timestamp data, a frequency deviation and a time deviation between the nodes by using a preset algorithm.
  • the calculating module 30 calculates, according to the timestamp data, a frequency deviation and a time deviation of the slave clock node relative to the master clock node by using a preset algorithm.
  • the slave clock node device calculates a phase sum corresponding to the timestamp data according to the timestamp data by using a first timer, and calculates the slave clock by using a frequency deviation formula according to the phase sum The frequency deviation of the node relative to the master clock node.
  • offset2 [(T1'-T2')+(T3'-T4')]/2
  • the frequency deviation F ((T2'-T1')-Theta-(T2-T1))/Time
  • the calculating module 30 calculates, by using the first timer, a time deviation of the slave clock node from the master clock node: the slave clock node device passes the first timer, according to the time The first time deviation is calculated as offset1 or offset2, and the calculation module 30 corrects the time counter of the detection message according to the calculated offset1 and/or offset2, and the detection message is The time counter is compared with the time counter of the non-detection message, that is, the clock of the detection message is corrected, and the clock of the time counter of the detection message is compared with the clock of the time counter of the 1588V2 message, and the calculation is performed. The difference is obtained, and the time deviation of the slave clock node relative to the master clock node device is obtained.
  • the timestamp data of the detection packet is obtained, and according to the timestamp data, the frequency deviation and the time deviation between the nodes are calculated by using a preset algorithm. It is realized that when the input reference frequency is too large or the crystal oscillator is aged and the clock source cannot be locked, the frequency deviation and time deviation between the two nodes can be effectively detected. In the process of calculating the frequency deviation and time deviation between the two nodes, it is not necessary to change the physical characteristics of the device where the two nodes are located, and the calculation cost is reduced.
  • FIG. 5 is a schematic diagram of functional modules of a second embodiment of a time synchronization deviation detecting apparatus provided herein, and a second embodiment of a time synchronization deviation detecting apparatus is proposed based on the first embodiment.
  • the time synchronization deviation detecting device further includes the following modules:
  • the setting module 40 is configured to set the frequency deviation and the maximum threshold and the minimum threshold corresponding to the time deviation;
  • the setting module 40 sets a maximum threshold value and a minimum threshold value of a frequency deviation of a slave clock node thereof with respect to a master clock node in the master clock node device, and sets the slave clock node relative to the master clock.
  • the output module 50 is configured to output an alarm message when any of the following conditions occurs:
  • the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold
  • the frequency deviation and/or the time deviation is less than a corresponding minimum threshold.
  • the slave clock node device detects, by using a second timer, whether the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold or less than a corresponding minimum gate at a certain time period. Limit.
  • the slave clock node device detects that the frequency deviation of the detection packet is greater than a maximum threshold value set by the slave timer or less than a minimum threshold value set by the slave timer, or detects the detection
  • the output module 50 outputs the alarm information to prompt the user to the frequency of the slave clock node relative to the master clock node.
  • the deviation and/or time deviation is within an abnormal range.
  • the output module 50 does not output an alarm message when it is between the minimum threshold and the maximum threshold that it sets.
  • the slave clock node device detects, by the second timer, the frequency deviation and/or the time deviation is greater than a corresponding maximum threshold or less than a corresponding minimum threshold every 15 minutes. .
  • the slave clock node device has calculated the frequency deviation and time deviation of 15 of the slave clock nodes relative to the master clock node by using the first timer, in the 15 frequency deviations and time deviations.
  • the second timer selects the maximum and minimum frequency deviation and time deviation, and simultaneously selects the frequency deviation and the time deviation calculated by the current time to be compared with the corresponding minimum threshold and maximum threshold respectively set.
  • the output module 50 outputs when the slave clock node device detects that the selected frequency offset and/or the time offset is not between the corresponding minimum threshold and the maximum threshold set by the second timer.
  • Alarm information corresponding to the frequency deviation and the time deviation may be the same or different, such as when the frequency deviation is not between its minimum threshold and the maximum threshold, the output module 50 outputs The first type of alarm sounds; when the time deviation is not between the minimum threshold and the maximum threshold, the output module 50 outputs a second alarm sound.
  • the alarm information includes, but is not limited to, an alarm sound, or a flashing form of an LED or the like.
  • the alarm information is output to prompt the user for the frequency deviation and time between the current two nodes.
  • the detection result of the deviation improves the efficiency of fault location between the two nodes,
  • the switching of the clock synchronization path improves the decision basis.
  • FIG. 6 is a schematic diagram of functional modules of a third embodiment of a time synchronization deviation detecting apparatus provided herein, and a third embodiment of a time synchronization deviation detecting apparatus is proposed based on the first embodiment.
  • the time synchronization deviation detecting device further includes the following modules:
  • the storage module 60 is configured to store the timestamp data
  • the timestamp data is stored after the slave clock node device obtains the timestamp data of the detection message of the slave clock node relative to the master clock node within a preset time.
  • the deleting module 70 is configured to delete the timestamp data and store new timestamp data when the preset condition is met;
  • the calculating module 30 is further configured to calculate, according to the new timestamp data, a frequency deviation and a time offset between the nodes by using a preset algorithm.
  • the calculation module 30 calculates the storage by using the first timer.
  • the time of the timestamp data is: the slave clock node device acquires the current time T1 and the time T2 storing the time stamp data by using the first timer, and subtracts the time T2 from the current time T1, when the current time When the difference between T1 minus the time T2 is greater than the preset time, the deleting module 70 deletes the timestamp data and stores new timestamp data.
  • the deleting module 70 deletes the timestamp data and stores the new timestamp data.
  • the calculating module 30 calculates, by using a first timer, the slave clock node by using a preset algorithm, according to the new timestamp data. Frequency deviation and time deviation of the master clock node.
  • the frequency deviation and the time deviation between the two nodes are calculated multiple times according to different time stamp data, and the accuracy of detecting the frequency deviation and the time deviation between the two nodes is improved.
  • the embodiment of the invention further provides a computer readable storage medium storing computer executable instructions for performing the above method.
  • the embodiment of the invention can effectively detect the frequency deviation and the time deviation between the nodes when the input reference frequency is too large or the crystal oscillator is aged and the clock source cannot be locked.

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Abstract

一种时间同步偏差检测方法和装置，所述包括：接收频率偏差和时间偏差的检测指令；根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据；根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。

Description

一种时间同步偏差检测方法和装置 技术领域
本文涉及但不限于网络管理领域，尤其涉及一种时间同步偏差检测方法和装置。
背景技术
近年来，随着移动通信技术的不断发展演进，基于1588V2的时间同步网络已经广泛应用于全球移动运营商。1588V2是一种基于数据包传送的同步技术标准，它采用时间戳机制和主从时钟(master-slave)方案，对时间进行编码传送，同时利用网络链路的对称性和时延测量技术，实现主从时钟的频率和时间的同步。
对分组网络全网时间同步情况以及各节点内部时钟时间性能进行实时检测，已成为运营商的迫切需求。slave时钟节点相对于master时钟节点的频率偏差性能和时间偏差性能是对分组网络全网时间同步情况最重要的检测指标之一。目前对1588V2频率恢复或频率偏差估算方法多采用最小二乘法估计模型，经过最小二乘回归拟合后得到频率或频偏。该方法比较常见，但实现起来比较复杂。而且在输入的参考频率偏大或者晶振老化，无法锁定时钟源的情况下，最小二乘法估计模型会检测失效。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本文提供一种时间同步偏差检测方法及装置，可以解决在输入的参考频率偏大或者晶振老化，无法锁定时钟源的情况下，对节点之间的频率偏差和时间偏差检测失败的技术问题。
本文提供的一种时间同步偏差检测方法，包括：
接收频率偏差和时间偏差的检测指令；
根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据；
根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
可选地，所述方法中，所述接收频率偏差和时间偏差的检测指令前，还包括：
设置所述频率偏差和所述时间偏差对应的最大门限值和最小门限值；
所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差后，还包括：
发生以下任一种情况时输出告警信息：
所述频率偏差和/或所述时间偏差大于对应的最大门限值；
所述频率偏差和/或所述时间偏差小于对应的最小门限值。
可选地，所述方法中，所述根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据后，还包括：
存储所述时间戳数据；
所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差后，还包括：
当满足预设条件时，删除所述时间戳数据，存储新的时间戳数据；
根据所述新的时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
可选地，上述方法中，所述删除所述时间戳数据，存储新的时间戳数据包括：
获取当前时间T1和存储所述时间戳数据的时间T2；
当所述当前时间T1减去所述时间T2的差大于所述预设时间时，删除所述时间戳数据，存储新的时间戳数据。
可选地，上述方法中，所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差包括：
根据所述时间戳数据计算得到与所述时间戳数据对应的相位和；
根据所述相位和，通过频率偏差公式计算得到所述节点之间的频率偏差。
可选地，上述方法中，所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的时间偏差包括：
根据所述时间戳数据计算得到第一时间偏差；
根据所述第一时间偏差校正所述检测报文的时钟，将所校正的检测报文的时钟与非检测报文的时钟进行对比，得到第二时间偏差，所述第二时间偏差为所述节点之间的时间偏差。
此外，本文还提供一种时间同步偏差检测装置，包括：
接收模块，设置为接收频率偏差和时间偏差的检测指令；
获取模块，设置为根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据；
计算模块，设置为根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
可选地，所述时间同步偏差检测装置还包括：
设置模块，设置为设置所述频率偏差和所述时间偏差对应的最大门限值和最小门限值；
输出模块，设置为发生以下任一种情况时输出告警信息：
所述频率偏差和/或所述时间偏差大于对应的最大门限值；
所述频率偏差和/或所述时间偏差小于对应的最小门限值。
可选地，所述时间同步偏差检测装置还包括：
存储模块，设置为存储所述时间戳数据；
删除模块，设置为当满足预设条件时，删除所述时间戳数据，存储新的时间戳数据；
所述计算模块，还设置为根据所述新的时间戳数据，通过预设算法计算 得到所述节点之间的频率偏差和时间偏差。
可选地，上述装置中，所述删除模块包括：
获取单元，设置为获取当前时间T1和存储所述时间戳数据的时间T2；
删除单元，设置为当所述当前时间T1减去所述时间T2的差大于所述预设时间时，删除所述时间戳数据，存储新的时间戳数据。
可选地，上述装置中，所述计算模块包括：
第一计算单元，设置为根据所述时间戳数据计算得到与所述时间戳数据对应的相位和；
第二计算单元，设置为根据所述相位和，通过频率偏差公式计算得到所述节点之间的频率偏差。
可选地，上述装置中，所述计算模块还包括：
第三计算单元，设置为根据所述时间戳数据计算得到第一时间偏差；
校正单元，设置为根据所述第一时间偏差校正所述检测报文的时钟，将所校正的检测报文的时钟与非检测报文的时钟进行对比，得到第二时间偏差，所述第二时间偏差为所述节点之间的时间偏差。
一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行上述方法。
本文通过当接收到频率偏差和时间偏差的检测指令时，获取检测报文的时间戳数据，根据所述时间戳数据，通过预设算法计算得到节点之间的频率偏差和时间偏差。实现了在输入的参考频率偏大或者晶振老化，无法锁定时钟源的情况下，能够有效地检测节点之间的频率偏差和时间偏差。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1为本文提供的时间同步偏差检测方法第一实施例的流程示意图；
图2为本文提供的时间同步偏差检测方法第二实施例的流程示意图；
图3为本文提供的时间同步偏差检测方法第三实施例的流程示意图；
图4为本文提供的时间同步偏差检测装置第一实施例的功能模块示意图；
图5为本文提供的时间同步偏差检测装置第二实施例的功能模块示意图；
图6为本文提供的时间同步偏差检测装置第三实施例的功能模块示意图。
本发明的实施方式
下文中将结合附图对本文的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本发明实施例提供一种时间同步偏差检测方法。
参照图1，图1为本文提供的时间同步偏差检测方法第一实施例的流程示意图。
在本实施例中，所述时间同步偏差检测方法包括如下步骤S10至S30：
步骤S10，接收频率偏差和时间偏差的检测指令；
步骤S20，根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据；
其中，从时钟端口(slave时钟节点)所在的设备与主时钟(master时钟)节点所在的设备通过IEEE(Institute of Electrical and Electronics Engineers，电气和电子工程师协会)1588V2协议进行通信。即slave时钟节点设备与master时钟节点设备通过IEEE 1588V2协议进行通信。所述IEEE 1588V2作为一种主从同步系统，在系统的同步过程中，master时钟周期性发布PTP(Precision Time Synchronization Protocol，精密时间同步协议)时间同步协议及时间信息， slave时钟节点接收master时钟节点发来的时间戳数据，系统据此计算出主从线路时间延迟及主从时间差，并利用该时间差调整本地时间，使slave时钟节点设备时间保持与master时钟节点设备时间一致的频率与相位。
所述slave时钟节点设备通过所述salve时钟节点发送检测报文和1588V2报文给所述master时钟节点设备。所述检测报文和所述1588V2报文通过不同的时间计数器处理对应的时间戳数据。可选地，所述不同的时间计数器使用相同的时钟，所述检测报文也是1588V2报文，所述检测报文和所述1588V2报文通过不同的通信信道在所述salve时钟节点设备和所述master时钟节点设备之间进行传输。所述1588V2报文的消息可分为事件消息和普通消息，所述事件消息包括Sync消息、Delay_Req消息、Pdelay_Req消息、Pdelay_Resp消息；普通消息包括announce消息、Follow_Up消息、Delay_Resp消息、Pdelay_Resp_Follow_Up消息、Management消息、Signaling消息。
可选地，当所述slave时钟节点设备接收到服务器发送的启动频率偏差和时间偏差的检测指令时，启动第一定时器和第二定时器，并在预设时间内获取所述slave时钟节点和所述master时钟节点之间的检测报文的时间戳数据。所述检测指令包括检测报文的使能标识，所述频率偏差和所述时间偏差的上报周期等。可选地，所述预设时间的单位为秒，例如，设置为60秒，所述slave时钟节点设备在60秒内获取第一组时间戳数据和最后一组时间戳数据，将所述第一组时间戳数据记为T1，T2，T3和T4，将所述最后一组时间戳数据记为T1'，T2'，T3'，T4'。例如，一组时间戳数据包括所述master时钟节点设备发送Sync消息的时间T1，所述slave时钟节点设备接收所述Sync消息的时间T2，所述slave时钟节点设备在接收到所述Sync消息后，发送Delay_Req消息给所述master时钟节点设备的时间T3，所述master时钟节点设备接收Delay_Req消息的时间T4。
步骤S30，根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
所述slave时钟节点设备根据所述时间戳数据，通过预设算法计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差。可选地，所述slave时钟节点设备通过第一定时器根据所述时间戳数据计算得到与所 述时间戳数据对应的相位和，根据所述相位和，通过频率偏差公式计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差。可选地，所述slave时钟节点设备计算所述slave时钟节点相对于所述master时钟节点的频率偏差的过程为：所述slave时钟节点设备根据第一组时间戳数据得到offset1＝[(T1-T2)+(T3-T4)]/2，根据第二组时间戳数据得到offset2＝[(T1'-T2')+(T3'-T4')]/2，将所述offset1和所述offset2相加得到相位和Theta，即所述相位和Theta＝offset1+offset2，得到所述相位和Theta之后，根据频率偏差的计算公式F＝((T2'-T1')-Theta-(T2-T1))/Time；Time＝(T1'-T1)计算得到所述slave时钟节点相对于所述master时钟节点设备的频率偏差。
可选地，所述slave时钟节点设备通过第一定时器计算所述slave时钟节点相对于所述master时钟节点的时间偏差的过程为：所述slave时钟节点设备通过第一定时器，根据所述时间戳数据计算得到第一时间偏差，所述第一时间偏差为offset1或者offset2，所述slave时钟节点设备根据计算得到的offset1和/或offset2校正所述检测报文的时间计数器，将所述检测报文的时间计数器与非检测报文的时间计数器进行对比，即校正所述检测报文的时钟，将所述检测报文的时间计数器的时钟与所述1588V2报文的时间计数器的时钟进行对比，计算出差值，得到所述slave时钟节点相对于所述master时钟节点的时间偏差。
本实施例通过当接收到频率偏差和时间偏差的检测指令时，获取检测报文的时间戳数据，根据所述时间戳数据，通过预设算法计算得到节点之间的频率偏差和时间偏差。实现了在输入的参考频率偏大或者晶振老化，无法锁定时钟源的情况下，能够有效地检测两节点之间的频率偏差和时间偏差。而且，在计算两节点之间的频率偏差和时间偏差的过程中，无需改变两节点所在设备的物理特性，降低了计算成本。
参照图2，图2为本文提供的时间同步偏差检测方法第二实施例的流程示意图，基于第一实施例提出时间同步偏差检测方法第二实施例。
在本实施例中，步骤S10之前，还包括：
步骤S40，分别设置所述频率偏差和所述时间偏差对应的最大门限值和 最小门限值；
可选地，所述slave时钟节点设备设置其slave时钟节点相对于所述master时钟节点设备中master时钟节点的频率偏差的最大门限值和最小门限值，同时设置所述slave时钟节点相对于所述master时钟节点的时间偏差的最大门限值和最小门限值，以及端口信息等，并存储这些信息。
另外，所述步骤S30之后，还包括：
步骤S50，发生以下任一种情况时输出告警信息：
所述频率偏差和/或所述时间偏差大于对应的最大门限值；
所述频率偏差和/或所述时间偏差小于对应的最小门限值。
可选地，所述slave时钟节点设备通过第二定时器在每隔一定的时间段，侦测所述频率偏差和/或所述时间偏差是否大于对应的最大门限值或小于对应的最小门限值。当所述slave时钟节点设备通过所述第二定时器侦测到所述检测报文的频率偏差大于其设置的最大门限值或小于其设置的最小门限值，或者侦测到所述检测报文的时间偏差大于其设置的最大门限值或小于其设置的最小门限值时，均输出告警信息，以提示用户所述slave时钟节点相对于所述master时钟节点的频率偏差和/或时间偏差处于不正常的范围内。当所述slave时钟节点设备通过所述第二定时器侦测到所述检测报文的频率偏差在其设置的最小门限值和最大门限值之间，且所述检测报文的时间偏差也在其设置的最小门限值和最大门限值之间时，不输出告警信息。
可选地，所述slave时钟节点设备通过所述第二定时器每隔15分钟侦测所述频率偏差和/或所述时间偏差是否大于对应的最大门限值或小于对应的最小门限值。在这15分钟内，所述slave时钟节点设备已经通过第一定时器计算得到15个所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差，在这15个频率偏差和时间偏差中，所述第二定时器选择最大和最小的频率偏差和时间偏差，同时选择当前时间所计算得到的频率偏差和时间偏差与其设置的对应的最小门限值和最大门限值进行对比。当所述slave时钟节点设备通过所述第二定时器侦测到所选择的频率偏差和/或时间偏差不在其设置的对应的最小门限值和最大门限值之间时，输出告警信息。可选地， 所述频率偏差和所述时间偏差对应的告警信息可以相同也可以不同，如当所述频率偏差不在其最小门限值和最大门限值之间时，输出第一种告警提示音；当所述时间偏差不在其最小门限值和最大门限值之间时，输出第二种告警提示音。所述告警信息包括但不限于以告警提示音，或者LED等闪烁的形式输出。
本实施例通过当所述频率偏差和/或所述时间偏差大于对应的最大门限值或小于对应的最小门限值时，输出告警信息，以提示用户当前两节点之间的频率偏差和时间偏差的检测结果，提高了两节点之间故障定位的效率，为时钟同步路径的切换提高决策依据。
参照图3，图3为本文提供的时间同步偏差检测方法第三实施例的流程示意图，基于第一实施例提出时间同步偏差检测方法第三实施例。
在本实施例中，步骤S20之后，上述方法还可以包括：
步骤S60，存储所述时间戳数据；
当所述slave时钟节点设备在预设时间内获取得到所述slave时钟节点相对于所述master时钟节点的检测报文的时间戳数据后，存储所述时间戳数据。
另外，所述步骤S30之后，上述方法还可以包括如下步骤S70和S80：
步骤S70，当满足预设条件时，删除所述时间戳数据，存储新的时间戳数据；
步骤S80，根据所述新的时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
可选地，当所述slave时钟节点设备根据所述时间戳数据，通过预设算法计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差后，通过第一定时器计算存储所述时间戳数据的时间。可以采用的算法为：所述slave时钟节点设备通过第一定时器获取当前时间T1和存储所述时间戳数据的时间T2，用所述当前时间T1减去所述时间T2，当所述当前时间T1减去所述时间T2的差大于所述预设时间时，删除所述时间戳数据，存储新的时间戳数据。如当所述当前时间T1减去所述时间T2的差大于60秒时，则删 除所述时间戳数据，存储新的时间戳数据。当所述salve时钟节点设备存储新的时间戳数据之后，所述salve时钟节点设备通过第一定时器，根据所述新的时间戳数据，通过预设算法计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差。
本实施例通过根据不同的时间戳数据多次计算两节点之间的频率偏差和时间偏差，提高所述两节点之间的频率偏差和时间偏差的检测的精确度。
本文还提供一种时间同步偏差检测装置。
参照图4，图4为本文提供的时间同步偏差检测装置第一实施例的功能模块示意图。
在本实施例中，所述时间同步偏差检测装置包括如下模块：
接收模块10，设置为接收频率偏差和时间偏差的检测指令；
获取模块20，设置为根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据；
slave时钟节点所在的设备与master时钟节点所在的设备可以通过IEEE(Institute of Electrical and Electronics Engineers，电气和电子工程师协会)1588V2协议进行通信。即slave时钟节点设备与master时钟节点设备可以通过IEEE 1588V2协议进行通信。所述IEEE 1588V2作为一种主从同步系统，在系统的同步过程中，主时钟(master时钟)周期性发布PTP(Precision Time Synchronization Protocol，精密时间同步协议)时间同步协议及时间信息，从时钟端口(slave时钟节点)接收主时钟端口(master时钟节点)发来的时间戳数据，系统可以据此计算出主从线路时间延迟及主从时间差，并利用该时间差调整本地时间，使从设备(slave时钟节点设备)时间保持与主设备(master时钟节点设备)时间一致的频率与相位。
所述获取模块20可以通过所述salve时钟节点发送检测报文和1588V2报文给所述master时钟节点设备。所述检测报文和所述1588V2报文通过不同的时间计数器处理对应的时间戳数据。可选地，所述不同的时间计数器使用相同的时钟，所述检测报文也是1588V2报文，所述检测报文和所述1588V2 报文通过不同的通信信道在所述salve时钟节点设备和所述master时钟节点设备之间进行传输。所述1588V2报文的消息可分为事件消息和普通消息，所述事件消息包括Sync消息、Delay_Req消息、Pdelay_Req消息、Pdelay_Resp消息；普通消息包括announce消息、Follow_Up消息、Delay_Resp消息、Pdelay_Resp_Follow_Up消息、Management消息、Signaling消息。
可选地，获取模块20在所述接收模块10接收到服务器发送的启动频率偏差和时间偏差的检测指令时，启动第一定时器和第二定时器，并在预设时间内获取所述slave时钟节点和所述master时钟节点之间的检测报文的时间戳数据。所述检测指令包括检测报文的使能标识，所述频率偏差和所述时间偏差的上报周期等。可选地，所述预设时间的单位为秒，如设置为60秒，所述slave时钟节点设备在60秒内获取第一组时间戳数据和最后一组时间戳数据，将所述第一组时间戳数据记为T1，T2，T3和T4，将所述最后一组时间戳数据记为T1'，T2'，T3'，T4'。如一组时间戳数据包括所述master时钟节点设备发送Sync消息的时间T1，所述slave时钟节点设备接收所述Sync消息的时间T2，所述slave时钟节点设备在接收到所述Sync消息之后，发送Delay_Req消息给所述master时钟节点设备的时间T3，所述master时钟节点设备接收Delay_Req消息的时间T4。
计算模块30，设置为根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
所述计算模块30根据所述时间戳数据，通过预设算法计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差。可选地，所述slave时钟节点设备通过第一定时器根据所述时间戳数据计算得到与所述时间戳数据对应的相位和，根据所述相位和，通过频率偏差公式计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差。可选地，所述slave时钟节点设备计算所述slave时钟节点相对于所述master时钟节的频率偏差的过程为：所述slave时钟节点设备根据第一组时间戳数据得到offset1＝[(T1-T2)+(T3-T4)]/2，根据第二组时间戳数据得到offset2＝[(T1'-T2')+(T3'-T4')]/2，将所述offset1和所述offset2相加得到相位和Theta，即所述相位和Theta＝offset1+offset2，得到所述相位和Theta之后，根 据频率偏差的计算公式F＝((T2'-T1')-Theta-(T2-T1))/Time；Time＝(T1'-T1)计算得到所述slave时钟节点相对于所述master时钟节点设备的频率偏差。
可选地，所述计算模块30通过第一定时器计算所述slave时钟节点相对于所述master时钟节点的时间偏差的过程为：所述slave时钟节点设备通过第一定时器，根据所述时间戳数据计算得到第一时间偏差，所述第一时间偏差为offset1或者offset2，所述计算模块30根据计算得到的offset1和/或offset2校正所述检测报文的时间计数器，将所述检测报文的时间计数器与非检测报文的时间计数器进行对比，即校正所述检测报文的时钟，将所述检测报文的时间计数器的时钟与所述1588V2报文的时间计数器的时钟进行对比，计算出差值，得到所述slave时钟节点相对于所述master时钟节点设备的时间偏差。
本实施例通过当接收到频率偏差和时间偏差的检测指令时，获取检测报文的时间戳数据，根据所述时间戳数据，通过预设算法计算得到节点之间的频率偏差和时间偏差。实现了在输入的参考频率偏大或者晶振老化，无法锁定时钟源的情况下，能够有效地检测两节点之间的频率偏差和时间偏差。在计算两节点之间的频率偏差和时间偏差的过程中，无需改变两节点所在设备的物理特性，降低了计算成本。
参照图5，图5为本文提供的时间同步偏差检测装置第二实施例的功能模块示意图，基于第一实施例提出时间同步偏差检测装置第二实施例。
在本实施例中，所述时间同步偏差检测装置还包括如下模块：
设置模块40，设置为设置所述频率偏差和所述时间偏差对应的最大门限值和最小门限值；
可选地，设置模块40设置其slave时钟节点相对于所述master时钟节点设备中master时钟节点的频率偏差的最大门限值和最小门限值，设置所述slave时钟节点相对于所述master时钟节点的时间偏差的最大门限值和最小门限值，以及端口信息等，并存储这些信息。
输出模块50，设置为发生以下任一种情况时输出告警信息：
所述频率偏差和/或所述时间偏差大于对应的最大门限值；
所述频率偏差和/或所述时间偏差小于对应的最小门限值。
可选地，所述slave时钟节点设备通过第二定时器在每隔一定的时间段，侦测所述频率偏差和/或所述时间偏差是否大于对应的最大门限值或小于对应的最小门限值。当所述slave时钟节点设备通过所述第二定时器侦测到所述检测报文的频率偏差大于其设置的最大门限值或小于其设置的最小门限值，或者侦测到所述检测报文的时间偏差大于其设置的最大门限值或小于其设置的最小门限值时，所述输出模块50输出告警信息，以提示用户所述slave时钟节点相对于所述master时钟节点的频率偏差和/或时间偏差处于不正常的范围内。当所述slave时钟节点设备通过所述第二定时器侦测到所述检测报文的频率偏差在其设置的最小门限值和最大门限值之间，并且所述检测报文的时间偏差也在其设置的最小门限值和最大门限值之间时，所述输出模块50不输出告警信息。
可选地，所述slave时钟节点设备通过所述第二定时器每隔15分钟侦测所述频率偏差和/或所述时间偏差是否大于对应的最大门限值或小于对应的最小门限值。在这15分钟内，所述slave时钟节点设备已经通过第一定时器计算得到15个所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差，在这15个频率偏差和时间偏差中，第二定时器选择最大和最小的频率偏差和时间偏差，同时选择当前时间所计算得到的频率偏差和时间偏差分别与其设置的对应的最小门限值和最大门限值进行对比。当所述slave时钟节点设备通过第二定时器侦测到所选择的频率偏差和/或时间偏差不在其设置的对应的最小门限值和最大门限值之间时，所述输出模块50输出告警信息。可选地，所述频率偏差和所述时间偏差对应的告警信息可以相同也可以不同，如当所述频率偏差不在其最小门限值和最大门限值之间时，所述输出模块50输出第一种告警提示音；当所述时间偏差不在其最小门限值和最大门限值之间时，所述输出模块50输出第二种告警提示音。所述告警信息包括但不限于以告警提示音，或者LED等闪烁的形式输出。
本实施例通过当所述频率偏差和/或所述时间偏差大于对应的最大门限值或小于对应的最小门限值时，输出告警信息，以提示用户当前两节点之间的频率偏差和时间偏差的检测结果，提高了两节点之间故障定位的效率，为 时钟同步路径的切换提高决策依据。
参照图6，图6为本文提供的时间同步偏差检测装置第三实施例的功能模块示意图，基于第一实施例提出时间同步偏差检测装置第三实施例。
在本实施例中，所述时间同步偏差检测装置还包括如下模块：
存储模块60，设置为存储所述时间戳数据；
可选地，当所述slave时钟节点设备在预设时间内获取得到所述slave时钟节点相对于所述master时钟节点的检测报文的时间戳数据之后，存储所述时间戳数据。
删除模块70，设置为满足预设条件时，删除所述时间戳数据，存储新的时间戳数据；
所述计算模块30，还设置为根据所述新的时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
可选地，当所述计算模块30根据所述时间戳数据，通过预设算法计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差之后，通过第一定时器计算存储所述时间戳数据的时间。可以采用的算法为：所述slave时钟节点设备通过第一定时器获取当前时间T1和存储所述时间戳数据的时间T2，用所述当前时间T1减去所述时间T2，当所述当前时间T1减去所述时间T2的差大于所述预设时间时，所述删除模块70删除所述时间戳数据，存储新的时间戳数据。如当所述当前时间T1减去所述时间T2的差大于60秒时，即满足预设条件，则所述删除模块70删除所述时间戳数据，存储新的时间戳数据。当所述salve时钟节点设备存储新的时间戳数据之后，所述计算模块30通过第一定时器，根据所述新的时间戳数据，通过预设算法计算得到所述slave时钟节点相对于所述master时钟节点的频率偏差和时间偏差。
本实施例通过根据不同的时间戳数据多次计算两节点之间的频率偏差和时间偏差，提高所述两节点之间的频率偏差和时间偏差的检测的精确度。
本发明实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行上述方法。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的每个模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序指令来实现其相应功能。本申请不限制于任何特定形式的硬件和软件的结合。
工业实用性
本发明实施例实现了在输入的参考频率偏大或者晶振老化，无法锁定时钟源的情况下，能够有效地检测节点之间的频率偏差和时间偏差。

Claims (12)

  1. 一种时间同步偏差检测方法，包括：
    接收频率偏差和时间偏差的检测指令；
    根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据；
    根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
  2. 如权利要求1所述的时间同步偏差检测方法，其中，所述接收频率偏差和时间偏差的检测指令前，所述方法还包括：
    分别设置所述频率偏差和所述时间偏差对应的最大门限值和最小门限值；
    所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差后，还包括：
    发生以下任一种情况时输出告警信息：
    所述频率偏差和/或所述时间偏差大于对应的最大门限值；
    所述频率偏差和/或所述时间偏差小于对应的最小门限值。
  3. 如权利要求1所述的时间同步偏差检测方法，其中，所述根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据后，还包括：
    存储所述时间戳数据；
    所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差后，还包括：
    当满足预设条件时，删除所述时间戳数据，存储新的时间戳数据；
    根据所述新的时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
  4. 如权利要求3所述的时间同步偏差检测方法，其中，所述当满足预设 条件时，删除所述时间戳数据，存储新的时间戳数据包括：
    获取当前时间T1和存储所述时间戳数据的时间T2；
    当所述当前时间T1减去所述时间T2的差大于所述预设时间时，删除所述时间戳数据，存储新的时间戳数据。
  5. 如权利要求1至4任一项所述的时间同步偏差检测方法，其中，所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差包括：
    根据所述时间戳数据计算得到与所述时间戳数据对应的相位和；
    根据所述相位和，通过频率偏差公式计算得到所述节点之间的频率偏差。
  6. 如权利要求1至4任一项所述的时间同步偏差检测方法，其中，所述根据所述时间戳数据，通过预设算法计算得到所述节点之间的时间偏差包括：
    根据所述时间戳数据计算得到第一时间偏差；
    根据所述第一时间偏差校正所述检测报文的时钟，将所校正的检测报文的时钟与非检测报文的时钟进行对比，得到第二时间偏差，所述第二时间偏差为所述节点之间的时间偏差。
  7. 一种时间同步偏差检测装置，包括：
    接收模块，设置为接收频率偏差和时间偏差的检测指令；
    获取模块，设置为根据所述检测指令，在预设时间内获取节点之间的检测报文的时间戳数据；
    计算模块，设置为根据所述时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
  8. 如权利要求7所述的时间同步偏差检测装置，还包括：
    设置模块，设置为设置所述频率偏差和所述时间偏差分别对应的最大门限值和最小门限值；
    输出模块，设置为发生以下任一种情况时输出告警信息：
    所述频率偏差和/或所述时间偏差大于对应的最大门限值；
    所述频率偏差和/或所述时间偏差小于对应的最小门限值。
  9. 如权利要求7所述的时间同步偏差检测装置，还包括：
    存储模块，设置为存储所述时间戳数据；
    删除模块，设置为当满足预设条件时，删除所述时间戳数据，存储新的时间戳数据；
    所述计算模块，还设置为根据所述新的时间戳数据，通过预设算法计算得到所述节点之间的频率偏差和时间偏差。
  10. 如权利要求9所述的时间同步偏差检测装置，其中，所述删除模块包括：
    获取单元，设置为获取当前时间T1和存储所述时间戳数据的时间T2；
    删除单元，设置为当所述当前时间T1减去所述时间T2的差大于所述预设时间时，删除所述时间戳数据，存储新的时间戳数据。
  11. 如权利要求7至10任一项所述的时间同步偏差检测装置，其中，所述计算模块包括：
    第一计算单元，设置为根据所述时间戳数据计算得到与所述时间戳数据对应的相位和；
    第二计算单元，设置为根据所述相位和，通过频率偏差公式计算得到所述节点之间的频率偏差。
  12. 如权利要求11所述的时间同步偏差检测装置，其中，所述计算模块还包括：
    第三计算单元，设置为根据所述时间戳数据计算得到第一时间偏差；
    校正单元，设置为根据所述第一时间偏差校正所述检测报文的时钟，将所校正的检测报文的时钟与非检测报文的时钟进行对比，得到第二时间偏差，所述第二时间偏差为所述节点之间的时间偏差。
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CN113259038A (zh) * 2021-04-29 2021-08-13 北京邮电大学 时间同步方法、节点、装置及存储介质
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