WO2017057242A1

WO2017057242A1 - Non-volatile semiconductor memory device

Info

Publication number: WO2017057242A1
Application number: PCT/JP2016/078202
Authority: WO
Inventors: 福夫大和田; 泰彦川嶋; 信司吉田; 谷口　泰弘; 櫻井　良多郎; 裕品川; 秀男葛西; 奥山　幸祐
Original assignee: 株式会社フローディア
Priority date: 2015-10-01
Filing date: 2016-09-26
Publication date: 2017-04-06
Also published as: IL257488A; TWI597827B; CN108076670A; CN108076670B; IL257488B; KR102437353B1; JP2017069478A; KR20180064329A; SG11201801237PA; TW201717322A; JP5951096B1

Abstract

Provided is a non-volatile semiconductor memory device that, compared to conventional devices, can alleviate read errors which occur due to a voltage fluctuation at the time of a data read operation, and can also reduce an increase in power consumption due to a voltage fluctuation. In a case of a manufacturing defect in which, conventionally, a voltage fluctuation occurs throughout an entire non-volatile semiconductor memory device as a result of a connection of a drain-side selection gate electrode and a source-side selection gate electrode, which are of different types and to which different voltage values are highly likely to be applied; compared to the foregoing, a non-volatile semiconductor memory device (1) can alleviate read errors which occur due to a voltage fluctuation at the time of a data read operation, and can also reduce an increase in power consumption due to an unintended voltage fluctuation.

Description

Nonvolatile semiconductor memory device

The present invention relates to a nonvolatile semiconductor memory device.

Conventionally, Japanese Unexamined Patent Application Publication No. 2011-129816 (Patent Document 1) discloses a memory cell in which a memory gate structure is disposed between two select gate structures (see Patent Document 1 and FIG. 15). . In practice, this memory cell includes a drain region to which a bit line is connected and a source region to which a source line is connected, and a selection gate structure, a memory is provided on a well between the drain region and the source region. A gate structure and another selection gate structure are arranged and formed in order. In a memory cell having such a structure, a charge storage layer is provided in the memory gate structure, and data is written by injecting charges into the charge storage layer, or charges in the charge storage layer are extracted. Thus, data can be erased.

Here, FIG. 9 is a schematic diagram showing an example of a circuit configuration of a conventional nonvolatile semiconductor memory device 100. FIG. In this case, the nonvolatile semiconductor memory device 100 includes, for example, a plurality of

memory cells

102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h arranged in a matrix, and

memory cells

102a and 102b arranged in the row direction. Memory

cell formation portions

101a, 101b, 101c, and 101d are configured for each of 102c, 102d, 102e, 102f, 102g, and 102h.

Also, the nonvolatile semiconductor memory device 100 includes

memory cells

102a, 102c, 102e, 102g (102b, 102d, 102f, 102h) shares one bit line BL1 (BL2), and a predetermined bit voltage can be applied uniformly to each bit line BL1, BL2. Further, the nonvolatile semiconductor memory device 100 shares, for example, the memory gate lines MGL1, MGL2, MGL3, MGL4 and the drain side select gate lines DGL1, DGL2, DGL3, DGL4 for each of the memory

cell forming portions

101a, 101b, 101c, 101d. A predetermined voltage can be applied to each of the memory gate lines MGL1, MGL2, MGL3, MGL4 and each of the drain side select gate lines DGL1, DGL2, DGL3, DGL4.

In this nonvolatile semiconductor memory device 100, one source-side selection gate line SGL and one source line SL are connected to all the

memory cells

102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h. A predetermined source gate voltage can be applied to the source side selection gate line SGL, and a predetermined source voltage can be applied to the source line SL.

Each

memory cell

102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h has the same configuration. For example, the memory cell 102a includes a memory gate electrode MG connected to the memory gate line MGL1, and a drain side. The drain side selection gate electrode DG to which the selection gate line DGL1 is connected, and the source side selection gate electrode SG to which the source side selection gate line SGL is connected. Then, each

memory cell

102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h can be injected with charge into the charge storage layer EC by the quantum tunnel effect caused by the voltage difference between the memory gate electrode MG and the channel layer. The data can be written.

Here, in such a conventional nonvolatile semiconductor memory device 100, for example, in a data read operation for reading data written in the memory cell 102a in the first row and the first column, a memory cell for reading data (hereinafter also referred to as a data read cell). A read voltage of 1.5 [V] is applied to the bit line BL1 connected to 102a, and 0 [V] is read to the bit line BL2 to which only the

memory cells

102b, 102d, 102f, and 102h that do not read data are connected. A forbidden voltage may be applied.

At this time, in the nonvolatile semiconductor memory device 100, 0 [V] is applied to the memory gate lines MGL1, MGL2, MGL3, and MLG4, 1.5 [V] is applied to the source-side selection gate line SGL, and the source line SL 0 [V] may be applied to Further, at this time, in the nonvolatile semiconductor memory device 100, the read gate voltage of 1.5 [V] is applied to the drain side selection gate line DGL1 connected to the data read cell 102a, and the

memory cells

102c, 102d, A read inhibit gate voltage of 0 [V] can be applied to the drain side select gate lines DGL2, DGL3, DGL4 to which only 102e, 102f, 102g, 102h are connected.

As a result, in the data read cell 102a, although the well just below the drain side select gate electrode DG connected to the bit line BL1 is in a conductive state, the charge is stored in the charge storage layer EC (data is written). ), The well just below the memory gate electrode MG becomes non-conductive, the electrical connection between the source line SL and the bit line BL1 is cut off, and the read voltage of 1.5 [V] of the bit line BL1 can be maintained as it is.

On the other hand, when no charge is stored in the charge storage layer EC of the data read cell 102a (when data is not written), the well just below the memory gate electrode MG becomes conductive, and the data read cell 102a passes through the data read cell 102a. The source line SL of 0 [V] is electrically connected to the bit line BL1 of 1.5 [V], and the 1.5 [V] applied to the bit line BL is read by the source line SL of 0 [V]. The voltage drops.

At this time, in the

other memory cells

102c, 102e, 102g sharing the bit line BL1 with the data read cell 102a, the drain side selection gate is caused by the voltage difference between the drain side selection gate lines DGL2, DGL3, DGL4 and the bit line BL1. The well immediately below the electrode DG becomes non-conductive and does not affect the read voltage of 1.5 [V] of the bit line BL1. Thus, the nonvolatile semiconductor memory device 100 can detect whether or not charges are accumulated in the charge accumulation layer EC of the data read cell 102a by detecting whether or not the read voltage of the bit line BL1 has changed.

Next, of the memory

cell formation units

101a, 101b, 101c, and 101d provided in the nonvolatile semiconductor memory device 100, for example, a planar layout of the memory cell formation unit 101b will be described. FIG. 10A is a schematic diagram illustrating an example of a planar layout when the memory cell formation portion 101b is viewed from above the semiconductor substrate. Here, a case where three

memory cells

102c, 102d, and 102i are provided in the memory cell formation portion 101b will be described.

The memory cell forming part 101b has a memory cell region ER3 in which

memory cells

102c, 102d, 102i are arranged, and one selection gate contact region ER6 is arranged at one end of the memory cell region ER3, Another select gate contact region ER7 is disposed at the other end of the memory cell region ER3. A selection gate electrode non-formation region ER1 (ER5) is disposed at the end of the selection gate contact region ER6 (ER7).

In this case, the memory cell formation unit 101b is configured so that the one selection gate electrode non-formation region ER1, the one selection gate contact region ER6, the memory cell region ER3, the other selection gate contact region ER7, and the other selection gate electrode non-formation A band-shaped memory gate electrode MG is extended over the region ER5. For example, the memory gate contact MGC is provided in the memory gate electrode MG of the selection gate electrode non-formation regions ER1 and ER5.

In the memory cell region ER3, a well W having a predetermined shape is formed on the surface of the semiconductor substrate. For example, the memory gate electrode MG intersects the memory placement regions W1, W2, and W3 formed in a strip shape in the well W. Is arranged. Here, the memory arrangement regions W1, W2, and W3 are divided into a source region WS side and a drain region WD side with the memory gate electrode MG as a boundary. In the memory cell formation portion 101b, the source regions WS of the memory placement regions W1, W2, and W3 are connected to each other, and the source regions WS are connected via the columnar source contacts SC to which the source lines SL (FIG. 9) are connected. A predetermined source voltage can be applied uniformly.

Further, in the memory cell formation portion 101b, the drain regions WD of the memory placement regions W1, W2, W3 are separated from each other, and different bit lines BL1, BL2, different via the bit contacts BC provided for the respective drain regions WD. A predetermined bit voltage can be individually applied to each drain region WD.

In the memory cell region ER3 of the memory cell formation portion 101b, one side wall 112 of the memory gate electrode MG is disposed on the drain region WD side of the well W, and the drain side selection gate electrode DG is formed along the side wall 112. ing. On the other hand, the other side wall 111 of the memory gate electrode MG is disposed on the source region WS side of the well W, and the source side selection gate electrode SG is formed along the side wall 111. In this case, the drain side selection gate electrode DG and the source side selection gate electrode SG are shared by the plurality of

memory cells

102c, 102d, 102i arranged in one direction together with the memory gate electrode MG. The drain side selection gate electrode DG and the source side selection gate electrode SG are insulated from the memory gate electrode MG by side wall spacers (not shown) made of an insulating material.

In the drain side selection gate electrode DG, a wide selection gate contact forming portion Ca provided with the drain side selection gate contact DGC is formed in one selection gate contact region ER7, and the drain side selection gate line DGL2 (FIG. The predetermined voltage from 9) can be applied via the drain-side selection gate contact DGC and the selection gate contact forming portion Ca.

In addition, a wide selection gate contact forming portion Cb provided with a source side selection gate contact SGC is formed in the other selection gate contact region ER6 in the source side selection gate electrode SG, and the source side selection gate line SGL A predetermined voltage from (FIG. 9) can be applied via the source side select gate contact SGC and the select gate contact forming portion Cb.

In addition, in the select gate electrode non-formation regions ER1 and ER5, the conductive layer made of a semiconductor material or the like is not formed along the side walls 111 and 112 and the end wall 113 of the memory gate electrode MG, and the drain side select gate electrode DG In addition, a physical cutting structure in which the source-side selection gate electrode SG is in a non-contact state is formed. In the memory cell formation portion 101b, the drain-side selection gate electrode DG and the source-side selection gate electrode SG are electrically disconnected due to the physical cutting structure of the selection gate electrode non-formation regions ER1, ER5. A predetermined voltage can be individually applied to the drain side selection gate electrode DG and the source side selection gate electrode SG.

JP 2011-129816 JP

By the way, in such a conventional memory cell formation portion 101b, as shown in FIG. 10B in which parts corresponding to those in FIG. 10A are assigned the same reference numerals, they are removed in the selection gate electrode non-formation regions ER1, ER5 in the manufacturing process. It is also conceivable that the semiconductor layer I that should have remained. At this time, in the memory cell formation portion 101b, there arises a problem that the drain side selection gate electrode DG and the source side selection gate electrode SG are electrically connected via the semiconductor layer I.

Here, for example, as shown in FIG. 9, in the data read operation for reading the data in the memory cell 102a in the first row and the first column, the drain side select gate electrode DG and the source side select in the memory cell formation portion 101b that does not read data. In the case where a short circuit failure is caused by electrical connection with the gate electrode SG, the drain side selection gate line DGL2 of 0 [V] and the source side selection gate line of 1.5 [V] in the memory cell formation portion 101b SGL is electrically connected (indicated by wiring L in FIG. 9).

As a result, in the nonvolatile semiconductor memory device 100, the voltage of 0 [V] of the drain side selection gate line DGL2 increases, or the source side selection gate line shared by all the

memory cells

102a, 102b,. The voltage of 1.5 [V] of SGL is lowered, and there is a possibility that a read malfunction may occur due to voltage fluctuations of the drain side selection gate line DGL2 and the source side selection gate line SGL.

Further, in the nonvolatile semiconductor memory device 100, when the drain side selection gate electrode DG and the source side selection gate electrode SG are electrically connected in the memory cell formation portion 101b and a short circuit defect occurs, the drain side selection gate line A leakage current is generated between the DGL 2 and the source-side selection gate line SGL, which causes a problem that power consumption during the data read operation increases.

Therefore, the present invention has been made in consideration of the above points. Compared to the conventional case, the present invention can reduce a read malfunction caused by a voltage fluctuation during a data read operation and can further reduce an increase in power consumption due to the voltage fluctuation. An object of the present invention is to propose a volatile semiconductor memory device.

In order to solve such a problem, a nonvolatile semiconductor memory device of the present invention includes a memory cell forming portion extending in one direction and having a memory gate electrode extending in a longitudinal direction, and extending in one direction. And at least another memory cell forming portion having a memory gate electrode extending along the longitudinal direction, and the one memory cell forming portion and the other memory cell forming portion are arranged in parallel at a predetermined distance. The one memory cell formation portion and the other memory cell formation portion are arranged on the semiconductor substrate so that the first selection gate electrode is disposed on the well of the semiconductor substrate via the first selection gate insulating film. A first selection gate structure having a second selection gate electrode on the well with a second selection gate insulating film interposed therebetween, the first selection gate structure, and the first selection gate structure. 2 Side walls between select gate structures A memory gate structure formed on the well in the order of a lower gate insulating film, a charge storage layer, an upper gate insulating film, and the memory gate electrode. The first selection gate electrode and the second selection gate electrode are not formed between the longitudinal end of the portion and the longitudinal end of the other memory cell formation portion, and the one memory cell formation A selection gate electrode non-formation region in which a longitudinal end of the first portion and a longitudinal end of the other memory cell formation portion are connected by a memory gate electrode, and the one memory cell formation portion and the other memory cell The memory gate electrode of the formation portion becomes an inner peripheral wall that circulates in a region surrounded by the one memory cell formation portion, the other memory cell formation portion, and the selection gate electrode non-formation region. 1 side wall, wherein the first selection gate electrode is provided.

In the nonvolatile semiconductor memory device of the present invention, even if a manufacturing failure occurs, the same type of first selection gate electrodes that are highly likely to be applied with the same voltage during a data read operation can be electrically connected to each other. Compared to the conventional case where voltage variations occur in the entire nonvolatile semiconductor memory device by connecting different types of first selection gate electrodes and second selection gate electrodes, which are likely to be applied with different voltage values. Thus, a read malfunction caused by voltage fluctuation during the data read operation can be reduced, and an increase in power consumption due to voltage fluctuation can be reduced.

It is the schematic which shows the cross-sectional structure of the memory cell provided in the non-volatile semiconductor memory device of this invention. It is the schematic which shows the circuit structure of the non-volatile semiconductor memory device by this invention. It is the table | surface which put together the voltage value at the time of various operation | movement of a non-volatile semiconductor memory device. It is the schematic which shows the planar layout of the non-volatile semiconductor memory device of this invention. FIG. 5 is a schematic diagram showing a planar layout when a short defect occurs in a predetermined memory cell array portion in the nonvolatile semiconductor memory device shown in FIG. 4. FIG. 3 is a schematic diagram showing a circuit configuration of a nonvolatile semiconductor memory device when a short failure occurs in a predetermined memory cell array unit. It is the schematic which shows the planar layout of the non-volatile semiconductor memory device by other embodiment. FIG. 8 is a schematic diagram showing a planar layout when a short defect occurs in a predetermined memory cell array portion in the nonvolatile semiconductor memory device shown in FIG. 7. It is the schematic which shows the circuit structure of the conventional non-volatile semiconductor memory device. FIG. 10A is a schematic diagram showing a planar layout of a conventional memory cell formation portion, and FIG. 10B is a schematic diagram showing a planar layout when a short circuit defect occurs in the memory cell formation portion shown in FIG. 10A.

Hereinafter, modes for carrying out the present invention will be described. The description will be in the following order.
<1. First Embodiment>
1-1. Configuration of memory cell 1-2. Circuit configuration of nonvolatile semiconductor memory device according to the present invention 1-3. Voltage during various operations in nonvolatile semiconductor memory device 1-4. Planar layout of nonvolatile semiconductor memory device 1-5. Nonvolatile semiconductor memory device when short circuit failure occurs 1-6. Action and effect <2. Nonvolatile Semiconductor Memory Device According to Other Embodiment>
2-1. Planar layout of nonvolatile semiconductor memory device according to other embodiment 2-2. Nonvolatile semiconductor memory device according to another embodiment when short circuit failure occurs <3. Other Embodiments>

(1) First Embodiment (1-1) Configuration of Memory Cell First, the configuration of memory cells arranged in a matrix in the nonvolatile semiconductor memory device of the present invention will be described below. As shown in FIG. 1, a memory cell 2a includes a memory gate structure 4a that forms an N-type transistor structure on a well W made of, for example, P-type Si, and an N-type MOS (Metal-Oxide-Semiconductor). A drain side select gate structure 5a that forms a transistor structure and a source side select gate structure 6a that also forms an N-type MOS transistor structure are formed.

On the surface of the well W, a drain region WD at one end of the drain side select gate structure 5a and a source region WS at one end of the source side select gate structure 6a are formed with a predetermined distance therebetween. Bit line BL1 is connected to region WD, and source line SL is connected to source region WS. Note that, on the surface of the well W, the low-concentration drain region WDa is formed adjacent to the drain region WD, and the sidewall SW formed along the side wall of the drain-side selection gate structure 5a includes the low-concentration drain region WDa. Arranged on drain region WDa. Further, the low-concentration source region WSa is formed adjacent to the source region WS on the surface of the well W, and the sidewall SW formed along the side wall of the source-side selection gate structure 6a includes the low-concentration source region WSa. Arranged on the source area WSa.

The memory gate structure 4a is formed on the well W between the low-concentration drain region WDa and the low-concentration source region WSa via, for example, silicon nitride (Si ₃ N ₄₎ via a lower gate insulating film 24a made of an insulating material such as SiO _2. ), Silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), hafnia (HfO2), etc., and the charge storage layer EC is also made of an insulating material. A memory gate electrode MG is provided via the upper gate insulating film 24b. Thus, the memory gate structure 4a has a configuration in which the charge storage layer EC is insulated from the well W and the memory gate electrode MG by the lower gate insulating film 24a and the upper gate insulating film 24b.

In addition to such a configuration, the memory gate structure 4a has a cap film CP formed of an insulating material formed on the memory gate electrode MG, and the silicide layer S1 on the upper surface of the drain side selection gate structure 5a. The silicide layer S2 on the upper surface of the source side select gate structure 6a is formed so as to be away from the upper surface of the memory gate electrode MG by the thickness of the cap film CP. Thus, the memory gate electrode MG in the region of the memory cell 2a has a structure in which no silicide layer is formed on the upper surface and is covered with the cap film CP.

In this case, the cap film CP can keep the silicide layer S1 of the drain side select gate structure 5a and the silicide layer S2 of the source side select gate structure 6a away from the memory gate electrode MG by the film thickness. Further, in this embodiment, the cap layer CP, for example on the lower cap film CPa made of an insulating material such as SiO _2, an upper cap film CPb made of an insulating material such as different SiN that is with the lower cap film CPa is It has a laminated structure.

Here, the memory gate electrode MG of the memory gate structure 4a is provided with a wall-shaped first side wall 11 and a wall-shaped second side wall 12 arranged to face the first side wall 11. In the memory gate structure 4a, each side wall of the lower gate insulating film 24a, the charge storage layer EC, the upper gate insulating film 24b, and the cap film CP extends along the first side wall 11 and the second side wall 12 of the memory gate electrode MG. The lower gate insulating film 24a, the charge storage layer EC, the upper gate insulating film 24b, and the cap film CP are formed in a region between the first sidewall 11 and the second sidewall 12 of the memory gate electrode MG.

The memory gate structure 4a is made of an insulating material along the second sidewall 12 of the memory gate electrode MG and the sidewalls of the lower gate insulating film 24a, the charge storage layer EC, the upper gate insulating film 24b, and the cap film CP. A side wall spacer 28a is formed, and the drain side select gate structure 5a is adjacent to the side wall spacer 28a. The sidewall spacer 28a formed between the memory gate structure 4a and the drain side selection gate structure 5a is formed with a predetermined film thickness, and the memory gate structure 4a, the drain side selection gate structure 5a, Can be insulated. Note that the film thickness of the side wall spacer 28a between the memory gate structure 4a and the drain side select gate structure 5a depends on the breakdown voltage of the side wall spacer 28a and the reading between the memory gate structure 4a and the drain side select gate structure 5a. In consideration of the current, it is desirable to select a width of 5 [nm] or more and 40 [nm] or less.

The drain side select gate structure 5a is formed on the well W between the side wall spacer 28a and the drain region WD with a film thickness of 9 [nm] or less, preferably 3 [nm] or less and made of an insulating material. 30 and the drain side select gate electrode DG1 is formed on the drain side select gate insulating film 30. Further, a silicide layer S1 is formed on the upper surface of the drain side selection gate electrode DG1 as the second selection gate electrode, and the drain side selection gate line DGL1 as the second selection gate line is connected to the silicide layer S1. ing.

Further, the memory gate structure 4a is insulated along the first sidewall 11 of the memory gate electrode MG and the sidewalls of the lower gate insulating film 24a, the charge storage layer EC, the upper gate insulating film 24b, and the cap film CP. A side wall spacer 28b made of a material is formed, and the source side select gate structure 6a is adjacent to the side wall spacer 28b. The sidewall spacer 28b formed between the memory gate structure 4a and the source-side selection gate structure 6a also has the same film thickness as 5 nm or more and 40 nm or less as one sidewall spacer 28a. The memory gate structure 4a and the source-side selection gate structure 6a can be insulated from each other.

The source side select gate structure 6a has a source side select gate insulating film made of an insulating material with a film thickness of 9 [nm] or less, preferably 3 [nm] or less, on the well W between the sidewall spacer 28b and the source region WS. The source-side selection gate electrode SG1 is formed on the source-side selection gate insulating film 33. The source-side selection gate electrode SG1 as the first selection gate electrode has a silicide layer S2 formed on the top surface, and the source-side selection gate line SGL as the first selection gate line is connected to the silicide layer S2. ing.

In addition, in the case of this embodiment, the source-side selection gate electrode SG1 and the drain-side selection formed along the first side wall 11 and the second side wall 12 of the memory gate electrode MG via the

side wall spacers

28a and 28b. Each of the gate electrodes DG1 is formed in a sidewall shape such that the top portion descends toward the well W as the distance from the memory gate electrode MG increases.

In the memory cell 2a, the source side select gate structure 6a and the drain side select gate structure 5a are formed in a sidewall shape along the side walls (first side wall 11 and second side wall 12) of the memory gate structure 4a, respectively. Even if the source side selection gate structure 6a and the drain side selection gate structure 5a are close to the memory gate structure 4a, the drain side selection gate electrode DG1 is formed by the cap film CP formed on the memory gate electrode MG. Since the silicide layer S1 on the upper side and the silicide layer S2 on the source-side selection gate electrode SG1 are separated from the memory gate electrode MG, the silicide layers S1, S2 and the memory gate electrode MG are short-circuited accordingly. It has been made to be able to prevent.

(1-2) Circuit Configuration of Nonvolatile Semiconductor Memory Device According to the Present Invention Next, the circuit configuration of the nonvolatile semiconductor memory device according to the present invention will be described. As shown in FIG. 2, in the nonvolatile semiconductor memory device 1, for example, a plurality of

memory cells

2a, 2b, 2d, 2e, 2g, 2h, 2i, and 2j are arranged in a matrix. Each

memory cell

2a, 2b, 2d, 2e, 2g, 2h, 2i, 2j has the same configuration as the memory cell 2a described in FIG. 1, and is a memory gate to which the memory gate line MGL is connected. The drain side selection gate electrode DG1 (DG2,...) Connected to the electrode MG, the drain side selection gate line DGL1 (DGL2, DGL3, DGL4), and the source side selection gate electrode SG1 connected to the source side selection gate line SGL (SG2,...)

The nonvolatile semiconductor memory device 1 includes memory

cell forming portions

3a, 3b, 3c, and 3d for each of the

memory cells

2a, 2b, 2d, 2e, 2g, 2h, 2i, and 2j arranged in the row direction. One memory cell array unit 1a (1c) is formed by pairing two adjacent memory

cell forming units

3a, 3b (3c, 3d), and a predetermined substrate voltage is applied to each memory

cell array unit

1a, 1c by the substrate voltage line Back. Can be applied.

Further, the nonvolatile semiconductor memory device 1 includes

memory cells

2a, 2d, 2g, 2i (2b, 2e, 2h, 2h, 2i, 2i) arranged in the column direction among the

memory cells

2a, 2b, 2d, 2e, 2g, 2h, 2i, 2j. 2j) share one bit line BL1 (BL2), and each bit line BL1, BL2 provides a predetermined value for each

memory cell

2a, 2d, 2g, 2i, 2b, 2e, 2h, 2j in the column direction. A bit voltage can be applied uniformly. Further, the nonvolatile semiconductor memory device 1 shares the drain side select gate lines DGL1, DGL2, DGL3, DGL4 for each of the memory

cell forming portions

3a, 3b, 3c, 3d, for example, and each drain side select gate line DGL1 , DGL2, DGL3, and DGL4 can apply a predetermined voltage to each of the memory

cell forming portions

3a, 3b, 3c, and 3d.

In this nonvolatile semiconductor memory device 100, one memory gate line MGL, one source-side selection gate line SGL, and one source line SL are connected to all the

memory cells

2a, 2b, 2d, 2e. , 2g, 2h, 2i, 2j, a predetermined memory gate voltage is applied to the memory gate line MGL, a predetermined source gate voltage is applied to the source-side selection gate line SGL, and a predetermined value is applied to the source line SL. A source voltage may be applied.

(1-3) Voltage during Various Operations in Nonvolatile Semiconductor Memory Device Next, various operations in such a nonvolatile semiconductor memory device 1 will be described. 3 shows, for example, a data write operation (“Prog”) in which charge is injected into the charge storage layer EC of the memory cell 2a in the nonvolatile semiconductor memory device 1 shown in FIG. 2, and the charge storage layer EC of the memory cell 2a. At the time of data read operation (“Read”) for detecting whether or not charges are accumulated in the memory cell and at the time of data erase operation (“Erase”) for extracting charges in the charge storage layer EC such as the memory cell 2a It is a table | surface which shows an example of the voltage value in.

In the column of “Prog” in FIG. 3, the voltage value (“selected column” and “selected row”) when the charge is injected into the charge storage layer EC of the memory cell 2 a and the charge in the charge storage layer EC of the memory cell 2 a Indicates a voltage value ("non-selected column" or "non-selected row") when no.

For example, when charge is injected into the charge storage layer EC of the memory cell 2a, as shown in the column “Prog” in FIG. 3, a 12 [V] charge storage gate is connected from the memory gate line MGL to the memory gate electrode MG. A voltage is applied, and a substrate voltage of 0 [V] can be applied to the well W (denoted as “Back” in FIG. 3). At this time, a gate-off voltage of 0 [V] is applied from the source-side selection gate line SGL to the source-side selection gate electrode SG1, and a source-off voltage of 0 [V] from the source line SL is applied to the source region WS. Can be applied. Thereby, the source-side selection gate structure 6a cuts off the electrical connection between the source region WS and the channel layer formation carrier region of the memory gate structure 4a, and forms the channel layer of the memory gate structure 4a from the source line SL. Application of voltage to the carrier region can be prevented.

On the other hand, a drain-side selection gate voltage of 1.5 [V] from the drain-side selection gate line DGL1 is applied to the drain-side selection gate electrode DG1, and a charge storage bit of 0 [V] from the bit line BL1 is applied to the drain region WD. A voltage can be applied. Thereby, the drain side select gate structure 5a can electrically connect the drain region WD and the channel layer forming carrier region of the memory gate structure 4a.

In the memory gate structure 4a, when the channel layer forming carrier region is electrically connected to the drain region WD, carriers are induced in the channel layer forming carrier region, and the channel layer having the same 0 [V] as the charge storage bit voltage Can be formed on the surface of the well W by the carrier. Thus, in the memory gate structure 4a, a large voltage difference (12 [V]) of 12 [V] is generated between the memory gate electrode MG and the channel layer, and the charge is generated in the charge storage layer EC by the quantum tunnel effect generated thereby. It can be injected and data can be written.

When a charge storage gate voltage necessary for injecting charges into the charge storage layer EC is applied to the memory gate electrode MG of the memory cell 2a, the memory cell 2a injects charges into the charge storage layer EC. When blocking, the source-side selection gate structure 6a cuts off the electrical connection between the well W in the region facing the memory gate electrode MG and the source region WS, and the drain-side selection gate structure 5a The electrical connection between the well W in the region facing the memory gate electrode MG and the drain region WD is cut off.

As a result, in the memory cell 2a to which data is not written, a depletion layer is formed in the channel layer forming carrier region, and the potential of the surface of the well W rises based on the charge storage gate voltage, and the memory gate electrode MG and the well Since the voltage difference on the W surface is reduced, charge injection into the charge storage layer EC can be prevented.

In the data read operation shown in the column “Read” in FIG. 3, for example, the bit line BL1 connected to the memory cell 2a to be read is precharged to 1.5 [V], for example, and the source line SL is set to 0. By detecting the potential of the bit line BL1 that changes depending on whether or not a current flows through the memory cell 2a at [V], it can be determined whether or not charges are accumulated in the charge accumulation layer EC of the memory cell 2a. . Specifically, when data is read from the memory cell 2a, if charge is accumulated in the charge accumulation layer EC of the memory gate structure 4a (when data is written), the well just below the memory gate structure 4a It becomes a non-conductive state at W, and the electrical connection between the drain region WD and the source region WS can be cut off. Thereby, in the memory cell 2a for reading data, the read voltage of 1.5 [V] on the bit line BL1 connected to the drain region WD can be maintained as it is.

On the other hand, when data is read from the memory cell 2a, if no charge is stored in the charge storage layer EC of the memory gate structure 4a (when data is not written), the well W immediately below the memory gate structure 4a is read. Becomes conductive, and the drain region WD and the source region WS are electrically connected. As a result, the 0 [V] source line SL and the 1.5 [V] bit line BL1 are electrically connected via the memory cell 2a. Connect. Thus, in the memory cell 2a that reads data, the read voltage of the bit line BL1 is applied to the source line SL of 0 [V], so that the read voltage of 1.5 [V] applied to the bit line BL1 is increased. descend.

Thus, in the nonvolatile semiconductor memory device 1, the data read operation of whether or not charges are accumulated in the charge accumulation layer EC of the memory cell 2a by detecting whether or not the read voltage of the bit line BL1 has changed. Can be executed. Note that a non-read voltage of 0 [V] can be applied to the bit line BL2 to which only the

memory cells

2b, 2e, 2h, and 2j from which data is not read are connected.

Incidentally, at the time of data erasing operation ("Erase" in FIG. 3) for extracting charges in the charge storage layer EC of the memory cell 2a, a memory of -12 [V] is transferred from the memory gate line MGL to the memory gate electrode MG. By applying the gate voltage, the charges in the charge storage layer EC are extracted toward the well W of 0 [V], and data can be erased.

(1-4) Planar Layout of Nonvolatile Semiconductor Memory Device Next, the planar layout of the above-described nonvolatile semiconductor memory device 1 will be described below. FIG. 4 is a schematic view showing a planar layout of the nonvolatile semiconductor memory device 1 of the present invention in which a plurality of memory

cell array portions

1a, 1b,... Are arranged on a semiconductor substrate as viewed from above the semiconductor substrate. In FIG. 4, among these memory

cell array portions

1a, 1b,..., A planar layout of one memory cell array portion 1a and a partial plane of another memory cell array portion 1b having the same configuration as the memory cell array portion 1a. Shows the layout. Since the memory

cell array portions

1a, 1b,... All have the same configuration, the following description will be focused on one memory cell array portion 1a.

Incidentally, FIG. 1 showing a cross-sectional configuration of the memory cell 2a shows a cross-sectional configuration in the AA ′ portion of FIG. In FIG. 4, in addition to the

side wall spacers

28a and 28b formed on the side wall of the memory gate structure 4a shown in FIG. 1, the drain side selection gate structure 5a and the source side selection gate structure 6a are formed. The side walls SW, silicide layers S1, S2, etc. are also not shown.

In the case of this embodiment, the memory cell array unit 1a includes one memory cell forming unit 3a and another memory cell forming unit 3b, and ends in the longitudinal direction of the paired memory

cell forming units

3a and 3b. Have select gate electrode non-formation regions ER1, ER5. The paired memory

cell forming portions

3a and 3b have a configuration in which the select gate electrode non-formation regions ER1 and ER5 are connected by the memory gate electrode MG. In this case, the memory cell array portion 1a has a predetermined configuration in which one memory cell forming portion 3a extending in one direction (row direction in FIG. 4) and another memory cell forming portion 3b extending in one direction are predetermined. It arrange | positions on a semiconductor substrate so that a distance may be provided and it may run in parallel.

A memory gate electrode MG is extended along the longitudinal direction in the memory

cell formation portions

3a and 3b, and a cap film CP is formed so as to cover the top of each memory gate electrode MG. The memory gate electrode MG Is provided outside in an unexposed state. For this reason, in FIG. 4 showing a planar layout as viewed from above the semiconductor substrate, the memory gate electrode MG does not appear in the memory

cell formation portions

3a and 3b, and the cap film CP is shown.

The memory gate electrode MG provided in one memory cell formation portion 3a is also extended from the end of the memory cell formation portion 3a to the selection gate electrode non-formation regions ER1 and ER5. It bends in the regions ER1 and ER5 and is connected to the end of the other memory cell forming portion 3b. Here, unlike the memory gate electrodes MG formed in the memory

cell formation portions

3a and 3b, the memory gate electrodes MG formed in the selection gate electrode non-formation regions ER1 and ER5 are covered with the cap film CP. It is exposed to the outside.

In the case of this embodiment, the memory gate electrode MG of the memory cell array portion 1a is formed in an endless square ring shape when viewed from above the semiconductor substrate, and the cap film CP is formed in the region of the memory

cell formation portions

3a and 3b. Since it is covered, the select gate electrode non-formation regions ER1 and ER5 that are not covered with the cap film CP have a configuration that is exposed to the outside in a U-shape.

Here, the memory cell formation portion 3a (3b) has a memory cell region ER3 in which a plurality of

memory cells

2a, 2b, 2c (2d, 2e, 2f) are formed along the longitudinal direction. 2 shows only the

memory cells

2a and 2b (2d and 2e), the memory cell 2c adjacent to the memory cell 2b (2e) is shown in FIG. (2f) is also illustrated.

In addition to the memory cell region ER3 described above, the memory cell formation portion 3a (3b) includes one select gate contact region ER6 provided at one end of the memory cell region ER3 and the other end of the memory cell region ER3. Other selection gate contact region ER7 provided in one end, one electrical disconnection region ER2 provided at the end of one selection gate contact region ER6, and other selection gate contact region ER7 provided in the other end And an electrical cutting region ER4. In this embodiment, the select gate electrode non-formation regions ER1 and ER5 are adjacent to the electrical cutting regions ER2 and ER4 located at the longitudinal ends of the memory cell formation portion 3a (3b). .

Here, in the memory cell region ER3, a well W having a predetermined shape is formed on the surface of the semiconductor substrate. For example, in the memory placement regions W1, W2, W3 formed in a strip shape in the well W, the memory

cell forming portion

3a , 3b are arranged to intersect. In the memory cell region ER3 of one memory cell formation portion 3a, a memory cell 2a (2b, 2c) having a memory gate structure 4a, a drain side selection gate structure 5a, and a source side selection gate structure 6a Is formed on the memory arrangement area W1 (W2, W3). Further, in the memory cell region ER3 of the other memory cell formation portion 3b, similarly to the one memory cell formation portion 3a, the memory gate structure 4b, the drain side selection gate structure 5b, and the source side selection gate structure Memory cells 2d (2e, 2f) having 6b are formed on the memory arrangement region W1 (W2, W3). Since the

memory cells

2b, 2c, 2d, 2e, 2f arranged in the memory cell region ER3 have the same configuration as the memory cell 2a described in FIG. 1, the description thereof is omitted here. .

The memory arrangement regions W1, W2, and W3 of the well W are divided into a source region WS side and a drain region WD side with the memory gate structure 4a (4b) as a boundary. Of the memory placement regions W1, W2, and W3, the source regions WS between the memory

cell formation portions

3a and 3b are connected to each other and share a columnar source contact SC provided at a predetermined position. The source contact SC has a configuration in which the source line SL (FIG. 2) is connected, and a predetermined source voltage applied from the source line SL is applied to the source region WS of each memory placement region W1, W2, W3. It can be applied uniformly.

On the other hand, the drain regions WD of the memory arrangement regions W1, W2, and W3 are separated from each other, and have a configuration in which columnar bit contacts BC are individually provided. Each bit contact BC is connected to a different bit line BL1, BL2,... (FIG. 2), and a predetermined bit voltage can be individually applied from the corresponding bit line BL1, BL2,. As a result, a predetermined bit voltage can be applied to each drain region WD of the memory cell forming portion 3a from the different bit lines BL1, BL2,.

In the case of this embodiment, the first side wall 11 of the memory gate electrode MG constituting the memory gate structure 4a is arranged in one memory cell forming portion 3a on the source region WS side of the well W, and this memory gate A source side select gate structure 6a is formed along the first side wall 11 of the electrode MG. Further, in this one memory cell forming portion 3a, the second side wall 12 of the memory gate electrode MG constituting the memory gate structure 4a is disposed on the drain region WD side of the well W, and the second side of the memory gate electrode MG is arranged. A drain side select gate structure 5a is formed along the two side walls 12.

In addition to such a configuration, in the other memory cell forming portion 3b paired with one memory cell forming portion 3a, the memory gate electrode MG in which the source side select gate structure 6a is formed in the one memory cell forming portion 3a. Similarly, the source side select gate structure 6b is formed along the first side wall 11 (inner peripheral wall). In addition to this, in the other memory cell formation portion 3b, along the second side wall 12 (outer peripheral wall) of the memory gate electrode MG in which the drain side selection gate structure 5a is formed in one memory cell formation portion 3a. Similarly, the drain side select gate structure 5b is formed.

In the source side select gate structure 6a (6b), a source side select gate electrode SG1 (SG2) formed in a sidewall shape is formed along the first side wall 11 of the memory gate structure 4a (4b). In addition, a wide selection gate contact formation portion Ca formed integrally with the source side selection gate electrode SG1 (SG2) is formed in one selection gate contact region ER6.

The selection gate contact forming portion Ca is formed with a planar portion 15a having a flat surface, and a columnar source side selection gate contact to which a source side selection gate line (not shown) is connected. An SGC is provided on the plane portion 15a. As a result, even in the sidewall-like source-side selection gate electrode SG1 (SG2) having a narrow width, a predetermined voltage from the source-side selection gate line SGL is passed through the source-side selection gate contact SGC and the selection gate contact forming portion Ca. Can be applied.

Further, the drain side select gate structure 5a (5b) has a drain side select gate electrode DG1 (DG2) formed in a side wall shape along the second side wall 12 of the memory gate structure 4a (4b). A wide selection gate contact forming portion Cb formed integrally with the drain side selection gate electrode DG1 (DG2) is formed in another selection gate contact region ER7.

Also in this selection gate contact formation portion Cb, a planar portion 15b having a flat surface is formed, and a columnar drain side selection gate contact DGC to which a drain side selection gate line DGL1 (DGL2) is connected, It is provided on the plane portion 15b. As a result, even in the sidewall-like drain-side selection gate electrode DG1 (DG2) having a narrow width, the predetermined voltage from the drain-side selection gate line DGL1 (DGL2) is applied to the drain-side selection gate contact DGC and the selection gate contact formation portion. It can be applied via Cb.

Incidentally, the selection gate contact formation portions Ca, Cb provided in the selection gate contact regions ER6, ER7 are connected to the source side selection gate electrode SG1 or the drain side selection gate electrode DG1, and the source side selection gate contact SGC or As long as the drain-side selection gate contact DGC can be formed, various other shapes may be used.

On the other hand, the electrical disconnect regions ER2, ER4 at the ends of the select gate contact regions ER6, ER7 are extended from the memory cell region ER3 by the memory gate structure 4a (4b). Unlike the source-side selection gate electrode SG1 (SG2) and the drain-side selection gate electrode DG1 (DG2) are not extended, these source-side selection gate electrode SG1 (SG2) and drain-side selection gate electrode DG1 (DG2) Thus, the selection gate electrode cutting part 103 is formed.

Here, the selection gate electrode cutting part 103 is composed of an i-type sidewall-like intrinsic semiconductor layer Ia, a sidewall-like inverse conductive semiconductor layer OC, and a sidewall-like intrinsic semiconductor layer Ib. The intrinsic semiconductor layer Ia, the reverse conductivity type semiconductor layer OC, and the intrinsic semiconductor layer Ib are arranged in this order along the first sidewall 11 and the second sidewall 12 of the memory gate electrode MG. Note that the reverse conductivity type semiconductor layer OC is formed of a different conductivity type (in this case, p-type) from the source side select gate electrode SG1 (SG2) and the drain side select gate electrode DG1 (DG2).

As described above, in the electrical disconnect regions ER2 and ER4, the first sidewall 11 and the second sidewall 11 of the memory gate electrode MG start from the n-type source side select gate electrode SG1 (SG2) and the drain side select gate electrode DG1 (DG2). Along the side wall 12, an i-type intrinsic semiconductor layer Ia, a p-type reverse conductivity semiconductor layer OC, and an i-type intrinsic semiconductor layer Ib are arranged in this order. As a result, in the memory cell array portion 1a, a pin junction is formed along the first sidewall 11 of the memory gate electrode MG, starting from the n-type source-side selection gate electrode SG1 (SG2) of the memory cell formation portion 3a (3b). As a result, the source side select gate electrodes SG1, SG2 formed along the same first side wall 11 can be electrically disconnected from each other. Similarly, on the second side wall 12 of the memory gate electrode MG, a pin junction is formed along the second side wall 12 starting from the n-type drain side select gate electrode DG1 (DG2) of the memory cell formation portion 3a (3b). The drain side select gate electrodes DG1 and DG2 formed along the same second side wall 12 can be electrically disconnected from each other.

Here, in the memory cell region ER3, the electrical disconnection regions ER2, ER4, and the selection gate contact regions ER6, ER7, as described above, the cap film CP is formed on the memory gate electrode MG. The cap film CP can prevent the upper surface of the memory gate electrode MG from being salicided.

On the other hand, in the select gate electrode non-formation regions ER1 and ER5, the cap film CP is not formed on the memory gate electrode MG, and the memory gate electrode MG is exposed to the outside. A columnar memory gate contact MGC is provided via a silicide layer (not shown) formed on the memory gate electrode MG. A memory gate line MGL (FIG. 2) is connected to the memory gate contact MGC, and a predetermined voltage can be applied from the memory gate line MGL. Thereby, the voltage of the memory gate line MGL can be applied to the memory gate electrode MG via the memory gate contact MGC.

As described above, in the nonvolatile semiconductor memory device 1, although the memory gate electrode MG is covered with the cap film CP in the memory cell region ER3, the selection gate contact regions ER6 and ER7, and the electrical disconnection regions ER2 and ER4, the selection is performed. A memory gate covered with the cap film CP in the memory cell region ER3 by applying a predetermined voltage from the memory gate electrode MG exposed in the gate electrode non-formation regions ER1 and ER5 via the memory gate contact MGC A predetermined voltage can also be applied to the electrode MG.

Incidentally, such a nonvolatile semiconductor memory device 1 includes a film forming process, a resist coating process, an exposure development process, an etching process, an impurity implantation process, a resist stripping process, etc., which are general CMOS (Complementary MOS) manufacturing processes. Therefore, the manufacturing method is omitted here.

(1-5) Nonvolatile Semiconductor Memory Device When Short Circuit Failure Occurs Next, the nonvolatile semiconductor memory device 1 when a short circuit failure occurs due to a manufacturing failure or the like will be described. 5 in which parts corresponding to those in FIG. 4 are denoted by the same reference numerals as those shown in FIG. 4, when the nonvolatile semiconductor memory device 1 shown in FIG. Non-volatility when the semiconductor material that will become the intrinsic semiconductor layers Ia and Ib of the selection gate electrode cutting portion 103 remains in the selection gate electrode non-formation regions ER1 and ER5 in the manufacturing process formed in ER2 and ER4. FIG. 2 shows a schematic diagram of a semiconductor memory device 21. FIG.

In this case, since the semiconductor material also remains in the select gate electrode non-formation regions ER1 and ER5, in the select gate electrode non-formation regions ER1 and ER5, for example, the semiconductor material along the first side wall 11 of the memory gate electrode MG. A side wall-like intrinsic semiconductor layer Id is formed, and a side wall-like intrinsic semiconductor layer Ie made of a semiconductor material is formed along the second side wall 12 of the memory gate electrode MG.

Thus, the first side wall 11 serving as the inner peripheral wall of the memory gate electrode MG has, for example, the intrinsic semiconductor layer Ia2, the reverse conductivity type semiconductor layer OCb, and the intrinsic semiconductor layer in the electrical cutting region ER2 of the one memory cell formation portion 3a. Id is formed in order, and the intrinsic semiconductor layer Id is formed as it is also on the first side wall 11 of the selection gate electrode non-formation region ER1 (ER5), and the intrinsic semiconductor layer Id is formed in another memory cell formation portion 3b. To the opposite conductivity type semiconductor layer OCc. In the other memory cell formation portion 3b, the intrinsic semiconductor layer Ia3, the reverse conductivity type semiconductor layer OCc, and the intrinsic semiconductor layer Id are arranged in this order along the first sidewall 11 of the memory gate electrode MG in the electrical cutting region ER2. It is formed.

At this time, for example, if foreign matter generated in the manufacturing process adheres to the reverse conductivity type semiconductor layers OCb and OCc, or if the defective formation of the reverse conductivity type semiconductor layers OCb and OCc occurs during manufacturing, the memory gate Intrinsic semiconductor layers Ia2, Id, Ia3 formed along the first side wall 11 of the electrode MG are electrically connected to each other. At this time, in the nonvolatile semiconductor memory device 21 of the present invention, the source side selection gate electrode SG1 of one memory cell formation portion 3a and the source side selection gate electrode SG2 of another memory cell formation portion 3b are both memory. Since the gate electrode MG is formed along the first side wall 11, the intrinsic semiconductor layers Ia2, Id, Ia3 formed along the first side wall 11 of the memory gate electrode MG are electrically connected to each other. Then, the source side select gate electrodes SG1, SG2 are electrically connected.

Here, FIG. 6 in which parts corresponding to those in FIG. 2 are assigned the same reference numerals shows a source side selection gate electrode SG1 of one memory cell formation portion 3a and a source side selection gate electrode of another memory cell formation portion 3b. 3 is a schematic diagram showing a circuit configuration of a nonvolatile semiconductor memory device 21 when SG2 is electrically connected. FIG. At this time, the memory

cell forming portions

3a and 3b of the memory cell array portion 1a are configured such that the source side select gate lines SGL shared by the memory

cell forming portions

3a and 3b are connected by the wiring La as shown in FIG. Can be considered.

In this case, for example, at the time of data read operation for detecting whether or not electric charge is stored in the charge storage layer EC of the memory cell 2a, the nonvolatile semiconductor memory device 21 uses the memory cell 2a for reading data and other data Since the same source-side selection gate line SGL is shared by the memory cells 2d and the like that do not read the memory cell, the source-side selection gate electrode SG1 of one memory cell formation portion 3a and the source side of another memory cell formation portion 3b Even if the selection gate electrode SG2 is electrically connected, voltage fluctuation does not occur in the 1.5 [V] source side selection gate line SGL, and a conventional read malfunction can be prevented.

Next, as shown in FIG. 5, the case where the semiconductor material remains along the second side wall 12 of the memory gate electrode MG exposed in the selection gate electrode non-formation region ER1 will be described. As shown in FIG. 5, in the memory cell array portion 1a, if the semiconductor material remains in the select gate electrode non-formation regions ER1 and ER5, the second memory gate electrode MG in the select gate electrode non-formation regions ER1 and ER5. A sidewall-like intrinsic semiconductor layer Ie made of a semiconductor material may be formed along the sidewall 12.

In this case, the second side wall 12 serving as the outer peripheral wall of the memory gate electrode MG is, for example, the reverse conductivity type semiconductor layer OCa in the electrical cutting region ER2 of one memory cell formation portion 3a and the other memory cell formation portion 3b. The reverse conductivity type semiconductor layer OCd in the electrical cutting region ER2 is connected to the intrinsic semiconductor layer Ie.

At this time, for example, when foreign matter generated in the manufacturing process adheres to the reverse conductivity type semiconductor layers OCa and OCd, or defective formation of the reverse conductivity type semiconductor layers OCa and OCd occurs at the time of manufacture, the memory gate Intrinsic semiconductor layers Ia1, Ie, Ia4 formed along the second side wall 12 of the electrode MG are electrically connected to each other. At this time, in the nonvolatile semiconductor memory device 21 of the present invention, the drain side selection gate electrode DG1 of one memory cell formation portion 3a and the drain side selection gate electrode DG2 of the other memory cell formation portion 3b are memory gate electrodes. Since the MG is formed along the same second side wall 12, the intrinsic semiconductor layers Ia1, Ie, Ia4 formed along the second side wall 12 of the memory gate electrode MG are electrically connected to each other. Then, the drain side select gate electrodes DG1 and DG2 are electrically connected.

At this time, as shown in FIG. 6, in the nonvolatile semiconductor memory device 21, one drain-side selection gate line DGL1 connected to the drain-side selection gate electrode DG1 in one memory cell formation portion 3a and another memory In the cell formation portion 3b, it can be considered that the other drain side selection gate line DGL2 connected to the drain side selection gate electrode DG2 is connected by the wiring Lb.

In this case, for example, at the time of data read operation for detecting whether or not charge is stored in the charge storage layer EC of the memory cell 2a, the nonvolatile semiconductor memory device 21 is connected to the memory cell 2a to which data is read. Since 1.5 [V] is applied to the drain-side selection gate line DGL1, while 0 [V] is applied to the other drain-side selection gate line DGL2 to which the memory cell 2d or the like that does not read data is connected. If the drain side selection gate electrode DG1 of the memory cell formation portion 3a and the drain side selection gate electrode DG2 of the other memory cell formation portion 3b are electrically connected, a voltage is applied to the drain side selection gate lines DGL1 and DGL2. Variations occur, and in this respect, a conventional read malfunction occurs.

However, in the nonvolatile semiconductor memory device 21 of the present invention, since the drain side select gate lines DGL1, DGL2, DGL3, DGL4 are individually provided in units of the memory

cell forming portions

3a, 3b, 3c, 3d, respectively, In this case, only the drain side selection gate line DGL1 of one memory cell formation portion 3a and the drain side selection gate line DGL2 of the other memory cell formation portion 3b are connected by the wiring Lb. Therefore, in the nonvolatile semiconductor memory device 21, the voltage fluctuation occurs only in the drain side selection gate lines DGL1, DGL2 connected to the memory

cell formation portions

3a, 3b, and the voltage fluctuation occurs in the other drain side selection gate lines DGL3, DGL4. It can be prevented from occurring.

Thus, in this nonvolatile semiconductor memory device 21, for example, even if the drain side select gate electrodes DG1 and DG2 are connected to each other in the memory

cell formation portions

3a and 3b, reading due to voltage fluctuations of the drain side select gate lines DGL1 and DGL2 Since the occurrence of malfunctions can be limited to only the memory

cell formation parts

3a and 3b, even if a short circuit failure occurs between these memory

cell formation parts

3a and 3b, read errors in other memory

cell formation parts

3c and 3d Can be prevented.

Incidentally, if a short circuit failure occurs in the memory

cell formation portions

3c and 3d that do not read data and the drain side select gate lines DGL3 and DGL4 are connected to each other, both of the drain side select gate lines DGL3 and DGL4 are connected. Since 0 [V] is applied, voltage fluctuation does not occur in the drain side select gate lines DGL3 and DGL4, and a conventional read malfunction can be prevented.

(1-6) Operation and Effect In the above configuration, in the nonvolatile semiconductor memory device 1, the same memory gate electrode MG is shared by one memory cell forming portion 3a and the other memory cell forming portion 3b, and the select gate electrode is not turned on. In the formation regions ER1 and ER5, one memory cell formation portion 3a and another memory cell formation portion 3b are connected by a memory gate electrode MG. Further, in the nonvolatile semiconductor memory device 1, the source side selection gate electrode SG1 of one memory cell formation portion 3a and the source side selection gate electrode SG2 of another memory cell formation portion 3b are connected to the first of the memory gate electrodes MG. 1 Along the side wall 11.

As a result, in the nonvolatile semiconductor memory device 1, even when foreign matter, a conductive material, or the like remains along the first side wall 11 of the memory gate electrode MG due to a manufacturing defect, one memory cell forming unit 3a and another The same type of source-side selection gate electrodes SG1, SG2 to which the same voltage is applied during the data read operation with the memory cell formation portion 3b can be electrically connected to each other, so that the source side due to a short failure during the data read operation Voltage fluctuations at the selection gate electrodes SG1, SG2 and voltage fluctuations at the drain side selection gate electrodes DG1, DG2 can be prevented.

Therefore, in the nonvolatile semiconductor memory device 1, in the case of a manufacturing defect, different types of drain-side selection gate electrodes and source-side selection gate electrodes, which are likely to be applied with different voltage values, are connected to each other and are nonvolatile. Compared to the case where voltage fluctuation occurs in the entire semiconductor memory device, it is possible to reduce a read malfunction caused by voltage fluctuation during a data read operation, and to reduce an increase in power consumption caused by unintended voltage fluctuation.

Further, in the nonvolatile semiconductor memory device 1, the drain side selection gate electrode DG1 of one memory cell formation portion 3a and the drain side selection gate electrode DG2 of another memory cell formation portion 3b are connected to the first of the memory gate electrodes MG. 2 Provided along the side wall 12.

As a result, in the nonvolatile semiconductor memory device 1, even when foreign matter, a conductive material, or the like remains along the second side wall 12 of the memory gate electrode MG due to manufacturing defects, one memory cell forming portion 3a and another Since the same type of drain-side selection gate electrodes DG1, DG2, which are highly likely to be applied with the same voltage during the data read operation, can be electrically connected to the memory cell formation portion 3b, the drain during the data read operation The probability of occurrence of voltage fluctuations at the side select gate electrodes DG1 and SG2 can be reduced.

Further, in this nonvolatile semiconductor memory device 1, even if different voltages are applied to the drain side select gate electrodes DG1, DG2 in which a short circuit defect has occurred, a different drain side is used for each memory

cell formation portion

3a, 3b,. Since the selection gate lines DGL1, DGL2,... Are connected, only the drain side selection gate electrode DG1 of one memory cell formation portion 3a and the drain side selection gate electrode DG2 of the other memory cell formation portion 3b are electrically connected. Connected, the voltage fluctuation can be limited to only the memory

cell forming portions

3a and 3b, and it is possible to prevent the voltage fluctuation from occurring except for the memory

cell forming portions

3a and 3b.

Therefore, in the nonvolatile semiconductor memory device 1, in the case of a manufacturing defect, different types of drain-side selection gate electrodes and source-side selection gate electrodes, which are likely to be applied with different voltage values, are connected to each other and are nonvolatile. Compared with the case where voltage fluctuation occurs in the entire semiconductor memory device, it is possible to reduce a read malfunction caused by voltage fluctuation during a data read operation, and to reduce an increase in power consumption due to unintended voltage fluctuation.

(2) Nonvolatile Semiconductor Memory Device According to Other Embodiment (2-1) Planar Layout of Nonvolatile Semiconductor Memory Device According to Other Embodiment In the above-described embodiment, an endless square as viewed from above the semiconductor substrate Although the nonvolatile semiconductor memory device 1 in which the memory gate electrode MG is formed in a ring shape and the two memory

cell forming portions

3a and 3b are provided in one memory cell array portion 1a has been described, the present invention is not limited to this, and FIG. 7, the memory gate electrode MG1 is formed in an endless ladder shape when viewed from above the semiconductor substrate, and three or more memory cells are formed in one memory cell array portion 41a. A non-volatile semiconductor memory device 41 provided with the forming

portions

3b, 3a, 3e,... May be applied.

In this case, the memory cell array unit 41a has a configuration in which a plurality of memory

cell forming units

3b, 3a, 3e,... Are arranged in parallel on a semiconductor substrate at a predetermined distance, and the memory

cell forming units

3b, 3b, 3a, 3e,... Share the same memory gate electrode MG1. In practice, the memory gate electrode MG1 extends in the direction in which the plurality of memory

cell formation portions

3b, 3a, 3e,... Are arranged in the selection gate electrode non-formation regions ER1, ER5, and each memory cell formation It is connected with the terminal of

part

3b, 3a, 3e, ....

In the case of this embodiment, for example, the memory cell forming portion 3a in the second row shown in FIG. 7 includes a memory gate on the source region WS side of the well W between the memory cell forming portion 3b in the third row. A first side wall 11 of the electrode MG1 is disposed, and a source side select gate electrode SG1 is formed along the first side wall 11. Further, in this memory cell formation portion 3a, the second sidewall 12 of the memory gate electrode MG1 is disposed on the drain region WD side of the well W between the memory cell formation portion 3e in the first row, and this second A drain side select gate electrode DG1 is formed along the side wall 12.

Here, the first side wall 11 of the memory gate electrode MG1 formed in the memory cell formation portion 3a in the second row extends to the memory cell formation portion 3b in the third row adjacent to the memory cell formation portion 3a. Thus, the first side wall 11 of the memory gate electrode MG1 in the memory cell formation portion 3b in the third row can be used as it is. Thus, in the adjacent memory

cell forming portions

3a and 3b, the first side wall 11 of the memory gate electrode MG1 is formed so as to circulate without a break. In the memory cell formation portion 3b in the third row, the source region WS is formed in the well W on the first side wall 11 side of the memory gate electrode MG1, and the source side selection gate electrode is formed along the first side wall 11. SG2 may be provided.

Thus, the memory cell forming portion 3b in the third row has the same source side along the first side wall 11 of the memory gate electrode MG1 in which the source side select gate electrode SG1 is formed in the memory cell forming portion 3a in the second row. A select gate electrode SG2 can be formed. In the memory cell formation portion 3b in the third row, the drain region WD is formed in the well W on the second side wall 12 side of the memory gate electrode MG1, and the drain side selection gate electrode DG2 is formed along the second side wall 12 Can be formed.

Incidentally, since the memory cell forming portion 3b in the third row is formed at one end of the memory cell array portion 41a as shown in FIG. 7, the second side wall 12 of the memory gate electrode MG1 is connected to the memory cell array portion. The second side wall 12 can be extended to the memory cell formation portion (not shown) disposed at the other end of the memory cell array portion 41a through the selection gate electrode non-formation regions ER1 and ER5. . In the memory cell formation portion formed at the other end of the memory cell array portion 41a, the drain side selection gate electrode along the second side wall 12 of the memory gate electrode MG1 is the same as the memory cell formation portion 3b in the third row. Can be formed.

On the other hand, the second sidewall 12 of the memory gate electrode MG1 circulates between the memory cell formation portion 3a in the second row and the memory cell formation portion 3e in the first row adjacent to the memory cell formation portion 3a on the other side. The memory

cell forming portions

3a and 3e adjacent to each other share the same second side wall 12 of the memory gate electrode MG1. In this case, in the memory cell formation portion 3e in the first row, the drain region WD is formed in the well W on the second side wall 12 side of the memory gate electrode MG1, and the drain side selection gate is formed along the second side wall 12. An electrode DG3 may be provided.

Thus, the memory cell forming portion 3e in the first row also has the same drain side along the second side wall 12 of the memory gate electrode MG1 in which the drain side select gate electrode DG1 is formed in the memory cell forming portion 3a in the second row. A select gate electrode DG3 can be formed. In the memory cell formation portion 3e in the first row, a source region WS is formed in the well W on the first side wall 11 side of the memory gate electrode MG1, and the source side selection gate electrode is formed along the first side wall 11. SG3 is formed.

Also in the nonvolatile semiconductor memory device 41, the voltage values of the respective parts during the data write operation (Prog), the data read operation (Read), and the data erase operation (Erase) are described in “(1 -3) Voltages in Various Operations of Nonvolatile Semiconductor Memory Device ”, the description is omitted here.

(2-2) Nonvolatile Semiconductor Memory Device According to Other Embodiment When Short Circuit Failure Occurs Next, the nonvolatile semiconductor memory device 41 when a short circuit failure occurs due to a manufacturing failure or the like will be described. Here, in FIG. 8 in which the same reference numerals are assigned to the corresponding parts to FIG. 7, when the nonvolatile semiconductor memory device 41 shown in FIG. 7 is manufactured, for example, the selection gate electrode cutting part 103 is formed by etching. Non-volatile semiconductor memory device 51 when the semiconductor material of the selection gate electrode cutting portion 103 remains in the selection gate electrode non-formation regions ER1, ER5 in the manufacturing process formed in the electrical cutting regions ER2, ER4. The schematic of is shown.

In this case, since the semiconductor material also remains in the select gate electrode non-formation regions ER1 and ER5, the select gate electrode non-formation regions ER1 and ER5 are made of the semiconductor material along the first sidewall 11 of the memory gate electrode MG. A sidewall-like intrinsic semiconductor layer Id is formed, and sidewall-like intrinsic semiconductor layers Ie, If made of a semiconductor material are formed along the second sidewall 12 of the memory gate electrode MG.

Here, for example, in the memory cell formation part 3a in the second row, the intrinsic semiconductor layer Ia2, the reverse conductivity type semiconductor layer OCb, and the intrinsic semiconductor layer Id are formed on the first side wall 11 of the memory gate electrode MG in the electrical disconnection region ER2. Are formed side by side, and the intrinsic semiconductor layer Id can also be formed in the select gate electrode non-formation region ER1 (ER5) as it is. As a result, the memory cell formation portion 3a is connected in series by the intrinsic semiconductor layer Id and the reverse conductivity type semiconductor layer OCc of the memory cell formation portion 3b in the third row sharing the first side wall 11 of the memory gate electrode MG1. Can be configured.

At this time, for example, if foreign matter generated in the manufacturing process adheres to the reverse conductivity type semiconductor layers OCb and OCc, or if the defective formation of the reverse conductivity type semiconductor layers OCb and OCc occurs during manufacturing, the memory gate Intrinsic semiconductor layers Ia2, Id, Ia3 formed along the first side wall 11 of the electrode MG1 are electrically connected to each other. At this time, in the nonvolatile semiconductor memory device 51 of the present invention, the source-side selection gate electrode SG1 of the memory cell formation portion 3a in the second row and the source-side selection gate electrode SG2 in the memory cell formation portion 3b of the third row are provided. Since the memory gate electrode MG1 is formed along the same first side wall 11, the intrinsic semiconductor layers Ia2, Id, Ia3 formed along the first side wall 11 of the memory gate electrode MG1 are electrically connected to each other. In this state, the source side select gate electrodes SG1, SG2 are electrically connected.

At this time, in the nonvolatile semiconductor memory device 51, similarly to the above-described embodiment, the source-side selection gate line SGL connected to the source-side selection gate electrode SG1 of one memory cell formation portion 3a and other memory cells It can be considered that the source side selection gate line SGL connected to the source side selection gate electrode SG2 of the formation part 3b is connected by the wiring La (FIG. 6).

In this case, for example, in the data read operation for detecting whether or not charges are accumulated in the charge accumulation layer EC of the memory cell 2a provided in the memory cell formation unit 3a in the second row, the nonvolatile semiconductor memory device 51 Since the memory cell 2a that reads data and the memory cell 2d that does not read data share the same source side selection gate line SGL, the source side selection gate electrode SG1 of the memory cell formation portion 3a in the second row And even if the source-side selection gate electrode SG2 of the memory cell formation part 3b in the third row is electrically connected, the voltage fluctuation does not occur in the 1.5-V source-side selection gate line SGL, A conventional read malfunction can be prevented.

Next, as shown in FIG. 8, in the select gate electrode non-formation regions ER1 and ER5 between the memory cell formation portion 3e in the first row and the memory cell formation portion 3a in the second row, the second sidewall of the memory gate electrode MG1 A case where the semiconductor material remains along the line 12 will be described. As shown in FIG. 8, when the semiconductor material remains in the select gate electrode non-formation regions ER1 and ER5 between the memory

cell formation portions

3a and 3e, the semiconductor material along the second side wall 12 of the memory gate electrode MG. A sidewall-like intrinsic semiconductor layer If may be formed.

In this case, on the second side wall 12 of the memory gate electrode MG between the memory

cell formation portions

3a and 3e, for example, the reverse conductivity type semiconductor layer OCa in the electrically disconnected region ER2 of the memory cell formation portion 3a in the second row, This is a structure in which the reverse conductivity type semiconductor layer OCe in the electrically disconnected region ER2 of the memory cell formation portion 3e in the first row is connected by the intrinsic semiconductor layer If.

At this time, for example, if foreign matter generated in the manufacturing process adheres to the reverse conductivity type semiconductor layers OCa, OCe, or if the reverse conductivity type semiconductor layers OCa, OCe are poorly formed at the time of manufacture, the memory gate Intrinsic semiconductor layers Ia1, If, Ia4 formed along the second side wall 12 of the electrode MG are electrically connected to each other.

At this time, in the nonvolatile semiconductor memory device 51 of the present invention, the drain side selection gate electrode DG1 of the memory cell formation portion 3a in the second row and the drain side selection gate electrode DG3 in the memory cell formation portion 3e of the first row are provided. Since the memory gate electrode MG1 is formed along the same second side wall 12, the intrinsic semiconductor layers Ia1, If, Ia4 formed along the second side wall 12 of the memory gate electrode MG1 are electrically connected to each other. In this state, the drain side select gate electrodes DG1 and DG3 are electrically connected to each other.

In this case, for example, in the data read operation for detecting whether or not charges are accumulated in the charge accumulation layer of the memory cell 2a arranged in the memory cell formation unit 3a in the second row, the nonvolatile semiconductor memory device 51 1.5 [V] is applied to the drain-side selection gate electrode DG1 of the memory cell formation portion 3a that reads data, while 0 [V] is applied to the drain-side selection gate electrode DG3 connected to the memory cell formation portion 3e that does not read data. Is applied. Therefore, also in the nonvolatile semiconductor memory device 51, the drain side selection gate electrode DG1 of the memory cell formation unit 3a in the second row and the drain side selection gate electrode DG3 of the memory cell formation unit 3e in the first row are electrically connected. If they are connected, voltage fluctuations occur in the drain side select gate electrodes DG1 and DG3, and in this respect, a conventional read malfunction occurs.

However, in the nonvolatile semiconductor memory device 51 of the present invention, the drain-side selection gate electrode lines are individually provided in units of the memory

cell formation portions

3b, 3a, 3e,. Only the drain side select gate line connected to the cell forming portion 3a and the drain side select gate line connected to the memory cell forming portion 3e in the first row are connected. Therefore, in the nonvolatile semiconductor memory device 51, as in the above-described embodiment, although voltage fluctuation occurs only in each drain-side selection gate line connected to the memory

cell formation units

3a and 3e, other memory cell formation units It is possible to prevent voltage fluctuations from occurring on the drain side select gate line connected to 3b.

According to the above configuration, even in the nonvolatile semiconductor memory device 41, as in the above-described embodiment, different types of drain-side selections that are likely to be applied with different voltage values in the case of a manufacturing failure as in the past. Compared to the case where voltage fluctuation occurs in the entire nonvolatile semiconductor memory device by connecting the gate electrode and the source side selection gate electrode, read malfunction caused by voltage fluctuation during data read operation can be reduced, and consumption due to unintended voltage fluctuation The increase in power can be reduced.

(3) Other Embodiments The present invention is not limited to the present embodiment, and various modifications may be made within the scope of the gist of the present invention. The voltage value may be applied. In the above-described embodiment, the case where the source-side selection gate electrodes SG1 and SG2 are used as the first selection gate electrode formed on the first sidewall of the memory gate electrode has been described. However, the present invention is not limited to this. Alternatively, the drain side select gate electrode may be formed on the first side wall of the memory gate electrode as the first select gate electrode. In this case, the second selection gate electrode formed on the second sidewall of the memory gate electrode is a source side selection gate electrode.

In the above-described embodiment, the description has been given of the case where the selection gate electrode cutting portion 103 that forms the pin junction with the drain side selection gate electrode DG1 and the source side selection gate electrode SG1 as a starting point is provided. However, the present invention is not limited to this, and a selection gate electrode cutting portion that forms a nin junction structure, a pip junction structure, an npn junction structure, or a pnp junction structure starting from the drain side selection gate electrode DG1 and the source side selection gate electrode SG1 is provided. May be. That is, between the first selection gate electrode of one memory cell formation portion and the first selection gate electrode of another memory cell formation portion, the first selection gate electrode and the second Either a reverse conductivity type semiconductor layer or an intrinsic semiconductor layer having a conductivity type different from that of the selection gate electrode is preferably provided.

Further, in the above-described embodiment, the case where the electrical cutting region ER2 (ER4) is disposed at the end of the selection gate contact region ER6 (ER7) has been described. However, the present invention is not limited thereto, and the electrical cutting region is not limited thereto. Only the selection gate electrode non-formation region ER1 (ER5) may be arranged at the end of the selection gate contact region ER6 (ER7) without providing ER2 (ER4).

Furthermore, regardless of the presence or absence of the electrical cutting regions ER2, ER4, the selection of forming a pin junction, nin junction structure, pip junction structure, npn junction structure, or pnp junction structure in the selection gate electrode non-formation regions ER1, ER5 A gate electrode cutting part may be provided. That is, on the side wall of the memory gate electrode in the selection gate electrode non-formation regions ER1, ER5, either a reverse conductivity type semiconductor layer having a conductivity type different from that of the first selection gate electrode and the second selection gate electrode or an intrinsic semiconductor layer It is good to be provided.

Furthermore, in the above-described embodiment, the case where the memory gate electrode MG (FIG. 4) or the endless ladder-like memory gate electrode MG1 (FIG. 7) in which the semiconductor substrate is viewed from the top when viewed from above is applied is described. However, the present invention is not limited to this, and the first selection gate electrode is provided on the first sidewall side of the memory gate electrode shared by one memory cell forming unit and the other memory cell forming unit. As long as each source-side selection gate electrode (or each drain-side selection gate electrode) can be provided, memory gate electrodes having various shapes may be applied.

Furthermore, in the above-described embodiment, the P-type well W is used to form a memory gate structure 4a that forms an N-type transistor structure and a drain-side selection gate structure 5a that forms an N-type MOS transistor structure. The source side select gate structure 6a that also forms an N-type MOS transistor structure has been described. However, the present invention is not limited to this, and an N-type well is used to form a P-type transistor. A memory gate structure that forms the structure, a drain-side selection gate structure that forms the P-type MOS transistor structure, and a source-side selection gate structure that also forms the P-type MOS transistor structure may be provided. In this case, since the N-type and P-type polarities of the memory cell 2a described in the above embodiment are reversed, the memory gate structure, the drain-side selection gate structure, the source-side selection gate structure, Each voltage applied to the bit line, the source line, etc. also changes accordingly.

Furthermore, in the above-described embodiment, for example, the case where data is written by injecting charges into the charge storage layer EC of the memory cell 2a and the data is erased by extracting charges from the charge storage layer EC has been described. However, the present invention is not limited to this, and conversely, data is written by extracting charges in the charge storage layer EC of the memory cell 2a, and data is erased by injecting charges into the charge storage layer EC. You may make it do.

Furthermore, in the above-described embodiment, as a cap film formed on the tops of the memory gate electrodes MG, MG1, on the lower cap film CPa, an upper part made of an insulating material such as SiN different from the lower cap film CPa. Although the cap film CP having a laminated structure in which the cap film CPb is laminated has been described, the present invention is not limited to this, and a single layer cap film or a cap film having a laminated structure of three or more layers may be used.

1, 21, 41, 51 Non-volatile

semiconductor memory device

2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i,

2j Memory cell

3a, 3b, 3c, 3d, 3e Memory

cell formation part

4a, 4b, 4c

Memory gate structure

5a, 5b, 5c Drain side selection gate structure (second selection gate structure)
6a, 6b, 6c Source side select gate structure (first select gate structure)
11 First sidewall 12 Second sidewall CP cap film ER1, ER5 Select gate electrode non-formation region MG, MG1 Memory gate electrode DG1, DG2, DG3 Drain side select gate electrode (second select gate electrode)
SG1, SG2, SG3 Source side select gate electrode (first select gate electrode)

Claims

One memory cell forming portion extending in one direction and having a memory gate electrode extending along the longitudinal direction, and another having a memory gate electrode extending in one direction and extending along the longitudinal direction A memory cell forming portion, and the one memory cell forming portion and the other memory cell forming portion are arranged on the semiconductor substrate so as to run in parallel with a predetermined distance,
The one memory cell forming portion and the other memory cell forming portion are:
A first select gate structure having a first select gate electrode on a well of the semiconductor substrate via a first select gate insulating film;
A second selection gate structure having a second selection gate electrode on the well via a second selection gate insulating film;
A sidewall spacer is provided between the first selection gate structure and the second selection gate structure, and a lower gate insulating film, a charge storage layer, an upper gate insulating film, and the memory gate electrode are arranged on the well in this order. And a memory gate structure stacked on
The first selection gate electrode and the second selection gate electrode are not formed between a longitudinal end of the one memory cell formation portion and a longitudinal end of the other memory cell formation portion, and A selection gate electrode non-formation region in which a longitudinal end of the one memory cell formation part and a longitudinal end of the other memory cell formation part are connected by a memory gate electrode;
In the memory gate electrode of the one memory cell forming portion and the other memory cell forming portion,
The first select gate electrode is provided on the first side wall side serving as an inner peripheral wall that circulates in a region surrounded by the one memory cell formation portion, the other memory cell formation portion, and the selection gate electrode non-formation region. A non-volatile semiconductor memory device, comprising:
The first selection gate structure is:
A source side select gate structure disposed on the well between the memory gate structure and a source region of the well;
The second select gate structure is
A drain side select gate structure disposed on the well between the memory gate structure and the drain region of the well;
The nonvolatile semiconductor memory device according to claim 1, wherein a source-side selection gate electrode is provided along the first sidewall on the memory gate electrode.
The first selection gate structure is:
A drain side select gate structure disposed on the well between the memory gate structure and the drain region of the well;
The second select gate structure is
A source side select gate structure disposed on the well between the memory gate structure and a source region of the well;
The nonvolatile semiconductor memory device according to claim 1, wherein the memory gate electrode is provided with a drain-side selection gate electrode along the first side wall.
A drain side selection gate line is connected to the drain side selection gate electrode,
The nonvolatile semiconductor memory device according to claim 3, wherein the drain-side selection gate line is provided for each memory cell formation unit.
Between the first selection gate electrode of the one memory cell formation portion and the first selection gate electrode of the other memory cell formation portion, a pin junction structure, a nin junction structure, a pip junction structure, an npn junction structure, 5. The nonvolatile semiconductor memory device according to claim 1, further comprising a selection gate electrode cutting portion that forms a pnp junction structure.
A cap film is provided on the memory gate electrode in the one memory cell formation portion and the other memory cell formation portion,
6. The selection gate electrode non-formation region, wherein the cap film is not formed on the memory gate electrode and a memory gate contact is provided on the memory gate electrode. 2. The nonvolatile semiconductor memory device according to item 1.