WO2017054559A1 - 时钟频率识别的方法和装置 - Google Patents

时钟频率识别的方法和装置 Download PDF

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Publication number
WO2017054559A1
WO2017054559A1 PCT/CN2016/090707 CN2016090707W WO2017054559A1 WO 2017054559 A1 WO2017054559 A1 WO 2017054559A1 CN 2016090707 W CN2016090707 W CN 2016090707W WO 2017054559 A1 WO2017054559 A1 WO 2017054559A1
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Prior art keywords
input signal
signal
pulses
network device
frequency
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PCT/CN2016/090707
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English (en)
French (fr)
Inventor
沈陆怡
许晓东
李亚兵
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中兴通讯股份有限公司
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Publication of WO2017054559A1 publication Critical patent/WO2017054559A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • This application relates to, but is not limited to, the field of terminal equipment technology.
  • Frequency synchronization is the most basic requirement in communication networks.
  • Frequency synchronization also known as clock synchronization, means that the frequency or phase between signals maintains a strictly specific relationship, with corresponding effective moments occurring at the same average rate to maintain all devices in the communication network operating at the same rate.
  • the communication device can cause errors such as bit errors or business interruptions.
  • Synchronous Digital Hierarchy (SDH) or Synchronous Ethernet Equipment is provided in accordance with ITUT G.781 in the International Telecommunication Union Telecommunication Standardization Sector (ITU-T).
  • the G.823 interface standard 2 megahertz (MHZ), 2 megabits per second (Mbit/s) clock interface, ITUT G.8262 puts performance requirements on clock performance such as drift, jitter, etc.
  • IEEE Institute of Electrical and Electronics Engineers
  • the source of 1pps+tod may be a device that conforms to the Chinese mobile format output, or it may be a GPS device.
  • GPS clock devices provide two types of output, one is the same as the GPS clock.
  • the clock uses a satellite signal to tame an Oven Controlled Crystal Oscillator (OCXO) or a cuckoo clock to obtain a high stability frequency.
  • OXO Oven Controlled Crystal Oscillator
  • a cuckoo clock cuckoo clock
  • the most widely used output standard interface of the GPS synchronous clock source device is the 10 MHz clock frequency signal, which serves as the synchronous clock frequency for transmitting high precision time information downstream.
  • the present invention provides a method and apparatus for clock frequency identification to determine the type of clock frequency to which an input signal is received, compared to an interface for adding different input signals to a network device in a related art, or according to different
  • the network device correspondingly modifies the configuration manner in the software, reduces the cost of the network device, and improves the accuracy of discriminating the input signal.
  • a method for clock frequency identification includes:
  • the network device After receiving the input signal, the network device acquires, according to an internal signal generated by the network device, a pulse number of the input signal in a preset period of the internal signal;
  • the network device determines the type of the clock frequency to which the input signal belongs according to the obtained number of pulses of the input signal.
  • the network device After the network device receives the input signal, the network device generates the The internal signal is a reference, and the number of pulses of the input signal is obtained within a preset period of the internal signal, including:
  • the network device After receiving the input signal, the network device starts with the second pulse signal generated inside the network device, and starts detecting the input signal when the first rising edge of the second pulse signal is detected. Pulse counting;
  • the network device stops counting when detecting that the second rising edge of the second pulse signal arrives, and acquires the number of pulses of the input signal in one cycle of the second pulse signal.
  • the network device determines, according to the obtained number of pulses of the input signal, a clock frequency type to which the input signal belongs, including:
  • the input signal is determined to be a clock frequency signal of the global positioning system.
  • a method for clock frequency identification includes:
  • the network device After receiving the input signal, the network device obtains the number of pulses of the internal signal generated by the network device within a preset period of the input signal, based on the input signal;
  • the network device determines the type of the clock frequency to which the input signal belongs according to the obtained number of pulses of the internal signal.
  • the network device acquires, according to the input signal, a number of pulses of an internal signal generated by the network device in a preset period of the input signal, including:
  • the network device After receiving the input signal, the network device starts to pulse the high frequency signal generated inside the network device when detecting that the first rising edge of the input signal arrives based on the input signal. Counting;
  • the network device stops counting when detecting that the second rising edge of the input signal arrives, and obtains the number of pulses of the high frequency signal in one cycle of the input signal.
  • the network device determines, according to the obtained number of pulses of the internal signal, a clock frequency type to which the input signal belongs, including:
  • the input signal is determined to be a clock frequency signal of the global positioning system.
  • the network device acquires, according to the input signal, a number of pulses of an internal signal generated by the network device in a preset period of the input signal, including:
  • the network device After receiving the input signal, the network device starts counting the pulse of the high frequency signal generated inside the network device when detecting that the rising edge of the input signal arrives based on the input signal. ;
  • the network device stops counting when detecting that the falling edge of the input signal arrives, and acquires the number of pulses of the high frequency signal in a half cycle of the input signal.
  • the network device determines, according to the obtained number of pulses of the internal signal, a clock frequency type to which the input signal belongs, including:
  • the input signal is determined to be a clock frequency signal of the global positioning system.
  • a device for recognizing a clock frequency comprising:
  • the pulse number acquisition module is configured to: after receiving the input signal, obtain, according to an internal signal generated by the network device, a pulse number of the input signal in a preset period of the internal signal;
  • the type discriminating module is configured to: determine, according to the number of pulses of the input signal acquired by the pulse number acquiring module, a clock frequency type to which the input signal belongs.
  • the pulse number acquisition module includes:
  • the pulse number counting unit is configured to: after receiving the input signal, start with a second rising edge signal generated inside the network device, and when detecting that the first rising edge of the second pulse signal arrives, start The pulses of the input signal are counted;
  • the pulse number acquisition unit is configured to stop counting when the second rising edge of the second pulse signal is detected, and acquire the number of pulses of the input signal in one cycle of the second pulse signal.
  • the type discriminating module includes:
  • the first determining unit is configured to: when the number of pulses of the input signal is within a first preset number range, determine that the input signal is a clock frequency signal of a synchronous digital system;
  • the second determining unit is configured to: when the number of pulses of the input signal is within a second preset number range, determine that the input signal is a clock frequency signal of the global positioning system.
  • a device for recognizing a clock frequency comprising:
  • Obtaining a module configured to: after receiving the input signal, obtain, according to the input signal, a number of pulses of an internal signal generated by the network device in a preset period of the input signal;
  • the determining module is configured to: determine, according to the number of pulses of the internal signal acquired by the acquiring module, a clock frequency type to which the input signal belongs.
  • the obtaining module includes:
  • a first counting unit configured to: after receiving the input signal, start to generate a high internal to the network device when detecting that the first rising edge of the input signal arrives based on the input signal The pulse of the frequency signal is counted;
  • the first obtaining unit is configured to stop counting when detecting that the second rising edge of the input signal arrives, and acquire the number of pulses of the high frequency signal in one cycle of the input signal.
  • the determining module includes:
  • a third determining unit configured to: when the number of pulses of the high frequency signal is within a third predetermined number range, determining that the input signal is a clock frequency signal of a synchronous digital system;
  • the fourth determining unit is configured to: when the number of pulses of the high frequency signal is within a fourth predetermined number range, determine that the input signal is a clock frequency signal of the global positioning system.
  • the obtaining module includes:
  • a second counting unit configured to: after receiving the input signal, start detecting a high frequency signal generated inside the network device when detecting that a rising edge of the input signal arrives based on the input signal Pulse counts;
  • the second obtaining unit is configured to stop counting when detecting that the falling edge of the input signal arrives, and acquire the number of pulses of the high frequency signal in a half cycle of the input signal.
  • the determining module includes:
  • a fifth determining unit configured to: when the frequency of the input signal calculated by the calculating unit is within a first preset frequency range, determining that the input signal is a clock frequency signal of a synchronous digital system;
  • the sixth determining unit is configured to: when the frequency of the input signal calculated by the calculating unit is within the second preset frequency range, determine that the input signal is a clock frequency signal of the global positioning system.
  • the method and device for identifying a clock frequency obtains a pulse of an input signal in a preset period of an internal signal by using an internal signal generated by the network device as a reference after receiving an input signal by the network device. And determining the type of the clock frequency to which the input signal belongs according to the number of pulses of the input signal, so that the corresponding frequency processing can be performed after the determination; the embodiment of the present invention implements the clock to which the input signal is received.
  • the frequency type is discriminated, so that the clock frequency port can be flexibly and effectively used, and the interface for receiving different input signals by the device is added on the network device compared with the related technology, or the configuration manner is modified according to different network devices in the software. The cost of the network device is reduced, and the accuracy of discriminating the input signal is improved.
  • FIG. 1 is a schematic flowchart of a method for clock frequency identification according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of another method for clock frequency identification according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart diagram of still another method for clock frequency identification according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart diagram of still another method for clock frequency identification according to an embodiment of the present disclosure
  • FIG. 5 is a schematic flowchart of a method for recognizing a clock frequency according to an embodiment of the present disclosure
  • FIG. 6 is a schematic flowchart diagram of a method for recognizing a clock frequency according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of an apparatus for recognizing a clock frequency according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another apparatus for recognizing a clock frequency according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another apparatus for clock frequency identification according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another apparatus for clock frequency identification according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of an apparatus for recognizing a clock frequency according to an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart diagram of a method for clock frequency identification according to an embodiment of the present invention.
  • the method for identifying the clock frequency provided by the embodiment of the embodiment may include the following steps, that is, steps 110 to 120:
  • Step 110 After receiving the input signal, the network device acquires, according to an internal signal generated by the network device, a number of pulses of the input signal in a preset period of the internal signal.
  • the method for identifying the clock frequency can be applied to the SDH clock, the Synchrous Ethernet Clock (SEC) clock, and the Packet Translate network (Packet Translate network) used in the same network device port.
  • PTN Packet Translate network
  • the network device in this embodiment may include a packet transport network (Packet Transport) Network, referred to as: PTN) equipment, optical line terminal (Optical Line Terminal, OLT for short) and ONU.
  • PTN packet transport network
  • OLT optical Line Terminal
  • a programmable logic device such as a Complex Programmable Logic Device (CPLD) or a Field-Programmable Gate Array (FPGA) may be built in the network device of this embodiment.
  • CPLD Complex Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the above input signal is generated by a clock frequency meter, a GPS clock meter, or the like connected to the outside of the network device.
  • the network device uses the internal signal generated by the network device as a reference, and uses the internal signal as a sampling frequency, and the CPLD/FPGA detects the rising edge or falling edge of the internal signal.
  • the internal signal in this embodiment may include, for example, a second pulse signal (ie, 1 pps) generated by a CPLD/FPGA, a high frequency signal generated by a network device system clock or a crystal oscillator, and the like, and the higher the frequency, the higher the accuracy.
  • the preset period may be set to one period or a plurality of periods, or may be flexibly set according to actual conditions, wherein one period may be a distance between two adjacent rising edges or falling edges of the internal signal.
  • Step 120 The network device determines the type of the clock frequency to which the input signal belongs according to the number of pulses of the acquired input signal.
  • the CPLD/FPGA configured in the network device determines the type of the input signal according to the number of pulses of the input signal obtained by the counter counting. For example, if 2048000 pulses are obtained, it is determined that the input signal is an SDH clock frequency of 2.048 MHz, if obtained With 10,000,000 pulses, it is determined that the input signal is a GPS synchronous clock frequency of 10 MHz.
  • the CPLD/FPGA selects the matching processing method according to the type determined by the input signal, and divides the input signal into frequency, that is, converts the input signal into a uniform frequency (ie, fixed frequency) of the network device. Then, the converted unified frequency is sent to the phase locked loop through the hardware link. After the phase locked loop is locked to follow the frequency source, the specific frequency is output according to the user's requirement and distributed to the entire system device for use, thereby completing the frequency synchronization function.
  • the method for identifying the clock frequency obtained by the embodiment of the present invention obtains the number of pulses of the input signal in a preset period of the internal signal by using the internal signal generated by the network device as a reference after the network device receives the input signal. And determining the type of the clock frequency to which the input signal belongs according to the number of pulses of the input signal obtained, so that the corresponding frequency processing can be performed after the discrimination;
  • the network device in the embodiment of the present invention can automatically determine the type of the clock frequency to which the input signal belongs, and implements flexible and effective use of the clock frequency port. Compared with the related art, the device receives different inputs on the network device.
  • the interface of the signal, or the corresponding modification of the configuration in the software according to different network devices reduces the cost of the network device, and improves the accuracy of discriminating the input signal.
  • FIG. 2 is a schematic flowchart diagram of another method for clock frequency identification according to an embodiment of the present invention.
  • the foregoing step 110 may include the following steps, that is, steps 111 to 112:
  • Step 111 After receiving the input signal, the network device starts counting the pulse of the input signal when detecting that the first rising edge of the second pulse signal arrives based on the second pulse signal generated inside the network device;
  • Step 112 The network device detects that the second rising edge of the second pulse signal arrives to stop counting, and acquires the number of pulses of the input signal in one cycle of the second pulse signal.
  • the network device uses the second pulse signal generated by the CPLD/FPGA as a reference in the port processing clock frequency mode, and uses the second pulse signal as the sampling frequency, and the trigger counter pulses the received input signal, for example, the statistical input signal is in a The number of pulses in the second pulse signal period.
  • the practical application may include the following method. Method 1: When the CPLD/FPGA receives the input signal and detects that the first rising edge of the second pulse signal arrives, the trigger counter starts counting the pulse of the input signal, and the second pulse signal When the second rising edge arrives, the counting is stopped, and the number of pulses of the input signal in one cycle of the second pulse signal is acquired.
  • Method 2 When the CPLD/FPGA receives the input signal, the counter starts counting the pulse of the input signal and triggers the clearing on the rising edge of the second pulse signal; since each input signal is from nothing, in the first second The count in the pulse signal may be less than one cycle, so the count value in the first second pulse signal needs to be discarded, that is, when the rising edge of the second second pulse signal arrives, the counter is cleared and the counting is restarted, in the next second.
  • the counting is stopped; then, according to the number of pulses of the input signal, whether the input signal is a 2.048 MHz signal or a 10 MHz signal is discriminated. In addition, it can also be used in multiple cycles of the second pulse signal.
  • the manner of counting the number of pulses of the input signal is not limited in the embodiment of the present invention.
  • the manner of obtaining the number of pulses of the input signal is only a schematic description of the embodiment, and is proposed by those skilled in the art. Other ways of obtaining the number of pulses of the input signal to perform the corresponding operations are all within the scope of protection of the embodiments of the present invention.
  • the second pulse signal is used as the sampling signal, and the number of pulses of the input signal is accurately counted.
  • FIG. 3 is a schematic flowchart diagram of still another method for clock frequency identification according to an embodiment of the present invention.
  • the foregoing step 120 may include the following steps, that is, steps 121 to 122:
  • Step 121 When the number of pulses of the input signal is within a first preset number range, determining that the input signal is a clock frequency signal of the synchronous digital system;
  • Step 122 When the number of pulses of the input signal is within a second preset number range, determine that the input signal is a clock frequency signal of the global positioning system.
  • the CPLD/FPGA determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the input signal.
  • the standard count of 2.048 MHz signal can reach 2048000 pulses in one second pulse period. Due to the frequency offset, the number of pulses obtained by the counter should allow a certain error.
  • the input signal is determined to be an SDH clock frequency of 2.048 MHz, and the first preset number range can be set to 2048000 ⁇ 12. If the number of pulses of the obtained input signal is within the second preset number range, it is determined that the input signal is a GPS clock frequency of 10 MHz, and the second preset number range may be set to 10000000 ⁇ 12.
  • the first preset number range and the second preset number range may be flexibly set according to actual conditions. After determining the type of the clock frequency to which the input signal belongs, the corresponding processing can be performed according to different clock frequencies, and the frequency is divided into frequency points required by the network device.
  • the SDH clock frequency of 2.048 MHz and the GPS clock frequency of 10 MHz share one port, and the user configuration operation is not required, and the frequency identification and selection processing functions are completed by a programmable logic device such as a CPLD/FPGA. . That is, only need to increase the programming content of the CPLD/FPGA, and upgrade the CPLD/FPGA file of the existing network to enable the network device to join the application.
  • the function of supporting the GPS clock frequency not only reduces the cost of the network equipment, but also meets the operation and maintenance requirements of the network operator.
  • FIG. 4 it is a schematic flowchart of another method for clock frequency identification provided by an embodiment of the present invention.
  • the method for identifying the clock frequency provided in this embodiment may include the following steps, that is, steps 210 to 220:
  • Step 210 After receiving the input signal, the network device acquires, according to the input signal, the number of pulses of the internal signal generated by the network device in the preset period of the input signal.
  • the method for identifying the clock frequency can be applied to identify an SDH clock, a synchronous Ethernet clock (SEC), a packet transport network (PTN) clock, a GPS synchronous clock, and the like used in the same network device port.
  • the network device in this embodiment may include a packet transport network (PTN) device, an optical line terminal (OLT), an ONU, and the like.
  • a programmable logic device such as a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) may be built in to complete the function of identifying and selecting a clock frequency.
  • the above input signal is generated by a clock frequency meter, a GPS clock meter, or the like connected to the outside of the network device.
  • the network device uses the input signal as a reference frequency as the reference frequency, and the CPLD/FPGA detects a preset period formed between the rising edge or the falling edge of the input signal. And triggering a built-in counter in the network device to calculate the number of pulses of the internal signal within a preset period of the input signal.
  • the internal signal in this embodiment may include, for example, a second pulse signal (ie, 1 pps) generated by a CPLD/FPGA, a high frequency signal generated by a network device system clock or a crystal oscillator, or the like, a high frequency signal provided by the network device itself, and a frequency thereof.
  • a second pulse signal ie, 1 pps
  • the preset period may be set to one period or a plurality of periods, or may be flexibly set according to actual conditions, wherein one period may be a distance between two adjacent rising edges or falling edges of the input signal.
  • Step 220 The network device determines the type of the clock frequency to which the input signal belongs according to the number of pulses of the obtained internal signal.
  • the CPLD/FPGA configured inside the network device determines the type of the input signal according to the number of pulses of the internal signal obtained by the counter, for example, if 9 pulses are obtained, the input signal is determined. The number is the SDH clock frequency of 2.048 MHz. If one pulse is obtained, it is determined that the input signal is a GPS synchronous clock frequency of 10 MHz.
  • the matching processing mode is selected to divide the input signal, that is, the input signal is converted into a uniform frequency (ie, a fixed frequency) of the network device. Then, the converted unified frequency is sent to the phase locked loop through the hardware link. After the phase locked loop is locked to follow the frequency source, the specific frequency is output according to the user's requirement and distributed to the entire system device for use, thereby completing the frequency synchronization function.
  • the method for identifying a clock frequency obtained by the embodiment of the present invention obtains the number of pulses of an internal signal generated by the network device in a preset period of the input signal after the network device receives the input signal and uses the input signal as a reference. And determining the type of the clock frequency to which the input signal belongs according to the number of pulses of the obtained internal signal, so that the corresponding frequency processing can be performed after the discrimination; the network device in the embodiment of the present invention can receive the input signal to which the input signal belongs.
  • the clock frequency type is automatically discriminated, and the clock frequency port is flexibly and effectively used.
  • the device receives an interface for receiving different input signals on the network device, or correspondingly modifies the configuration according to different network devices in the software. The way, the cost of the network device is reduced, and the accuracy of discriminating the input signal is improved.
  • FIG. 5 is a schematic flowchart diagram of a method for recognizing a clock frequency according to an embodiment of the present invention.
  • the step 210 may include the following steps, that is, steps 211 to 212:
  • Step 211 After receiving the input signal, the network device starts counting the pulse of the high frequency signal generated inside the network device when detecting that the first rising edge of the input signal arrives based on the input signal;
  • Step 212 The network device stops counting when detecting that the second rising edge of the input signal arrives, and acquires the number of pulses of the high frequency signal in one cycle of the input signal.
  • the high frequency signal generated by the system clock or the crystal oscillator in the network device may include 77.76 MHz and 19.44 MHz, and the following will be explained by taking the 19.44 MHz high frequency signal as a reference.
  • Input signal For the reference the input signal is used as the sampling frequency, and the trigger counter counts the pulses of the 19.44 MHz high frequency signal generated by the device system clock or the crystal oscillator.
  • the network device calculates the number of high-frequency signal pulses between two rising edges or falling edges of the input signal in the port processing clock frequency mode; that is, after receiving the input signal, the CPLD/FPGA
  • the counter starts counting the number of pulses of the high frequency signal, and stops counting when the second rising edge of the input signal arrives, and can obtain the pulse of the high frequency signal in one cycle of the input signal.
  • the CPLD/FPGA determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the 19.44 MHz high frequency signal.
  • the pulses of the high frequency signal may be counted in a plurality of cycles of the input signal.
  • the embodiment of the present invention does not limit the manner of acquiring the number of pulses of the high frequency signal, and the manner of obtaining the number of pulses of the high frequency signal is only This is a schematic illustration of the embodiment.
  • the high frequency signal is used as the sampling frequency, and the number of pulses of the input signal is accurately counted.
  • the step 220 may include the following steps, that is, steps 221 to 222:
  • Step 221 When the number of pulses of the high frequency signal is within a third preset number range, determining that the input signal is a clock frequency signal of the synchronous digital system;
  • Step 222 When the number of pulses of the high frequency signal is within a fourth preset number range, determine that the input signal is a clock frequency signal of the global positioning system.
  • the CPLD/FPGA determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the high frequency signal.
  • the input signal when the number of pulses of the high frequency signal is within a third preset number range, the input signal is determined to be an SDH clock frequency of 2.048 MHz, and the third preset number range It can be set to 8 to 10 pulses; when the number of pulses of the high frequency signal is within the fourth preset number range, it is determined that the input signal is a GPS clock frequency of 10 MHz, and the fourth preset number range can be set to 1 to 3 pulses.
  • the third preset number range and the fourth preset number range may be flexibly set according to actual conditions. Alternatively, the intermediate value 5 of the two may be used as a determination limit.
  • the input signal is determined to be The SDH clock frequency of 2.048 MHz; if the number of pulses of the obtained high frequency signal is greater than 5, it is determined that the input signal is a GPS clock frequency of 10 MHz.
  • the CPLD/FPGA divides the input signal into frequency points required by the network device.
  • the SDH clock frequency of 2.048 MHz and the GPS clock frequency of 10 MHz share one port, and the user configuration operation is not required, and the frequency identification and selection processing functions are completed by a programmable logic device such as a CPLD/FPGA. , reducing the cost of network equipment.
  • FIG. 6 is a schematic flowchart diagram of a method for recognizing a clock frequency according to an embodiment of the present invention.
  • the step 210 may include the following steps, that is, steps 213 to 214:
  • Step 213 After receiving the input signal, the network device starts counting the pulse of the high frequency signal generated internally in the network device when detecting that the rising edge of the input signal arrives based on the input signal;
  • Step 214 The network device stops counting when detecting that the falling edge of the input signal arrives, and acquires the number of pulses of the high frequency signal in a half cycle of the input signal.
  • the high frequency signal generated by the system clock or the crystal oscillator in the network device may include 77.76 MHz and 19.44 MHz, and the following will be explained by taking the 19.44 MHz high frequency signal as a reference. Based on the input signal, the input signal is used as the sampling frequency, and the pulse of the 19.44 MHz high frequency signal is counted by the counter.
  • the network device obtains the number of high-frequency signal pulses between the rising edge and the falling edge of the input signal in the port processing clock frequency mode, that is, when the CPLD/FPGA receives the input signal, the input is When the rising edge of the signal comes, the counter starts counting the number of pulses of the high-frequency signal, and stops counting when the falling edge of the input signal arrives, and the number of pulses of the 19.44 MHz high-frequency signal in the half cycle of the input signal can be obtained. Then, the CPLD/FPGA determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the high frequency signal.
  • the pulses of the high frequency signal may be counted in a plurality of cycles of the input signal.
  • the embodiment of the present invention does not limit the manner of acquiring the number of pulses of the high frequency signal, and the manner of obtaining the number of pulses of the high frequency signal. This is only a schematic illustration of the present embodiment.
  • the high frequency signal is used as the sampling frequency, and the frequency of the high frequency signal is also high in accuracy, so that the number of pulses of the input signal is accurately counted.
  • the step 220 may include the following steps, that is, steps 223 to 225:
  • Step 224 When the frequency of the input signal is within the first preset frequency range, determine that the input signal is a clock frequency signal of the synchronous digital system;
  • Step 225 When the frequency of the input signal is within the second preset frequency range, determine that the input signal is a clock frequency signal of the global positioning system.
  • the CPLD/FPGA calculates the frequency of the input signal according to the number of pulses of the high frequency signal, and determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the frequency of the obtained input signal. .
  • the 19.44 MHz high-frequency signal is used as the sampling frequency. Assuming that the sampling frequency is N, the number of pulses obtained by counting is X, and the sampling period is 1/N, and the number of pulses X and sampling are obtained.
  • the calculated frequency should allow for certain errors due to the presence of frequency offsets.
  • the first preset frequency range can be set to 2.048 MHz ⁇ 26 Hz; when the frequency of the input signal is at the second
  • the preset frequency range is within, it is determined that the input signal is an SDH clock frequency of 2.048 MHz, and the second preset frequency range can be set to 10 MHz ⁇ 120 Hz.
  • the first preset frequency range and the second preset frequency range may also be set according to actual conditions, and are not limited and invented.
  • the CPLD/FPGA divides the input signal into frequency points required by the network device according to different frequency processing methods. That is, the programmable logic device can be divided into clock frequencies according to their own requirements according to different frequency processing methods, and provided to the network device to use a synchronous clock source to achieve the ultimate goal of network device clock frequency synchronization.
  • the SDH clock frequency of 2.048 MHz and the GPS clock frequency of 10 MHz share one port, and the user configuration operation is not required, and the frequency identification and selection processing functions are completed by a programmable logic device such as a CPLD/FPGA. . That is, only need to increase the programming content of the CPLD/FPGA, and upgrade the CPLD/FPGA file of the existing network to enable the network device to add the function of supporting the GPS frequency in the application, thereby reducing the cost of the network device.
  • FIG. 7 is a schematic structural diagram of an apparatus for recognizing a clock frequency according to an embodiment of the present invention.
  • the device for identifying the clock frequency provided by this embodiment may include: a pulse number acquisition module 10 and a type discrimination module 20.
  • the pulse number acquisition module 10 is configured to: after receiving the input signal, obtain the number of pulses of the input signal in a preset period of the internal signal based on an internal signal generated by the network device.
  • the device for identifying the clock frequency can be applied to identify an SDH clock, a synchronous Ethernet (SEC) clock, a packet transport network (PTN) clock, a GPS synchronous clock, and the like used in the same network device port.
  • the network device in this embodiment may already include a packet transport network (PTN) device, an optical line terminal (OLT), an ONU, and the like.
  • a programmable logic device such as a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) may be built in to complete the function of identifying and selecting a clock frequency.
  • the above input signal is generated by a clock frequency meter, a GPS clock meter, or the like connected to the outside of the network device.
  • the pulse number acquisition module 10 uses the internal signal generated by the network device as a reference, and uses the internal signal as a sampling frequency, and the CPLD/FPGA detects the rising or falling edge of the internal signal.
  • the preset period is formed, and the pulse number acquisition module 10 is triggered to trigger the built-in counter in the network device to calculate the number of pulses of the input signal within a preset period of the internal signal.
  • the internal signal in this embodiment may include, for example, a second pulse signal (ie, 1 pps) generated by a CPLD/FPGA, and is produced by a network device system clock or a crystal oscillator. The higher the frequency of the generated high-frequency signal, the higher the accuracy.
  • the preset period may be set to one period or a plurality of periods, or may be flexibly set according to actual conditions, wherein one period may be a distance between two adjacent rising edges or falling edges of the internal signal.
  • the type discriminating module 20 is configured to determine the type of the clock frequency to which the input signal belongs according to the number of pulses of the input signal acquired by the pulse number acquisition module 10.
  • the CPLD/FPGA configured inside the network device determines the type of the input signal according to the number of pulses of the input signal obtained by the counter counting. For example, if 2048000 pulses are obtained, it is determined that the input signal is 2.048 MHz SDH.
  • the clock frequency if 10,000,000 pulses are obtained, determines that the input signal is a GPS synchronous clock frequency of 10 MHz.
  • the CPLD/FPGA selects the matching processing method according to the type determined by the input signal, and divides the input signal into frequency, that is, converts the input signal into a uniform frequency (ie, fixed frequency) of the network device. Then, the converted unified frequency is sent to the phase locked loop through the hardware link. After the phase locked loop is locked to follow the frequency source, the specific frequency is output according to the user's requirement and distributed to the entire system device for use, thereby completing the frequency synchronization function.
  • the device for identifying the clock frequency obtained by the embodiment of the present invention obtains the pulse of the input signal in the preset period of the internal signal by using the internal signal generated by the network device as a reference after receiving the input signal by the pulse number acquisition module. And determining, by the type discriminating module, the type of the clock frequency to which the input signal belongs according to the number of pulses of the input signal, so that the corresponding frequency processing can be performed after the discriminating; the network device in the embodiment of the invention can receive Automatically discriminating the type of clock frequency to which the input signal belongs, and implementing flexible and efficient use of the clock frequency port, compared with the related art, adding an interface for receiving different input signals to the device on the network device, or according to different network devices The corresponding modification of the configuration in the software reduces the cost of the network device and improves the accuracy of discriminating the input signal.
  • FIG. 8 is a schematic structural diagram of another apparatus for recognizing a clock frequency according to an embodiment of the present invention.
  • the pulse number acquisition module 10 may include:
  • the pulse number counting unit 11 is configured to: after receiving the input signal, start to pulse the input signal when the first rising edge of the second pulse signal is detected, based on the second pulse signal generated inside the network device. Counting;
  • the pulse number acquisition unit 12 is configured to stop counting when the second rising edge of the second pulse signal is detected, and obtain the number of pulses of the input signal in one cycle of the second pulse signal.
  • the network device uses the second pulse signal generated by the CPLD/FPGA as a reference in the port processing clock frequency mode, and uses the second pulse signal as the sampling frequency, and the pulse number counting unit 11 triggers the counter to pulse count the received input signal. For example, the number of pulses of the input signal in one second pulse signal period is counted.
  • the practical application may include the following method. Method 1: When the CPLD/FPGA receives the input signal and detects that the first rising edge of the second pulse signal arrives, the pulse number counting unit 11 triggers the counter to start the pulse of the input signal. The counting is performed, and the counting by the pulse number acquiring unit 12 stops when the second rising edge of the second pulse signal arrives, and the number of pulses of the input signal in one cycle of the second pulse signal is acquired.
  • Method 2 After the CPLD/FPGA receives the input signal, the pulse counting unit 11 triggers the counter to start counting the pulse of the input signal, and the pulse number acquiring unit 12 triggers the clearing by the rising edge of the second pulse signal; Since each input signal is from scratch, the count in the first second pulse signal may be less than one cycle, so the count value in the first second pulse signal needs to be discarded, that is, on the rising edge of the second second pulse signal.
  • the counter is cleared, the counting is restarted, and the counting is stopped when the rising edge of the next second pulse signal arrives; then, according to the number of pulses of the input signal, whether the input signal is a 2.048 MHz signal or a 10 MHz signal is discriminated.
  • the pulse of the input signal may be counted in a plurality of cycles of the second pulse signal.
  • the embodiment of the present invention does not limit the manner of acquiring the number of pulses of the input signal, and the method for obtaining the number of pulses of the input signal is only For the schematic description of the embodiments, other ways of obtaining the number of pulses of the input signal to perform the corresponding operations proposed by those skilled in the art are within the protection scope of the embodiments of the present invention.
  • the second pulse signal is used as the sampling signal, and the number of pulses of the input signal is accurately counted.
  • the type discriminating module 20 may include:
  • the first determining unit 21 is configured to: when the number of pulses of the input signal is within a first preset number range, determine that the input signal is a clock frequency signal of the synchronous digital system;
  • the second determining unit 22 is configured to determine that the input signal is a clock frequency signal of the global positioning system when the number of pulses of the input signal is within a second predetermined number range.
  • the type discriminating module 20 determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the input signal.
  • the standard count of 2.048 MHz signal can reach 2048000 pulses in one second pulse period. Due to the frequency offset, the number of pulses obtained by the counter should allow a certain error.
  • the input signal is determined to be an SDH clock frequency of 2.048 MHz, and the first preset number range can be set to 2048000 ⁇ 12. If the number of pulses of the obtained input signal is within the second preset number range, it is determined that the input signal is a GPS clock frequency of 10 MHz, and the second preset number range may be set to 10000000 ⁇ 12.
  • the first preset number range and the second preset number range may be flexibly set according to actual conditions. After determining the type of the clock frequency to which the input signal belongs, the corresponding processing can be performed according to different clock frequencies, and the frequency is divided into frequency points required by the network device.
  • the SDH clock frequency of 2.048 MHz and the GPS clock frequency of 10 MHz share one port, and the user configuration operation is not required, and the frequency identification and selection processing functions are completed by a programmable logic device such as a CPLD/FPGA. . That is, only need to increase the programming content of the CPLD/FPGA, and upgrading the CPLD/FPGA file of the existing network can enable the network device to add the function of supporting the GPS clock frequency in the application, thereby reducing the cost of the network device and the network operator. Operation and maintenance requirements.
  • FIG. 9 is a schematic structural diagram of another apparatus for clock frequency identification according to an embodiment of the present invention.
  • the device for identifying the clock frequency provided by this embodiment may include: an obtaining module 30 and a discriminating module 40.
  • the obtaining module 30 is configured to: after receiving the input signal, obtain the number of pulses of the internal signal generated by the network device in the preset period of the input signal based on the input signal.
  • the device for identifying the clock frequency can be applied to identify the SDH clock, the synchronous Ethernet clock (SEC), the packet transport network (PTN) clock, the GPS synchronous clock, and the like used in the same network device port.
  • the network device in this embodiment may include a packet transport network (PTN) device, Optical line terminals (OLT) and ONUs.
  • a programmable logic device such as a complex programmable logic device (CPLD) or a field programmable gate array (FPGA) may be built in to complete the function of identifying and selecting a clock frequency.
  • the above input signal is generated by a clock frequency meter, a GPS clock meter, or the like connected to the outside of the network device.
  • the network device uses the input signal as a reference frequency as the reference frequency, and the CPLD/FPGA detects a preset period formed between the rising edge or the falling edge of the input signal.
  • the acquisition module 30 triggers a built-in counter in the network device to calculate the number of pulses of the internal signal within a preset period of the input signal.
  • the internal signal in this embodiment may include, for example, a second pulse signal (ie, 1 pps) generated by a CPLD/FPGA, a high frequency signal generated by a network device system clock or a crystal oscillator, or the like, a high frequency signal provided by the network device itself, and a frequency thereof.
  • a second pulse signal ie, 1 pps
  • the preset period may be set to one period or a plurality of periods, or may be flexibly set according to actual conditions, wherein one period may be a distance between two adjacent rising edges or falling edges of the input signal.
  • the determining module 40 is configured to determine the type of the clock frequency to which the input signal belongs according to the number of pulses of the internal signal acquired by the obtaining module 30.
  • the CPLD/FPGA configured inside the network device determines the type of the input signal according to the number of pulses of the internal signal obtained by the counter counting. For example, if 9 pulses are obtained, it is determined that the input signal is an SDH clock of 2.048 MHz. Frequency, if one pulse is obtained, it is determined that the input signal is a GPS synchronous clock frequency of 10 MHz.
  • the discriminating module 40 determines the type according to the input signal
  • the CPLD/FPGA selects a matching processing manner to divide the input signal, that is, converts the input signal into a uniform frequency (ie, a fixed frequency) of the network device. Then, the converted unified frequency is sent to the phase locked loop through the hardware link. After the phase locked loop is locked to follow the frequency source, the specific frequency is output according to the user's requirement and distributed to the entire system device for use, thereby completing the frequency synchronization function.
  • the device for identifying the clock frequency obtained by the embodiment of the present invention obtains the number of pulses of the internal signal generated by the network device in the preset period of the input signal after the input module receives the input signal, and the acquisition module uses the input signal as a reference. And determining, by the discriminating module, the type of the clock frequency to which the input signal belongs according to the number of pulses of the obtained internal signal, so that the corresponding frequency processing can be performed after the discriminating; the network device in the embodiment of the invention can receive the input signal
  • the clock frequency type is automatically determined, which enables flexible and efficient use of the clock frequency port.
  • the interface for receiving different input signals on the network device is added, or the configuration of the network device is modified according to different network devices, thereby reducing the cost of the network device and improving the accuracy of discriminating the input signal.
  • FIG. 10 is a schematic structural diagram of another apparatus for clock frequency identification according to an embodiment of the present invention.
  • the acquiring module 30 may include:
  • the first counting unit 31 is configured to: after receiving the input signal, start detecting the pulse of the high frequency signal generated inside the network device when the first rising edge of the input signal is detected based on the input signal count;
  • the first obtaining unit 32 is configured to stop counting when the second rising edge of the input signal is detected, and acquire the number of pulses of the high frequency signal in one cycle of the input signal.
  • the high frequency signal generated by the system clock or the crystal oscillator in the network device may include 77.76 MHz and 19.44 MHz, and the following will be explained by taking the 19.44 MHz high frequency signal as a reference. Taking the input signal as a reference and using the input signal as the sampling frequency, the acquisition module 30 triggers the counter to count the pulses of the 19.44 MHz high frequency signal generated by the device system clock or the crystal oscillator.
  • the acquiring module 30 triggers the counter to calculate the number of high-frequency signal pulses between two adjacent rising edges or falling edges of the input signal; that is, when the first counting unit 31 After receiving the input signal, the counter starts counting the number of pulses of the high frequency signal when the first rising edge of the input signal arrives, and the first obtaining unit 32 stops counting when the second rising edge of the input signal arrives, and can be obtained.
  • the number of pulses of the high frequency signal during one cycle of the input signal.
  • the CPLD/FPGA determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the 19.44 MHz high frequency signal.
  • the pulses of the high frequency signal may be counted in a plurality of cycles of the input signal.
  • the embodiment of the present invention does not limit the manner of acquiring the number of pulses of the high frequency signal, and the manner of obtaining the number of pulses of the high frequency signal is only This is a schematic illustration of the embodiment.
  • the high frequency signal is used as the sampling frequency, and the number of pulses of the input signal is accurately counted.
  • the determining module 40 may include:
  • the third determining unit 41 is configured to: when the number of pulses of the high frequency signal is within a third preset number range, determine that the input signal is a clock frequency signal of the synchronous digital system;
  • the fourth determining unit 42 is configured to determine that the input signal is a clock frequency signal of the global positioning system when the number of pulses of the high frequency signal is within a fourth predetermined number range.
  • the determination module 40 determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the high frequency signal.
  • the input signal when the number of pulses of the high frequency signal is within a third preset number range, the input signal is determined to be an SDH clock frequency of 2.048 MHz, and the third preset number range It can be set to 8 to 10 pulses; when the number of pulses of the high frequency signal is within the fourth preset number range, it is determined that the input signal is a GPS clock frequency of 10 MHz, and the fourth preset number range can be set to 1 to 3 pulses.
  • the third preset number range and the fourth preset number range may be flexibly set according to actual conditions. Alternatively, the intermediate value 5 of the two may be used as a determination limit.
  • the CPLD/FPGA divides the input signal into frequency points required by the network device.
  • the SDH clock frequency of 2.048 MHz and the GPS clock frequency of 10 MHz share one port, and the user configuration operation is not required, and the frequency identification and selection processing functions are completed by a programmable logic device such as a CPLD/FPGA. , reducing the cost of network equipment.
  • FIG. 11 is a schematic structural diagram of an apparatus for recognizing a clock frequency according to an embodiment of the present invention.
  • the acquiring module 30 may include:
  • the second counting unit 33 is configured to: after receiving the input signal, based on the input signal, When it detects that the rising edge of the input signal arrives, it starts counting pulses of the high frequency signal generated inside the network device;
  • the second obtaining unit 34 is configured to stop counting when detecting that the falling edge of the input signal arrives, and acquire the number of pulses of the high frequency signal in a half cycle of the input signal.
  • the high frequency signal generated by the system clock or the crystal oscillator in the network device may include 77.76 MHz and 19.44 MHz, and the following will be explained by taking the 19.44 MHz high frequency point signal as a reference. Taking the input signal as a reference, the input signal is taken as the sampling frequency, and the counter is triggered by the acquisition module 30 to count the pulses of the 19.44 MHz high frequency signal.
  • the network device obtains the number of high-frequency signal pulses between the rising edge and the falling edge of the input signal by the second counting unit 33 in the mode of the port processing clock frequency, that is, when the CPLD/FPGA receives After the input signal, the counter starts counting the number of pulses of the high frequency signal when the rising edge of the input signal comes, and the second acquisition unit 34 stops counting when the falling edge of the input signal arrives, and can obtain the half cycle of the input signal.
  • the number of pulses in the 19.44 MHz high frequency signal Then, the CPLD/FPGA determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the number of pulses of the high frequency signal.
  • the pulses of the high frequency signal may be counted in a plurality of cycles of the input signal.
  • the embodiment of the invention does not limit the number of pulses of the high frequency signal, and the method of obtaining the number of pulses of the high frequency signal is only A schematic illustration of this embodiment.
  • the high frequency signal is used as the sampling frequency, and the frequency of the high frequency signal is also high in accuracy, so that the number of pulses of the input signal is accurately counted.
  • the determining module 40 may include:
  • the fifth determining unit 44 is configured to: when the frequency of the input signal calculated by the calculating unit 43 is within the first preset frequency range, determine that the input signal is a clock frequency signal of the synchronous digital system;
  • the sixth determining unit 45 is configured to: when the frequency of the input signal calculated by the calculating unit 43 is When the second preset frequency range is within, the input signal is determined to be a clock frequency signal of the global positioning system.
  • the calculating unit 43 calculates the frequency of the input signal according to the number of pulses of the high frequency signal, and determines whether the input signal is a 2.048 MHz signal or a 10 MHz signal according to the frequency of the obtained input signal. .
  • the 19.44 MHz high-frequency signal is used as the sampling frequency. Assuming that the sampling frequency is N, the number of pulses obtained by counting is X, and the sampling period is 1/N, and the number of pulses X and sampling are obtained.
  • the calculated frequency should allow for certain errors due to the presence of frequency offsets.
  • the first preset frequency range can be set to 2.048 MHz ⁇ 26 Hz; when the frequency of the input signal is at the second
  • the preset frequency range is within, it is determined that the input signal is an SDH clock frequency of 2.048 MHz, and the second preset frequency range can be set to 10 MHz ⁇ 120 Hz.
  • the first preset frequency range and the second preset frequency range may also be set according to actual conditions, and are not limited and invented.
  • the CPLD/FPGA divides the input signal into the frequency points required by the network device according to the processing manner of different frequencies. That is, the programmable logic device can be divided into clock frequencies according to their own requirements according to different frequency processing methods, and provided to the network device to use a synchronous clock source to achieve the ultimate goal of network device clock frequency synchronization.
  • the SDH clock frequency of 2.048 MHz and the GPS clock frequency of 10 MHz share one port, and the user configuration operation is not required, and the frequency identification and selection processing functions are completed by a programmable logic device such as a CPLD/FPGA. . That is, only need to increase the programming content of the CPLD/FPGA, and upgrade the CPLD/FPGA file of the existing network to enable the network device to add the function of supporting the GPS frequency in the application, thereby reducing the cost of the network device.
  • all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
  • the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
  • the device/function module/functional unit in the above embodiment When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium.
  • the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • the network device after the network device receives the input signal, using the internal signal generated by the network device as a reference, acquiring the number of pulses of the input signal in a preset period of the internal signal, and according to the acquired input signal
  • the number of pulses is determined by the type of the clock frequency to which the input signal belongs, so that the corresponding frequency processing can be performed after the discriminating; the embodiment of the invention realizes discriminating the type of the clock frequency to which the input signal belongs, so that the clock frequency can be
  • the port is flexible and effective to use. Compared with the related technology, the device adds an interface for receiving different input signals on the network device, or according to different network devices in the software to modify the configuration manner, thereby reducing the cost of the network device and improving the cost. The accuracy of discriminating the input signal.

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Abstract

一种时钟频率识别的方法和装置，其中，该方法包括：网络设备在接收到输入信号后，以该网络设备所产生的内部信号为基准，获取在该内部信号的预设周期内输入信号的脉冲个数；网络设备根据获取的输入信号的脉冲个数对该输入信号所属的时钟频率类型进行判别。

Description

时钟频率识别的方法和装置 技术领域
本申请涉及但不限于终端设备技术领域。
背景技术
在通信网络中，频率同步是最基本的要求。频率同步也称时钟同步，指信号间的频率或相位保持某种严格的特定关系，其相对应的有效瞬间以同一平均速率出现，以维持通信网络中所有设备能以同一速率运行。一旦时钟不同步，通信设备会产生误码或业务时断时续等问题。同步数字体系(Synchronous Digital Hierarchy，简称为：SDH)或同步以太网设备按照国际电信联盟电信标准分局(International Telecommunication Union Telecommunication Standardization Sector，简称为：ITU-T)中的ITUT G.781都提供满足ITUT G.823接口标准的2兆赫兹(MHZ)、2每秒兆比特(Mbit/s)时钟接口，ITUT G.8262对时钟的性能如漂移、抖动等提出了性能要求。
随着无线网络的发展，网络中的组网模式越来越灵活。有线网络下光网络单元(Optical Network Unit，简称为：ONU)接移动基站将是未来一种应用趋势。中国移动为了不受限于美国的全球定位系统(Global Positioning System，简称为：GPS)，提出了两种替代方案。一种是通过有线传输网络传送精准的时间信号，另一种是通过我国自主研发的北斗卫星提供时间信号源，使用GPS与北斗卫星双模授时，互为主备。从时间的来源和传输两方面相结合摆脱对美国GPS的依赖。有线网络中传输时间的方式在相关技术中有两种，一种是使用电气和电子工程师协会(Institute of Electrical and Electronics Engineers，简称为：IEEE)定义的IEEE 1588V2协议通过报文完成时间同步，另一种是通过秒脉冲加天时间的透传方式，即每秒脉冲(pulses per second，1pps)+tod(Time of Day)。无论哪种方式，要达到无线移动网络对于时间高精度的要求都离不开时钟频率的同步。
在1pps+tod的透传组网中，1pps+tod的来源可能是符合中国移动格式输出的设备，也可以是GPS设备。GPS时钟设备提供两类输出，一类是GPS时钟同 步，该时钟利用卫星信号驯服恒温晶体振荡器(Oven Controlled Crystal Oscillator，简称为：OCXO)或者铷钟获得高稳定度频率。另一类是通过时钟同步后，本地恢复得到更稳定的时标信息，包括1pps+tod信息。GPS时钟设备除了采用GPS设备外，还可选择北斗星系统，性能更高。GPS同步时钟源设备的输出标准接口中应用最广的是10MHZ时钟频率信号，该信号作为下游传递高精度时间信息的同步时钟频率。
相关技术在网络设备中，都支持2MHZ频率(例如2.048MHZ的SDH时钟频率)接口，增加了时间同步后，10MHZ频率(例如10MHZ的GPS时钟频率)的应用增加，而面临以下问题：(1)在相关技术中的设备上增加器件，提供接受不同时钟频率的接口，此时设备硬件需要更换，布网人工替换成本提高。(2)在相关技术中的软件中增加配置，根据外部不同设备连接，相应修改配置；用户需要知道设备外部连接的确切信号频率，一旦配置错误，则无法正确识别信号，造成时钟频率同步失败，时间传递精度不达标，影响下游无线网络通信，引起手机用户通话掉线等问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本文提供一种时钟频率识别的方法和装置，以实现对接收到输入信号所属的时钟频率类型进行判别，相比于相关技术中在网络设备上增加器件接收不同输入信号的接口，或者根据不同的网络设备在软件中相应修改配置的方式，降低了网络设备的成本，并且提高了对输入信号进行判别的准确性。
一种时钟频率识别的方法，包括：
网络设备在接收到输入信号后，以所述网络设备所产生的内部信号为基准，获取在所述内部信号的预设周期内所述输入信号的脉冲个数；
所述网络设备根据获取的所述输入信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
可选地，所述网络设备在接收到输入信号后，以所述网络设备所产生的 内部信号为基准，获取在所述内部信号的预设周期内所述输入信号的脉冲个数，包括：
所述网络设备在接收到所述输入信号后，以所述网络设备内部产生的秒脉冲信号为基准，在检测到所述秒脉冲信号的第一上升沿到达时，开始对所述输入信号的脉冲进行计数；
所述网络设备在检测到所述秒脉冲信号的第二上升沿到达时停止计数，获取在所述秒脉冲信号的一个周期内所述输入信号的脉冲个数。
可选地，所述网络设备根据获取的所述输入信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别，包括：
当所述输入信号的脉冲个数在第一预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
当所述输入信号的脉冲个数在第二预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
一种时钟频率识别的方法，包括：
网络设备在接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内所述网络设备所产生的内部信号的脉冲个数；
所述网络设备根据获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
可选地，所述网络设备在接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内所述网络设备所产生的内部信号的脉冲个数，包括：
所述网络设备在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的第一上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
所述网络设备在检测到所述输入信号的第二上升沿到达时停止计数，得获取在所述输入信号的一个周期内所述高频信号的脉冲个数。
可选地，所述网络设备根据获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别，包括：
当所述高频信号的脉冲个数在第三预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
当所述高频信号的脉冲个数在第四预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
可选地，所述网络设备在接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内所述网络设备所产生的内部信号的脉冲个数，包括：
所述网络设备在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
所述网络设备在检测到所述输入信号的下降沿到达时停止计数，获取在所述输入信号的半个周期内所述高频信号的脉冲个数。
可选地，所述网络设备根据获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别，包括：
所述网络设备根据所述高频信号的频率N，以及所述在所述输入信号的半个周期内所述高频信号的脉冲个数X，计算所述输入信号的频率R，其中，R＝N/(2*X)；
当所述输入信号的频率在第一预设频率范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
当所述输入信号的频率在第二预设频率范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
一种时钟频率识别的装置，包括：
脉冲个数获取模块，设置为：在接收到输入信号后，以网络设备所产生的内部信号为基准，获取在所述内部信号的预设周期内所述输入信号的脉冲个数；
类型判别模块，设置为：根据所述脉冲个数获取模块获取的所述输入信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
可选地，所述脉冲个数获取模块包括：
脉冲个数计数单元，设置为：在接收到所述输入信号后，以所述网络设备内部产生的秒脉冲信号为基准，在检测到所述秒脉冲信号的第一上升沿到达时，开始对所述输入信号的脉冲进行计数；
脉冲个数获取单元，设置为：在检测到所述秒脉冲信号的第二上升沿到达时停止计数，获取在所述秒脉冲信号的一个周期内所述输入信号的脉冲个数。
可选地，所述类型判别模块包括：
第一判定单元，设置为：当所述输入信号的脉冲个数在第一预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
第二判定单元，设置为：当所述输入信号的脉冲个数在第二预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
一种时钟频率识别的装置，包括：
获取模块，设置为：在接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内网络设备所产生的内部信号的脉冲个数；
判别模块，设置为：根据所述获取模块获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
可选地，所述获取模块包括：
第一计数单元，设置为：在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的第一上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
第一获取单元，设置为：在检测到所述输入信号的第二上升沿到达时停止计数，获取在所述输入信号的一个周期内所述高频信号的脉冲个数。
可选地，所述判别模块包括：
第三判定单元，设置为：当所述高频信号的脉冲个数在第三预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
第四判定单元，设置为：当所述高频信号的脉冲个数在第四预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
可选地，所述获取模块包括：
第二计数单元，设置为：在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
第二获取单元，设置为：在检测到所述输入信号的下降沿到达时停止计数，获取在所述输入信号的半个周期内所述高频信号的脉冲个数。
可选地，所述判别模块包括：
计算单元，设置为：根据所述高频信号的频率N，以及所述在所述输入信号的半个周期内所述高频信号的脉冲个数X，计算所述输入信号的频率R，其中，R＝N/(2*X)；
第五判定单元，设置为：当所述计算单元计算得到的所述输入信号的频率在第一预设频率范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
第六判定单元，设置为：当所述计算单元计算得到的所述输入信号的频率在第二预设频率范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
本发明实施例提供的时钟频率识别的方法和装置，通过在网络设备在接收到输入信号后，以该网络设备所产生的内部信号为基准，获取在内部信号的预设周期内输入信号的脉冲个数，并根据获取的输入信号的脉冲个数该对输入信号所属的时钟频率类型进行判别，从而可以在判别后执行相应的频率处理；本发明实施例实现了对接收到输入信号所属的时钟频率类型进行判别，从而可以对时钟频率端口进行灵活及有效使用，相比于相关技术在网络设备上增加器件接收不同输入信号的接口，或者根据不同的网络设备在软件中相应修改配置的方式，降低了网络设备的成本，并且提高了对输入信号进行判别的准确性。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1为本发明实施例提供的一种时钟频率识别的方法的流程示意图；
图2为本发明实施例提供的另一种时钟频率识别的方法的流程示意图；
图3为本发明实施例提供的又一种时钟频率识别的方法的流程示意图；
图4为本发明实施例提供的再一种时钟频率识别的方法的流程示意图；
图5为本发明实施例提供的还一种时钟频率识别的方法的流程示意图；
图6为本发明实施例提供的还一种时钟频率识别的方法的流程示意图；
图7为本发明实施例提供的一种时钟频率识别的装置的结构示意图；
图8为本发明实施例提供的另一种时钟频率识别的装置的结构示意图；
图9为本发明实施例提供的又一种时钟频率识别的装置的结构示意图；
图10为本发明实施例提供的再一种时钟频率识别的装置的结构示意图；
图11为本发明实施例提供的还一种时钟频率识别的装置的结构示意图。
本发明的实施方式
下文中将结合附图对本发明的实施方式进行详细说明。需要说明的是，在不冲突的情况下，本文中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸根据一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
如图1所示，为本发明实施例提供的一种时钟频率识别的方法的流程示意图。本实施例实施例提供的时钟频率识别的方法可以包括如下步骤，即步骤110～步骤120：
步骤110、网络设备在接收到输入信号后，以该网络设备所产生的内部信号为基准，获取在该内部信号的预设周期内输入信号的脉冲个数。
本实施例中，时钟频率识别的方法可应用于在同一网络设备端口中使用的SDH时钟、同步以太网(Synchrous Ethernet Clock，简称为：SEC)时钟、包传送网(Packet Translate network，简称为：PTN)时钟、GPS同步时钟等进行识别。本实施例中的网络设备可以包括分组传送网(Packet Transport  Network，简称为：PTN)设备、光线路终端(Optical Line Terminal，简称为：OLT)和ONU等。
本实施例的网络设备中可以内置有复杂可编程逻辑器件(Complex Programmable Logic Device，简称为：CPLD)、或者现场可编程门阵列(Field－Programmable Gate Array，简称为：FPGA)等可编程逻辑器件完成对时钟频率的识别及选择处理功能。上述输入信号是与网络设备外部连接的时钟频率仪表、GPS时钟仪表等产生的。在实际应用中，网络设备在接收到输入信号后，以该网络设备所产生的内部信号为基准，将该内部信号作为采样频率，CPLD/FPGA检测内部信号到来的上升沿或者下降沿之间形成的预设周期，并触发网络设备中内置计数器计算在该内部信号的预设周期内，输入信号的脉冲个数。本实施例中的内部信号例如可以包括以CPLD/FPGA所产生的秒脉冲信号(即1pps)、由网络设备系统钟或者晶振产生的高频信号等，其频率越高精度也越高。上述预设周期可设置为一个周期或者多个周期，也可根据实际情况而灵活设置，其中，一个周期可为内部信号两个相邻的上升沿或者下降沿之间的距离。
步骤120、网络设备根据获取的输入信号的脉冲个数对该输入信号所属的时钟频率类型进行判别。
在网络设备内部配置的CPLD/FPGA根据计数器计数得到的输入信号的脉冲个数，确定输入信号所属的类型，例如，若得到2048000个脉冲，则判定输入信号是2.048MHZ的SDH时钟频率，若得到10000000个脉冲，则判定输入信号是10MHZ的GPS同步时钟频率。CPLD/FPGA根据输入信号所确定的类型，选择匹配的处理方式对输入信号进行分频处理，即将输入信号转换为该网络设备的统一频率(即固定频率)。然后将转换后的统一频率经过硬件链路送至锁相环，锁相环锁定跟随频率源后，将按照用户需求输出特定频率并分发给整个系统设备使用，从而完成频率同步的功能。
本发明实施例提供的时钟频率识别的方法，通过在网络设备在接收到输入信号后，以该网络设备所产生的内部信号为基准，获取在内部信号的预设周期内输入信号的脉冲个数，并根据获取的输入信号的脉冲个数该对输入信号所属的时钟频率类型进行判别，从而可以在判别后执行相应的频率处理； 本发明实施例中的网络设备能够对接收到输入信号所属的时钟频率类型进行自动判别，实现了对时钟频率端口进行灵活及有效使用，相比于相关技术中在网络设备上增加器件接收不同输入信号的接口，或者根据不同的网络设备在软件中相应修改配置的方式，降低了网络设备的成本，并且提高了对输入信号进行判别的准确性。
可选地，图2为本发明实施例提供的另一种时钟频率识别的方法的流程示意图。在图1所示实施例的基础上，本实施例提供的时钟频率识别的方法中，上述步骤110可以包括如下步骤，即步骤111～步骤112：
步骤111、网络设备在接收到输入信号后，以该网络设备内部产生的秒脉冲信号为基准，在检测到该秒脉冲信号的第一上升沿到达时，开始对输入信号的脉冲进行计数；
步骤112、网络设备检测到该秒脉冲信号的第二上升沿到达时停止计数，获取在该秒脉冲信号的一个周期内输入信号的脉冲个数。
本实施例中将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS同步时钟频率共用一个端口为例进行详细说明。
网络设备在端口处理时钟频率的模式下，将CPLD/FPGA产生的秒脉冲信号为基准，将该秒脉冲信号作为采样频率，触发计数器对接收的输入信号进行脉冲计数，例如，统计输入信号在一个秒脉冲信号周期内的脉冲个数。实际应用中可以包括以下方法，方法一：当CPLD/FPGA接收到输入信号，并检测到秒脉冲信号的第一个上升沿到达时，触发计数器开始对输入信号的脉冲进行计数，在秒脉冲信号的第二个上升沿到达时停止计数，获取在秒脉冲信号的一个周期内输入信号的脉冲个数。方法二：当CPLD/FPGA接收到输入信号后，计数器开始对输入信号的脉冲进行计数，并按秒脉冲信号的上升沿触发清零；由于每次输入信号从无到有，在第一个秒脉冲信号内的计数可能不满一个周期，因此需要将第一个秒脉冲信号内的计数值丢弃，即在第二个秒脉冲信号上升沿到达时，将计数器清零，重新开始计数，在下一个秒脉冲信号的上升沿到达时停止计数；然后按照输入信号的脉冲个数，判别该输入信号是2.048MHZ信号还是10MHZ信号。另外，也可以在秒脉冲信号的多个周期 内对输入信号的脉冲进行计数，本发明实施例不限制获取输入信号的脉冲个数的方式，上述获取输入信号的脉冲个数的方式仅为本实施方式的示意性说明，本领域技术人员提出的其它获取输入信号的脉冲个数以执行相应的操作的方式，均在本发明实施例的保护范围内。本发明实施例以秒脉冲信号作为采样信号，实现了对输入信号的脉冲个数进行准确计数。
可选地，图3为本发明实施例提供的又一种时钟频率识别的方法的流程示意图。在图1所示实施例的基础上，本实施例提供的时钟频率识别的方法中，上述步骤120可以包括如下步骤，即步骤121～步骤122：
步骤121、当输入信号的脉冲个数在第一预设个数范围内时，判定该输入信号为同步数字体系的时钟频率信号；
步骤122、当输入信号的脉冲个数在第二预设个数范围内时，判定该输入信号为全球定位系统的时钟频率信号。
本实施例将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口为例进行详细说明。在上述得到输入信号的脉冲个数后，CPLD/FPGA按照输入信号的脉冲个数判别该输入信号是2.048MHZ信号还是10MHZ信号。在一个秒脉冲周期内2.048MHZ信号标准计数可达到2048000个脉冲，由于频偏的存在，计数器得到的脉冲个数应当允许有一定误差。在实际应用中，假设得到输入信号的脉冲个数在第一预设个数范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第一预设个数范围可设置为2048000±12个；假设得到的输入信号的脉冲个数在第二预设个数范围内时，则判定输入信号为10MHZ的GPS时钟频率，该第二预设个数范围可设置为10000000±12个。上述第一预设个数范围及第二预设个数范围可根据实际情况而灵活设置。在确定输入信号所属的时钟频率类型后，可根据不同时钟频率进行相应处理，将其分频成网络设备需要的频点。
本实施例在同一个网络设备中，2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口，且不需要增加用户配置操作，通过CPLD/FPGA等可编程逻辑器件完成频率识别和选择处理功能。即只需要增加CPLD/FPGA的编程内容，升级现网的CPLD/FPGA文件就能使网络设备达到在应用中加入 支持GPS时钟频率的功能，既降低了网络设备的成本，也符合网络运营商的运维要求。
可选地，如图4所示，为本发明实施例提供的再一种时钟频率识别的方法的流程示意图。本实施例提供的时钟频率识别的方法可以包括如下步骤，即步骤210～步骤220：
步骤210、网络设备在接收到输入信号后，以该输入信号为基准，获取在该输入信号的预设周期内网络设备所产生的内部信号的脉冲个数。
本实施例中，时钟频率识别的方法可应用于在同一网络设备端口中使用的SDH时钟、同步以太网时钟(SEC)、包传送网(PTN)时钟、GPS同步时钟等进行识别。本实施例中的网络设备可以包括分组传送网(PTN)设备、光线路终端(OLT)和ONU等。
本实施例的网络设备中可以内置有复杂可编程逻辑器件(CPLD)、或者现场可编程门阵列(FPGA)等可编程逻辑器件完成对时钟频率的识别及选择处理功能。上述输入信号是与网络设备外部连接的时钟频率仪表、GPS时钟仪表等产生的。在实际应用中，网络设备在接收到输入信号后，以输入信号为基准，将该输入信号作为采样频率，CPLD/FPGA检测该输入信号到来的上升沿或者下降沿之间形成的预设周期，并触发网络设备中内置计数器计算在该输入信号的预设周期内，内部信号的脉冲个数。本实施例中的内部信号例如可以包括以CPLD/FPGA所产生的秒脉冲信号(即1pps)、由网络设备系统钟或者晶振产生的高频信号等由网络设备本身提供的高频信号，其频率越高精度也越高。上述预设周期可设置为一个周期或者多个周期，也可根据实际情况而灵活设置，其中，一个周期可为输入信号两个相邻的上升沿或者下降沿之间的距离。
步骤220、网络设备根据获取的内部信号的脉冲个数对输入信号所属的时钟频率类型进行判别。
在网络设备内部配置的CPLD/FPGA根据计数器计数得到的内部信号的脉冲个数，确定输入信号所属的类型，例如，若得到9个脉冲，则判定输入信 号是2.048MHZ的SDH时钟频率，若得到1个脉冲，则判定输入信号是10MHZ的GPS同步时钟频率。CPLD/FPGA根据输入信号所确定的类型后，选择匹配的处理方式对输入信号进行分频处理，即将输入信号转换为该网络设备的统一频率(即固定频率)。然后将转换后的统一频率经过硬件链路送至锁相环，锁相环锁定跟随频率源后，将按照用户需求输出特定频率并分发给整个系统设备使用，从而完成频率同步的功能。
本发明实施例提供的时钟频率识别的方法，通过在网络设备在接收到输入信号后，以该输入信号为基准，获取在输入信号的预设周期内网络设备所产生的内部信号的脉冲个数，并根据获取的内部信号的脉冲个数该对输入信号所属的时钟频率类型进行判别，从而可以在辨别后执行相应的频率处理；本发明实施例中的网络设备能够对接收到输入信号所属的时钟频率类型进行自动判别，实现了对时钟频率端口进行灵活及有效使用，相比于相关技术中在网络设备上增加器件接收不同输入信号的接口，或者根据不同的网络设备在软件中相应修改配置的方式，降低了网络设备的成本，并且提高了对输入信号进行判别的准确性。
可选地，图5为本发明实施例提供的还一种时钟频率识别的方法的流程示意图。在上述图4所示实施例的基础上，在本实施例提供的时钟频率识别的方法中，上述步骤210可以包括如下步骤，即步骤211～步骤212：
步骤211、网络设备在接收到输入信号后，以该输入信号为基准，在检测到该输入信号的第一上升沿到达时，开始对该网络设备内部产生的高频信号的脉冲进行计数；
步骤212、网络设备在检测到该输入信号的第二上升沿到达时停止计数，获取在该输入信号的一个周期内高频信号的脉冲个数。
本实施例中将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS同步时钟频率共用一个端口为例进行详细说明。
在网络设备中由系统钟或者晶振产生的高频信号可包括77.76MHZ和19.44MHZ，以下将以19.44MHZ高频信号做基准为例进行说明。以输入信号 为基准，将该输入信号作为采样频率，触发计数器对设备系统钟或晶振产生的19.44MHZ高频信号的脉冲进行计数。在实际应用中，网络设备在端口处理时钟频率的模式下，计数器在输入信号相邻两个上升沿或下降沿之间计算高频信号脉冲个数；即CPLD/FPGA当接收到输入信号后，在输入信号的第一个上升沿到来时计数器开始计算高频信号的脉冲个数，在输入信号第二个上升沿到达时停止计数，可以获取到在输入信号的一个周期内高频信号的脉冲个数。然后，CPLD/FPGA按照19.44MHZ高频信号的脉冲个数，判别该输入信号是2.048MHZ信号还是10MHZ信号。另外，也可以在输入信号的多个周期内对高频信号的脉冲进行计数，本发明实施例不限制获取高频信号的脉冲个数的方式，上述获取高频信号的脉冲个数的方式仅为本实施方式的示意性说明。本实施例以高频信号作为采样频率，实现了对输入信号的脉冲个数进行准确计数。
可选地，在上述图5所示实施例的基础上，本实施例提供的时钟频率识别的方法中，上述步骤220可以包括如下步骤，即步骤221～步骤222：
步骤221、当高频信号的脉冲个数在第三预设个数范围内时，判定输入信号为同步数字体系的时钟频率信号；
步骤222、当高频信号的脉冲个数在第四预设个数范围内时，判定输入信号为全球定位系统的时钟频率信号。
本实施例将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口为例进行详细说明。在上述得到高频信号的脉冲个数后，CPLD/FPGA按照高频信号的脉冲个数判别该输入信号是2.048MHZ信号还是10MHZ信号。在实际应用中，由于频偏的存在，当高频信号的脉冲个数在第三预设个数范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第三预设个数范围可设置为8～10个脉冲；当高频信号的脉冲个数在第四预设个数范围内时，则判定输入信号为10MHZ的GPS时钟频率，该第四预设个数范围可设置为1～3个脉冲。上述第三预设个数范围及第四预设个数范围可根据实际情况而灵活设置。可选地，也可将两者的中间值5作为判定界限，若得到的高频信号的脉冲个数小于或等于5，则判定输入信号为 2.048MHZ的SDH时钟频率；若得到的高频信号的脉冲个数大于5，则判定输入信号为10MHZ的GPS时钟频率。最后确定输入信号所属的时钟频率类型后，CPLD/FPGA对该输入信号进行分频成网络设备所需频点。
本实施例在同一个网络设备中，2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口，且不需要增加用户配置操作，通过CPLD/FPGA等可编程逻辑器件完成频率识别和选择处理功能，降低了网络设备的成本。
可选地，图6为本发明实施例提供的还一种时钟频率识别的方法的流程示意图。在上述图4所示实施例的基础上，在本实施例提供的时钟频率识别的方法中，上述步骤210可以包括如下步骤，即步骤213～步骤214：
步骤213、网络设备在接收到输入信号后，以该输入信号为基准，在检测到该输入信号的上升沿到达时，开始对该网络设备内内部产生的高频信号的脉冲进行计数；
步骤214，网络设备在检测到输入信号的下降沿到达时停止计数，获取在该输入信号的半个周期内高频信号的脉冲个数。
本实施例中将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS同步时钟频率共用一个端口为例进行详细说明。
在网络设备中由系统钟或者晶振产生的高频信号可包括77.76MHZ和19.44MHZ，以下将以19.44MHZ高频信号做基准为例进行说明。以输入信号为基准，将该输入信号作为采样频率，并由计数器对19.44MHZ高频信号的脉冲进行计数。在实际应用中，网络设备在端口处理时钟频率的模式下，在输入信号相邻的上升沿与下降沿之间获取高频信号脉冲个数，即当CPLD/FPGA接收到输入信号后，在输入信号的上升沿到来时计数器开始计算高频信号的脉冲个数，在输入信号的下降沿到达时停止计数，可以获取到在输入信号的半个周期内19.44MHZ高频信号的脉冲个数。然后，CPLD/FPGA按照高频信号的脉冲个数，判别该输入信号是2.048MHZ信号还是10MHZ信号。另外，也可以在输入信号的多个周期内对高频信号的脉冲进行计数，本发明实施例不限制获取高频信号的脉冲个数的方式，上述获取高频信号的脉冲个数的方式 仅为本实施方式的示意性说明。本实施例以高频信号作为采样频率，高频信号的频率也高精度也越高，实现了对输入信号的脉冲个数进行准确计数。
可选地，在上述图6所示实施例的基础上，本实施例提供的时钟频率识别的方法中，上述步骤220可以包括如下步骤，即步骤223～步骤225：
步骤223、网络设备根据高频信号的频率N，以及在输入信号的半个周期内高频信号的脉冲个数X，计算该输入信号的频率R，其中，R＝N/(2*X)；
步骤224、当输入信号的频率在第一预设频率范围内时，判定该输入信号为同步数字体系的时钟频率信号；
步骤225、当输入信号的频率在第二预设频率范围内时，判定该输入信号为全球定位系统的时钟频率信号。
本实施例将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口为例进行详细说明。在上述得到19.44MHZ高频信号的脉冲个数后，CPLD/FPGA按照高频信号的脉冲个数计算输入信号的频率，并根据得到的输入信号的频率判别该输入信号是2.048MHZ信号还是10MHZ信号。举例来说，以19.44MHZ高频信号作为采样频率，假设采样频率为N，计数得到的脉冲个数为X，由采样频率N得到采样周期为1/N，将得到的脉冲个数X和采样频率N计算得到在输入信号的一个周期内高频信号的持续时间为t，其中，t＝2*X*(1/N)；由于信号的波形为正弦，即高低电平的占空比都是0.5，则需要将算出高电平的时间乘以2，得到一个周期的时长，取倒数得到输入信号的频率；再根据采样频率N及时间t计算输入信号的频率R，其中，R＝1/t＝N/(2*X)。
在实际应用中，由于频偏的存在，计算出的频率应当允许有一定误差。当输入信号的频率在第一预设频率范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第一预设频率范围可设置为2.048MHZ±26HZ；当输入信号的频率在第二预设频率范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第二预设频率范围可设置为10MHZ±120HZ。上述第一预设频率范围及第二预设频率范围也可根据实际情况进行设置，并不限定并发明。然后 CPLD/FPGA按照判定结果，根据不同频率的处理方式，将输入信号分频成网络设备需要的频点。即可编程逻辑器件可按照不同频率的处理方式分频成符合自身需求的时钟频率，并提供给网络设备可用同步时钟源，达到网络设备时钟频率同步的最终目的。
本实施例在同一个网络设备中，2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口，且不需要增加用户配置操作，通过CPLD/FPGA等可编程逻辑器件完成频率识别和选择处理功能。即只需要增加CPLD/FPGA的编程内容，升级现网的CPLD/FPGA文件就能使网络设备达到在应用中加入支持GPS频率的功能，降低了网络设备的成本。
如图7所示，为本发明实施例提供一种时钟频率识别的装置的结构示意图。本实施例提供的时钟频率识别的装置可以包括：脉冲个数获取模块10和类型判别模块20。
其中，脉冲个数获取模块10，设置为：在接收到输入信号后，以网络设备所产生的内部信号为基准，获取在该内部信号的预设周期内输入信号的脉冲个数。
本实施例中，时钟频率识别的装置可应用于在同一网络设备端口中使用的SDH时钟、同步以太网(SEC)时钟、包传送网(PTN)时钟、GPS同步时钟等进行识别。本实施例中的网络设备可已包括分组传送网(PTN)设备、光线路终端(OLT)和ONU等。
本实施例的网络设备中可以内置有复杂可编程逻辑器件(CPLD)、或者现场可编程门阵列(FPGA)等可编程逻辑器件完成对时钟频率的识别及选择处理功能。上述输入信号是与网络设备外部连接的时钟频率仪表、GPS时钟仪表等产生的。在实际应用中，脉冲个数获取模块10在接收到输入信号后，以网络设备所产生的内部信号为基准，将该内部信号作为采样频率，CPLD/FPGA检测内部信号到来的上升沿或者下降沿之间形成的预设周期，并调用脉冲个数获取模块10触发网络设备中内置计数器计算在该内部信号的预设周期内，输入信号的脉冲个数。本实施例中的内部信号例如可以包括以CPLD/FPGA所产生的秒脉冲信号(即1pps)、由网络设备系统钟或者晶振产 生的高频信号等，其频率越高精度也越高。上述预设周期可设置为一个周期或者多个周期，也可根据实际情况而灵活设置，其中，一个周期可为内部信号两个相邻的上升沿或者下降沿之间的距离。
类型判别模块20，设置为：根据脉冲个数获取模块10获取的输入信号的脉冲个数对该输入信号所属的时钟频率类型进行判别。
在网络设备内部配置的CPLD/FPGA根据计数器计数得到的输入信号的脉冲个数，由类型判别模块20确定输入信号所属的类型，例如，若得到2048000个脉冲，则判定输入信号是2.048MHZ的SDH时钟频率，若得到10000000个脉冲，则判定输入信号是10MHZ的GPS同步时钟频率。CPLD/FPGA根据输入信号所确定的类型，选择匹配的处理方式对输入信号进行分频处理，即将输入信号转换为该网络设备的统一频率(即固定频率)。然后将转换后的统一频率经过硬件链路送至锁相环，锁相环锁定跟随频率源后，将按照用户需求输出特定频率并分发给整个系统设备使用，从而完成频率同步的功能。
本发明实施例提供的时钟频率识别的装置，通过脉冲个数获取模块在接收到输入信号后，以网络设备所产生的内部信号为基准，获取在内部信号的预设周期内输入信号的脉冲个数，并由类型判别模块根据获取的输入信号的脉冲个数该对输入信号所属的时钟频率类型进行判别，从而可以在判别后执行相应的频率处理；本发明实施例中的网络设备能够对接收到输入信号所属的时钟频率类型进行自动判别，实现了对时钟频率端口进行灵活及有效使用，相比于相关技术中在网络设备上增加器件接收不同输入信号的接口，或者根据不同的网络设备在软件中相应修改配置的方式，降低了网络设备的成本，并且提高了对输入信号进行判别的准确性。
可选地，图8为本发明实施例提供的另一种时钟频率识别的装置的结构示意图。在上述图7所示装置的结构基础上，本实施例提供的时钟频率识别的装置中，上述脉冲个数获取模块10可以包括：
脉冲个数计数单元11，设置为：在接收到输入信号后，以网络设备内部产生的秒脉冲信号为基准，在检测到该秒脉冲信号的第一上升沿到达时，开始对输入信号的脉冲进行计数；
脉冲个数获取单元12，设置为：在检测到该秒脉冲信号的第二上升沿到达时停止计数，得到在该秒脉冲信号的一个周期内输入信号的脉冲个数。
本实施例中将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS同步时钟频率共用一个端口为例进行详细说明。
网络设备在端口处理时钟频率的模式下，将CPLD/FPGA产生的秒脉冲信号为基准，将该秒脉冲信号作为采样频率，由脉冲个数计数单元11触发计数器对接收的输入信号进行脉冲计数，例如，统计输入信号在一个秒脉冲信号周期内的脉冲个数。实际应用中可以包括以下方法，方法一：当CPLD/FPGA接收到输入信号，并检测到秒脉冲信号的第一个上升沿到达时，由脉冲个数计数单元11触发计数器开始对输入信号的脉冲进行计数，并且由脉冲个数获取单元12在秒脉冲信号的第二个上升沿到达时停止计数，获取在秒脉冲信号的一个周期内输入信号的脉冲个数。方法二：当CPLD/FPGA接收到输入信号后，由脉冲个数计数单元11触发计数器开始对输入信号的脉冲进行计数，并由脉冲个数获取单元12按秒脉冲信号的上升沿触发清零；由于每次输入信号从无到有，在第一个秒脉冲信号内的计数可能不满一个周期，因此需要将第一个秒脉冲信号内的计数值丢弃，即在第二个秒脉冲信号上升沿到达时，将计数器清零，重新开始计数，在下一个秒脉冲信号的上升沿到达时停止计数；然后按照输入信号的脉冲个数，判别该输入信号是2.048MHZ信号还是10MHZ信号。另外，也可以在秒脉冲信号的多个周期内对输入信号的脉冲进行计数，本发明实施例不限制获取输入信号的脉冲个数的方式，上述获取输入信号的脉冲个数的方式仅为本实施方式的示意性说明，本领域技术人员提出的其它获取输入信号的脉冲个数以执行相应的操作的方式，均在本发明实施例的保护范围内。本发明实施例以秒脉冲信号作为采样信号，实现了对输入信号的脉冲个数进行准确计数。
可选地，在图8所示实施例的基础上，本实施例中，上述类型判别模块20可以包括：
第一判定单元21，设置为：当输入信号的脉冲个数在第一预设个数范围内时，判定该输入信号为同步数字体系的时钟频率信号；
第二判定单元22，设置为：在输入信号的脉冲个数在第二预设个数范围内时，判定该输入信号为全球定位系统的时钟频率信号。
本实施例将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口为例进行详细说明。在上述得到输入信号的脉冲个数后，类型判别模块20按照输入信号的脉冲个数判别该输入信号是2.048MHZ信号还是10MHZ信号。在一个秒脉冲周期内2.048MHZ信号标准计数可达到2048000个脉冲，由于频偏的存在，计数器得到的脉冲个数应当允许有一定误差。在实际应用中，假设得到输入信号的脉冲个数在第一预设个数范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第一预设个数范围可设置为2048000±12个；假设得到的输入信号的脉冲个数在第二预设个数范围内时，则判定输入信号为10MHZ的GPS时钟频率，该第二预设个数范围可设置为10000000±12个。上述第一预设个数范围及第二预设个数范围可根据实际情况而灵活设置。在确定输入信号所属的时钟频率类型后，可根据不同时钟频率进行相应处理，将其分频成网络设备需要的频点。
本实施例在同一个网络设备中，2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口，且不需要增加用户配置操作，通过CPLD/FPGA等可编程逻辑器件完成频率识别和选择处理功能。即只需要增加CPLD/FPGA的编程内容，升级现网的CPLD/FPGA文件就能使网络设备达到在应用中加入支持GPS时钟频率的功能，既降低了网络设备的成本，也符合网络运营商的运维要求。
可选地，如图9所示，为本发明实施例提供的又一种时钟频率识别的装置的结构示意图。本实施例提供的时钟频率识别的装置可以包括：获取模块30和判别模块40。
其中，获取模块30，设置为：在接收到输入信号后，以该输入信号为基准，获取在该输入信号的预设周期内网络设备所产生的内部信号的脉冲个数。
本实施例中，时钟频率识别的装置可应用于在同一网络设备端口中使用的SDH时钟、同步以太网时钟(SEC)、包传送网(PTN)时钟、GPS同步时钟等进行识别。本实施例中的网络设备可以包括分组传送网(PTN)设备、 光线路终端(OLT)和ONU等。
本实施例的网络设备中可以内置有复杂可编程逻辑器件(CPLD)、或者现场可编程门阵列(FPGA)等可编程逻辑器件完成对时钟频率的识别及选择处理功能。上述输入信号是与网络设备外部连接的时钟频率仪表、GPS时钟仪表等产生的。在实际应用中，网络设备在接收到输入信号后，以输入信号为基准，将该输入信号作为采样频率，CPLD/FPGA检测该输入信号到来的上升沿或者下降沿之间形成的预设周期，并由获取模块30触发网络设备中内置计数器计算在该输入信号的预设周期内，内部信号的脉冲个数。本实施例中的内部信号例如可以包括以CPLD/FPGA所产生的秒脉冲信号(即1pps)、由网络设备系统钟或者晶振产生的高频信号等由网络设备本身提供的高频信号，其频率越高精度也越高。上述预设周期可设置为一个周期或者多个周期，也可根据实际情况而灵活设置，其中，一个周期可为输入信号两个相邻的上升沿或者下降沿之间的距离。
判别模块40，设置为：根据获取模块30获取的内部信号的脉冲个数对输入信号所属的时钟频率类型进行判别。
在网络设备内部配置的CPLD/FPGA根据计数器计数得到的内部信号的脉冲个数，由判别模块40确定输入信号所属的类型，例如，若得到9个脉冲，则判定输入信号是2.048MHZ的SDH时钟频率，若得到1个脉冲，则判定输入信号是10MHZ的GPS同步时钟频率。判别模块40根据输入信号所确定的类型后，CPLD/FPGA选择匹配的处理方式对输入信号进行分频处理，即将输入信号转换为该网络设备的统一频率(即固定频率)。然后将转换后的统一频率经过硬件链路送至锁相环，锁相环锁定跟随频率源后，将按照用户需求输出特定频率并分发给整个系统设备使用，从而完成频率同步的功能。
本发明实施例提供的时钟频率识别的装置，通过获取模块在接收到输入信号后，以该输入信号为基准，获取在输入信号的预设周期内网络设备所产生的内部信号的脉冲个数，并由判别模块根据获取的内部信号的脉冲个数该对输入信号所属的时钟频率类型进行判别，从而可以在辨别后执行相应的频率处理；本发明实施例中的网络设备能够对接收到输入信号所属的时钟频率类型进行自动判别，实现了对时钟频率端口进行灵活及有效使用，相比于相 关技术中在网络设备上增加器件接收不同输入信号的接口，或者根据不同的网络设备在软件中相应修改配置的方式，降低了网络设备的成本，并且提高了对输入信号进行判别的准确性。
可选地，图10为本发明实施例提供的再一种时钟频率识别的装置的结构示意图。在上述图9所示装置的结构基础上，在本实施例提供的时钟频率识别的装置中，上述获取模块30可以包括：
第一计数单元31，设置为：在接收到输入信号后，以该输入信号为基准，在检测到该输入信号的第一上升沿到达时，开始对网络设备内部产生的高频信号的脉冲进行计数；
第一获取单元32，设置为：在检测到该输入信号的第二上升沿到达时停止计数，获取在该输入信号的一个周期内所述高频信号的脉冲个数。
本实施例中将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS同步时钟频率共用一个端口为例进行详细说明。
在网络设备中由系统钟或者晶振产生的高频信号可包括77.76MHZ和19.44MHZ，以下将以19.44MHZ高频信号做基准为例进行说明。以输入信号为基准，将该输入信号作为采样频率，由获取模块30触发计数器对设备系统钟或晶振产生的19.44MHZ高频信号的脉冲进行计数。在实际应用中，网络设备在端口处理时钟频率的模式下，获取模块30触发计数器在输入信号相邻两个上升沿或下降沿之间计算高频信号脉冲个数；即当第一计数单元31接收到输入信号后，在输入信号的第一个上升沿到来时计数器开始计算高频信号的脉冲个数，由第一获取单元32在输入信号第二个上升沿到达时停止计数，可以获取到在输入信号的一个周期内高频信号的脉冲个数。然后，CPLD/FPGA按照19.44MHZ高频信号的脉冲个数，判别该输入信号是2.048MHZ信号还是10MHZ信号。另外，也可以在输入信号的多个周期内对高频信号的脉冲进行计数，本发明实施例不限制获取高频信号的脉冲个数的方式，上述获取高频信号的脉冲个数的方式仅为本实施方式的示意性说明。本实施例以高频信号作为采样频率，实现了对输入信号的脉冲个数进行准确计数。
可选地，在上述图10所示实施例的基础上，在本实施例中，上述判别模块40可以包括：
第三判定单元41，设置为：当高频信号的脉冲个数在第三预设个数范围内时，判定输入信号为同步数字体系的时钟频率信号；
第四判定单元42，设置为：当高频信号的脉冲个数在第四预设个数范围内时，判定输入信号为全球定位系统的时钟频率信号。
本实施例将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口为例进行详细说明。在上述得到高频信号的脉冲个数后，判别模块40按照高频信号的脉冲个数判别该输入信号是2.048MHZ信号还是10MHZ信号。在实际应用中，由于频偏的存在，当高频信号的脉冲个数在第三预设个数范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第三预设个数范围可设置为8～10个脉冲；当高频信号的脉冲个数在第四预设个数范围内时，则判定输入信号为10MHZ的GPS时钟频率，该第四预设个数范围可设置为1～3个脉冲。上述第三预设个数范围及第四预设个数范围可根据实际情况而灵活设置。可选地，也可将两者的中间值5作为判定界限，若得到的高频信号的脉冲个数小于或等于5，则判定输入信号为2.048MHZ的SDH时钟频率；若得到的高频信号的脉冲个数大于5，则判定输入信号为10MHZ的GPS时钟频率。最后确定输入信号所属的时钟频率类型后，CPLD/FPGA对该输入信号进行分频成网络设备所需频点。
本实施例在同一个网络设备中，2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口，且不需要增加用户配置操作，通过CPLD/FPGA等可编程逻辑器件完成频率识别和选择处理功能，降低了网络设备的成本。
可选地，图11为本发明实施例提供的还一种时钟频率识别的装置的结构示意图。在上述图9所示装置的结构基础上，在本实施例提供的时钟频率识别的装置中，上述获取模块30可以包括：
第二计数单元33，设置为：在接收到输入信号后，以该输入信号为基准， 在检测到该输入信号的上升沿到达时，开始对网络设备内部产生的高频信号的脉冲进行计数；
第二获取单元34，设置为：在检测到该输入信号的下降沿到达时停止计数，获取在该输入信号的半个周期内所述高频信号的脉冲个数。
本实施例中将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS同步时钟频率共用一个端口为例进行详细说明。
在网络设备中由系统钟或者晶振产生的高频信号可包括77.76MHZ和19.44MHZ，以下将以19.44MHZ高频点信号做基准为例进行说明。以输入信号为基准，将该输入信号作为采样频率，并由获取模块30触发计数器对19.44MHZ高频信号的脉冲进行计数。在实际应用中，网络设备在端口处理时钟频率的模式下，由第二计数单元33在输入信号相邻的上升沿与下降沿之间获取高频信号脉冲个数，即当CPLD/FPGA接收到输入信号后，在输入信号的上升沿到来时计数器开始计算高频信号的脉冲个数，由第二获取单元34在输入信号的下降沿到达时停止计数，可以获取到在输入信号的半个周期内19.44MHZ高频信号的脉冲个数。然后，CPLD/FPGA按照高频信号的脉冲个数，判别该输入信号是2.048MHZ信号还是10MHZ信号。另外，也可以在输入信号的多个周期内对高频信号的脉冲进行计数，发明实施例不限制获取高频信号的脉冲个数的方式，上述获取高频信号的脉冲个数的方式仅为本实施方式的示意性说明。本实施例以高频信号作为采样频率，高频信号的频率也高精度也越高，实现了对输入信号的脉冲个数进行准确计数。
可选地，在上述图11所示实施例的基础上，在本实施例中，上述判别模块40可以包括：
计算单元43，设置为：根据高频信号的频率N，以及在输入信号的半个周期内高频信号的脉冲个数X，计算该输入信号的频率R，其中，R＝N/(2*X)；
第五判定单元44，设置为：当计算单元43计算得到的输入信号的频率在第一预设频率范围内时，判定该输入信号为同步数字体系的时钟频率信号；
第六判定单元45，设置为：当计算单元43计算得到的输入信号的频率在 第二预设频率范围内时，判定该输入信号为全球定位系统的时钟频率信号。
本实施例将以在同一个网络设备中，将2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口为例进行详细说明。在上述得到19.44MHZ高频信号的脉冲个数后，计算单元43按照高频信号的脉冲个数计算输入信号的频率，并根据得到的输入信号的频率判别该输入信号是2.048MHZ信号还是10MHZ信号。举例来说，以19.44MHZ高频信号作为采样频率，假设采样频率为N，计数得到的脉冲个数为X，由采样频率N得到采样周期为1/N，将得到的脉冲个数X和采样频率N计算得到在输入信号的一个周期内高频信号的持续时间为t，其中，t＝2*X*(1/N)；由于信号的波形为正弦，即高低电平的占空比都是0.5，则需要将算出高电平的时间乘以2，得到一个周期的时长，取倒数得到输入信号的频率；再根据采样频率N及时间t计算输入信号的频率R，其中，R＝1/t＝N/(2*X)。
在实际应用中，由于频偏的存在，计算出的频率应当允许有一定误差。当输入信号的频率在第一预设频率范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第一预设频率范围可设置为2.048MHZ±26HZ；当输入信号的频率在第二预设频率范围内时，则判定输入信号为2.048MHZ的SDH时钟频率，该第二预设频率范围可设置为10MHZ±120HZ。上述第一预设频率范围及第二预设频率范围也可根据实际情况进行设置，并不限定并发明。然后CPLD/FPGA按照判定结果，根据不同频率的处理方式，将输入信号分频成网络设备需要的频点。即可编程逻辑器件可按照不同频率的处理方式分频成符合自身需求的时钟频率，并提供给网络设备可用同步时钟源，达到网络设备时钟频率同步的最终目的。
本实施例在同一个网络设备中，2.048MHZ的SDH时钟频率和10MHZ的GPS时钟频率共用一个端口，且不需要增加用户配置操作，通过CPLD/FPGA等可编程逻辑器件完成频率识别和选择处理功能。即只需要增加CPLD/FPGA的编程内容，升级现网的CPLD/FPGA文件就能使网络设备达到在应用中加入支持GPS频率的功能，降低了网络设备的成本。
本领域普通技术人员可以理解上述实施例的全部或部分步骤可以使用计算机程序流程来实现，所述计算机程序可以存储于一计算机可读存储介质中， 所述计算机程序在相应的硬件平台上(根据系统、设备、装置、器件等)执行，在执行时，包括方法实施例的步骤之一或其组合。
可选地，上述实施例的全部或部分步骤也可以使用集成电路来实现，这些步骤可以被分别制作成一个个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。
上述实施例中的装置/功能模块/功能单元可以采用通用的计算装置来实现，它们可以集中在单个的计算装置上，也可以分布在多个计算装置所组成的网络上。
上述实施例中的装置/功能模块/功能单元以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。上述提到的计算机可读取存储介质可以是只读存储器，磁盘或光盘等。
工业实用性
本发明实施例通过在网络设备在接收到输入信号后，以该网络设备所产生的内部信号为基准，获取在内部信号的预设周期内输入信号的脉冲个数，并根据获取的输入信号的脉冲个数该对输入信号所属的时钟频率类型进行判别，从而可以在判别后执行相应的频率处理；本发明实施例实现了对接收到输入信号所属的时钟频率类型进行判别，从而可以对时钟频率端口进行灵活及有效使用，相比于相关技术在网络设备上增加器件接收不同输入信号的接口，或者根据不同的网络设备在软件中相应修改配置的方式，降低了网络设备的成本，并且提高了对输入信号进行判别的准确性。

Claims (16)

  1. 一种时钟频率识别的方法，包括：
    网络设备在接收到输入信号后，以所述网络设备所产生的内部信号为基准，获取在所述内部信号的预设周期内所述输入信号的脉冲个数；
    所述网络设备根据获取的所述输入信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
  2. 根据权利要求1所述的时钟频率识别的方法，其中，所述网络设备在接收到输入信号后，以所述网络设备所产生的内部信号为基准，获取在所述内部信号的预设周期内所述输入信号的脉冲个数，包括：
    所述网络设备在接收到所述输入信号后，以所述网络设备内部产生的秒脉冲信号为基准，在检测到所述秒脉冲信号的第一上升沿到达时，开始对所述输入信号的脉冲进行计数；
    所述网络设备在检测到所述秒脉冲信号的第二上升沿到达时停止计数，获取在所述秒脉冲信号的一个周期内所述输入信号的脉冲个数。
  3. 根据权利要求1或2所述的时钟频率识别的方法，其中，所述网络设备根据获取的所述输入信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别，包括：
    当所述输入信号的脉冲个数在第一预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
    当所述输入信号的脉冲个数在第二预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
  4. 一种时钟频率识别的方法，包括：
    网络设备在接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内所述网络设备所产生的内部信号的脉冲个数；
    所述网络设备根据获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
  5. 根据权利要求4所述的时钟频率识别的方法，其中，所述网络设备在 接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内所述网络设备所产生的内部信号的脉冲个数，包括：
    所述网络设备在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的第一上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
    所述网络设备在检测到所述输入信号的第二上升沿到达时停止计数，获取在所述输入信号的一个周期内所述高频信号的脉冲个数。
  6. 根据权利要求5所述的时钟频率识别的方法，其中，所述网络设备根据获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别，包括：
    当所述高频信号的脉冲个数在第三预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
    当所述高频信号的脉冲个数在第四预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
  7. 根据权利要求4所述的时钟频率识别的方法，其中，所述网络设备在接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内所述网络设备所产生的内部信号的脉冲个数，包括：
    所述网络设备在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
    所述网络设备在检测到所述输入信号的下降沿到达时停止计数，获取在所述输入信号的半个周期内所述高频信号的脉冲个数。
  8. 根据权利要求7所述的时钟频率识别的方法，其中，所述网络设备根据获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别，包括：
    所述网络设备根据所述高频信号的频率N，以及所述在所述输入信号的半个周期内所述高频信号的脉冲个数X，计算所述输入信号的频率R，其中，R＝N/(2*X)；
    当所述输入信号的频率在第一预设频率范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
    当所述输入信号的频率在第二预设频率范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
  9. 一种时钟频率识别的装置，包括：
    脉冲个数获取模块，设置为：在接收到输入信号后，以网络设备所产生的内部信号为基准，获取在所述内部信号的预设周期内所述输入信号的脉冲个数；
    类型判别模块，设置为：根据所述脉冲个数获取模块获取的所述输入信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
  10. 根据权利要求9所述的时钟频率识别的装置，其中，所述脉冲个数获取模块包括：
    脉冲个数计数单元，设置为：在接收到所述输入信号后，以所述网络设备内部产生的秒脉冲信号为基准，在检测到所述秒脉冲信号的第一上升沿到达时，开始对所述输入信号的脉冲进行计数；
    脉冲个数获取单元，设置为：在检测到所述秒脉冲信号的第二上升沿到达时停止计数，获取在所述秒脉冲信号的一个周期内所述输入信号的脉冲个数。
  11. 根据权利要求9或10所述的时钟频率识别的装置，其中，所述类型判别模块包括：
    第一判定单元，设置为：当所述输入信号的脉冲个数在第一预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
    第二判定单元，设置为：当所述输入信号的脉冲个数在第二预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
  12. 一种时钟频率识别的装置，包括：
    获取模块，设置为：在接收到输入信号后，以所述输入信号为基准，获取在所述输入信号的预设周期内网络设备所产生的内部信号的脉冲个数；
    判别模块，设置为：根据所述获取模块获取的所述内部信号的脉冲个数对所述输入信号所属的时钟频率类型进行判别。
  13. 根据权利要求12所述的时钟频率识别的装置，其中，所述获取模块包括：
    第一计数单元，设置为：在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的第一上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
    第一获取单元，设置为：在检测到所述输入信号的第二上升沿到达时停止计数，获取在所述输入信号的一个周期内所述高频信号的脉冲个数。
  14. 根据权利要求13所述的时钟频率识别的装置，其中，所述判别模块包括：
    第三判定单元，设置为：当所述高频信号的脉冲个数在第三预设个数范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
    第四判定单元，设置为：当所述高频信号的脉冲个数在第四预设个数范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
  15. 根据权利要求12所述的时钟频率识别的装置，其中，所述获取模块包括：
    第二计数单元，设置为：在接收到所述输入信号后，以所述输入信号为基准，在检测到所述输入信号的上升沿到达时，开始对所述网络设备内部产生的高频信号的脉冲进行计数；
    第二获取单元，设置为：在检测到所述输入信号的下降沿到达时停止计数，获取在所述输入信号的半个周期内所述高频信号的脉冲个数。
  16. 根据权利要求15所述的时钟频率识别的装置，其中，所述判别模块包括：
    计算单元，设置为：根据所述高频信号的频率N，以及所述在所述输入信号的半个周期内所述高频信号的脉冲个数X，计算所述输入信号的频率R，其中，R＝N/(2*X)；
    第五判定单元，设置为：当所述计算单元计算得到的所述输入信号的频 率在第一预设频率范围内时，判定所述输入信号为同步数字体系的时钟频率信号；
    第六判定单元，设置为：当所述计算单元计算得到的所述输入信号的频率在第二预设频率范围内时，判定所述输入信号为全球定位系统的时钟频率信号。
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