WO2017052658A1 - Strates superposées intégrées d'îlots de puces fonctionnels dans un dispositif à semi-conducteur - Google Patents

Strates superposées intégrées d'îlots de puces fonctionnels dans un dispositif à semi-conducteur Download PDF

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Publication number
WO2017052658A1
WO2017052658A1 PCT/US2015/052494 US2015052494W WO2017052658A1 WO 2017052658 A1 WO2017052658 A1 WO 2017052658A1 US 2015052494 W US2015052494 W US 2015052494W WO 2017052658 A1 WO2017052658 A1 WO 2017052658A1
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Prior art keywords
die
small
dies
base
package
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PCT/US2015/052494
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English (en)
Inventor
Don W. Nelson
Brennen Mueller
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Intel Corporation
JUN, Kimin
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Publication date
Application filed by Intel Corporation, JUN, Kimin filed Critical Intel Corporation
Priority to PCT/US2015/052494 priority Critical patent/WO2017052658A1/fr
Priority to TW105125785A priority patent/TW201724408A/zh
Publication of WO2017052658A1 publication Critical patent/WO2017052658A1/fr

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    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory

Definitions

  • the present disclosure relates to configurations for semiconductor dies in a package and in particular to an assembly with dies of different sizes connected together.
  • integrated circuit dies are made ever smaller. These dies are mounted closer together so that the connections between these dies are also made shorter.
  • the shortest connection is a connection that is made within an integrated circuit package.
  • dies are mounted side by side on a package substrate and connected together through the package substrate or directly with wires.
  • dies are mounted one on top of the other for a direct connection without any intervening wire or package substrate. This is sometimes called a stacked die package.
  • One die can be placed over another using a pick and place machine or a variety of other types of equipment. The combination can be packaged as if it is a single die with double the height.
  • Combining multiple dies into a single package allows for two or more different types of dies to be placed into a single package. This may be referred to as heterogeneous integration of die-to-die connections.
  • the dies may be made using different materials such as Si, Ge, III-V, SiC, etc..
  • the dies may be made using different technology nodes such as 22 nm, 14 nm, 10 nm, etc... These differences may be combined and combined with other types of differences so that different types of dies from different processes and different fabricators may be placed into a single compact package.
  • Heterogeneous materials or different technologies are integrated at the packaging level. This requires that the dies be large and thick so that the dies can be manipulated with pick-and- place equipment. This also uses coarse-pitch, low density electrical connections because the pick-and-place equipment has a limited accuracy for matching up electrical connections.
  • Figure 1 is a side cross-sectional view diagram of a portion of a multiple die package according to an embodiment.
  • Figure 2 is a side cross-sectional view diagram of a portion of a second multiple die package according to an embodiment.
  • Figure 3 is a side cross-sectional view diagram of a portion of a third multiple die package according to an embodiment.
  • Figure 4 is a side cross-sectional view diagram of a portion of a fourth multiple die package according to an embodiment.
  • Figure 5 is a side cross-sectional view diagram of a portion of a fifth multiple die package according to an embodiment.
  • Figure 6 is a side cross-sectional view diagram of a portion of a sixth multiple die package according to an embodiment.
  • Figure 7 is a side cross-sectional view diagram of a set of small dies on a device wafer over a larger island according to an embodiment.
  • Figure 8 is a side cross-sectional view diagram of the small dies joined to the larger island according to an embodiment.
  • Figure 9 is a side cross-sectional view diagram of the small dies and the larger island over a base die according to an embodiment.
  • Figure 10 is a side cross-sectional view diagram of the assembled dies of Figure 9 according to an embodiment.
  • Figure 11 is a block diagram of a computing device incorporating an integrated hybrid semiconductor die package according to an embodiment.
  • Island transfer can transfer thin dies with high density electrical connections. Since these electrical connections are in the interconnect stack, connection lengths are shorter than routing though a package. In other words, the electrical connections made through on-die routing are shorter than those made through packaging. By stacking multiple islands on top of each other, interconnect distances are substantially reduced over simple single strata islands. Longer distances sacrifice power and signal integrity.
  • multiple strata of different islands of silicon may be integrated. Different technologies may be placed on the same die, or different design blocks may be placed on top of other dies. This allows for different graphics or some other different product to be installed over the same host die to create different packages for different markets or for different system integrators. As an example, different server makers may wish to use different islands with the same host die to suit different connection, communication, graphics, or computing uses.
  • three or more strata may be stacked in a hierarchical manner.
  • the different dies may be stacked vertically while surrounded by the normal metal connectivity and dielectric oxides.
  • Any single island bonded to the base wafer may also have one or more islands bonded to it.
  • the stacked island approach described herein permits multiple technologies to be integrated into a single chip. Even technologies that otherwise are not possible on the same technology of a base die may be integrated into the base die using stacked islands.
  • a functional island may be bonded to a main chip at the wafer level. Bonding at the wafer level allows for thin islands (10s of micrometers or less thick) to be accurately placed on a main device wafer. The island and main chip are electrically connected to form a functional device
  • Figure 1 is a side cross-sectional view diagram of a portion of a multiple die package.
  • the base die 102 is formed on a substrate 104.
  • the bottom structure of the base die may be a redistribution layer, a molding compound, or some other material.
  • the base die has multiple metal layers 106 over the die circuitry 105 and opposite the substrate 104.
  • the metal layers are formed within and between layers of inter-layer dielectric (ILD). Islands are placed within and between the metal layers. The islands are in the form of small dies of different types.
  • a top metal layer 108 of interconnect is formed over the islands to connect the islands and the base die to external components.
  • Vertical vias 110 or columns connect the base die to the top interconnect layer while other vertical vias 112 connect the islands to the top interconnect layer.
  • a single island 114 is placed over some metal layers 106.
  • the island is placed face up so that the bottom side substrate is facing toward the base die substrate.
  • the island is embedded in dielectric and connected to the top metal layer 108 by vertical vias. While only one via is shown, there may be many more.
  • the vias may be used to connect the island to external components and to the base die.
  • the second via extends to lower metal layers 106 and may be used to couple the island directly to the base die or to any other component or connection that is connected to the metal layers.
  • two additional islands 130, 132 are placed over the base die 102 between metal layers 106, 108 and are also covered in dielectric.
  • the two additional islands are also shown as being face up like the die 114 on the opposite side. In this case the two islands are positioned one over the other to form a stack of two face-up small dies over the base die.
  • These dies are different sizes and may be of different types made in the same or different technologies. Due to the different sizes, the larger lower die may have routing that goes beside the smaller upper level die to connect to the top layer.
  • a large island 124 is mounted over metal layers 106 of the base die.
  • the larger island is built on a substrate 128 that is facing the base die so that the larger island is face up as shown.
  • Two additional smaller islands 120, 122 are mounted over the larger island 128 and are also mounted face up. As shown, these three islands are all mounted face up so that connections are made using vertical vias above each die.
  • the dies may be connected to each other and to the base die using the vertical vias through the top metal layer. These connections are added later after the dies are mounted over the base die.
  • Figure 2 is a cross-sectional side view diagram of a base die with islands showing bonding the second layer die islands in a face-down configuration. This allows additional interconnects on the top of the large die island. This configuration may be more complex to manufacture, but it provides a shorter interconnect between the two layers of islands. In addition, routing resources of the base die are not needed to move data between the two layers of dies. Signal paths are also shorter, and signal resources in areas above the islands are made available for other routing.
  • Figure 2 shows the same base die 102 with a substrate 104 shown at the bottom of the diagram.
  • a face up island 114 on one side of this portion of the base die is connected with a vertical via 112 to the top metal layer 108 as in Figure 1.
  • This metal layer may connect the island 114 to external or internal resources.
  • One vertical via 110 connects the base die to the top metal layer and another vertical via 114 connects the base die to the island.
  • the other side of the die has two layers of islands 240, 242. However, in contrast to Figure 1 , in this case the islands are face-to-face.
  • the top layer of the lower level die 242 faces the top layer of the upper level die 240. This allows for direct connections 244 between the two dies.
  • the lower die may make direct connections 246 to the top metal layer 108 of the base die.
  • the upper die may make direct connections (not shown) to the lower metal layers of the base die.
  • a larger island 224 on a substrate 228 that is facing the base die substrate In the center of the base die, there is a larger island 224 on a substrate 228 that is facing the base die substrate.
  • the larger island is mounted face up as in the example of Figure 1.
  • the smaller islands are facing the larger island so that the smaller islands are face-to-face with the larger island.
  • This allows for direct connections 230 between the top layer of each small island to the top layer of the large island.
  • other vertical vias 232 may be formed from the face of the large island to the top metal layers 108.
  • the face-to-face configuration provides short direct connections between the islands.
  • Figure 3 is a side view cross-sectional diagram of the base die that shows a third configuration in which all of the islands are face down and the larger island is stacked on top of the smaller islands. This eliminates direct interconnections between the islands but provides for direct connection to the base die.
  • the base die 102 has been formed on or attached to a substrate 104.
  • the base die has circuitry layers 105 and metal layers 106 over the circuitry.
  • an island 314 is installed face down between metal layers 106, 108 and surrounded by ILD or some other dielectric material.
  • the face down die may use direct vertical connections 312 that link it to the lower metal layers 106. This connection allows the island to connect directly to the base die or to any of the other islands through the metal layers.
  • the direct connection may also connect through a metal layer to a vertical via 314 that connects to a top metal layer 108 to connect the island to external components. While only one connection 312 to the island is shown, typically there may be many more and each connection may be coupled differently, to the base die, to another island, or externally.
  • the dies On the other end of the die, two islands 330, 332, are stacked face down in two different levels of the metal layers. The islands are also connected directly through the ILD using vias or columns 334, 336. At the metal layers, the dies may be connected to each other or to the base die or to an external component depending on the purpose and use for the die.
  • the die there are three islands, two 320, 322 at one level and a larger die 324 at another level of the metal layers. These are also all mounted face down so that the substrates are directed away from the substrate 104 of the base die. Vias or columns 326, 328 are used to connect the dies to the metal layers 106 of the base die. The metal layers may be used to make connections to the other dies of the group of three, to other islands, to the base die or externally.
  • Figure 4 shows a fourth configuration as a cross-sectional side view diagram of the base die 102 with the substrate 104 on the bottom and islands in various configurations.
  • the small islands 420 422 are at a lower level face up with the large island 424 mounted face down above the smaller islands. This allows the large island 424 to connect directly both to the small islands 420 through short direct connections and it allows the large island to connect directly to the base die through direct connections 432 to the lower metal layers 106 of the base die.
  • These vertical vias or columns 432 may be formed between or on either side of the small islands.
  • Figure 5 shows a fifth configuration in a side view cross-sectional diagram of a portion of the base die with islands embedded in the ILD.
  • the base die 102 has a single island 114 on one end as in Figure 1 and two stacked islands 130, 132 each on a different level of the metal layers at the other end as in Figure 1.
  • the larger island 528 is at a lower level of the metal layers closer to the base die substrate. It is positioned so that the face of the larger island die faces the base die and the lower metal layers. As a result it is able to make direct connections 526 to the metal layers of the base die.
  • the two smaller islands are at a higher level of the metal layers and are positioned facing the higher metal layers.
  • Direct connections 528 may be made from the faces of the upper islands to the top layer 108 of the base die. Since the substrates of the islands at different levels are facing each other there are no connections shown between the islands.
  • TSVs through silicon vias
  • Figure 6 is a side cross-sectional view of a portion of an alternative base die with islands on both sides of the circuitry.
  • Figure 6 shows an example of applying the principles discussed herein to both sides of the die. Multiple stacks of islands may be placed on both sides of the active silicon of the base die.
  • the original substrate or core has been thinned or removed and replaced with a redistribution layer 660 made of build-up film or some other material.
  • a redistribution layer 660 made of build-up film or some other material.
  • an additional handle or carrier wafer at the top or bottom of the die stack may be used. This would aid in providing heat or thermal management and for packaging the stack of dies.
  • the base die 602 has an embedded circuitry layer 605 with multiple levels of metal layers 606, 608 above the circuitry. There are also multiple levels of metal layers 660, 658 below the circuitry layer.
  • the base die has islands placed alone or in stacked configurations over some of the metal layers. In this example, the islands are in the same configuration as in Figure 1 , however, any of the configurations described in Figures 1 -5 may be used and the dies may be combined in different ways.
  • one end has a single face up island 614 connected to the top metal layer 608.
  • the other end has two face up islands in a stacked configuration also connected directly to the top metal layer.
  • the center of the base die 602 has three islands mounted face up.
  • the larger island 624 is at the lower level and the two smaller islands 620, 622 are mounted at a higher level above the larger die.
  • the base die On the other side or bottom side of the base die, below the lower redistribution layer 660, additional islands are mounted between the bottom metal layers 660, 658 and also within a bottom ILD. These islands are mounted face down in that they face the base die and not the outer metal layers 658. In this case, the islands 652, 654, 656 are all at the same level of the metal layers and are not stacked. However, any of the stacked configurations and orientations may be used. The islands may be face up or face down. Stacked islands may be facing the same direction or in opposite directions and may be face-to-face or back-to-back. These orientations may be combined to provide different functions with different combinations of dies.
  • Figures 7-10 show an example process for combining the small island dies into stacks and placing the stacks in a location so that the stack may be fully embedded inside a base die.
  • Figure 7 is a side cross-sectional diagram of a set of small dies 704 formed on a device wafer 702.
  • the device wafer is the substrate on which the dies have been formed and securely carries the dies.
  • the dies have been covered in a dielectric 706 and diced by sawing, scribing, or etching so that there is a scribe trench or saw kerf through the dies and the wafer 702.
  • the dies are referred to as small meaning only that they are smaller than the base die and the larger island to which they will be attached.
  • the device wafer contains many small dies to be transferred to dies that have been formed on a base die wafer.
  • the dies may be functional materials which are beneficial to integrate with the base wafer. Examples of such functional materials may include silicon, germanium, silicon carbide, III-V and Ill-nitride compound semiconductors. Because the small dies are formed independently on a separate wafer, they may be formed using a different technology, different materials, or different process nodes than the other islands and different from the base die.
  • the small dies may be power, radio-frequency, optical, memory, or other types of devices that are best formed separate from the base wafer.
  • the small islands 704 are attached to a temporary carrier 708 for handling. They may be attached to the temporary carrier before dicing and before applying the ILD between the dies. Through silicon vias may be formed through the substrate to allow for connections through the substrate 702 on the back side of the dies. For a face-to-face configuration, the device wafer 702 may be inverted and the substrate attached to the temporary carrier 110. Alternatively, for a face-to-face connection, the islands may be handled using the device wafer on which they were formed.
  • a temporary adhesive may be selected to withstand any mechanical forces that may be caused during grinding the wafer and any thermal or mechanical overburden during wafer thinning (not shown) or any other mechanical or thermal processes. These forces may include shear forces, compressive forces, tensile forces, etc.
  • the temporary adhesive is also selected so that the dies may easily be debonded from the carrier when desired.
  • One such class of adhesive is polymer adhesives. Polymer adhesives may include
  • Inorganic adhesives may include H-implanted silicon (or silicon implanted with other volatile species), or amorphous Si:H.
  • the small islands 704 are aligned using the temporary carrier 708 over a larger island
  • This larger island may be formed also on a substrate 712 and then attached to a temporary carrier 718.
  • the face of the die is attached to the carrier for a back-to-back connection, however, the substrate may be attached to the temporary carrier or the device wafer may be used. While only one large island and two small islands are shown, the described process may be performed so that part or all of a wafer of such islands may be attached together in one operation. Only a few dies are shown in order to simplify the diagram.
  • through-die-vias may be added to the back side of any or all of islands to allow the islands to be directly connected for a back-to-back configuration. This may be done after wafer thinning so that the islands are small enough to easily be embedded within the metal layers.
  • Through-die vias may are drilled, etched, or bored through the back side substrate or wafer to make contact with the front end circuitry of the dies or with other through- die vias. The drilled holes are then filled with a metal such as Cu, Ti, or Ta to make the connection. The holes may be overfilled so that the metallic surfaces at the tops of the vias are exposed.
  • Figure 8 shows a process stage after the two temporary carriers 708, 718 are pressed together to attach the islands to each other.
  • the substrates 702, 712 of the dies are attached to each other. This may be done using an adhesive or a metal bonding technique. For face-to-face or via-to-via connections, a solder or metal compression bond may be used to attach the dies together.
  • the lower temporary carrier 718 has been removed. The combination may be handled using the top side temporary carrier 708.
  • the top side carrier may be removed and the stack may be handled using the bottom side carrier.
  • Figure 9 is a diagram of the dies 704, 714 and temporary carrier 708 aligned over the base die 724 so that the lower and larger island is face down over the base die metal layers.
  • the larger base die 724 has also been formed on a base die wafer 722.
  • the base wafer 722 also has an underlying stack.
  • the base die has a conductive redistribution layer or other metal or conductive layers with conductive lines or traces over the die.
  • the two wafers 708, 722 are brought together for example by moving the carrier wafer toward the base dies.
  • a variety of different bonding mechanisms may be used to connect the small island stack to the base die. In some
  • metal inter-diffusion is used through the bonding boundary with grain growth.
  • higher temperatures may cause faster and stronger bonding.
  • higher temperatures also affect the characteristics of other materials of the dies and even those near the inter-metal diffusion bonds, such as ILDs at the hybrid bonding interface.
  • Using a lower temperature as described herein reduces or eliminates any negative impact on materials other than the bonding metals.
  • the metals are bonded at room temperature. In other embodiments, the temperature is elevated to 100°C or even to 200°C or to some temperature in between. This promotes diffusion between the metals without damaging other materials.
  • the temporary carrier with the dies that are not bonded may be removed. In some embodiments, the bonded metal may be allowed to cool before separation. This will provide for an even stronger metal-to-metal bond.
  • the temporary carrier 708 is removed as shown in Figure 10, the attached islands remain metal bonded or adhesive bonded to the base die. The base wafer is further processed to embed the transferred islands fully into the interconnect stack.
  • the further processing includes additional dielectric 134, additional conductive posts or vias and conductive contact pads or lines to connect to other components. As shown, the smaller islands are fully embedded within the ILD of the base die. This allows special functions and specialized dies to be incorporated into a larger die assembly without any change in packaging and other processing aspects of the base die.
  • the base die 724 typically there will be many more. These dies are formed on a wafer together with many other dies. Accordingly, the functional dies and the base dies may be carried on their respective wafers and manipulated as a group. The transfer operations may be performed using wafer handlers so that many small dies are transferred to many base dies in one operation. The temporary carrier may then be moved to transfer more small dies to the same base die wafer at a different location or it may be moved to transfer small dies to the dies of a different base die wafer.
  • FIG 19 illustrates a computing device 11 in accordance with one implementation of the invention.
  • the computing device 11 houses a board 2.
  • the board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6.
  • the processor 4 is physically and electrically coupled to the board 2.
  • the at least one communication chip 6 is also physically and electrically coupled to the board 2.
  • the communication chip 6 is part of the processor 4.
  • computing device 11 may include other components that may or may not be physically and electrically coupled to the board 2.
  • these other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non- volatile memory (e.g., ROM) 9, flash memory (not shown), a graphics processor 12, a digital signal processor (not shown), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth).
  • volatile memory e.g., DRAM
  • non- volatile memory e.g., ROM
  • flash memory not
  • the communication chip 6 enables wireless and/or wired communications for the transfer of data to and from the computing device 11.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 6 may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term
  • LTE long term evolution
  • Ev-DO HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA,
  • the computing device 11 may include a plurality of communication chips 6.
  • a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 4 of the computing device 11 includes an integrated circuit die packaged within the processor 4.
  • the integrated circuit die of the processor, memory devices, communication devices, or other components include or are packaged with one or more islands.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the computing device 11 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 11 may be any other electronic device that processes data including a wearable device.
  • Embodiments may be implemented as a part of one or more memory chips, controllers,
  • CPUs Central Processing Unit
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • references to “one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) of the invention so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.
  • Some embodiments pertain to a multiple die package that includes a base die, the base die having a plurality of metal layers over top side circuitry, a first small die placed on the base die at a first level of the metal layers, a second small die placed on the base die above the first small die at a second level of the metal layers, a plurality of metal routing lines and vias within the metal layers to connect the first small die and the second small die to the base die, and a package to cover the base die and the small dies together.
  • first small die and the second small die each have a substrate on a back side and a front side opposite the back side and wherein the first small die and the second small die have one of the two front sides facing the base die, the two back sides facing the base die, the first small die front side facing the base die and the second small die front side not facing the base die, or the first small die back side facing the base die and the second small die front side facing the base die.
  • the first small die is larger than the second small die, the package further comprising a third small die placed on the base die above the first small die at the second level of the metal layers.
  • the first small die is smaller than the second small die, the package further comprising a third small die placed on the base die at the first level of the metal layers.
  • Further embodiments include additional metal routing lines and vias within the metal layers to connect the base die to external components.
  • Further embodiments include additional metal routing lines and vias within the metal layers to connect the second small die to external components.
  • the second small die is formed on a wafer, attached to a temporary carrier, aligned over the first small die using the temporary carrier, and applied against the first small die using the temporary carrier, the second small die having a hybrid metal bond to the first small die.
  • Further embodiments include landing pads on the base die at locations to be bonded to a small die, the landing pads being formed over a dielectric layer, and metal contacts on the first small die to bond to the landing pads.
  • Further embodiments include a dielectric covering the first small die, the second small die, the base die and the metal routing layers.
  • Some embodiments pertain to a method that includes attaching a first plurality of small dies on a first wafer to a first temporary carrier, aligning the small dies over a second plurality of small dies on a second wafer using the first temporary carrier, applying the first plurality of small dies against the second plurality of small dies using the first temporary carrier so that a subset of the first small dies bond to respective second small dies, separating the first temporary carrier so that the subset of first bonded small dies are attached to a respective second small die and the remaining first small dies are separated with the first temporary carrier, attaching the second plurality of small dies to a second temporary carrier, aligning the second plurality of small dies over a plurality of larger base dies on a base wafer using the second temporary carrier, applying the second small dies against the base dies using the second temporary carrier so that a subset of the second small dies bond to respective base dies, separating the second temporary carrier so that the subset of bonded second small dies are attached to a
  • applying the first small dies further comprises pressing the first small dies against the second small dies.
  • applying further comprises heating the first small dies while pressing the first small dies, the heating being at a temperature less than a solder reflow temperature.
  • the first temporary carrier is attached to the front side of the first small dies, the method further comprising forming vias through the back sides of the first small dies to connect to a respective second small die.
  • the first temporary carrier is attached to the back side of the first small dies, the method further comprising forming through silicon vias on the front sides of the first small dies to connect to a respective second small die.
  • the bond between the first set of small dies and the second set of small dies is a metal compression bond.
  • Further embodiments include forming the first plurality of small dies using a first fabrication technology and forming the plurality of base dies using a second fabrication technology different from the first fabrication technology.
  • Some embodiments pertain to a computing system that includes a system board, a mass memory connected to the system board, a communication chip connected to the system board, and a multiple die package connected to the system board, the package including a base die, the base die having a plurality of metal layers over top side circuitry, a first small die placed on the base die at a first level of the metal layers, a second small die placed on the base die above the first small die at a second level of the metal layers, a plurality of metal routing lines and vias within the metal layers to connect the first small die and the second small die to the base die, and a package to cover the base die and the small dies together.
  • the first small die is smaller than the second small die, the package further comprising a third small die placed on the base die at the first level of the metal layers.
  • Further embodiments include a dielectric covering the first small die, the second small die, the base die and the metal routing layers.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne des strates superposées intégrées d'îlots de puces fonctionnels sur un dispositif à semi-conducteur. Un exemple est un boîtier de puces multiples qui comprend une puce de base avec une pluralité de couches métalliques sur un ensemble de circuits côté supérieur. Une première petite puce est placée sur la puce de base à un premier niveau des couches métalliques. Une seconde petite puce est placée sur la puce de base au-dessus de la première petite puce à un second niveau des couches métalliques. Le boîtier a une pluralité de lignes de routage métalliques et de trous d'interconnexion dans les couches métalliques pour connecter la première petite puce et la seconde petite puce à la puce de base et un boîtier pour recouvrir l'ensemble constitué par la puce de base et les petites puces.
PCT/US2015/052494 2015-09-25 2015-09-25 Strates superposées intégrées d'îlots de puces fonctionnels dans un dispositif à semi-conducteur WO2017052658A1 (fr)

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PCT/US2015/052494 WO2017052658A1 (fr) 2015-09-25 2015-09-25 Strates superposées intégrées d'îlots de puces fonctionnels dans un dispositif à semi-conducteur
TW105125785A TW201724408A (zh) 2015-09-25 2016-08-12 半導體元件中之功能性晶片島狀部的積體堆疊層

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CN113097130A (zh) * 2020-03-27 2021-07-09 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11437344B2 (en) 2020-03-27 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer bonding method

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