WO2017052605A1 - Barrière de diffusion de couche de redistribution - Google Patents

Barrière de diffusion de couche de redistribution Download PDF

Info

Publication number
WO2017052605A1
WO2017052605A1 PCT/US2015/052289 US2015052289W WO2017052605A1 WO 2017052605 A1 WO2017052605 A1 WO 2017052605A1 US 2015052289 W US2015052289 W US 2015052289W WO 2017052605 A1 WO2017052605 A1 WO 2017052605A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
redistribution layer
diffusion barrier
semiconductor devices
exposed surface
Prior art date
Application number
PCT/US2015/052289
Other languages
English (en)
Inventor
Hsiao-Kang Chang
Doug B. INGERLY
James Y. JEONG
Ashish BHATIA
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/052289 priority Critical patent/WO2017052605A1/fr
Priority to TW105125181A priority patent/TW201721780A/zh
Publication of WO2017052605A1 publication Critical patent/WO2017052605A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05007—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05547—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05657—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16108—Disposition the bump connector not being orthogonal to the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Definitions

  • the present disclosure relates to stacked die integrated circuits.
  • Stacked die or three-dimensional integrated circuits frequently include a number of dies that are stacked vertically within the package.
  • Such a three-dimensional package may include a die including a logic circuit on which one or more dies, each containing a memory circuit are stacked.
  • Semiconductor devices on such stacked dies may be interconnected using a number of through silicon vias (TSVs).
  • TSVs through silicon vias
  • a TSV electrically couples to a pad on an upper die and electrically couples to the redistribution layer of the lower die. While a portion of the redistribution layer may be exposed to facilitate electrical coupling with other dies within the stack, the redistribution layer may be protected by a dielectric material such as one or more metallic nitride compounds.
  • thermocompression bonding may be used to bond the upper die to the lower die in stacked die or three-dimensional integrated circuits.
  • liquefied solder may attack the interconnect on the redistribution layer and may, at times, cause the formation of intermetallic compounds within the redistribution layer.
  • intermetallic compounds weaken the physical strength of the bond between the upper die and lower die and may additionally cause increased electrical resistance within the connection, degrading performance and potentially leading to premature failure of the three-dimensional semiconductor device.
  • FIG. 1 A is a cross-section of an example first die that includes a redistribution layer covered by a diffusion barrier and a dielectric layer, in accordance with at least one embodiment of the present disclosure
  • FIG. IB is a cross-section of an example three-dimensional semiconductor package that includes a second die electrically coupled to the first die depicted in FIG. 1A, in accordance with at least one embodiment of the present disclosure;
  • FIG. 1 C is an electron micrograph depicting the example three-dimensional semiconductor package depicted in FIG. IB, in accordance with at least one embodiment of the present disclosure
  • FIG. 2A is a cross-section of another example first die that includes a redistribution layer covered by a diffusion barrier, in accordance with at least one embodiment of the present disclosure
  • FIG. 2B is a cross-section of an example three-dimensional semiconductor package that includes a second die electrically coupled to the first die depicted in FIG. 2A, in accordance with at least one embodiment of the present disclosure
  • FIG. 3 is a high-level flow diagram of an example method for forming a three- dimensional semiconductor package, in accordance with at least one embodiment of the present disclosure.
  • FIG. 4 is a high-level flow diagram of another example method for forming a three- dimensional semiconductor package, in accordance with at least one embodiment of the present disclosure.
  • Three-dimensional integrated circuits may be produced by stacking and interconnecting two or more semiconductor dies. Such stacked dies may be interconnected using electrical connections such as a number of through-silicon vias (TSVs) that conductively and communicably couple in any desired manner, at least some of the stacked dies included in the 3D-IC package. At times, the stacked dies are mechanically and electrically coupled using temperature and pressure (thermal compression bonding). In such instances, the heat and pressure causes solder to melt and physically and electrically couple the dies within the 3D-IC. However, the heat and pressure used to liquefy the solder may, at times, cause the liquefied solder to consume all or a portion of the interconnect between the dies.
  • TSVs through-silicon vias
  • the liquefied solder can attack copper redistribution layers within the stack, causing the formation of post-thermocompression bonding (post-TCB) intermetallic compounds (IMCs).
  • post-TCB post-thermocompression bonding
  • IMCs may degrade either or both the strength of the physical connection between dies and the performance (i.e., resistance) of the electrical connection between the dies and may contribute a shortened 3D-IC life or even premature failure of the 3D-IC.
  • the formation of post-thermocompression bonding IMCs in redistribution layers may be reduced or even eliminated by disposing a diffusion barrier across at least a portion of the redistribution layer prior to physically and electrically coupling the dies within the stack.
  • the diffusion barrier effectively seals the redistribution layer and may prevent the formation of IMCs caused when the liquefied solder attacks the interconnect between the dies. For example, IMCs created when liquefied solder seeps into the redistribution layer.
  • the presence of the diffusion barrier on the redistribution layer of the lower chip effectively prevents the solder from consuming the interconnect between the dies, thereby causing premature failure of the three-dimensional integrated circuit package.
  • the diffusion barrier may be selectively disposed across to all or a portion of the redistribution layer. At times, the diffusion barrier may be applied to the redistribution layer using one or more plating processes, for example an electro-less plating process that beneficially does not require additional patterning layers.
  • a three-dimensional integrated circuit may include a first die that includes a number of semiconductor devices.
  • the first die may include a redistribution layer having at least one exposed surface and disposed proximate at least a portion of the first die and communicably coupled to at least one of the number of semiconductor devices in the first die.
  • the first die may additionally include a diffusion barrier disposed proximate at least a portion 01 tne redistribution layer, the diffusion barrier including at least one electrically conductive path to the redistribution layer and extending across at least a portion of the at least one exposed surface of the redistribution layer.
  • a three-dimensional integrated circuit fabrication method may include communicably coupling a redistribution layer to a number of semiconductor devices disposed in, on, or about a first die. The method may further include depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer and extending across the at least one exposed surface of the redistribution layer. The method may additionally include providing an electrically conductive path to the redistribution layer, the electrically conductive path proximate at least a portion of the diffusion barrier.
  • a three-dimensional integrated circuit system may include a means for communicably coupling a redistribution layer to a number of semiconductor devices disposed in, on, or about a first die.
  • the system may further include a means for depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer and extending across the at least one exposed surface of the redistribution layer.
  • the system may additionally include a means for providing an electrically conductive path to the
  • the electrically conductive path proximate at least a portion of the diffusion barrier.
  • FIG. 1A is a cross-sectional view of a semiconductor device 100 that includes a redistribution layer 104 at least partially covered by a diffusion barrier 106, in accordance with at least one embodiment of the present disclosure.
  • semiconductor devices 100 may provide a layer within a three-dimensional integrated circuit (3D-IC).
  • the redistribution layer 104 is disposed on or across at least a portion of a first die 102 and is electrically conductively coupled to any number of electronic components and/or semiconductor devices in, on, or across the first die 102.
  • at least a portion of the diffusion barrier 106 may be covered by an electrically non-conductive dielectric layer 108.
  • an electrically conductive path 110 may be formed through the dielectric layer 108.
  • the electrically conductive path 110 may conductively couple the redistribution layer 104 to one or more systems or devices, such as one or more stacked second dies, that are stacked above or otherwise positioned external to the first die 102.
  • the electrically conductive path 110 may include a void or similar aperture that provides access through the dielectric layer 108 to the redistribution layer 104.
  • the electrically conductive path 1 lw may oe a soiaer, copper, or noble metal electrical contact, disc, pad, or similar device physically coupled to the diffusion barrier 106 and conductively coupled to the redistribution layer 104.
  • the electrically conductive path 110 includes an electrical contact, a joint, crevice, or seam 112 may be formed between the dielectric layer 108 and the electrical contact.
  • the first die 102 may include any number or type of electronic components or semiconductor devices.
  • the first die 102 may include electronic components such as resistors, capacitors, and inductors.
  • the first die 102 may include one or more semiconductor devices such as diodes, transistors, and similar.
  • the first die 102 may include electronic components and semiconductor devices configurable to provide one or more specialized and particular configurable circuits or machines. For example, the electronic components and
  • semiconductor devices in, on, or about the first die 102 may be coupled or otherwise connected in a manner that provides one or more circuits capable of executing a machine- readable instruction set.
  • the machine-readable instruction set may transform at least a portion of the electronic components and semiconductor devices in, on, or about the first die 102 into a specialized circuit or particular machine that performs a specific function or achieves a particular objective.
  • Such specialized circuits or particular machines may include, without limitation, one or more processing cores, one or more microprocessors, one or more systems on a chip (SoCs), one or more application specific integrated circuits (ASICs), one or more digital signal processors (DSPs), one or more field programmable gate arrays (FPGAs), or similar.
  • the one or more specialized circuits or particular machines in, on, or about the first die 102 may receive input in the form of signals or data.
  • signals or data may be generated or otherwise provided by one or more devices, such as one or more sensors or one or more storage devices disposed external to the first die 102.
  • the signals or data may be received by the first die 102 via the one or more redistribution layers 104 patterned or otherwise disposed on the first die 102.
  • the one or more redistribution layers 104 may be selectively electrically coupled to a number of electronic components or semiconductor devices in, on, or about the first die 102.
  • the redistribution layer 104 may relocate bond pads for one or more electronic or semiconductor devices in, on, or about the first die 102.
  • the redistribution layer 104 may include a conductive layer placed over the surface of the first die 102.
  • the redistribution layer 104 may be patterned and metallized to proviae new oonu paas at new locations on or about the first die 102. Such pads may facilitate or otherwise assist in the construction of stacked dies, such as stacked dies used in 3D-IC fabrication.
  • the redistribution layer 104 may be electrically isolated from the first die 102, except at locations such as connections or bond pads to electronic components or semiconductor devices in, on, or about the first die 102.
  • a uniform or a patterned insulative layer such as a nitride layer, may be selectively disposed or otherwise deposited across all or a portion of the first die 102.
  • Such an insulative layer may be used to selectively electrically isolate all or a portion of the redistribution layer 104 from electronic components or semiconductor devices in, on, or about the first die 102.
  • the redistribution layer 104 may include one or more conductive materials, such as copper or copper containing alloys.
  • a diffusion barrier 106 may be selectively disposed or deposited across all or a portion of one or more exposed surfaces of the redistribution layer 104. In some embodiments, the diffusion barrier 106 may be more- or-less uniformly distributed across all or a portion of the redistribution layer 104.
  • the diffusion barrier 106 may include a layer composed of one or more electrically conductive materials.
  • the diffusion barrier 106 may include one or more barrier materials (e.g. , a barrier metal) that chemically isolates the interconnection to the redistribution layer 104 from liquefied solder used to interconnect the first die to one or more second or stacked dies.
  • the diffusion barrier 106 may provide an electrical connection between the redistribution layer 104 and the liquefied solder.
  • the diffusion barrier 106 may prevent the formation of intermetallic compounds in the redistribution layer 104. When present, such intermetallic compounds may contaminate, physically weaken, or compromise the electrical properties of the interconnection between the first die 102 and one or more second or stacked dies.
  • the diffusion barrier 106 may have a relatively high electrical conductivity characteristic of an electrical conductor in order to provide a low resistance electrical connection to both the liquefied solder and the copper containing redistribution layer 104.
  • the material forming the diffusion barrier may also maintain a low copper diffusivity to chemically isolate the copper containing redistribution layer 104 from the liquefied solder forming the connection to one or more stacked dies.
  • the thickness of the diffusion barrier 106 may depend, at times, on the material used to provide the diffusion barrier 106. Generally, the diffusion barrier 106 may be sufficiently thick to prevent contamination oi tne underlying redistribution layer 104 and may be sufficiently thin to maintain an acceptable resistance.
  • the diffusion barrier 106 may have a thickness of about 0.05 micrometers ( ⁇ ) or less; about 0.1 ⁇ or less; about 0.5 ⁇ or less; about 1 ⁇ or less; about 1.5 ⁇ or less; or about 2 ⁇ or less.
  • the diffusion barrier 106 may include one or more electrically conductive metals, one or more electrically conductive ceramics, or combinations thereof. In some instances, the diffusion barrier 106 may include one or more non-solder wettable materials - such materials may inhibit the flow of solder across the surface of the diffusion barrier.
  • Non- limiting example diffusion barriers 106 may include aluminum, gold, chromium, nickel, nichrome, tantalum, hafnium, niobium, zirconium, vanadium, tungsten, ruthenium, tantalum nitride, indium oxide, copper silicide, tungsten nitride, titanium nitride, cobalt, or compounds containing one or more of the above. In some instances, one or more dopants may be added to the diffusion barrier 106.
  • the diffusion barrier 106 may be applied to the redistribution layer 104 using any current or future developed deposition, plating, or coating technology.
  • the diffusion barrier 106 may be electro-less plated on or across all or a portion of the redistribution layer 104.
  • An example electro-less plating system to deposit the diffusion barrier 106 on the redistribution layer 104 may include, but is not limited to, a process including a cleaning bath, an activation bath, and a plating bath.
  • the plating bath may include an ion-exchange bath.
  • the electro-less plating system permits the selective deposition of the diffusion barrier 106 on or across all or a portion of the exposed surfaces of the redistribution layer 104.
  • the dielectric layer 108 may be selectively or uniformly disposed across all or a portion of the redistribution layer 104.
  • dielectric materials include nitrides (e.g. , silicon nitride), oxides (e.g. , silicon oxide), or organic polymers.
  • the dielectric layer 108 may be patterned and thus may be selectively deposited or coextensive with all or a portion of the redistribution layer 104.
  • the dielectric layer 108 may be disposed more or less uniformly across the first die 102, including across all or a portion of the redistribution layer 104.
  • the dielectric layer 108 may be patterned to provide a void, aperture, or device providing similar access to the diffusion barrier 106 beneath the dielectric layer 108. Such patterning of the dielectric layer 108 may be performed using a photoresist process in which an open hole providing the electrically conductive path 110 through the dielectric layer 108 to the diffusion layer 106.
  • An example photoresist process may inciuae photoresist patterning, etching, and photoresist removal from the dielectric layer 108.
  • the etchant used in the photoresist process may attack the joint where the dielectric layer 108 extends from the redistribution layer 104 to the surface of the first die 102.
  • the etchant tends to concentrate in the joint at the juncture of the redistribution layer 104 and the surface of the first die 102.
  • a seam defect that compromises the integrity of the dielectric layer may form where the etchant penetrates through the joint.
  • the etchant may contact and chemically attack or physically comprise the integrity of the redistribution layer 104 or the diffusion barrier 106.
  • FIG. IB is a cross-sectional view of a stacked, three-dimensional integrated circuit
  • (3D-IC) device that includes a first die 102 as described in detail above with regard to FIG. 1A and a second die 120, in accordance with at least one embodiment of the present disclosure.
  • solder 122 electrically and physically couples a pad 124 on the second die 120 to the redistribution layer 104 on the first die 102.
  • the solder 122 physically and electrically couples to a contact or pad 124 to one or more semiconductor devices in or on the second die 120.
  • the second die 120 may include any number or type of electronic components or semiconductor devices.
  • the second die 120 may include electronic components such as resistors, capacitors, and inductors.
  • the second die 120 may include one or more semiconductor devices such as diodes, transistors, and similar.
  • the second die 120 may include electronic and semiconductor components configurable to perform one or more specialized functions and/or provide one or more particular circuits or machines.
  • the second die 120 may include electronic components and semiconductor devices suitable for providing a data storage device such as a random access memory (RAM), dynamic random access memory (DRAM), ferroelectric RAM (FeRAM), conductive-bridging RAM (CBRAM), parallel random-access machine (PRAM), silicon-oxide-nitride-oxide-silicon (SONOS), resistive RAM (RRAM), domain wall memory (DWM), nano-RAM (NRAM), or combinations thereof.
  • RAM random access memory
  • DRAM dynamic random access memory
  • FeRAM ferroelectric RAM
  • CBRAM conductive-bridging RAM
  • PRAM parallel random-access machine
  • SONOS silicon-oxide-nitride-oxide-silicon
  • RRAM resistive RAM
  • NRAM nano-RAM
  • the one or more configurable circuits provided by the second die 120 may communicate with the first die and may provide data to one or more processing cores on the first die 102.
  • the electrical contact 110 may provide a logic/memory interface (LMI) between one or more logic devices (e.g. , processing cores) in, on, or about the first die 102 and one or more memory or storage devices (e.g. , RAM in, on, or aooui ine second die 120.
  • LMI logic/memory interface
  • a number of electrical components or semiconductor devices in, on, or about the second die 120 may electrically conductively couple to a pad 124 or similar electrically conductive structure that facilitates the physical bonding of the second die 120 with the first die 102 and the electrical coupling of the electronic components and semiconductor devices in, on, or about the second die 120 with the electronic components and semiconductor devices in, on, or about the first die 102.
  • a solder ball or similar structure may be physically coupled to the pad 124 to facilitate the electrical and physical coupling of the second die 120 to the first die 102.
  • FIG. 1 C is a cross-sectional electron micrograph showing the first die 102, the redistribution layer 104, the diffusion barrier 106, the second die 120, and the solder 122 that physically and electrically couples the first die 102 to the pad 124 on the second die 120, in accordance with at least one embodiment of the present disclosure.
  • FIG. 2A is a cross-sectional view of a semiconductor device 200 that includes a redistribution layer 104 at least partially covered by a diffusion barrier 106 and an electrically conductive path 110 in the form of a patterned electrical contact 210, in accordance with at least one embodiment of the present disclosure.
  • the electrical contact 210 may be patterned directly on a portion of the diffusion barrier 106.
  • the solder 122 may preferentially bond to the electrical contact 210 while the non-solder wettable diffusion layer 106 minimizes the flow of solder 122 beyond the electrical contact 210.
  • Such a configuration may eliminate the need for a patterned dielectric layer 104 on the diffusion barrier 106.
  • the elimination of the dielectric layer 108 in the embodiment depicted in FIG. 2A may beneficially eliminate the possibility of seam defects in the dielectric layer 108 discussed above.
  • the electrical contact 210 may include one or more pads, contacts, or similar structures deposited on at least a portion of the diffusion barrier 106 and suitable for providing an electrically conductive connection to the redistribution layer 104. In some implementations, the electrical contact 210 may be photolithographed on the surface of the diffusion barrier 106. In some implementations, the electrical contact 210 may include one or more noble metals, such as gold, silver, platinum, or combinations or compounds thereof. In some implementations, the electrical contact 210 may be deposited on ai least a portion of the diffusion barrier 106 using any current or future developed deposition technique that includes, but is not limited to, a plating bath, an ion exchange bath, or the like.
  • the electrical contact 110 may be patterned onto the diffusion barrier 106 ⁇ e.g., using one or more immersion baths) and the electrical contact 110 may be selectively deposited onto the activated portion of the diffusion barrier 106 ⁇ e.g., using an ion exchange bath).
  • FIG. 2B is a cross-sectional view of a stacked, three-dimensional integrated circuit (3D IC) device that includes a first die 102 as described in detail above with regard to FIG. 2 A and a second die 120, in accordance with at least one embodiment of the present disclosure.
  • 3D IC three-dimensional integrated circuit
  • solder 122 electrically and physically couples a pad 124 on the second die 120 to the redistribution layer 104 via the electrical contact 210 on the first die 102.
  • the solder 122 physically and electrically couples to a contact or pad 124 to one or more semiconductor devices in or on the second die 120.
  • FIG. 3 is a high-level flow diagram of an illustrative method 300 of forming a first die that includes a redistribution layer 106 covered at least in part by a diffusion barrier 108, in accordance with at least one embodiment of the present disclosure.
  • the solder 122 used to physically and electrically connect the various dies 102, 120 included in the stack may, on occasion, attack copper and copper containing structures such as redistribution layers 104 in underlying dies. When such an attack occurs, intermetallic compounds may form in the redistribution layer 104, structurally weakening the
  • the method 300 commences at 302.
  • the redistribution layer 104 is communicably coupled to any number of semiconductor devices disposed in, on, or across the first die 102.
  • the first die 102 may include any type or number of semiconductor materials.
  • the first die 102 may include electronic components, such as resistors, capacitors, inductors, and conductive traces that interconnect at least some of the electronic components and semiconductor devices in, on, or across the first die 102.
  • the electronic components and semiconductor devices may be selectively coupleable to provide one or more specialized or particular machines, for example one or more specialized or particular processors or controllers.
  • the electronic components and semiconductor devices may be arranged to form a number of circuits capable of executing one or more macnine-reaaaDie instruction sets.
  • the redistribution layer 104 may electrically couple to at least some of the electrical components and semiconductor devices in, on, or about the first die 102 in manner that permits unidirectional or bidirectional communication between at least a portion of the electrical components and semiconductor devices in, on, or about the first die 102 with one or more external electrical components and semiconductor devices, such as electrical components and semiconductor devices on one or more dies stacked with the first die 102.
  • the redistribution layer 104 may be disposed across the surface of the first die 102 using any current or future developed deposition system, process, or technique such as
  • the diffusion barrier 106 may be disposed proximate and may extending partially or completely across the at least one exposed surface of the redistribution layer 104.
  • the diffusion barrier 104 may include one or more electrically conductive materials that prevents the solder 122 that physically and electrically couples the first die 102 to one or more other dies from attacking the interconnect and forming one or more intermetallic compounds in the redistribution layer 104.
  • the diffusion barrier 106 may be disposed proximate the at least one exposed surface of the redistribution layer 104 using any current or future deposition process, method, or technique, such as electrodeposition, electro-less plating, or similar.
  • a non-limiting illustrative deposition process includes an electro-less plating process in which the redistribution layer 104 is cleaned and activated prior to immersion in a plating bath. Such electro-less plating processes may cause the selective deposition of the diffusion barrier 106 on only areas that have been previously cleaned and activated (e.g. , the exposed surfaces of the redistribution layer 104).
  • the diffusion barrier 106 may include one or more non- solder wettable materials.
  • a non- solder wettable material is a material that resists or inhibits the flow of solder thereupon. Such a material may beneficially assist in limiting the extent of the solder connection to the diffusion barrier 106.
  • Non-limiting example diffusion barriers 106 may include aluminum, gold, chromium, nickel, nichrome, tantalum, hafnium, niobium, zirconium, vanadium, tungsten, ruthenium, tantalum nitride, indium oxide, copper silicide, tungsten nitride, titanium nitride, cobalt, or compounds containing one or more of the above. In some instances, one or more dopants may be added to the diffusion barrier 106.
  • an electrically conductive path 1 10 is provided to the redistribution layer.
  • at least a portion of the dielectric layer 108 disposed proximate and across at least a portion of the redistribution layer 106 may be removed to provide ine electrically conductive path 110.
  • At least a portion of the dielectric layer 108 may be removed, for example using photolithography, such that an aperture through the dielectric layer 108 provides all or a portion of the electrically conductive path 110.
  • an electrically conductive path 110 in the form of an electrically conductive material 210, may be disposed proximate at least a portion of the diffusion barrier 106. The method 300 concludes at 310.
  • FIG. 4 is a high-level flow diagram of an illustrative method 400 of physically and electrically coupling at least a second die that includes a number of semiconductor devices to a first die 102 that includes a redistribution layer 104 and a diffusion layer 106, in accordance with at least one embodiment of the present disclosure.
  • a number of dies may be stacked one atop the other.
  • the solder 122 used to physically and electrically connect the various dies 102, 120 included in the stack may, on occasion, chemically attack copper and copper containing structures such as redistribution layers 104. On occasion, such chemical attack results in the formation of intermetallic compounds (IMCs) within the copper structures.
  • IMCs intermetallic compounds
  • the addition of the diffusion barrier 106 to the redistribution layer 104 has been found to reduce the likelihood of intermetallic compounds formation with the redistribution layer 104, improving the physical strength and electrical conductivity of the resultant 3D-IC.
  • the method 400 commences at 402.
  • a number of electrical components or semiconductor devices in the second die 120 are communicably coupled to a number of electrical components or semiconductor devices in the first die 102.
  • the communicable coupling is performed using solder 122.
  • solder 122 may, at times, take the form of a ball grid array second die 120 that is joined to the first die by application of heat to the stacked package.
  • the communicable coupling may be performed using solder 122 and a number of thru silicon vias linking the number of electronic components or semiconductor devices in, on, or about the second die 120 to the number of electronic components or semiconductor devices in, on, or about the first die 102.
  • the solder used to join the second die 120 to the first die 102 may attack the copper or copper containing redistribution layer 104 on the first die 102.
  • the presence of the diffusion barrier 106 limits the ability of the solder to attack the copper in the redistribution layer 104.
  • FIGs. 1A, IB, 1 C, above ine soiaer izz bonds directly to an electrically conductive diffusion barrier 106 via an electrically conductive path 110 through the dielectric layer 108.
  • the solder 122 bonds to an electrical contact 210 that may be, in turn, physically and electrically coupled to an electrically conductive diffusion barrier 106.
  • the first die 102 may include electronic components and semiconductor devices that when combined, provide one or more circuits such as a single or multi-core microprocessor capable of executing machine-readable instruction sets.
  • the second die 120 may include electronic components and semiconductor devices that, when combined provide one or more circuits such as one or more storage devices capable of storing machine -readable instruction sets or machine-readable data. In such instances, when such devices are combined, the diffusion barrier 108 and the solder 122 form a portion of a logic/memory interface (LMI).
  • LMI logic/memory interface
  • the semiconductor device may include a first die that includes a number of semiconductor devices including a redistribution layer having at least one exposed surface and disposed proximate at least a portion of the first die and communicably coupled to at least one of the number of semiconductor devices in the first die.
  • the semiconductor device may additionally include a diffusion barrier disposed proximate at least a portion of the redistribution layer, the diffusion barrier including at least one electrically conductive path to the redistribution layer and extending across at least a portion of the at least one exposed surface of the redistribution layer.
  • Example 2 may include elements of example 1 where the diffusion barrier may include at least one of: a cobalt containing material or a nickel containing material.
  • Example 3 may include elements of example 2 where the diffusion barrier further comprises an electro-less plated diffusion barrier.
  • Example 4 may include the elements of example 1 and may additionally include a second die that includes a number of semiconductor devices, the number of semiconductor devices in the second die communicably coupled to at least some of the number of semiconductor devices in the first die through the electrically conductive path to the redistribution layer.
  • Example 5 may include the elements of example 4 the first die comprises a logic die in which the number of semiconductor devices provide at least one circuit capable of executing a machine -readable instruction set, the second die comprises a memory die in which the number of semiconductor devices provide at least one storage circuit, ana ine electrically conductive path includes a logic/memory interface.
  • Example 6 may include the elements of example 1 where the electrically conductive path comprises an electrical contact using one or more noble metals or noble metal alloys.
  • Example 7 may include the elements of example 6 where the one or more noble metals comprise at least one of: gold, silver, or platinum.
  • Example 8 may include elements of any of examples 1 through 7 where the diffusion barrier comprises at least one non-solder wettable material.
  • Example 9 may include elements of any of examples 1 through 5 and may additionally include a dielectric layer disposed proximate at least a portion of the diffusion barrier, where the electrically conductive path comprises an aperture that penetrates through the dielectric layer to the diffusion barrier.
  • Example 10 may include elements of example 9 where the electrically conductive path further comprises a solder cap physically and electrically coupled to the diffusion barrier, the solder cap forming a seam with the dielectric layer.
  • the semiconductor fabrication method may include communicably coupling a redistribution layer to a number of semiconductor devices disposed in, on, or about a first die.
  • the method may additionally include depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer and extending across the at least one exposed surface of the redistribution layer.
  • the method may further include providing an electrically conductive path to the redistribution layer, the electrically conductive path proximate at least a portion of the diffusion barrier.
  • Example 12 may include elements of example 11 where depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer may include depositing a diffusion barrier that includes at least one non-solder wettable material proximate at least a portion of an exposed surface of the redistribution layer.
  • Example 13 may include elements of example 12 where depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer may include depositing a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on at least a portion of the exposed surface of the redistribution layer.
  • Example 14 may include elements example 13 where depositing a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material proximate on at least a portion of the exposed surface of the redistribution layer may inciuae electro-less plating a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on at least a portion of the exposed surface of the redistribution layer may inciuae electro-less plating a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on at least a portion of the exposed surface of the
  • Example 15 may include elements of example 14 where depositing a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on at least a portion of the exposed surface of the redistribution layer may include: cleaning the exposed surface of the redistribution layer, activating the exposed surface of the
  • redistribution layer depositing the cobalt containing material or nickel containing material across at least a portion of the activated exposed surface of the redistribution layer.
  • Example 16 may include elements of example 11 and may further include electrically conductively coupling through the electrically conductive path the number semiconductor devices in the first die to a number of semiconductor devices in a second die stacked proximate at least a portion of the first die.
  • Example 17 may include elements of example 16 where electrically conductively coupling through the electrically conductive path the number semiconductor devices in the first die to a number of semiconductor devices in a second die may include soldering the number of the semiconductor devices in the second die to the number semiconductor devices in the first die through the electrically conductive path.
  • Example 18 may include the elements of example 16 where communicably coupling a redistribution layer to a number of semiconductor devices disposed in, on, or about a first die comprises communicably coupling a redistribution layer to a number of semiconductor devices disposed in a logic die in which the number of semiconductor devices provide a circuit capable of executing machine-readable instruction sets, where electrically
  • conductively coupling the number semiconductor devices in the first die to a number of semiconductor devices in a second die comprises electrically conductively coupling the number of semiconductor devices in the first die to the number semiconductor devices in the second die, the number semiconductor devices in the second die providing one or more data storage circuits or structures.
  • Example 19 may include elements of example 11 where providing an electrically conductive path to the redistribution layer may include patterning an electrical contact that may include a noble metal or a noble metal alloy on the diffusion barrier.
  • Example 20 may include elements of example 19 where patterning an electrical contact comprising a noble metal or a noble metal alloy on the diffusion barrier may include patterning an electrical contact comprising at least one of: a gold containing material, a suver containing material, or a platinum containing material on the diffusion barrier.
  • Example 21 may include elements of any of examples 11 through 20 where providing an electrically conductive path to the redistribution layer may include disposing a dielectric layer proximate at least a portion of the diffusion barrier, patterning an aperture through the dielectric layer using a photoresist material, and etching the aperture through the dielectric layer, the aperture providing the electrically conductive path to the diffusion barrier.
  • the semiconductor system may include a means for communicably coupling a redistribution layer to a number of semiconductor devices disposed in a first die.
  • the system may further include a means for depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer and extending across the at least one exposed surface of the redistribution layer.
  • the system may additionally include a means for providing an electrically conductive path to the redistribution layer, the electrically conductive path proximate at least a portion of the diffusion barrier.
  • Example 23 may include elements example 22 where the means for depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer may include a means for depositing a diffusion barrier that includes at least one non-solder wettable material proximate at least a portion of an exposed surface of the redistribution layer.
  • Example 24 may include elements of example 23 where the means for depositing a diffusion barrier proximate at least a portion of an exposed surface of the redistribution layer may include a means for depositing a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on the portion of the exposed surface of the redistribution layer.
  • Example 25 may include elements of example 24 where the means for depositing a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on the portion of the exposed surface of the redistribution layer may include a means for electro-less plating a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on the portion of the exposed surface of the redistribution layer.
  • Example 26 may include elements of example 25 where the means for electro-less plating a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on the portion of the exposed surface of the redistribution layer may include: a means for cleaning the exposed surface of the redistribution layer, a means ior activating the exposed surface of the redistribution layer, and a means for depositing the cobalt containing material or nickel containing material across at least a portion of the activated exposed surface of the redistribution layer.
  • the means for electro-less plating a diffusion barrier including at least one of: a cobalt containing material or a nickel containing material on the portion of the exposed surface of the redistribution layer may include: a means for cleaning the exposed surface of the redistribution layer, a means ior activating the exposed surface of the redistribution layer, and a means for depositing the cobalt containing material or nickel containing material across at least a portion of the activated exposed surface of the red
  • Example 27 may include elements of example 22 and may additionally include a means for electrically conductively coupling through the electrically conductive path the number semiconductor devices in the first die to a number of semiconductor devices in a second die stacked proximate at least a portion of the first die.
  • Example 28 may include elements of example 27 where the means for electrically conductively coupling a number of the semiconductor devices in a second die to the number semiconductor devices in the first die may include a means for electrically coupling the number of the semiconductor devices in the second die to the number semiconductor devices in the first die through the electrically conductive path.
  • Example 29 may include elements of example 27 where the means for communicably coupling a redistribution layer to a number of semiconductor devices disposed in, on, or about a first die may include a means for communicably coupling a redistribution layer to a number of semiconductor devices disposed in a logic die in which the number of
  • semiconductor devices provide a circuit capable of executing machine-readable instruction sets and where the means for electrically conductively coupling the number semiconductor devices in the first die to a number of semiconductor devices in a second die may include a means for electrically conductively coupling the number of semiconductor devices in the first die to the number semiconductor devices in the second die, the number semiconductor devices in the second die providing one or more data storage circuits or structures.
  • Example 30 may include elements of example 22 where the means for providing an electrical coupling to the redistribution layer may include a means for patterning an electrically conductive cap comprising a noble metal or a noble metal alloy on the portion of the diffusion barrier.
  • Example 31 may include elements of example 30 where the means for patterning an electrical contact comprising a noble metal or a noble metal alloy on the diffusion barrier may include a means for patterning an electrical contact comprising at least one of: a gold containing material, a silver containing material, or a platinum containing material on the diffusion barrier.
  • Example 32 may include elements of any of examples 22 through 31 where the means for providing an electrically conductive path to the redistribution layer may include a means for disposing a dielectric layer proximate at least a portion of the diffusion Darner, a means for patterning an aperture through the dielectric layer using a photoresist material, and a means for etching the aperture through the dielectric layer, the aperture providing the electrically conductive path to the diffusion barrier.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne des circuits intégrés tridimensionnels qui comprennent un certain nombre de puces empilées et interconnectées. Dans certains cas, la brasure utilisée pour connecter les puces peut attaquer les points d'interconnexion, en particulier quand ces points d'interconnexion comprennent des matériaux contenant du cuivre. Dans ce cas, la formation de composés intermétalliques en conséquence de l'attaque chimique de la structure contenant du cuivre par la brasure liquéfiée peut être réduite ou même éliminée par utilisation d'une barrière de diffusion. La barrière de diffusion peut être disposée sur l'ensemble ou une partie de la surface apparente des structures contenant du cuivre, telles que des couches de redistribution sur une première puce. Une couche diélectrique peut être disposée sur l'ensemble de la barrière de diffusion et un chemin électroconducteur, qui comprend une ouverture à travers la couche diélectrique, peut être ménagé. Un chemin électroconducteur qui comprend un matériau mouillable par la brasure peut être disposé sur la barrière de diffusion.
PCT/US2015/052289 2015-09-25 2015-09-25 Barrière de diffusion de couche de redistribution WO2017052605A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2015/052289 WO2017052605A1 (fr) 2015-09-25 2015-09-25 Barrière de diffusion de couche de redistribution
TW105125181A TW201721780A (zh) 2015-09-25 2016-08-08 重新分配層擴散阻障

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/052289 WO2017052605A1 (fr) 2015-09-25 2015-09-25 Barrière de diffusion de couche de redistribution

Publications (1)

Publication Number Publication Date
WO2017052605A1 true WO2017052605A1 (fr) 2017-03-30

Family

ID=58386927

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/052289 WO2017052605A1 (fr) 2015-09-25 2015-09-25 Barrière de diffusion de couche de redistribution

Country Status (2)

Country Link
TW (1) TW201721780A (fr)
WO (1) WO2017052605A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110931442A (zh) * 2018-09-19 2020-03-27 台湾积体电路制造股份有限公司 电子装置及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000065487A (ko) * 1999-04-06 2000-11-15 윤종용 칩 스케일 패키지
JP2004363319A (ja) * 2003-06-04 2004-12-24 Toshiba Corp 実装基板及び半導体装置
US20110045668A1 (en) * 2009-08-18 2011-02-24 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing wafer level device package
US20120025383A1 (en) * 2010-07-28 2012-02-02 International Business Machines Corporation Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure
US20130119527A1 (en) * 2011-11-14 2013-05-16 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000065487A (ko) * 1999-04-06 2000-11-15 윤종용 칩 스케일 패키지
JP2004363319A (ja) * 2003-06-04 2004-12-24 Toshiba Corp 実装基板及び半導体装置
US20110045668A1 (en) * 2009-08-18 2011-02-24 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing wafer level device package
US20120025383A1 (en) * 2010-07-28 2012-02-02 International Business Machines Corporation Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure
US20130119527A1 (en) * 2011-11-14 2013-05-16 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110931442A (zh) * 2018-09-19 2020-03-27 台湾积体电路制造股份有限公司 电子装置及其制造方法

Also Published As

Publication number Publication date
TW201721780A (zh) 2017-06-16

Similar Documents

Publication Publication Date Title
TWI402939B (zh) 包含一矽貫通電極之積體電路結構及形成該積體電路結構之方法
TWI223427B (en) Interconnections to copper ICS
JP5284314B2 (ja) 小型電子機器、その形成方法、およびシステム
TWI594385B (zh) 半導體元件及其製造方法
TWI625835B (zh) 半導體裝置及其製作方法
US8039385B1 (en) IC devices having TSVS including protruding tips having IMC blocking tip ends
US9966347B2 (en) Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
US9721886B2 (en) Preservation of fine pitch redistribution lines
US20080303154A1 (en) Through-silicon via interconnection formed with a cap layer
TW201140783A (en) Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
TW201128753A (en) Semiconductor devices, packaging assemblies, and method for manufacturing semiconductor devices
TW200843064A (en) Surface structure of a packaging substrate and a fabricating method thereof
KR102574452B1 (ko) 반도체 칩 및 이를 포함하는 반도체 패키지
EP3275009A1 (fr) Plot de connexion métallique à couche d'interconnexion de cobalt et pâte à braser sur celui-ci
US9627335B2 (en) Method for processing a semiconductor workpiece and semiconductor workpiece
TW201133708A (en) Vias and conductive routing layers in semiconductor substrates
JP5248627B2 (ja) 半導体のマイクロパッド形成方法
WO2017052605A1 (fr) Barrière de diffusion de couche de redistribution
CN102254842A (zh) 电镀工艺中的活化处理
JP2008288607A (ja) 電子部品実装構造の製造方法
US8697565B2 (en) Shallow via formation by oxidation
US11302660B2 (en) Semiconductor devices and semiconductor packages including the same
KR101313690B1 (ko) 반도체 소자의 본딩 구조물 형성 방법
US10796956B2 (en) Contact fabrication to mitigate undercut
US20230387051A1 (en) Bonding structures of integrated circuit devices and method forming the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15904940

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE