Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
  • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
  • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the present disclosure relates generally to electronic apparatus, and more particularly, to method and apparatuses for managing entering or exiting of power-down modes for multiple cores.
• a typical electronic apparatus such as a processor within wireless devices, may include various cores operating within different power domains.
• a core may vary from a collection of transistors or circuits to an execution unit. Increasingly, the cores may enter or exit power-down modes at various times to manage power consumption.
• the power-down modes vary and may include a power-collapse mode, in which all power is disconnected from the cores.
• Other power-down modes may include gating the clocks with the cores (e.g., disabling clocking in the cores).
• Yet other power-down modes may include adjusting the operating voltages and frequencies of the cores. While the entering and exiting of the power-down modes may conserve power, such changes of power-down modes may lead to various drawbacks.
• One design challenge is to manage the entering or exiting of the power-down modes for multiple cores and mitigate the drawbacks.
• the apparatus includes a first circuit configured to receive one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The first circuit further selects one or more of the cores to enter or to exit the requested power- down mode or modes based on inrush current information associated with the power- down modes. A second circuit is configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores.
• the method includes receiving one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The method further includes selecting one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes and effecting entering or exiting the requested power-down mode or modes in the selected one or more of the cores.
• the apparatus includes a first circuit configured to receive a plurality of requests from a plurality of cores. Each of the requests is to enter or to exit a plurality of power-down modes. The first circuit further selects ones of the cores to enter or to exit different power-down modes. A second circuit is configured to effect entering or exiting the requested power-down modes in the selected ones of the cores.
• the method includes receiving a plurality of requests from a plurality of cores. Each of the requests is to enter or to exit one of a plurality of power-down modes. The method further includes selecting ones of the cores to enter or to exit the requested power-down modes and effecting entering or exiting the requested power-down modes in the selected ones of the cores.
• FIG. 1 is a block diagram of an exemplary embodiment of a processor configured to mange entering or exiting of power-down modes for multiple cores based on inrush current information.
• FIG. 2 is a block diagram of an exemplary embodiment of the power manager of
• FIG. 1 operating as a token manager.
• FIG. 3 is a timing diagram of the operations of requesting and granting tokens.
• FIG. 4 is a flowchart of operations of an exemplary embodiment of the power manager control selecting one or more cores to grant requests.
• FIG. 5 is a block diagram of an exemplary embodiment of the power manager control.
• any of these apparatus or methods may be implemented as an integrated circuit, or as part of an integrated circuit.
• the integrated circuit may be an end product, such as a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), programmable logic, or any other suitable integrated circuit.
• DSP digital signal processor
• ASIC application specific integrated circuit
• the integrated circuit may be integrated with other chips, discrete circuit elements, and/or other components as part of either an intermediate product, such as a motherboard, or an end product.
• the end product can be any suitable product that includes integrated circuits, including by way of example, a cellular phone, personal digital assistant (PDA), laptop computer, a desktop computer (PC), a computer peripheral device, a multimedia device, a video device, an audio device, a global positioning system (GPS), a wireless sensor, or any other suitable device.
• a cellular phone personal digital assistant (PDA), laptop computer, a desktop computer (PC), a computer peripheral device, a multimedia device, a video device, an audio device, a global positioning system (GPS), a wireless sensor, or any other suitable device.
• PDA personal digital assistant
• PC desktop computer
• GPS global positioning system
• wireless sensor or any other suitable device.
• connection may include a signal line.
• connection may include a signal line.
• connected means any connection or coupling, either direct or indirect, between two or more elements, and can encompass the presence of one or more intermediate elements between two elements that are “connected” or “coupled” together.
• the coupling or connection between the elements can be physical, logical, or a combination thereof.
• two elements can be considered to be “connected” or “coupled” together by the use of one or more wires, cables and/or printed electrical connections, as well as by the use of electromagnetic energy, such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region and the optical (both visible and invisible) region, as several non- limiting and non-exhaustive examples.
• any reference to an element herein using a designation such as "first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.
• an apparatus with circuits for managing the entering or exiting of power-down modes for multiple cores may be a processor for wireless communication application.
• the apparatus may include a power management circuit configured to select the cores for entering or exiting power-down modes based on inrush current information.
• the power management circuit is configured as a token manager receiving requests from the cores for entering or exiting power-down modes and issuing tokens to the selected cores to grant the requests.
• aspects and applications of the disclosure may not be limited to the described exemplary embodiments.
• the apparatus of present disclosure is not limited to a processor, and the power management circuit is not limited to the token manger. Accordingly, all references to a specific application are intended only to illustrate exemplary aspects of the memory with the understanding that such aspects may have a wide differential of applications.
• FIG. 1 is a block diagram of an exemplary embodiment of a processor 100 configured to mange entering or exiting of power-down modes for multiple cores based on inrush current information.
• the processor 100 may be, for example, a processor for wireless communication.
• an exemplary apparatus may include the processor 100 or a cell phone incorporating the processor 100.
• the processor 100 may be a stand along processor or integrated in an end product, such as mobile phone, desktop computer, laptop computer, tablet computer, or the like.
• the processor 100 includes cores 110 (110-1, 110-2, 110-3, and 110-4).
• a core may be, for example, a collection of circuits.
• the cores 110 may be processor or execution units executing instructions.
• the processor 100 may further include additional function blocks (not shown for clarity) such as a graphic processor unit, a digital signal processors (DSP), a wireless modem, and a wireless local area network or WLAN block interfacing with the cores 110.
• DSP digital signal processors
• WLAN wireless local area network or WLAN block interfacing with the cores 110.
• Each of the cores 110 may include a power-down mode circuit 104 (104-1, 104-
• the power-down mode circuits 104 may effect the corresponding cores 110 to enter or to exit various power-down modes. Thus, the power-down mode circuits 104 may cause the corresponding cores 110 to power up from a power-down mode, to power down to a power-down mode, or to transition among the various power-down modes.
• Examples of the power-down modes may include a power-collapse mode, in which all power is disconnected from the cores. Accordingly, the power-collapse mode may draw no current as all power is disconnected.
• Other power-down modes may include a clock-gating mode that disables clocking in the cores.
• Yet other power-down modes may include adjusting the operating voltages and frequencies of the cores. The entering and the exiting of the various power-down modes may take different amount of time. For example, entering and exiting the power-collapse mode may take more cycles than the other power-down modes.
• the power-down mode circuits 104 may effect the corresponding core 110 to enter into the power-collapse mode or the clock-gating mode (e.g., powering down the core 110).
• the power-down mode circuit 104 may likewise effect the core 110 to exit the power-down modes and return to full-power operations (e.g., powering up the core 110).
• the power-down mode circuit 104 may effect the corresponding core 110 to transition among the power-collapse mode and the clock- gating mode.
• the processor 100 further includes the power manager 105, the inrush current information storage 120, and the power-down mode priority storage 122.
• the power manager 105 may be configured to select among the cores 110 for entering or exiting power-down modes by selectively controlling the power-down mode circuits 104.
• the power manager 105 may include a processor (such as one of the cores 110) executing software instructions.
• the power manager 105 may select among the cores 110 based on inrush current information stored in the inrush current information storage 120 and/or the power-down mode priorities stored in the power- down mode priority storage 122.
• the stored inrush current information and/or the power-down mode priorities may be programmable (e.g., changed by software instructions).
• the inrush current information storage 120 may be, for example, registers storing inrush current information including inrush current caused by entering or exiting the various power-down modes.
• the process of entering and exiting the various power- down modes may cause inrush current in the cores 110 to spike, even to the point of exceeding the capability of current supplies to the cores 110.
• the power manager 105 may determine a number and an order of the cores 110 to be selected for entering or exiting the power-down modes efficiently without causing excessive inrush current.
• the power-down mode priority storage 122 may be, for example, registers storing power-down mode priorities.
• the priorities may be, for example, based on the times to enter or to exit the power-down modes. For example, the power-collapse mode may take the longest to enter or to exit, and therefore, the power-collapse mode may have the lowest priority. In some examples, the priorities may be based on power saving of the power-down modes.
• the power manager 105 may further receive an inrush current budget and select the cores 110 based on the inrush current budget.
• the inrush current budget may be based on the current limit of the power supply (e.g., the power management integrated circuit or PMIC).
• the inrush current budget may be further based on present operations of the cores, even the cores not requesting to enter or to exit the power-down modes. For example, in the cases some of the cores are operating in high performance modes (thus consuming more power), the inrush current budget may be reduced.
• FIG. 2 is a block diagram of an exemplary embodiment of the power manager
• a token may be a signaling indicating a grant or allowance to enter or exit power-down modes.
• the power manager 105 includes a power manager control 205 configured to receive one or more requests to enter or to exit power-down modes from the cores 110 (core 110-1 to core 110-4). Each of the one or more requests indicates that one of the cores wishes to enter or to exit one of the power-down modes.
• the multiple cores 110 may send the requests to enter or to exit the power-down modes independently and in parallel.
• the core 110-1 may request a power- up from a power-collapse mode.
• the core 110-2 may request a power-down from a full-power operation to a clock-gating mode.
• the 110-3 may request transitioning from the power-collapse mode to the clock-gating mode, and so forth. All the requests may be made at the same time. As described above, enacting all the requests to enter or to exit the power-down modes in the multiple cores 110 may cause the inrush current to spike.
• the power manager control 205 may be further configured to select one or more of the cores 110 to grant to tokens so as not to cause the inrush current to spike exceeding an inrush current threshold (e.g., the inrush current budget). Additional features of this selection process are presented with FIGs. 4-5.
• the process of requesting and granting the token is described below.
• the power manager 105 e.g., the power manager control 205 communicate with the cores 110 via the signaling REQ 206 (206-1 to 206-4 for each of the cores 110) and the signaling ACK 207 (207-1 to 207-4 for each of the cores 110).
• each of the cores 110 may independently and in parallel request a token from the power manager 105 by asserting the signaling REQ 206.
• the signaling REQ 206 may be carried by multiple signals lines to indicate the desired action and the desired resulting power-down mode (e.g., indicating the desire to exit from the current power-down mode to a full-power operation, to enter a desired power-down mode, the identity of the desired power-down mode, etc.).
• the power manager 105 receives the signaling REQ 206.
• the signaling REQ 206 is provided as input to logic gates or components within the power manager control 205.
• the power manager 105 asserts the signaling ACK 207 (207-1 to 207-4 for each of the cores 110).
• the power-down mode circuits 104 of the selected cores 110 effect the requested power-down actions (e.g., to enter or to exit power-down modes).
• the power-down mode circuit 104 de-asserts both the signaling REQ 206 (to terminate the request) and the signaling ACK 207 (to indicate a completion of the requested power-down action).
• the power manager 105 further includes the token register 230 and the core status register 240 to manage the requests and the tokens.
• the token register 230 includes multiples bits (231 to 234), each of which corresponds to one of the cores 110.
• the bits 231-234 indicate that a request for token from the corresponding cores 110 is active.
• the bit 231 stores the value "1" to indicate that the corresponding core 110-1 is requesting a token (e.g., the signaling REQ 206-1 is asserted).
• the bits 233 and 234 store the value "0" to indicate that the corresponding cores 110-3 and 110- 4 are not requesting a token (e.g., the signaling REQ 206-2 to 206-4 are de-asserted).
• the core status register 240 stores the current power-modes of the cores.
• the core status register 240 includes bits 240-1 to 240-4, each of which corresponds to one of the cores 110.
• the bit 240-1 stores the value CO, indicating that the core 110-1 is in the full-power operation state.
• the 240-2 stores the value CI, indicating that the core 110-2 is in the power-collapse mode.
• the 240-3 stores the value C2, indicating that the core 110-2 is in clock-gating mode, and so forth.
• the power manager 105 Via the token register 230 and the core status register 240, the power manager 105 is able to keep track the current states of token requests and status of each of the cores 110 (e.g., full-power operation state or one of the power-down modes).
• FIG. 3 is a timing diagram of the operations of requesting and granting tokens.
• one or more of the cores 110 request a token to enter or to exit power-down modes by asserting (e.g., pulling high) the signaling REQ 206.
• the power manager 105 e.g., the power manager control 205 issues a token to the selected core or cores 110 by asserting (e.g., pulling high) the signaling ACK 207.
• a power-down mode circuit 104 of the selected core or cores effect the requested power- down mode operation.
• the power-down mode circuit 104 causes the corresponding core 110 to power up to the full-power operation state, to power down to one of the power-down modes from the full-power operation state, or to transition among the power-down modes (at A).
• the power-down mode circuit 104 notifies the power manager 105 the release of the token by de-asserting (e.g., pulling low) both the signaling REQ 206 and the signaling ACK 207.
• FIG. 4 is a flowchart of operations of an exemplary embodiment of the power manager control 205 selecting one or more cores 110 to grant requests.
• the operations may be performed by the power manager control 205.
• one or more requests from a plurality of cores are received.
• the power manager control 205 receives the requests by providing the signaling REQ 206 as input to logic gates or components within the power manager control 205.
• each of the one or more requests is a request to enter or to exit one of a multiple of power-down modes. Referring to FIG.
• the power manager control 205 receives token requests from the cores 110 (110-1 to 110-4) by receiving the low state of the signaling REQ 206-1 and the signaling REQ 206-2. The power manager control 205 then saves the requests in the token register 230 by storing "l"s in the bits 231 and 232, indicating respectively that the core 110-1 and 110-2 are requesting to enter or to exit at least one of the power-down modes.
• the power-down modes vary and may include a power-collapse mode, in which all power is disconnected from the cores.
• Other power-down modes may include gating the clocks with the cores (e.g., disabling clocking in the cores).
• Yet other power-down modes may include adjusting the operating voltages and frequencies of the cores.
• the requests to enter or to exit the power-down modes may include, for example, powering- up the requesting core by exiting one of the power-down modes to a full-power operation state and powering-down the requesting core by entering one of the power- down modes from a full-power operation state. Such requests may also include transitioning among the various power-down modes.
• a priority is assigned to each of the cores.
• the assignment may be based on the power-down modes requested by the cores 110 and the power-down mode priorities stored within the power-down mode priority storage 122.
• the priorities may be, for example, based on the times to enter or to exit the power-down modes.
• the power-collapse mode may take the longest to enter or to exit, and therefore, the power-collapse mode may have the lowest priority.
• the power manager control 205 may assign priorities to the cores 110 based on the states of the cores stored in the core status register 240 and the power-down modes indicated by the signaling REQ 206.
• the power manager control 205 may fast-track the selection of cores 110 for granting requests independent of the power-down modes.
• the power manager control 205 may select the cores based on predetermine priorities not based on the power-down modes.
• the predetermine priorities may be a fixed order of core 110-1, core 110-2, core 110-3, and core 110-4.
• the fast- tracked selection is determined to be within an inrush current budget by selecting only one core.
• the inrush current budget may be based on the current limit of the power supply (e.g., PMIC). In some examples, the inrush current budget may be further based on present operations of the cores, even the cores not requesting to enter or to exit the power-down modes. For example, in the cases some of the cores are operating in high performance modes (thus consuming more power), the inrush current budget may be reduced.
• PMIC current limit of the power supply
• the inrush current budget may be further based on present operations of the cores, even the cores not requesting to enter or to exit the power-down modes. For example, in the cases some of the cores are operating in high performance modes (thus consuming more power), the inrush current budget may be reduced.
• one or more of the cores are selected to enter or to exit the requested power-down mode or modes.
• the selection may be based on the priorities assigned in operation 403.
• the selection may be further based on inrush current information associated with the power-down modes. For example, the inrush currents of the highest priorities are compared with the inrush current budget to allow a maximum selection of cores without exceeding the current budge. In such fashion, the number of the selected cores may be determined.
• the selection of cores 110 allows for granting the maximum number of requests from the highest priority cores 110 (e.g., the cores 110 requesting to enter or to exit the power-down modes of highest priorities) within the inrush current budget. Such selection may be made using the inrush current information of the highest priority cores 110.
• the remaining inrush current budget may be utilized by selecting cores 110 of lower priorities (e.g., requesting to enter or exit power-down modes of lower priories) requiring inrush currents within the remaining inrush current budget. In such fashion, the core or cores 110 requesting to enter or to exit a first power-down mode and the core or cores 110 requesting to enter or to exit a second, different power- down mode may be selected concurrently.
• "concurrently” may stand for selecting and/or granting requests for entering or exiting different power-down modes at substantially the same time. In some examples, “concurrently” may stand for selecting and/or granting requests for entering or exiting different power-down modes with substantial, nontrivial overlaps as understood by persons of ordinary skill in the art.
• the power-down mode or modes requested by the selected one or more of the cores are entered or exited.
• the power- down mode circuits 104 of the selected cores 110 e.g., from operations 404 and 408 may cause the selected cores 110 to enter the requested power-down modes or to exit the current power-down mode.
• priorities of unselected ones of the cores are increased.
• the inrush current budget may be increase.
• the power manager control 205 may retum to 408 (via operation 413) to select another core or cores to grant requests.
• Increasing the priorities of the unselected cores which may be of lower priorities to start with, prevents starvation of these cores.
• FIG. 5 is a block diagram of an exemplary embodiment of the power manager control 205.
• the block diagram may be an exemplary embodiment of a hardware implementation of the power manager control 205 and may include various (e.g., hardware and/or software) components. In some examples, theses components described below may include instructions executed by one of the cores 110-1 - 110-4.
• the power manager control 205 and the components contained therein, presented below, may include circuits, processor or processors, software executing on the processor or processors, or combinations thereof. These components may include circuits for generating the signals for the functions described infra or signal lines carrying those signals.
• a component, or any portion of a component, or any combination of components may be implemented with one or more processors.
• processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure.
• DSPs digital signal processors
• FPGAs field programmable gate arrays
• PLDs programmable logic devices
• state machines gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure.
• One or more processors in the processing system may execute software.
• Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
• the power manager control 205 includes the priority assignment component
• the priority assignment component 502 receives the requested power-down modes (to enter or to exit from) and the requesting cores 110 from the request processing component 506.
• the priority assignment component 502 further receives the power-down mode priorities from the programmable power-down mode priority storage 122.
• the priority assignment component 502 assigns priorities to the cores based on the power-down mode priorities (which, for example, may be based on the time to enter or exit the power-down modes)(e.g., operation 403).
• the priority assignment component 502 may increase the priorities of the unselected cores so as not to starve the unselected cores (e.g., operation 412).
• the core selection component 504 receives the assigned priorities of the requesting cores from the priority assignment component 502.
• the core selection component 504 also receives the inrush current information and the inrush current budget.
• the inrush current information may include the inrush current consumed to enter or to exit each of the power-down modes.
• the inrush current information may be received from the inrush current information storage 120 and may be programmable by software.
• the inrush current budget may be a limit based on the power supplied (e.g., the PMIC).
• the inrush current budget may further be adjusted based on the present operations of the cores 110. For example, some of the cores 110 may be engaging the current-consuming operations such that the inrush current budget is reduced.
• the core selection component 504 takes in all the requests and tries to accommodate the maximum number of requests concurrently abiding by the inrush current budget. For example, the core selection component 504 may grant the maximum number of requests from the highest priority cores 110 (e.g., the cores 110 requesting to enter or to exit the power-down modes of highest priorities) within the inrush current budget. Such determination may be made using the inrush current information of the highest priority cores 110. The core selection component 504 may further utilize the remaining inrush current budget by selecting cores 110 of lower priorities (e.g., requesting to enter or exit power-down modes of lower priories) requiring inrush currents within the remaining inrush current budget.
• the core selection component 504 may grant the maximum number of requests from the highest priority cores 110 (e.g., the cores 110 requesting to enter or to exit the power-down modes of highest priorities) within the inrush current budget.
• the core selection component 504 may further utilize the remaining inrush current budget by selecting cores 110 of lower priorities (e.g., requesting to
• the core selection component 504 may select concurrently the core or cores 110 requesting to enter or to exit a first power-down mode and the core or cores 110 requesting to enter or to exit a second, different power-down mode. Accordingly, the core selection component 504 is configured to select the one or more of the cores 110 to grant the power-down mode requests based on an the inrush current budget. Moreover, the number of the one or more of the cores 110 selected is based on the inrush current budget. See, for example, operation 408.
• the core selection component 504 may select requesting cores
• the core selection component 504 may utilize priorities independent of the power-down modes, such as a fixed order core 110-1, core 110-2, core 110-3, and then core 110-4. To ensure that the selection of cores 110 independent of the power-down modes is within the inrush current budget, a limited number (e.g., one) of the cores 110 may be selected in this fashion. See, e.g., operation 404.
• the core selection component 504 may in parallel or subsequently proceed with the selection of the requesting cores 110 based on the power-down modes (operation 408).
• the core selection component 504 receives notification of a completion of one of the selected cores 110 from the request processing component 506. In response, the core selection component 504 may perform the selections described above of the unselected cores 110 and new requesting cores 110. The unselected cores 110 may have increased priorities from the previous selection so as not to starve those cores 110.
• the request processing component 506 interfaces with cores 110 via the signaling REQ 206 and the signaling ACK 207 to receive requests and to grant requests to enter or to exit power-down modes. To grant requests, the request processing component 506 receives the core selection from the core selection component 504. Upon a completion of one of the requests, the request processing component 506 sends the notification to the core selection component 504.

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• 2016
  • 2016-01-29 US US15/010,237 patent/US9886081B2/en active Active
  • 2016-08-30 EP EP16767411.8A patent/EP3350669B1/en active Active
  • 2016-08-30 WO PCT/US2016/049504 patent/WO2017048503A2/en not_active Ceased
  • 2016-08-30 KR KR1020187010548A patent/KR102681069B1/ko active Active
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  • 2016-08-30 CN CN201680053355.4A patent/CN108027636B/zh active Active

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