WO2017045338A1 - 一种使锁相环系统快速锁定的自动频带校准方法 - Google Patents

一种使锁相环系统快速锁定的自动频带校准方法 Download PDF

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WO2017045338A1
WO2017045338A1 PCT/CN2016/073264 CN2016073264W WO2017045338A1 WO 2017045338 A1 WO2017045338 A1 WO 2017045338A1 CN 2016073264 W CN2016073264 W CN 2016073264W WO 2017045338 A1 WO2017045338 A1 WO 2017045338A1
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frequency
frequency band
band
division ratio
calibration
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French (fr)
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吴建辉
丁欣
陈超
黄成�
李红
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02—Automatic frequency control
    • H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
    • H03J7/06—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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  • the invention relates to an automatic frequency band calibration (AFC) method for quickly locking a Phase Locked Loop (PLL) system, and belongs to the communication technology.
  • AFC automatic frequency band calibration
  • phase-locked loop is an important part of the RF transceiver system. More and more applications have higher requirements on the frequency switching speed of the transceiver in operation, which requires the phase-locked loop to be quickly locked.
  • the tuning curve of the Voltage-Controlled Oscillator is often designed into multiple lines, and the tuning gain of each curve is relatively small, so that the loop stability and the large enough frequency can be considered. Coverage.
  • VCO Voltage-Controlled Oscillator
  • the interference of factors such as process and temperature automatically determines the control method of the frequency band. In the traditional scanning search mode, the time spent locking to a specific frequency point is mostly consumed in the search of the frequency band, and is no longer applicable to applications that need fast locking. We must explore a faster and more efficient way to select a band.
  • the present invention provides an automatic band calibration method that facilitates fast locking of a phase locked loop system.
  • An automatic band calibration method for quickly locking a phase locked loop system using an automatic band calibration system for automatic band calibration, the automatic band calibration system is initially in a calibration mode, and the calibration mode is in a working mode after completion;
  • the working process in the calibration mode includes the following steps:
  • step (1.3) judging whether the control voltage signal Vctrl is locked within a limited voltage range by correcting the output value of the window comparator: if there is no lock, the frequency division ratio jumps until the lock; if locked, proceeds to step (1.4);
  • step (1.4) saving the control frequency signal Vctrl locked frequency band i characteristic division ratio actual value Div_data[i], proceeds to step (1.5);
  • step (1.5) If i ⁇ n, adjust the characteristic frequency division ratio of frequency band i+1 according to Eva_data[i] and Div_data[i] Value Eva_data[i+1], enter step (1.6); if i ⁇ n, proceed to step (1.7);
  • the working process in working mode includes the following steps:
  • the output value of the working window comparator determines whether the preset band code Fre_data is correct: if it is not correct, the correction is performed; the upper and lower limits of the correction window comparator output value are within the upper and lower limits of the output value of the working window comparator.
  • the frequency division ratio hopping method is: if the control voltage signal Vctrl is higher than the upper limit voltage of the correction window comparator, the frequency division ratio jumps downward; if the control voltage signal Vctrl is low To correct the lower limit voltage of the window comparator, the division ratio jumps up.
  • the correction is performed by using a frequency band code corresponding to the actual frequency division ratio actual value which is the second closest to the target frequency division ratio Div_in.
  • the band is pre-coded until the preset band is encoded correctly.
  • the digital processing part of the method is implemented by the Verilog language, and the correction window comparator and the working window comparator are implemented by an analog circuit; in order to ensure the stability of the timing and the timeliness of the sampling, the window comparator and the Verilog implemented by the analog circuit are implemented.
  • the clocks of the digital part of the language implementation are uniformly given by the digital part.
  • the clock of the digital part is slightly delayed than the clock of the window comparator to ensure that the control voltage signal Vctrl is processed in time after sampling, and the timing is ensured.
  • the automatic band calibration system is initially in the correction mode, and the working state of the phase locked loop is different from the conventional mode.
  • the traditional phase locked loop adopts the idea of a fixed frequency division ratio, and the feedback control voltage signal Vctrl Change, lock frequency.
  • the method has the following characteristics in the calibration mode: a fixed frequency band, and the output of the correction window comparator controls the frequency division ratio hopping to find a suitable frequency, so that the control voltage signal Vctrl can be locked in a small voltage range.
  • the phase-locked loop lock control voltage signal Vctrl is used to sequentially obtain the characteristic frequency division ratio of each frequency band, thereby realizing the correction of the corresponding characteristic frequency of each frequency band in the actual circuit.
  • the determination of the upper and lower limits of the correction window comparator is related to the nature of the phase-locked loop itself, and the window range is usually small (near the intermediate value of the control voltage signal Vctrl variation range), but it is necessary to ensure that at least one of the phases is locked.
  • the frequency at which the ring system is accurate In order to shorten the correction time, an estimated value is given for the characteristic division ratio of each frequency band, and the estimated value of the next frequency band is corrected based on the correction result of the previous frequency band.
  • the frequency band is automatically determined, and the accurate frequency band coding is directly preset to shorten the locking time.
  • the correction window comparator of the method locks the control voltage signal Vctrl near the intermediate value, and the characteristic division ratio of the frequency band is also about the intermediate value of all the frequency points in the frequency band.
  • the estimation process of automatically selecting the frequency band according to the externally-divided frequency division ratio is to determine which of the characteristic frequencies of the target frequency point is closer, and the frequency band corresponding to the characteristic frequency is the frequency band of the target frequency point.
  • the digital processing part is implemented by the Verilog language, and the correction window comparator and the working window comparator are realized by the analog circuit.
  • the window comparator consists of two analog op amps with a buffer amplifier stage and sample-and-hold logic, and the samples are clocked.
  • the window comparator is configured to convert the size of the control voltage signal Vctrl into a two-digit code: if the control voltage signal Vctrl is higher than the upper limit voltage, output "10"; if the control voltage signal Vctrl is lower than the lower limit voltage, output "01”; if control The voltage signal Vctrl is between the upper and lower voltage limits, and outputs "11".
  • the two-digit code is input to the digital portion for controlling the frequency division ratio or band code transition.
  • the automatic band calibration method for quickly locking the phase-locked loop system provided by the present invention only needs to adopt a correction algorithm different from the conventional idea at the beginning of the whole system startup, and then in the normal working state It can directly and accurately find the frequency band and realize the fast locking of the phase-locked loop.
  • the correction method of the lock control voltage signal Vctrl is used to correct the key points, overcome the adverse effects caused by factors such as process and temperature, and only need a small number of registers to record and calculate correction data of a large number of frequency points. For a phase-locked loop system with more frequency points, it can save resources and achieve fast switching lock.
  • FIG. 1 is a block diagram showing the overall structure of an AFC module in the present invention
  • FIG. 2 is a schematic diagram of an AFC module in the present invention
  • Figure 3 is a flow chart of the digital part algorithm
  • Figure 4 is a schematic diagram of window voltage setting
  • Figure 5 shows the internal digital and comparator clock simulation results (four clocks are reserved during design);
  • Figure 8 shows the normal working phase and automatically estimates the band coding simulation.
  • An automatic band calibration method for quickly locking a phase-locked loop system the AFC module corrects the frequency band of the VCO, and automatically selects a frequency band according to the target frequency point, thereby realizing fast locking of the phase locked loop.
  • the invention adopts closed-loop correction, controls the frequency division ratio jump of the frequency divider, locks the Vctrl voltage by the phase-locked loop loop, sequentially obtains the characteristic frequency division ratio of each frequency band, and realizes the corresponding characteristic frequency of each frequency band in the actual circuit. Correction, and use the register to save the feature division ratio control word.
  • the outside world Based on the result of the characteristic frequency division ratio latched in the above process, under normal working conditions, the outside world gives the frequency division ratio corresponding to the target frequency point, automatically calculates the frequency band in which the frequency point is located, and directly sets the frequency band coding to realize the phase locked loop.
  • Quick lock The AFC algorithm proposed in the present invention adopts a calibration idea different from the conventional idea, and only needs a small number of registers to record and calculate correction data of a large number of frequency points, thereby saving resources and realizing fast locking of the phase locked loop.
  • the above automatic band calibration method for quickly locking the phase locked loop system uses an automatic band calibration system for automatic band calibration.
  • the automatic band calibration system is initially in the calibration mode, and the calibration mode is in the working mode.
  • the window comparator 1 correction window comparator
  • the window comparator 2 working window comparator
  • Figure 1 shows the block diagram of the basic structure of the AFC module.
  • Figure 2 shows the schematic diagram of the AFC module.
  • Figure 3 shows the flow chart of the Verilog language description of the digital part of the schematic.
  • PFD/CP is the phase frequency detector and charge pump
  • LPF is the low pass filter
  • VCO is the voltage controlled oscillator
  • DIV is the frequency divider
  • the output of window comparator 1 is cmp1
  • rst_n is the reset signal
  • clk is the clock signal
  • clk0 is the internal clock signal after frequency division
  • clk_out is the external clock after frequency division
  • div_in is the target division ratio that needs to be locked for external reference
  • div_out is the output control divider
  • the frequency division ratio, fre_out is the frequency band encoding of the output control voltage controlled oscillator.
  • the switches S1 and S2 are all at the 0 position, and the circuit is in the band correction mode.
  • the frequency band coding of the VCO is placed at a fixed value, and the window comparator 1 converts the state of the Vctrl signal into a two-bit code to control the frequency division ratio transition: if Vctrl is higher than the upper limit voltage, the frequency division ratio jumps downward. If Vctrl is lower than the lower limit voltage, the division ratio jumps up. If Vctrl is in the window voltage range, the frequency division ratio is maintained. At this time, the frequency band Vctrl is considered to be locked, and the calibration is completed.
  • the corresponding frequency division ratio is the characteristic frequency division ratio of the frequency band, and is stored in the register for subsequent estimation. use.
  • the initial value of the characteristic division ratio is given according to the simulation result of the VCO design stage, which reduces the time for the jump to find the locked state.
  • the system automatically performs the calibration of the next band until all the bands are calibrated and the system enters the standby state and can work normally.
  • the window range of window comparator 1 is related to the nature of the phase-locked loop itself. The window range is usually small, but it is necessary to ensure that at least one of the phase-locked loop systems has a frequency that is accurate. As shown in FIG. 4, where V 1.1 and V 1.2 are the upper and lower voltage limits of the window comparator 1.
  • the switches S1 and S2 are all in the 1 position, and the external frequency is directly set according to the target frequency point to be locked.
  • the characteristic division ratio control word of each frequency band saved in the correction stage is read at this stage, and is used to judge the frequency band in which the target frequency point is located, and the AFC system directly calculates the frequency band coding of the VCO.
  • the upper and lower voltage limits V 1.1 and V 1.2 of the window comparator 1 of the present invention lock Vctrl near the intermediate value, and the characteristic division ratio of the frequency band is also about the intermediate value of all frequency points in the frequency band.
  • the estimation process of automatically selecting the frequency band according to the externally provided frequency division ratio is to determine which of the characteristic frequencies of the target frequency point is closer, and the frequency band corresponding to the characteristic frequency is the frequency band of the target frequency point. Since there is enough overlap between all the frequency bands in the design process, this calculation method can ensure that the preset frequency band is covered by the target frequency point.
  • V 1.1 and V 1.2 are the upper and lower voltage limits of the window comparator 2, and the window comparator 2 has a large window width, and its function is to limit Vctrl to an effective range, and at the same time, for calculating the frequency band. Do further verification correctly.
  • the two window comparator circuits used in the present invention have the same structure except that the reference window voltages are different.
  • the window comparator consists of two analog op amps with a buffer amplifier stage and sample-and-hold logic, and the samples are clocked.
  • all data processing and operations are implemented in the Verilog language.
  • the clock of the analog window comparator and the clock of the digital processing part are uniformly given by the digital part.
  • the analog window comparator is sampled by the clock drive, and only after a short period of time, the clock-driven digital portion of the digital processing portion operates. Four clocks with different frequencies are reserved during design, so that the speed can be increased only during the test without affecting the timing.
  • Figure 6.1, Figure 6.2, Figure 7.1, and Figure 7.2 show the simulation results of the calibration phase, and simulate the variation of the Vctrl signal.
  • Vctrl is higher than the upper limit voltage of the window comparator, the band code is kept, and the frequency division ratio code jumps to a direction where the frequency division is relatively small; when Vctrl is lower than the lower limit voltage, the band code is maintained, and the frequency division ratio is coded to a frequency division ratio.
  • the simulation results show that the switching of the band coding and the frequency division coding are consistent with the design and the logic is correct.
  • Figure 8 shows the simulation results of the band coding in the automatic estimation stage.
  • the simulation results show that the system can correctly estimate the number. (Note: For multi-bit band coding and division ratio coding, in order to make the results more intuitive, only the numerical changes in the characteristic bits are shown in the simulation results.)

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Abstract

一种使锁相环系统快速锁定的自动频带校准方法，使用AFC模块对VCO的频带进行校正，并且根据目标频点自动选择频带，实现锁相环的快速锁定。该方法采用闭环校正，控制分频器的分频比跳变，利用锁相环环路锁定Vctrl电压，依次得到每条频带的特征分频比，实现每条频带在实际电路中对应的特征频率的校正，并用寄存器保存特征分频比控制字。基于上述过程中锁存的特征分频比结果，正常工作状态下，外界给出目标频点所对应的分频比，自动推算出频点所处的频带，直接置频带编码，实现锁相环的快速锁定。该方法提出的AFC算法仅需数目较小的寄存器就可记录、推算大量频点的校正数据，既节约资源又可实现锁相环的快速锁定。

Description

一种使锁相环系统快速锁定的自动频带校准方法 技术领域
本发明涉及一种使锁相环(Phase Locked Loop，简称PLL)系统快速锁定的自动频带校准(简称AFC)方法，属于通信技术。
背景技术
锁相环是射频收发系统的重要组成部分，越来越多的应用对工作中收发机的频率切换速度有较高的要求，这就需要锁相环能快速锁定。
在设计过程中，压控振荡器(Voltage-Controlled Oscillator，简称VCO)的调谐曲线往往被设计成多条，每条曲线的调谐增益比较小，这样就可以兼顾环路稳定性和足够大的频率覆盖范围。实现锁相环的快速锁定，除了提高环路本身的性能以外，就是要实现快速准确的频带选择。受工艺、温度等因素的影响，锁相环系统中的VCO的频带会发生偏移，这就使得基于仿真的直接预判断的结果非常不可靠，必须寻求一种在环路建立情况下能够克服工艺、温度等因素的干扰自动确定频带的控制方法。传统的扫描寻找方式下，锁定到特定频点耗费的时间，大部分都消耗在频带的寻找上，对于需要快速锁定的应用来说就不再适用。我们必须探究更快速有效的频带选择方式。
发明内容
发明目的：为了克服现有技术中存在的不足，本发明提供一种有助于锁相环系统快速锁定的自动频带校准方法。
技术方案：为实现上述目的，本发明采用的技术方案为：
一种使锁相环系统快速锁定的自动频带校准方法，采用自动频带校准系统进行自动频带校准，自动频带校准系统启动之初处于校正模式，校正模式完成后处于工作模式；
校正模式时的工作过程包括如下步骤：
(1.1)校正完成标志信号mark＝0；频带总数为n，i＝0，进入步骤(1.2)；
(1.2)频带i的频带编码为Fre_data[i]，频带i的特征分频比预估值为Eva_data[i]，进入步骤(1.3)；
(1.3)通过校正窗口比较器的输出值判断控制电压信号Vctrl是否锁定在限定电压范围内：若没有锁定，则分频比跳变直至锁定；若锁定，则进入步骤(1.4)；
(1.4)保存控制电压信号Vctrl锁定时频带i的特征分频比实际值Div_data[i]，进入步骤(1.5)；
(1.5)若i<n，则根据Eva_data[i]和Div_data[i]调整频带i+1的特征分频比预估 值Eva_data[i+1]，进入步骤(1.6)；若i≥n，则进入步骤(1.7)；
(1.6)i＝i++，返回步骤(1.2)；
(1.7)所有频带都校正完成，校正完成标志信号mark＝1；
工作模式时的工作过程包括如下步骤：
(2.1)校正完成标志信号mark＝1，外部给定需要锁定的目标分频比Div_in；
(2.2)根据校正模式完成时确定的特征分频比实际值Div_data[i]与频带编码Fre_data[i]的关系，将与目标分频比Div_in距离最近的特征分频比实际值对应的频带编码作为预置频带编码Fre_data；
(2.3)工作窗口比较器的输出值判断预置频带编码Fre_data是否正确：若不正确则进行修正；校正窗口比较器输出值上下限在工作窗口比较器输出值上下限范围内。
优选的，所述步骤(1.3)中，分频比跳变的方法为：若控制电压信号Vctrl高于校正窗口比较器的上限电压，则分频比向下跳变；若控制电压信号Vctrl低于校正窗口比较器的下限电压，则分频比向上跳变。
优选的，所述步骤(2.3)中，若预置频带编码不正确，则进行修正，修正的方法为：将与目标分频比Div_in距离次近的特征分频比实际值对应的频带编码作为预置频带编码，直至预置频带编码正确。
优选的，该方法中的数字处理部分通过Verilog语言实现，校正窗口比较器和工作窗口比较器均通过模拟电路实现；为了保证时序的稳定和采样的时效性，模拟电路实现的窗口比较器和Verilog语言实现的数字部分的时钟均由数字部分统一给出。数字部分的时钟比窗口比较器的时钟略滞后，以保证控制电压信号Vctrl采样后及时作出处理，同时保证时序准确。
本发明方法中，自动频带校准系统启动之初处于校正模式，此时锁相环的工作状态与传统方式不同，传统的锁相环采用的思路是固定分频比，反馈控制控制电压信号Vctrl的变化，锁定频率。本方法在校正模式下特点为：固定频带，通过校正窗口比较器的输出控制分频比的跳变，寻找到一个合适的频率，使得控制电压信号Vctrl可以锁定在较小的电压范围内。利用锁相环环路锁定控制电压信号Vctrl依次得到每条频带的特征分频比，实现每条频带在实际电路中对应的特征频率的校正。
本方法中，校正窗口比较器的上下限值的确定与锁相环本身的性质相关，窗口范围通常比较小(控制电压信号Vctrl变化范围的中间值附近)，但是要保证其中至少有一个锁相环系统精度可达的频点。为了缩短校正时间，对每一频带的特征分频比给出预估值，并且根据前一频带的校正结果修正下一频带的预估值。
校正完成后，依据校正结果，根据外置的目标频点，自动判断所处频带，直接预置准确的频带编码，缩短锁定时间。本方法的校正窗口比较器将控制电压信号Vctrl锁定在中间值附近，频带的特征分频比也约为频带上所有频点的中间值。根据外部提供的分频比自动选择频带的推算过程，就是判断目标频点距离哪一个特征频率更近，则这一特征频率对应的频带为目标频点所在频带。
本发明实际电路中，数字处理部分通过Verilog语言实现，校正窗口比较器和工作窗口比较器均通过模拟电路实现。窗口比较器由两个模拟运算放大器构成，带有缓冲放大级和采样保持逻辑电路，采样由时钟控制。窗口比较器用于将控制电压信号Vctrl的大小转化为两位数字编码：若控制电压信号Vctrl高于上限电压，输出“10”；若控制电压信号Vctrl低于下限电压，输出“01”；若控制电压信号Vctrl处于上下电压限之间，输出“11”。两位数字编码输入到数字部分，用于控制分频比或频带编码的跳变。
有益效果：本发明提供的使锁相环系统快速锁定的自动频带校准方法，与现有技术相比，只需要在整个系统启动之初采用区别于传统思路的校正算法，后续正常工作状态下就能够直接准确的找到频带，实现锁相环的快速锁定。所运用的锁定控制电压信号Vctrl的校正方法，对关键点进行校正，克服工艺、温度等因素造成的不利影响，仅需数目较小的寄存器就可记录、推算大量频点的校正数据，对于目标频点较多的锁相环系统来说，既节约资源又可实现快速切换锁定。
附图说明
图1为本发明中AFC模块的整体结构框图；
图2为本发明中AFC模块的原理图；
图3为数字部分算法流程图；
图4为窗口电压设定示意图；
图5数字部分内部及比较器时钟仿真结果(设计时预留了4路时钟)；
图6.1校正阶段，频带编码自动切换数模联合仿真(模拟信号结果)；
图6.2校正阶段，频带编码自动切换数模联合仿真(数字信号结果)；
图7.1校正阶段，分频比编码跳变锁定数模联合仿真(模拟信号结果)；
图7.2校正阶段，分频比编码跳变锁定数模联合仿真(数字信号结果)；
图8正常工作阶段，自动推算置频带编码仿真。
具体实施方式
下面结合附图对本发明作更进一步的说明。
一种使锁相环系统快速锁定的自动频带校准方法，AFC模块对VCO的频带进行校正，并且根据目标频点自动选择频带，实现锁相环的快速锁定。本发明采用闭环校正，控制分频器的分频比跳变，利用锁相环环路锁定Vctrl电压，依次得到每条频带的特征分频比，实现每条频带在实际电路中对应的特征频率的校正，并用寄存器保存特征分频比控制字。基于上述过程中锁存的特征分频比结果，正常工作状态下，外界给出目标频点所对应的分频比，自动推算出频点所处的频带，直接置频带编码，实现锁相环的快速锁定。本发明中提出的AFC算法采用区别于传统思路的校准思想，仅需数目较小的寄存器就可记录、推算大量频点的校正数据，既节约资源又可实现锁相环的快速锁定。
上述使锁相环系统快速锁定的自动频带校准方法，采用自动频带校准系统进行自动频带校准，自动频带校准系统启动之初处于校正模式，校正模式完成后处于工作模式。实际电路中，窗口比较器1(校正窗口比较器)和窗口比较器2(工作窗口比较器)用模拟电路实现，数字处理部分用Verilog语言描述。如图1所示为AFC模块基本结构的框图，图2所示为AFC模块的原理图，图3所示为原理图中数字部分Verilog语言描述的流程图。图中PFD/CP为鉴频鉴相器及电荷泵，LPF为低通滤波器，VCO为压控振荡器，DIV为分频器，窗口比较器1的输出为cmp1，窗口比较器2的输出为cmp2；rst_n为复位信号，clk为时钟信号，clk0为分频后内部时钟信号，clk_out为分频后外部时钟；div_in为外部给定需要锁定的目标分频比，div_out为输出控制分频器的分频比，fre_out为输出控制压控振荡器的频带编码。
电路启动初期，开关S1、S2都处于0位置，电路处于频带校正模式。VCO的频带编码被置于一固定值，窗口比较器1将Vctrl信号所处的状态转变为两位编码，控制分频比的跳变：若Vctrl高于上限电压，分频比向下跳变；若Vctrl低于下限电压，分频比向上跳变。若Vctrl处于窗口电压范围内，分频比保持，此时认为该频带Vctrl锁定，校准完成，此时对应的分频比为该频带的特征分频比，保存在寄存器中，用于后续的推算使用。特征分频比初值根据VCO设计阶段的仿真结果给出，减小了跳变寻找锁定状态的时间。一条频带锁定完成后，系统自动进行下一条频带的校准，直到所有频带校准完成，系统进入待命状态，可以正常工作了。窗口比较器1的窗口范围与锁相环本身的性质相关，窗口范围通常比较小，但是要保证其中至少有一个锁相环系统精度可达的频点。如 图4所示，其中V1.1和V1.2为窗口比较器1的上下电压限。
正常工作状态下，开关S1、S2都处于1位置，外界根据需要锁定的目标频点对分频比进行直接置数。在校正阶段保存的每一条频带的特征分频比控制字在此阶段被读取，并用于判断目标频点所处频带，AFC系统计算后直接对VCO置频带编码。如图4所示，本发明中窗口比较器1的上下电压限V1.1和V1.2将Vctrl锁定在中间值附近，频带的特征分频比也约为频带上所有频点的中间值。根据外部提供的分频比自动选择频带的推算过程，就是判断目标频点距离哪一个特征频率更近，则这一特征频率对应的频带则为目标频点所在频带。由于在设计过程中，所有的频带之间留有足够的重合范围，所以这一推算方法能够保证推算预置的频带覆盖目标频点。图4中，V1.1和V1.2为窗口比较器2的上下电压限，窗口比较器2的窗口宽度很大，它的作用是将Vctrl限定在有效的范围内，同时用于对频带的推算是否正确做进一步的验证。
本发明中所用到的两个窗口比较器电路结构相同，只是参考的窗口电压不同。窗口比较器由两个模拟运算放大器构成，带有缓冲放大级和采样保持逻辑电路，采样由时钟控制。除此之外，所有的数据处理与运算都通过Verilog语言实现。为了保证时序的稳定和采样的时效性，模拟窗口比较器的时钟和数字处理部分的时钟由数字部分统一给出。如图5所示，为时钟信号波形，模拟窗口比较器在时钟驱动下采样，仅延时一小段时间后数字处理部分的时钟驱动数字部分工作。设计时预留了4路频率不一样的时钟，目的是在测试时可以在不影响时序的情况下仅可能提高速度。
图6.1、图6.2、图7.1、图7.2为校准阶段仿真结果，对Vctrl信号的变化情况进行模拟。当Vctrl高于窗口比较器的上限电压时，频带编码保持，分频比编码向分频比较小的方向跳变；当Vctrl低于下限电压时，频带编码保持，分频比编码向分频比更大的方向跳变；当Vctrl处于窗口范围内时，认为当前频带校准完成，频带编码向下一频带跳变。仿真结果表明，频带编码的切换和分频比编码的跳变与设计的一致，逻辑正确。图8为对自动推算置数阶段频带编码的仿真结果，仿真结果表明，系统能够正确的推算置数。(注：对于多位的频带编码和分频比编码，为了使结果更直观，仿真结果中只展示了有特征的位上的数值变化。)
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (4)

  1. 一种使锁相环系统快速锁定的自动频带校准方法，其特征在于：采用自动频带校准系统进行自动频带校准，自动频带校准系统启动之初处于校正模式，校正模式完成后处于工作模式；
    校正模式时的工作过程包括如下步骤：
    (1.1)校正完成标志信号mark＝0；频带总数为n，i＝0，进入步骤(1.2)；
    (1.2)频带i的频带编码为Fre_data[i]，频带i的特征分频比预估值为Eva_data[i]，进入步骤(1.3)；
    (1.3)通过校正窗口比较器的输出值判断控制电压信号Vctrl是否锁定在限定电压范围内：若没有锁定，则分频比跳变直至锁定；若锁定，则进入步骤(1.4)；
    (1.4)保存控制电压信号Vctrl锁定时频带i的特征分频比实际值Div_data[i]，进入步骤(1.5)；
    (1.5)若i<n，则根据Eva_data[i]和Div_data[i]调整频带i+1的特征分频比预估值Eva_data[i+1]，进入步骤(1.6)；若i≥n，则进入步骤(1.7)；
    (1.6)i＝i++，返回步骤(1.2)；
    (1.7)所有频带都校正完成，校正完成标志信号mark＝1；
    工作模式时的工作过程包括如下步骤：
    (2.1)校正完成标志信号mark＝1，外部给定需要锁定的目标分频比Div_in；
    (2.2)根据校正模式完成时确定的特征分频比实际值Div_data[i]与频带编码Fre_data[i]的关系，将与目标分频比Div_in距离最近的特征分频比实际值对应的频带编码作为预置频带编码Fre_data；
    (2.3)工作窗口比较器的输出值判断预置频带编码Fre_data是否正确：若不正确则进行修正；校正窗口比较器输出值上下限在工作窗口比较器输出值上下限范围内。
  2. 根据权利要求1所述的使锁相环系统快速锁定的自动频带校准方法，其特征在于：所述步骤(1.3)中，分频比跳变的方法为：若控制电压信号Vctrl高于校正窗口比较器的上限电压，则分频比向下跳变；若控制电压信号Vctrl低于校正窗口比较器的下限电压，则分频比向上跳变。
  3. 根据权利要求1所述的使锁相环系统快速锁定的自动频带校准方法，其特征在于：所述步骤(2.3)中，若预置频带编码不正确，则进行修正，修正的方法为：将与目 标分频比Div_in距离次近的特征分频比实际值对应的频带编码作为预置频带编码，直至预置频带编码正确。
  4. 根据权利要求1所述的使锁相环系统快速锁定的自动频带校准方法，其特征在于：该方法中的数字处理部分通过Verilog语言实现，校正窗口比较器和工作窗口比较器均通过模拟电路实现；为了保证时序的稳定和采样的时效性，模拟电路实现的窗口比较器和Verilog语言实现的数字部分的时钟均由数字部分统一给出。
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