WO2017041457A1 - 阵列基板行驱动单元的保护电路和阵列基板 - Google Patents

阵列基板行驱动单元的保护电路和阵列基板 Download PDF

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Publication number
WO2017041457A1
WO2017041457A1 PCT/CN2016/075339 CN2016075339W WO2017041457A1 WO 2017041457 A1 WO2017041457 A1 WO 2017041457A1 CN 2016075339 W CN2016075339 W CN 2016075339W WO 2017041457 A1 WO2017041457 A1 WO 2017041457A1
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WIPO (PCT)
Prior art keywords
voltage
output
output end
module
switch
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PCT/CN2016/075339
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English (en)
French (fr)
Inventor
上官星辰
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/515,017 priority Critical patent/US10984690B2/en
Priority to EP16843397.7A priority patent/EP3349203A4/en
Publication of WO2017041457A1 publication Critical patent/WO2017041457A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the utility model relates to an ESD or EOS protection of an array on-board (GOA) unit, and more particularly to a protection circuit and an array substrate of a GOA unit.
  • GOA array on-board
  • Electrostatic Discharge is currently the number one killer of electronic devices.
  • TFT-LCDs are susceptible to ESD and cause display abnormality due to, for example, a large display screen area of a thin film transistor type liquid crystal display (TFT-LCD), and an electronic device including a TFT-LCD in direct contact with a human body.
  • TFT-LCDs are also susceptible to electrical overstress (EOS).
  • array substrate row drive (GOA) cells are generally integrated on the outside of the display panel and are more susceptible to ESD or EOS. Especially in various ultra-thin (Air) electronic devices, it is more likely that the GOA unit is broken down, causing the display panel to display an abnormality.
  • GOA array substrate row drive
  • ESD or EOS protection is required for the GOA unit, thereby enhancing the reliability of the display panel, thereby improving the quality of the electronic device.
  • the present invention provides a protection circuit for an array substrate row driving GOA unit, which is connected to a gate line signal output end of a GOA unit, wherein the protection circuit includes: a first voltage strobe a module having an input coupled to the output of the first voltage source and configured to output the first voltage source at an output thereof when the gate line signal output should output an effective drive voltage of the gate drive signal An output voltage of the output terminal; a first protection module having an input connected to an output of the first voltage gating module and an output connected to the gate line; wherein an output at an output of the first voltage source The first protection module outputs the output voltage of the output end of the first voltage source as the adjusted gate drive signal if the voltage and the current output voltage of the gate line signal output meet the first predetermined condition.
  • the protection circuit further includes: a second voltage gating module, wherein the input end is connected to the output end of the second voltage source, and is configured to output a gate at the output end of the gate line signal When the non-effective driving voltage of the driving signal is output, the second voltage source is output at the output end thereof An output voltage of the output; a second protection module having an input connected to an output of the second voltage gating module and an output connected to the gate line; wherein, at an output of the second voltage source When the output voltage and the current output voltage of the gate line signal output end meet the second predetermined condition, the second protection module outputs the output voltage of the output end of the second voltage source as the adjusted gate drive signal.
  • the embodiment of the present invention further provides an array substrate, including the protection circuit of the above-mentioned array substrate row driving GOA unit.
  • FIG. 1 is a schematic diagram of a GOA unit and its gate drive signal in accordance with an embodiment of the present invention
  • FIG. 2 is a schematic block diagram of a protection circuit connected to a gate line signal output end of an array substrate row driving GOA unit according to an embodiment of the present invention
  • FIG. 3 is another schematic block diagram of a protection circuit connected to a gate line signal output end of an array substrate row driving GOA unit according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a first protection module for protecting a high voltage of a gate drive signal output by a GOA unit according to an embodiment of the present invention
  • FIG. 5 is a schematic circuit diagram of the first protection module shown in FIG. 4 according to an embodiment of the present invention.
  • FIG. 6 is still another schematic block diagram of a protection circuit connected to a gate line signal output end of an array substrate row driving GOA unit according to an embodiment of the present invention
  • FIG. 7 is still another schematic block diagram of a protection circuit connected to a gate line signal output end of an array substrate row driving GOA unit according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram of a second protection module that protects a low voltage of a gate drive signal output by a GOA unit, in accordance with an embodiment of the present invention
  • FIG. 9 is a schematic circuit diagram of the second protection module shown in FIG. 8 according to an embodiment of the present invention.
  • FIG. 10 is a combined circuit diagram of a first protection module and a second protection module for protecting a high voltage and a low voltage of a gate drive signal output by a GOA unit according to an embodiment of the present invention
  • FIG. 11 is a specific circuit diagram of a protection circuit in accordance with an embodiment of the present invention.
  • Figure 12 is a schematic block diagram of an nth stage shift register of a GOA unit
  • FIG. 13 is a schematic block diagram of a control module in accordance with an embodiment of the present invention.
  • the array substrate includes a pixel array, a data driving circuit, and a gate driving circuit (ie, a GOA unit).
  • the pixel array includes M rows and N columns
  • the GOA unit has M gate lines
  • the pixels in the same row in the pixel array are all connected to the same gate line
  • the data driving circuit has N data lines
  • the pixel arrays are in the same column.
  • the pixels are all connected to the same data line.
  • the connection manner of the pixel array, the data driving circuit and the GOA unit in the array substrate is not limited thereto, and the present invention is not limited by the connection manner of the pixel array, the data driving circuit and the GOA unit.
  • the gate drive signal of the gate line output of the GOA unit is generally a square wave pulse signal having a high voltage VGH and a low voltage VGL.
  • the high voltage VGH is the on voltage
  • the low voltage VGL is the off voltage
  • the high voltage VGH is the off voltage
  • the low voltage VGL is the on voltage.
  • an N-type TFT will be taken as an example for development.
  • the TFT connected to the gate line in the pixel array is an N-type TFT
  • the gate driving signal is at the low voltage VGL
  • the TFT is in an off state, and the data signal on the data line is not transmitted to the pixel, thereby A row of pixels connected by the gate line is not displayed according to the data signal currently outputted on the data line
  • the gate drive signal is at a high voltage VGH
  • the TFT is in an on state, and the data signal on the data line can be transmitted to the pixel, thereby A row of pixels connected to the gate line is displayed according to the data signal currently output on the data line.
  • the waveform of the gate drive signal may be distorted. Such distortion may not only cause abnormal image display on the liquid crystal panel, but may even cause TFT in the pixel circuit on the liquid crystal panel. damage.
  • the high voltage sum of the gate driving signals respectively outputted to the GOA unit is proposed.
  • the concept of low voltage protection is proposed.
  • FIG. 2 is a schematic block diagram of a protection circuit connected to a gate line signal output terminal of an array substrate row driving GOA unit, in accordance with an embodiment of the present invention.
  • the protection circuit includes a first voltage gating module 21 and a first protection module 22.
  • the input end of the first voltage gating module 21 is connected to the output end of the first voltage source, and the output end of the first voltage gating module 21 is connected to the input end of the first protection module 22.
  • the output end of the first voltage gating module 21 outputs an output voltage of the output end of the first voltage source when the gate line signal output terminal should output an effective driving voltage of the gate driving signal.
  • the other input terminal of the first protection module 22 is connected to the gate line signal output terminal VG, and the output terminal VGG of the first protection module 22 is connected to the gate line.
  • the first protection module outputs an output voltage of an output end of the first voltage source when an output voltage of an output end of the first voltage source and a current output voltage of the gate line signal output end meet a first predetermined condition
  • the output is used as the gate drive signal.
  • the effective driving voltage of the gate driving signal may be a high voltage or may be a low voltage.
  • the effect of the ESD or EOS on the output voltage of the gate line signal output terminal may be embodied as a voltage surge, which may be a positive impact or may be a negative impact.
  • the following description is made by taking an example in which the effective driving voltage of the gate driving signal is a high voltage and the ineffective driving voltage of the gate driving signal is a low voltage.
  • the effective driving voltage enables a transistor connected to the gate line to be turned on, and the non-effective driving voltage cannot turn on a transistor connected to the gate line.
  • the effective driving voltage of the gate driving signal may have an impact, and in the case where the amplitude of the impact is very high, it may directly break through the TFT in the pixel circuit receiving the gate driving signal. Therefore, it is necessary to suppress such an impact.
  • the output end of the first voltage source includes a first output end, the output voltage of the first output end is a first power supply high voltage VDD1, and the input end of the first voltage gating module includes The first input end, the output end of the first voltage gating module includes a first output end, and the input end of the first protection module includes a first input end and a third input end, the first protection module An input terminal is coupled to the first output terminal of the first voltage gating module, and a third input terminal of the first protection module is coupled to the gate line signal output terminal.
  • the first output end of the first voltage gating module 21 outputs the first power supply high voltage VDD1, which is in normal operation.
  • the first protection module 22 outputs the current output of the gate line signal output terminal. The voltage VG is pulled down to the first power supply high voltage VDD1, and the output end of the first protection module 22 outputs the first power supply high voltage VDD1 as the adjusted gate drive signal VGG.
  • the effective level (high level) of the gate drive signal may not only have a positive impact but also a negative impact, so it is necessary to suppress not only the positive impact but also the negative impact.
  • FIG 3 is another schematic block diagram of a protection circuit coupled to a gate line signal output of a row substrate driving GOA cell in accordance with an embodiment of the present invention.
  • the output end of the first voltage source further includes a second output end
  • the output voltage of the second output end is a first power supply low voltage VSS1
  • the first voltage gating module 21 further includes The second input end of the first voltage gating module 21 is connected to the second output end of the first voltage source
  • the input end of the first protection module 22 further includes a second input end.
  • the second input end of the first protection module 22 is connected to the second output end of the first voltage gating module 21 .
  • the second output end of the first voltage gating module 21 outputs the first power source low voltage VSS1
  • the first protection module 22 pulls up the current output voltage of the gate line signal output terminal to the first power source low voltage. VSS1, and the output of the first protection module 22 outputs the first power The source low voltage VSS1 serves as an adjusted gate drive signal.
  • the first power supply high voltage VDD1, the normal high voltage VGH of the gate drive signal, and the first power supply low voltage VSS1 should satisfy the following relationship: VDD1>VGH>VSS1.
  • FIG. 4 is a schematic diagram of a first protection module 22 that protects a high voltage of a gate drive signal output by a GOA unit, in accordance with an embodiment of the present invention.
  • the first protection module 22 is configured to control or adjust the high voltage VGH of the gate drive signal VG.
  • the first protection module 22 may include a first resistor R1 and a first protection element S1.
  • the first resistor R1 is connected between the gate line signal output end and the output end AA of the first protection module 22, and the first protection element S1 is connected to the output end of the first protection module 22 and
  • the first output terminal V1 (ie, VDD1) of the first voltage gating module 21 is between.
  • the first protection element S1 can absorb ESD or EOS energy when ESD or EOS occurs, or release ESD or EOS energy into other circuits.
  • the first protection element S1 may be a diode, a varistor, or a high molecular polymer that is rapidly switching, or may be an ESD/EOS protection circuit composed of a plurality of semiconductor elements or other elements.
  • the first protection element S1 When the high voltage VGH of the gate drive signal VG exceeds the high voltage VDD1 of the first voltage source due to the influence of ESD or EOS, the first protection element S1 is turned on, the ESD or EOS energy is absorbed, or ESD is Or EOS energy is released to the first voltage source, specifically to the first output of the first voltage source via the first voltage gating module 21, such that the output of the first protection module 22 Outputting the high voltage VDD1 of the first output terminal of the first voltage source as the adjusted gate driving signal VGG, that is, the high voltage VGH of the adjusted gate driving signal VGG is the first of the first voltage source The high voltage VDD1 at the output.
  • the first protection module 22 may further include a second protection element S2.
  • the second protection element S2 is connected between the output end of the first protection module 22 and the second output end V2 of the first voltage gating module 21 (ie, VSS1).
  • the second protection element S2 can absorb ESD or EOS energy when ESD or EOS occurs, or release ESD or EOS energy into other circuits.
  • the second protection element S2 may be a diode, a varistor, or a high molecular polymer that is rapidly switching, or may be an ESD/EOS protection circuit composed of a plurality of semiconductor elements or other elements.
  • the second protection element S2 When the high voltage VGH of the gate drive signal VG is lower than the low voltage VSS1 of the second output terminal of the first voltage source due to the influence of ESD or EOS, the second protection element S2 is turned on, and ESD or EOS energy is used. Absorbing, or releasing ESD or EOS energy to the first voltage source, Bulkly discharged to the second output of the first voltage source via the first voltage gating module 21 such that the output of the first protection module 22 will be the second output of the first voltage source
  • the low voltage VSS1 is output as the adjusted gate drive signal VGG, that is, the high voltage VGH of the adjusted gate drive signal VGG is the low voltage VSS1 of the first output terminal of the first voltage source.
  • the first power supply low voltage VSS1 may be, for example, a common ground voltage VGND.
  • the first protection module 22 may further include a first capacitor C1 connected to the gate line signal output end and the second output end of the first voltage gating module 21, as needed. between.
  • FIG. 5 is a schematic circuit diagram of the first protection module 22 shown in FIG. 4, in accordance with an embodiment of the present invention.
  • the first protection element S1 is a first diode D1
  • the second protection element S2 is a second diode D2.
  • An anode and a cathode of the first diode D1 are respectively connected to an output end of the first protection module 22 and a first output end V1 (ie, VDD1) of the first voltage gating module 21, the second two
  • the anode and the cathode of the pole tube D2 are respectively connected to the second output terminal V2 of the first voltage gating module 21 (ie, VSS1) and the output end of the first protection module 22.
  • the first diode D1 when the high voltage VGH of the gate driving signal VG exceeds the high voltage VDD1 of the first voltage source due to the influence of ESD or EOS, the first diode D1 is turned on, via the first voltage
  • the gating module 21 releases the ESD or EOS energy to the first output of the first voltage source such that the output of the first protection module 22 sets the high voltage of the first output of the first voltage source
  • the VDD1 output is used as the adjusted gate drive signal VGG, that is, the high voltage VGH of the adjusted gate drive signal VGG is the first power supply high voltage VDD1.
  • the second diode D2 is turned on, via the a voltage gating module 21, releasing ESD or EOS energy to a second output of the first voltage source, such that an output of the first protection module 22 will be a second output of the first voltage source
  • the low voltage VSS1 is output as the adjusted gate drive signal VGG, that is, the high voltage VGH of the adjusted gate drive signal VGG is the first power supply low voltage VSS1.
  • the high voltage VGH of the gate driving signal VG can be clamped within a certain voltage range, specifically within the range of VSS1 to VDD1, by the first voltage gating module 21 and the first protection module 22, thereby ESD or EOS can be prevented from causing damage to the TFTs in the pixel circuit.
  • VDD1 is slightly higher than the normal VGH and VSS is slightly lower than the normal VGH, specifically, for example, VDD is 0.5V higher than the normal VGH and VSS is 0.5V lower than the normal VGH, which can make adjustment
  • the high voltage VGH of the subsequent gate driving signal VGG is within a predetermined high voltage range, so that the pixel circuit can normally read the data signal on the data line, thereby being able to display normally, avoiding the gate caused by ESD or EOS The display abnormality caused by the distortion of the pole drive signal VG.
  • FIG. 6 is still another schematic block diagram of a protection circuit connected to a gate line signal output terminal of an array substrate row driving GOA unit, in accordance with an embodiment of the present invention.
  • the protection circuit further includes a second voltage gating module 23 and a second protection module 24.
  • the input end of the first voltage gating module 21 is connected to the output end of the first voltage source, and the output end of the first voltage gating module 21 is connected to the input end of the first protection module 22.
  • An output terminal of the first voltage gating module 21 outputs an output voltage of an output end of the first voltage source when an output driving voltage (eg, a high voltage) of the gate driving signal is to be outputted at the output of the gate line signal .
  • the other input end of the first protection module 22 is connected to the gate line signal output terminal, and the output end of the first protection module 22 is connected to the gate line.
  • the input end of the second voltage gating module 23 is connected to the output end of the second voltage source, and the output end of the second voltage gating module 23 is connected to the input end of the second protection module 24.
  • the gate line signal output end outputs a non-effective driving voltage (eg, a low voltage) of the gate driving signal
  • an output end of the second voltage gating module 23 outputs an output of the output end of the second voltage source. Voltage.
  • the other input of the second protection module 24 is coupled to the gate signal output.
  • the first protection module 22 and the second protection module 24 share a part of the circuit, and the other input end of the first protection module 22 and the other input end of the second protection module 24 are the same input end.
  • the same input terminal is connected to the gate line signal output end, one end of the shared circuit is the same input end, and the other end is connected to the gate line.
  • the second protection module 24 sets the second voltage source The output voltage output of the output is used as the adjusted gate drive signal.
  • the non-effective driving voltage (low voltage) of the gate driving signal may have an impact, and in the case where the amplitude of the impact is very high, it may directly break through the receiving of the gate driving signal.
  • the TFT in the pixel circuit is therefore required to suppress such an impact.
  • an output end of the second voltage source includes a first output end, an output voltage of the first output end is a second power supply high voltage, and an input end of the second voltage gating module includes a first
  • An input end of the second voltage gating module includes a first output end
  • an input end of the second protection module includes a first input end and a third input end, and the first end of the second protection module The input end is connected to the first output end of the second voltage gating module
  • the third input end of the second protection module is connected to the gate line signal output end.
  • the third input end of the first protection module and the third input end of the second protection module are the same input end.
  • the first output end of the second voltage gating module 23 outputs the second power supply high voltage VDD2, which is normal.
  • VDD2>VGL in the working condition and in a case where the current output voltage VG of the gate line signal output terminal is higher than the second power source high voltage VDD2, the second protection module 24 outputs the current of the gate line signal output end
  • the output voltage VG is pulled down to the second power supply high voltage VDD2, and the output of the second protection module 24 outputs the second power supply high voltage VDD2 as the adjusted gate drive signal VGG.
  • the non-effective driving voltage (low voltage) of the gate driving signal may not only have a positive impact but also a negative impact, so it is necessary to suppress not only the positive impact but also the negative shock.
  • FIG. 7 is still another schematic block diagram of a protection circuit connected to a gate line signal output terminal of an array substrate row driving GOA unit, in accordance with an embodiment of the present invention.
  • the output end of the second voltage source further includes a second output terminal, and the output voltage of the second output terminal is a second power supply low voltage VSS2.
  • the input of the second voltage gating module 23 further includes a second input, and the second input of the second voltage gating module 23 is coupled to the second output of the second voltage source.
  • the output of the second voltage gating module 23 further includes a second output terminal V4
  • the input end of the second protection module 24 further includes a second input terminal, the second protection module A second input of 24 is coupled to a second output V4 of the second voltage gating module 23.
  • the second output terminal V4 of the second voltage gating module 23 outputs the second power source low voltage VSS2, and In a case where the current output voltage of the gate line signal output terminal is lower than the second power source low voltage VSS2, the second protection module 24 pulls up the current output voltage of the gate line signal output terminal to the second power source low. Voltage VSS2, and the output of the second protection module 24 outputs the first The two power supply low voltage VSS2 is used as the adjusted gate drive signal.
  • the second power supply high voltage VDD2, the low voltage VGL of the gate drive signal, and the second power supply low voltage VSS2 should satisfy the following relationship: VDD2>VGL>VSS2.
  • the first power supply low voltage VSS1 may be higher than the second power supply high voltage VDD2, or the first power supply low voltage VSS1 may be the same as the second power supply high voltage VDD2, as needed. Therefore, the first power supply high voltage VDD1, the high voltage VGH of the gate drive signal, the first power supply low voltage VSS1, the second power supply high voltage VDD2, and the low voltage VGL of the gate drive signal.
  • the second power supply low voltage VSS2 should satisfy the following relationship: VDD1>VGH>VSS1 ⁇ VDD2>VGL>VSS2.
  • VSS1 and VDD2 may be the common ground voltage GND.
  • FIG. 8 is a schematic diagram of a second protection module 24 that protects the low voltage of the gate drive signal output by the GOA unit, in accordance with an embodiment of the present invention.
  • the second protection module 24 is configured to control the low voltage VGL of the gate driving signal VG.
  • the second protection module 24 may include a first resistor R1 and a third protection element S3.
  • the first protection module 22 and the second protection module 24 share the first resistor R1.
  • the first resistor R1 is connected between the gate line signal output end and the output end of the second protection module 24, and the output ends of the first protection module 22 and the second protection module 24 are the same output. end.
  • the third protection element S3 is connected between the output of the second protection module 24 and the first output of the second voltage gating module 23 .
  • the third protection element S3 When the low voltage VGL of the gate drive signal VG exceeds the high voltage VDD2 of the second voltage source due to the influence of ESD or EOS, the third protection element S3 is turned on, absorbing ESD or EOS energy, or ESD Or EOS energy is released to the second voltage source, in particular via the second voltage gating module 23 to the first output of the second voltage source, such that the output of the second protection module 24
  • the high voltage VDD2 of the first output end of the second voltage source is output as the adjusted gate drive signal VGG, that is, the low voltage VGL of the adjusted gate drive signal VGG is the second power supply high voltage VDD2.
  • the second protection module 24 may further include a second capacitor C2.
  • the second capacitor C2 is connected between the gate line signal output end and the first output end of the second voltage gate module 22.
  • the second protection module 24 may further include a fourth protection element S4.
  • the fourth protection element S4 is connected between the output end of the second protection module 24 and the second output end of the second voltage gating module 23.
  • the fourth protection element S4 When the low voltage VGL of the gate drive signal VG is lower than the low voltage VSS2 of the second voltage source due to the influence of ESD or EOS, the fourth protection element S4 is turned on, absorbing ESD or EOS energy, or ESD or EOS energy is released to the first voltage source, specifically to the second output of the first voltage source via the second voltage gating module 23, thereby causing the output of the second protection module 24
  • the terminal outputs the low voltage VSS2 of the second output end of the second voltage source as the adjusted gate drive signal VGG, that is, the low voltage VGL of the adjusted gate drive signal VGG is the second power supply low voltage VSS2 .
  • the third protection element S3 and the fourth protection element S4 may absorb ESD or EOS energy when ESD or EOS occurs, or release ESD or EOS energy into other circuits.
  • the third protection element S3 and the fourth protection element S4 may be diodes, varistors, or high molecular polymers that are rapidly switching, or may be ESD/EOS composed of various semiconductor elements or other components. Protection circuit.
  • FIG. 9 is a schematic circuit diagram of the second protection module 24 of FIG. 8 in accordance with an embodiment of the present invention.
  • the third protection element S3 is a third diode D3
  • the fourth protection element S4 is a fourth diode D4.
  • An anode and a cathode of the third diode D3 are respectively connected to an output end of the second protection module 24 and a first output end of the second voltage gating module 23, and an anode of the fourth diode D4 And a cathode connected to the second output end of the second voltage gating module 23 and the output end of the second protection module 24, respectively.
  • the third diode D3 is turned on, via the second voltage a gating module 23, releasing ESD or EOS energy to a first output of the second voltage source such that an output of the second protection module 24 is to a high voltage of a first output of the second voltage source
  • the VDD2 output is used as the adjusted gate drive signal VGG, that is, the high voltage VGH of the adjusted gate drive signal VGG is the second power supply high voltage VDD2.
  • the fourth diode D4 is turned on, via the Two voltage gating module 23, releasing ESD or EOS energy to the second of the second voltage source An output terminal, so that the output end of the second protection module 24 outputs the low voltage VSS2 of the second output end of the second voltage source as the adjusted gate drive signal VGG, that is, the adjusted gate drive signal
  • the low voltage VGL of VGG is the second power supply low voltage VSS2.
  • the low voltage VGL of the gate driving signal VG can be clamped within a certain voltage range, specifically within the range of VSS2 to VDD2, by the second voltage gating module 23 and the second protection module 24, thereby ESD or EOS can be prevented from causing damage to the TFTs in the pixel circuit.
  • VDD2 is slightly higher than VGL and VSS2 is slightly lower than VGL, specifically, for example, VDD2 is 0.5V higher than VGL and VSS2 is 0.5V lower than VGL, so that the adjusted gate can be made.
  • the low voltage VGL of the pole drive signal VGG is within a predetermined low voltage range, so that the pixel circuit can normally read the data signal on the data line, so that the display can be performed normally, and the gate drive signal due to ESD or EOS is avoided.
  • the display caused by the distortion of the VG is abnormal.
  • FIG. 10 is a combined circuit diagram of a first protection module 22 and a second protection module 24 that protects a high voltage and a low voltage of a gate drive signal output by a GOA unit, in accordance with an embodiment of the present invention.
  • the first voltage gating module 21 applies the first power source high voltage VDD1 of the first voltage source to the input terminal V1 shown in FIG. 10 and The first power supply low voltage VSS1 of the first voltage source is applied to the input terminal V2 shown in FIG. 10, and the second voltage gate module 23 does not apply the second power supply high voltage VDD2 of the second voltage source to FIG.
  • the input terminal V3 does not apply the second power supply low voltage VSS2 of the second voltage source to the input terminal V4 shown in FIG.
  • the output voltage VG is higher than the second power supply high voltage VDD2 (in normal operation, the high voltage outputted by the gate line signal output terminal is higher than the second power supply high voltage VDD2), the third diode D3 and the fourth diode D4 It will not turn on.
  • the second voltage gating module 23 applies the second power source high voltage VDD2 of the second voltage source to the input terminal V3 shown in FIG. 10 and Applying the second power supply low voltage VSS2 of the second voltage source to the input terminal V4 shown in FIG. 10, and the first voltage gating module 21 does not apply the first power supply high voltage VDD1 of the first voltage source to FIG. Input V1 and does not apply the first power supply low voltage VSS1 of the first voltage source It is applied to the input terminal V2 shown in FIG.
  • the third diode D3 is turned on, and the current output voltage VG at the output end of the gate line signal is low.
  • the fourth diode D4 is turned on; but since the input terminals V1 and V2 shown in FIG. 10 have no input voltage, that is, floating, even if the current of the gate line signal output terminal is present
  • the output voltage VG is lower than the first power supply low voltage VSS1 (under normal operation, the low voltage output from the gate line signal output terminal is lower than the first power supply low voltage VSS1), the first diode D1 and the second diode D2 It will not turn on.
  • FIG. 11 is a detailed circuit diagram of a protection circuit in accordance with an embodiment of the present invention.
  • the first voltage gating module 21 includes a first switch SW1 and a second switch SW2, and a first end of the first switch SW1 is connected to a first output end of the first voltage source,
  • the second end of the first switch SW1 is the first output end V1 of the first voltage gating module, the third end of the first switch SW1 is the control end, and the first end of the second switch SW2 is Connected to the second output end of the first voltage source, the second end of the second switch SW2 is the second output end V2 of the first voltage gating module 21, and the third end of the second switch SW2
  • the end is the control end.
  • the third end of the first switch SW1 and the third end of the second switch SW2 are connected to the control end Con1.
  • the second voltage gating module 23 includes a third switch SW3 and a fourth switch SW4, and a first end of the third switch SW3 is connected to a first output end of the second voltage source,
  • the second end of the third switch SW3 is the first output end V3 of the second voltage gating module, the third end of the third switch SW3 is the control end, and the first end of the fourth switch SW4 is Connected to the second output end of the second voltage source, the second end of the fourth switch SW4 is the second output end V4 of the second voltage gating module 23, and the third end of the fourth switch SW4 The end is the control end.
  • the third end of the third switch SW3 and the third end of the fourth switch SW4 are connected to the control end Con2.
  • the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 may be implemented by TFTs, and may all be N-type TFTs, or may both be P-type TFTs.
  • the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 are all N-type TFTs, or both are P-type TFTs
  • the first control terminal Con1 and the second control terminal The signal of Con2 is inverted.
  • the second control terminal Con2 When the first control terminal Con1 is at a high level, the second control terminal Con2 is at a low level; when the first control terminal Con1 is at a low level, the second control terminal Con1 is at a high level.
  • first switch SW1 and the second switch SW2 are N-type TFTs and the third switch SW3 and the fourth switch SW4 are P-type TFTs, or the first switch SW1 and the second switch SW2 are P-type TFTs and third
  • the first control terminal in the case where the switch SW3 and the fourth switch SW4 are N-type TFTs Con1 and the second control terminal Con2 can be the same control terminal.
  • Figure 12 is a schematic block diagram of an nth stage shift register of a GOA unit.
  • the shift register includes an input module, an output module, and a reset module, and a connection point between the input module and the output module is a drive signal output control node CON.
  • the input module receives a gate drive signal outputted by a shift stage register of a previous stage (ie, an n-1th stage), and the reset module receives a gate drive of a shift register output of a next stage (ie, an n+1th stage) signal.
  • the output module of the shift register outputs an active level (eg, a high level) of the gate drive signal when the drive signal output control node is at an active level (eg, a high level).
  • the first control terminal Con1 and the driving signal output control node CON Connected the driving signal output control node CON may be connected to an input terminal of the inverter, and the inverter inverts and outputs a signal input from the driving signal output control node CON, the second control terminal Con2 Connected to the output of the inverter.
  • the protection circuit according to an embodiment of the present invention may further include a control module.
  • Figure 13 is a schematic block diagram of a control module in accordance with an embodiment of the present invention.
  • the control module can include an input module, a reset module, and an inverter.
  • the input module receives a gate drive signal outputted by a shift stage register of a previous stage (ie, an n-1th stage), and the reset module receives a gate drive of a shift register output of a next stage (ie, an n+1th stage) signal.
  • the input module and the reset module may be the same as the input module and the reset module shown in FIG. 12, and details are not described herein again. It is necessary to ensure that the level of the first control terminal Con1 of the control circuit in FIG. 13 is the same as the level of the drive signal output control node CON of the shift register in FIG.
  • the drive signal output control node CON is at a high level
  • the gate line signal output terminal outputs a high level of the gate drive signal
  • the first control terminal Con1 is at a high level
  • the first switch SW1 and the second switch SW2 are N-type TFTs
  • the third switch SW3 and the fourth switch SW4 are also N-type TFTs
  • the signals of the first control terminal Con1 and the second control terminal Con2 are inverted.
  • the first control terminal Con1 is at a high level
  • the second control terminal Con2 is at a low level
  • the first switch SW1 and the second switch SW2 are turned on
  • the third switch SW3 and the fourth switch SW4 are turned off.
  • the first switch SW1 and the second switch SW2 are N-type TFTs
  • the third switch SW3 and the fourth switch SW4 are P-type TFTs
  • the first control end Con1 and the second control end Con2 are the same control end.
  • the inverter shown in Fig. 13 can be omitted.
  • the first switch SW1 and the second switch SW2 are turned on, and output the first voltage source at the second end of the first switch SW1
  • the first power supply high voltage, and the first power supply low voltage of the first voltage source is outputted at the second end of the second switch SW2, and the third switch SW3 and the fourth switch SW4 are turned off.
  • the embodiment of the present invention is described above by taking the high voltage of the gate driving signal as an effective driving voltage.
  • the embodiment of the present invention is not limited thereto, and the effective driving voltage of the gate driving signal may be a low voltage.
  • the high level of the gate driving signal can be made within a predetermined high level range and the gate driving signal is made
  • the low level is within a predetermined low level, thereby not only avoiding TFT damage in the pixel circuit due to voltage shock generated by EDS or EOS on the gate driving signal, but also eliminating gate driving signal distortion caused by EDS or EOS. Causes the display panel to display an adverse effect on the abnormality.
  • the embodiment of the present invention further provides an array substrate, comprising the protection circuit of the array substrate driving GOA unit of any of the above.

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Abstract

一种阵列基板行驱动单元的保护电路，涉及阵列基板行驱动GOA单元的ESD或EOS防护。所述保护电路包括：第一电压选通模块(21)，其被配置为在栅线信号输出端(VG)应输出栅极驱动信号的有效驱动电压时，输出所述第一电压源的输出端的输出电压(VDD1)；第一保护模块(22)，其输入端与所述第一电压选通模块(21)的输出端连接，并且其输出端与栅线连接；其中，在所述第一电压源的输出电压(VDD1)与所述栅线信号输出端(VG)的当前输出电压满足第一预定条件的情况下，所述第一保护模块(22)将所述第一电压源的输出端的输出电压(VDD1)输出作为调整后的栅极驱动信号(VGG)。

Description

阵列基板行驱动单元的保护电路和阵列基板 技术领域
本实用新型涉及阵列基板行驱动(Gate on Array，GOA)单元的ESD或EOS防护，并且更具体地涉及一种GOA单元的保护电路和阵列基板。
背景技术
静电放电(Electrical Static Discharge，ESD)是目前电子设备的头号杀手。在显示领域内，由于例如薄膜晶体管型液晶显示器(TFT-LCD)的显示屏幕面积大、包括TFT-LCD的电子设备与人体直接接触等原因，TFT-LCD容易受到ESD影响而造成显示异常。此外，TFT-LCD还容易受到过渡电性应力(Electrical Over Stress，EOS)的影响。
在显示领域内，阵列基板行驱动(GOA)单元一般都集成在显示面板的外侧，比较容易受到ESD或EOS的影响。尤其在各种超薄型(Air)的电子设备中，更容易导致GOA单元被击穿，导致显示面板显示异常。
因此，需要针对GOA单元进行ESD或EOS防护，从而增强显示面板的可靠度，进而提升电子设备的品质。
发明内容
为了解决上述技术问题，本实用新型提供了一种阵列基板行驱动GOA单元的保护电路，其与GOA单元的栅线信号输出端连接，其特征在于，所述保护电路包括：第一电压选通模块，其输入端与第一电压源的输出端连接，并且被配置为在所述栅线信号输出端应输出栅极驱动信号的有效驱动电压时，在其输出端输出所述第一电压源的输出端的输出电压；第一保护模块，其输入端与所述第一电压选通模块的输出端连接，并且其输出端与栅线连接；其中，在所述第一电压源的输出端的输出电压与所述栅线信号输出端的当前输出电压满足第一预定条件的情况下，所述第一保护模块将所述第一电压源的输出端的输出电压输出作为调整后的栅极驱动信号。
根据本实用新型实施例，所述保护电路还包括：第二电压选通模块，其输入端与第二电压源的输出端连接，并且被配置为在所述栅线信号输出端应输出栅极驱动信号的非有效驱动电压时，在其输出端输出所述第二电压源的 输出端的输出电压；第二保护模块，其输入端与所述第二电压选通模块的输出端连接，并且其输出端与所述栅线连接；其中，在所述第二电压源的输出端的输出电压与所述栅线信号输出端的当前输出电压满足第二预定条件的情况下，所述第二保护模块将所述第二电压源的输出端的输出电压输出作为调整后的栅极驱动信号。
本实用新型实施例还提供了一种阵列基板，包括上述任一阵列基板行驱动GOA单元的保护电路。
本实用新型的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本实用新型而了解。本实用新型的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
通过结合附图对本实用新型实施例进行更详细的描述，本实用新型的上述以及其它目的、特征和优势将变得更加明显。附图用来提供对本实用新型实施例的进一步理解，并且构成说明书的一部分，与本实用新型实施例一起用于解释本实用新型，并不构成对本实用新型的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
图1是根据本实用新型实施例的GOA单元及其栅极驱动信号的示意图；
图2是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的一种示意性框图；
图3是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的另一种示意性框图；
图4是根据本实用新型实施例的对GOA单元输出的栅极驱动信号的高电压进行防护的第一保护模块的原理图；
图5是根据本实用新型实施例的图4所示的第一保护模块的示意性电路图；
图6是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的又一种示意性框图；
图7是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的再一种示意性框图；
图8是根据本实用新型实施例的对GOA单元输出的栅极驱动信号的低电压进行防护的第二保护模块的原理图；
图9是根据本实用新型实施例的图8所示的第二保护模块的示意性电路图；
图10是根据本实用新型实施例的对GOA单元输出的栅极驱动信号的高电压和低电压进行防护的第一保护模块和第二保护模块的组合电路图；
图11是根据本实用新型实施例的保护电路的具体电路图；
图12是一种GOA单元的第n级移位寄存器的示意性框图；以及
图13是根据本实用新型实施例的控制模块的示意性框图。
具体实施方式
为了使得本实用新型实施例的目的、技术方案和优点更为明显，下面将参照附图详细描述本实用新型的示例实施例。显然，所描述的示例实施例仅仅是本实用新型的一部分实施例，而不是本实用新型的全部实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本实用新型的保护范围之内。
这里，需要注意的是，在附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
图1是根据本实用新型实施例的阵列基板及其栅极驱动信号的示意图。由图1中的右图可见，阵列基板包括像素阵列、数据驱动电路和栅极驱动电路(即，GOA单元)。
例如，像素阵列包括M行N列，GOA单元具有M条栅线，像素阵列中位于同一行的像素均连接到同一条栅线，数据驱动电路具有N条数据线，像素阵列中位于同一列的像素均连接到同一条数据线。应了解，阵列基板中的像素阵列、数据驱动电路和GOA单元的连接方式不限于此，本实用新型不受像素阵列、数据驱动电路和GOA单元的连接方式的限制。
如图1中的左图可见，通常GOA单元的栅线输出的栅极驱动信号为方波脉冲信号，该脉冲信号具有高电压VGH和低电压VGL。对于N型TFT而言，高电压VGH为导通电压，低电压VGL为截止电压；对于P型TFT而言，高电压VGH为截止电压，低电压VGL为导通电压。下面，以N型TFT为例展开描述。
在像素阵列中与栅线连接的TFT为N型TFT的情况下，在栅极驱动信号处于低电压VGL时，TFT处于截止状态，不会将数据线上的数据信号传递到像素，从而与该栅线连接的一行像素不会根据数据线上当前输出的数据信号进行显示；在栅极驱动信号处于高电压VGH时，TFT处于导通状态，可以将数据线上的数据信号传递到像素，从而与该栅线连接的一行像素会根据数据线上当前输出的数据信号进行显示。
然而，由于静电放电ESD或过渡电性应力EOS的影响，可能使得栅极驱动信号的波形发生畸变，这样的畸变不仅可能造成液晶面板上图像显示异常，甚至可能造成液晶面板上像素电路中TFT的损坏。
为了避免由于ESD或EOS的影响使得栅极驱动信号的波形发生畸变导致显示异常或像素电路损坏的现象，根据本实用新型实施例，提出了分别对GOA单元输出的栅极驱动信号的高电压和低电压进行防护的概念。
图2是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的一种示意性框图。
如图2所示，所述保护电路包括第一电压选通模块21和第一保护模块22。
第一电压选通模块21的输入端与第一电压源的输出端连接，第一电压选通模块21的输出端与第一保护模块22的输入端连接。在所述栅线信号输出端应输出栅极驱动信号的有效驱动电压时，所述第一电压选通模块21的输出端输出所述第一电压源的输出端的输出电压。
第一保护模块22的另一输入端与所述栅线信号输出端VG连接，并且第一保护模块22的输出端VGG与栅线连接。
在所述第一电压源的输出端的输出电压与所述栅线信号输出端的当前输出电压满足第一预定条件的情况下，所述第一保护模块将所述第一电压源的输出端的输出电压输出作为所述栅极驱动信号。
根据具体电路设计，所述栅极驱动信号的有效驱动电压可以为高电压，或者也可以为低电压。所述ESD或EOS对所述栅线信号输出端的输出电压的影响可以体现为电压冲击，该电压冲击可以为正冲击或者可以为负冲击。下面以所述栅极驱动信号的有效驱动电压为高电压、且所述栅极驱动信号的非有效驱动电压为低电压为例展开描述。所述有效驱动电压能够使与栅线连接的晶体管导通，所述非有效驱动电压不能使与栅线连接的晶体管导通。
由于受到ESD或EOS的影响，所述栅极驱动信号的有效驱动电压可能出现冲击，在该冲击的幅度非常高的情况下，可能直接击穿接收所述栅极驱动信号的像素电路中的TFT，因此需要抑制这样的冲击。
根据本实用新型实施例，所述第一电压源的输出端包括第一输出端，所述第一输出端的输出电压为第一电源高电压VDD1，所述第一电压选通模块的输入端包括第一输入端，所述第一电压选通模块的输出端包括第一输出端，所述第一保护模块的输入端包括第一输入端和第三输入端，所述第一保护模块的第一输入端与所述第一电压选通模块的第一输出端连接，所述第一保护模块的第三输入端与所述栅线信号输出端连接。
具体地，在所述栅线信号输出端应输出栅极驱动信号的高电压VGH时，所述第一电压选通模块21的第一输出端输出所述第一电源高电压VDD1，在正常工作情况下VDD1>VGH，并且在所述栅线信号输出端的当前输出电压VG高出所述第一电源高电压VDD1的情况下，所述第一保护模块22将所述栅线信号输出端的当前输出电压VG下拉至所述第一电源高电压VDD1，并且所述第一保护模块22的输出端输出所述第一电源高电压VDD1作为调整后的栅极驱动信号VGG。
应了解，由于受到ESD或EOS的影响，所述栅极驱动信号的有效电平(高电平)不仅可能出现正冲击还可能出现负冲击，因此不仅需要抑制正冲击还需要抑制负冲击。
图3是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的另一种示意性框图。
如图3所示，所述第一电压源的输出端还包括第二输出端，所述第二输出端的输出电压为第一电源低电压VSS1，所述第一电压选通模块21还包括第二输入端，所述第一电压选通模块21的第二输入端与所述第一电压源的第二输出端连接，所述第一保护模块22的输入端还包括第二输入端，所述第一保护模块22的第二输入端与所述第一电压选通模块21的第二输出端连接。
具体地，在所述栅线信号输出端应输出栅极驱动信号的高电压时，所述第一电压选通模块21的第二输出端输出所述第一电源低电压VSS1，并且在所述栅线信号输出端的当前输出电压低于所述第一电源低电压VSS1的情况下，所述第一保护模块22将所述栅线信号输出端的当前输出电压上拉至所述第一电源低电压VSS1，并且所述第一保护模块22的输出端输出所述第一电 源低电压VSS1作为调整后的栅极驱动信号。
所述第一电源高电压VDD1、所述栅极驱动信号的正常高电压VGH、以及所述第一电源低电压VSS1应满足以下关系：VDD1>VGH>VSS1。
图4是根据本实用新型实施例的对GOA单元输出的栅极驱动信号的高电压进行防护的第一保护模块22的原理图。所述第一保护模块22用于控制或调整所述栅极驱动信号VG的高电压VGH。
如图4所示，所述第一保护模块22可以包括第一电阻R1和第一保护元件S1。所述第一电阻R1连接在所述栅线信号输出端与所述第一保护模块22的输出端AA之间，所述第一保护元件S1连接在所述第一保护模块22的输出端和所述第一电压选通模块21的第一输出端V1(即VDD1)之间。
所述第一保护元件S1可以在ESD或EOS发生时将ESD或EOS能量吸收，或者将ESD或EOS能量释放至其它回路中。例如，所述第一保护元件S1可以是开关迅速的二极管、压敏电阻、或高分子聚合物，也可以是由多种半导体元件或其它元件组成的ESD/EOS防护电路。
在所述栅极驱动信号VG的高电压VGH由于ESD或EOS的影响而超出第一电压源的高电压VDD1时，所述第一保护元件S1导通，将ESD或EOS能量吸收，或者将ESD或EOS能量释放至所述第一电压源，具体地经由所述第一电压选通模块21释放至所述第一电压源的第一输出端，从而使所述第一保护模块22的输出端将所述第一电压源的第一输出端的高电压VDD1输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的高电压VGH为所述第一电压源的第一输出端的高电压VDD1。
此外，如图4所示，所述第一保护模块22还可以包括第二保护元件S2。所述第二保护元件S2连接在所述第一保护模块22的输出端和所述第一电压选通模块21的第二输出端V2(即，VSS1)之间。所述第二保护元件S2可以在ESD或EOS发生时将ESD或EOS能量吸收，或者将ESD或EOS能量释放至其它回路中。例如，所述第二保护元件S2可以是开关迅速的二极管、压敏电阻、或高分子聚合物，也可以是由多种半导体元件或其它元件组成的ESD/EOS防护电路。
在所述栅极驱动信号VG的高电压VGH由于ESD或EOS的影响而低于第一电压源的第二输出端的低电压VSS1时，所述第二保护元件S2导通，将ESD或EOS能量吸收，或者将ESD或EOS能量释放至所述第一电压源，具 体地经由所述第一电压选通模块21释放至所述第一电压源的第二输出端，从而使所述第一保护模块22的输出端将所述第一电压源的第二输出端的低电压VSS1输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的高电压VGH为所述第一电压源的第一输出端的低电压VSS1。例如，所述第一电源低电压VSS1可以例如为公共地电压VGND。
此外，根据需要，所述第一保护模块22还可以包括第一电容C1，所述第一电容C1连接在所述栅线信号输出端与所述第一电压选通模块21的第二输出端之间。
图5是根据本实用新型实施例的图4所示的第一保护模块22的示意性电路图。
如图5所示，所述第一保护元件S1为第一二极管D1，所述第二保护元件S2为第二二极管D2。
所述第一二极管D1的阳极和阴极分别连接所述第一保护模块22的输出端和所述第一电压选通模块21的第一输出端V1(即VDD1)，所述第二二极管D2的阳极和阴极分别连接所述第一电压选通模块21的第二输出端V2(即VSS1)和所述第一保护模块22的输出端。
一方面，在所述栅极驱动信号VG的高电压VGH由于ESD或EOS的影响而超出第一电压源的高电压VDD1时，所述第一二极管D1导通，经由所述第一电压选通模块21，将ESD或EOS能量释放至所述第一电压源的第一输出端，从而使所述第一保护模块22的输出端将所述第一电压源的第一输出端的高电压VDD1输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的高电压VGH为所述第一电源高电压VDD1。
另一方面，在所述栅极驱动信号VG的高电压VGH由于ESD或EOS的影响而低于第一电压源的低电压VSS1时，所述第二二极管D2导通，经由所述第一电压选通模块21，将ESD或EOS能量释放至所述第一电压源的第二输出端，从而使所述第一保护模块22的输出端将所述第一电压源的第二输出端的低电压VSS1输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的高电压VGH为所述第一电源低电压VSS1。
由此，通过第一电压选通模块21和第一保护模块22可以将栅极驱动信号VG的高电压VGH箝位在一定的电压范围之内，具体地在VSS1到VDD1的范围之内，从而可以避免ESD或EOS对像素电路中的TFT造成损坏。更 进一步，通过适当地选择VSS1和VDD1的大小，例如，VDD1略高于正常VGH且VSS略低于正常VGH，具体地例如VDD比正常VGH高0.5V且VSS比正常VGH低0.5V，可以使得调整后的栅极驱动信号VGG的高电压VGH在预定的高电压范围内，从而使得像素电路能够正常地读取数据线上的数据信号，从而能够正常地进行显示，避免了由于ESD或EOS造成栅极驱动信号VG的畸变所导致的显示异常。
图6是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的又一种示意性框图。
如图6所示，除了第一电压选通模块21和第一保护模块22之外，所述保护电路还包括第二电压选通模块23和第二保护模块24。
如前所述，第一电压选通模块21的输入端与第一电压源的输出端连接，第一电压选通模块21的输出端与第一保护模块22的输入端连接。在所述栅线信号输出端应输出栅极驱动信号的有效驱动电压(例如，高电压)时，所述第一电压选通模块21的输出端输出所述第一电压源的输出端的输出电压。第一保护模块22的另一输入端与所述栅线信号输出端连接，并且第一保护模块22的输出端与栅线连接。
第二电压选通模块23的输入端与第二电压源的输出端连接，第二电压选通模块23的输出端与第二保护模块24的输入端连接。在所述栅线信号输出端应输出栅极驱动信号的非有效驱动电压(例如，低电压)时，所述第二电压选通模块23的输出端输出所述第二电压源的输出端的输出电压。第二保护模块24的另一输入端与所述栅线信号输出端连接。
所述第一保护模块22和第二保护模块24共用一部分电路，所述第一保护模块22的所述另一输入端和所述第二保护模块24的所述另一输入端为同一输入端，该同一输入端与所述栅线信号输出端连接，所述共用的电路的一端为所述同一输入端，并且另一端与所述栅线连接。
具体地，在所述第二电压源的输出端的输出电压与所述栅线信号输出端的当前输出电压满足第二预定条件的情况下，所述第二保护模块24将所述第二电压源的输出端的输出电压输出作为调整后的栅极驱动信号。
由于受到ESD或EOS的影响，所述栅极驱动信号的非有效驱动电压(低电压)可能出现冲击，在该冲击的幅度非常高的情况下，可能直接击穿接收所述栅极驱动信号的像素电路中的TFT，因此需要抑制这样的冲击。
根据本实用新型实施例，所述第二电压源的输出端包括第一输出端，所述第一输出端的输出电压为第二电源高电压，所述第二电压选通模块的输入端包括第一输入端，所述第二电压选通模块的输出端包括第一输出端，所述第二保护模块的输入端包括第一输入端和第三输入端，所述第二保护模块的第一输入端与所述第二电压选通模块的第一输出端连接，所述第二保护模块的第三输入端与所述栅线信号输出端连接。这里，所述第一保护模块的第三输入端和所述第二保护模块的第三输入端为共用的同一输入端。
具体地，在所述栅线信号输出端应输出栅极驱动信号的低电平VGL时，所述第二电压选通模块23的第一输出端输出所述第二电源高电压VDD2，在正常工作情况下VDD2>VGL，并且在所述栅线信号输出端的当前输出电压VG高出所述第二电源高电压VDD2的情况下，所述第二保护模块24将所述栅线信号输出端的当前输出电压VG下拉至所述第二电源高电压VDD2，并且所述第二保护模块24的输出端输出所述第二电源高电压VDD2作为调整后的栅极驱动信号VGG。
应了解，由于受到ESD或EOS的影响，所述栅极驱动信号的非有效驱动电压(低电压)不仅可能出现正冲击还可能出现负冲击，因此不仅需要抑制正冲击还需要抑制负冲击。
图7是根据本实用新型实施例的与阵列基板行驱动GOA单元的栅线信号输出端连接的保护电路的再一种示意性框图。
如图7所示，所述第二电压源的输出端还包括第二输出端，所述第二输出端的输出电压为第二电源低电压VSS2。
第二电压选通模块23的输入端还包括第二输入端，第二电压选通模块23的第二输入端与第二电压源的第二输出端连接。除了第一输出端V3之外，第二电压选通模块23的输出端还包括第二输出端V4，所述第二保护模块24的输入端还包括第二输入端，所述第二保护模块24的第二输入端与所述第二电压选通模块23的第二输出端V4连接。
具体地，在所述栅线信号输出端应输出栅极驱动信号的低电平时，所述第二电压选通模块23的第二输出端V4输出所述第二电源低电压VSS2，并且在所述栅线信号输出端的当前输出电压低于所述第二电源低电压VSS2的情况下，所述第二保护模块24将所述栅线信号输出端的当前输出电压上拉至所述第二电源低电压VSS2，并且所述第二保护模块24的输出端输出所述第 二电源低电压VSS2作为调整后的栅极驱动信号。
所述第二电源高电压VDD2、所述栅极驱动信号的低电压VGL、以及所述第二电源低电压VSS2应满足以下关系：VDD2>VGL>VSS2。
根据需要，所述第一电源低电压VSS1可以高于所述第二电源高电压VDD2，或者所述第一电源低电压VSS1可以与所述第二电源高电压VDD2相同。因此，第一电源高电压VDD1、栅极驱动信号的高电压VGH、第一电源低电压VSS1、第二电源高电压VDD2、栅极驱动信号的低电压VGL。第二电源低电压VSS2应满足以下关系：VDD1>VGH>VSS1≥VDD2>VGL>VSS2。
在VGL小于零的情况下，可选地VSS1和VDD2可以为公共地电压GND。
图8是根据本实用新型实施例的对GOA单元输出的栅极驱动信号的低电压进行防护的第二保护模块24的原理图。所述第二保护模块24用于控制所述栅极驱动信号VG的低电压VGL。
如图8所示，所述第二保护模块24可以包括第一电阻R1和第三保护元件S3。所述第一保护模块22和第二保护模块24共用所述第一电阻R1。
所述第一电阻R1连接在所述栅线信号输出端与所述第二保护模块24的输出端之间，所述第一保护模块22和所述第二保护模块24的输出端为同一输出端。所述第三保护元件S3连接在所述第二保护模块24的输出端和所述第二电压选通模块23的第一输出端之间。
在所述栅极驱动信号VG的低电压VGL由于ESD或EOS的影响而超出第二电压源的高电压VDD2时，所述第三保护元件S3导通，将ESD或EOS能量吸收，或者将ESD或EOS能量释放至所述第二电压源，具体地经由所述第二电压选通模块23释放至所述第二电压源的第一输出端，从而使所述第二保护模块24的输出端将所述第二电压源的第一输出端的高电压VDD2输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的低电压VGL为所述第二电源高电压VDD2。
此外，如图8所示，所述第二保护模块24还可以包括第二电容C2。所述第二电容C2连接在所述栅线信号输出端与所述第二电压选通模块22的第一输出端之间。
此外，如图8所示，所述第二保护模块24还可以包括第四保护元件S4。 所述第四保护元件S4连接在所述第二保护模块24的输出端和所述第二电压选通模块23的第二输出端之间。
在所述栅极驱动信号VG的低电压VGL由于ESD或EOS的影响而低于第二电压源的低电压VSS2时，所述第四保护元件S4导通，将ESD或EOS能量吸收，或者将ESD或EOS能量释放至所述第一电压源，具体地经由所述第二电压选通模块23释放至所述第一电压源的第二输出端，从而使所述第二保护模块24的输出端将所述第二电压源的第二输出端的低电压VSS2输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的低电压VGL为所述第二电源低电压VSS2。
所述第三保护元件S3和所述第四保护元件S4可以在ESD或EOS发生时将ESD或EOS能量吸收，或者将ESD或EOS能量释放至其它回路中。例如，所述第三保护元件S3和所述第四保护元件S4可以是开关迅速的二极管、压敏电阻、或高分子聚合物，也可以是由多种半导体元件或其它元件组成的ESD/EOS防护电路。
图9是根据本实用新型实施例的图8所示的第二保护模块24的示意性电路图。
如图9所示，所述第三保护元件S3为第三二极管D3，所述第四保护元件S4为第四二极管D4。
所述第三二极管D3的阳极和阴极分别连接所述第二保护模块24的输出端和所述第二电压选通模块23的第一输出端，所述第四二极管D4的阳极和阴极分别连接所述第二电压选通模块23的第二输出端和所述第二保护模块24的输出端。
一方面，在所述栅极驱动信号VG的低电压VGL由于ESD或EOS的影响而超出第二电压源的高电压VDD2时，所述第三二极管D3导通，经由所述第二电压选通模块23，将ESD或EOS能量释放至所述第二电压源的第一输出端，从而使所述第二保护模块24的输出端将所述第二电压源的第一输出端的高电压VDD2输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的高电压VGH为所述第二电源高电压VDD2。
另一方面，在所述栅极驱动信号VG的低电压VGL由于ESD或EOS的影响而低于第二电压源的低电压VSS2时，所述第四二极管D4导通，经由所述第二电压选通模块23，将ESD或EOS能量释放至所述第二电压源的第二 输出端，从而使所述第二保护模块24的输出端将所述第二电压源的第二输出端的低电压VSS2输出作为调整后的栅极驱动信号VGG，即使得调整后的栅极驱动信号VGG的低电压VGL为所述第二电源低电压VSS2。
由此，通过第二电压选通模块23和第二保护模块24可以将栅极驱动信号VG的低电压VGL箝位在一定的电压范围之内，具体地在VSS2到VDD2的范围之内，从而可以避免ESD或EOS对像素电路中的TFT造成损坏。更进一步，通过适当地选择VSS2和VDD2的大小，例如，VDD2略高于VGL且VSS2略低于VGL，具体地例如VDD2比VGL高0.5V且VSS2比VGL低0.5V，可以使得调整后的栅极驱动信号VGG的低电压VGL在预定的低电压范围内，从而使得像素电路能够正常地读取数据线上的数据信号，从而能够正常地进行显示，避免了由于ESD或EOS造成栅极驱动信号VG的畸变所导致的显示异常。
图10是根据本实用新型实施例的对GOA单元输出的栅极驱动信号的高电压和低电压进行防护的第一保护模块22和第二保护模块24的组合电路图。
在所述栅线信号输出端应输出栅极驱动信号的高电压VGH时，第一电压选通模块21将第一电压源的第一电源高电压VDD1施加到图10所示的输入端V1并且将第一电压源的第一电源低电压VSS1施加到图10所示的输入端V2，而第二电压选通模块23不将第二电压源的第二电源高电压VDD2施加到图10所示的输入端V3并且不将第二电压源的第二电源低电压VSS2施加到图10所示的输入端V4。在此情况下，在所述栅线信号输出端的当前输出电压VG超出所述第一电源高电压VDD1时，第一二极管D1导通，在所述栅线信号输出端的当前输出电压VG低于所述第一电源低电压VSS1时，第二二极管D2导通；但由于图10所示的输入端VDD2和VSS2没有输入电压，即浮置，因此即使所述栅线信号输出端的当前输出电压VG高于第二电源高电压VDD2(在正常工作情况下，栅线信号输出端输出的高电压高于第二电源高电压VDD2)，第三二极管D3和第四二极管D4也不会导通。
在所述栅线信号输出端应输出栅极驱动信号端的低电压VGL时，第二电压选通模块23将第二电压源的第二电源高电压VDD2施加到图10所示的输入端V3并且将第二电压源的第二电源低电压VSS2施加到图10所示的输入端V4，而第一电压选通模块21不将第一电压源的第一电源高电压VDD1施加到图10所示的输入端V1并且不将第一电压源的第一电源低电压VSS1施 加到图10所示的输入端V2。在此情况下，在所述栅线信号输出端的当前输出电压VG超出所述第二电源高电压VDD2时，第三二极管D3导通，在所述栅线信号输出端的当前输出电压VG低于所述第二电源低电压VSS2时，第四二极管D4导通；但由于图10所示的输入端V1和V2没有输入电压，即浮置，因此即使所述栅线信号输出端的当前输出电压VG低于第一电源低电压VSS1(在正常工作情况下，栅线信号输出端输出的低电压低于第一电源低电压VSS1)，第一二极管D1和第二二极管D2也不会导通。
图11是根据本实用新型实施例的保护电路的具体电路图。
如图11所示，所述第一电压选通模块21包括第一开关SW1和第二开关SW2，所述第一开关SW1的第一端与所述第一电压源的第一输出端连接，所述第一开关SW1的第二端为所述第一电压选通模块的第一输出端V1，所述第一开关SW1的第三端为控制端，所述第二开关SW2的第一端与所述第一电压源的第二输出端连接，所述第二开关SW2的第二端为所述第一电压选通模块21的第二输出端V2，所述第二开关SW2的第三端为控制端。所述第一开关SW1的第三端和第二开关SW2的第三端与控制端Con1连接。
如图11所示，所述第二电压选通模块23包括第三开关SW3和第四开关SW4，所述第三开关SW3的第一端与所述第二电压源的第一输出端连接，所述第三开关SW3的第二端为所述第二电压选通模块的第一输出端V3，所述第三开关SW3的第三端为控制端，所述第四开关SW4的第一端与所述第二电压源的第二输出端连接，所述第四开关SW4的第二端为所述第二电压选通模块23的第二输出端V4，所述第四开关SW4的第三端为控制端。所述第三开关SW3的第三端和第四开关SW4的第三端与控制端Con2连接。
在第一开关SW1、第二开关SW2、第三开关SW3、第四开关SW4可以由TFT实现，并且可以均为N型TFT，或可以均为P型TFT。
在第一开关SW1、第二开关SW2、第三开关SW3、第四开关SW4均为N型TFT，或者均为P型TFT的情况下，所述第一控制端Con1和所述第二控制端Con2的信号反相。在第一控制端Con1为高电平时，第二控制端Con2为低电平；在第一控制端Con1为低电平时，第二控制端Con1为高电平。
在第一开关SW1和第二开关SW2为N型TFT且第三开关SW3和第四开关SW4为P型TFT的情况下，或者在第一开关SW1和第二开关SW2为P型TFT且第三开关SW3和第四开关SW4为N型TFT的情况下第一控制端 Con1和第二控制端Con2可以为同一控制端。
图12是一种GOA单元的第n级移位寄存器的示意性框图。
如图12所示，所述移位寄存器包括输入模块、输出模块和复位模块，所述输入模块和输出模块之间的连接点为驱动信号输出控制节点CON。
所述输入模块接收上一级(即第n-1级)移位寄存器输出的栅极驱动信号，所述复位模块接收下一级(即第n+1级)移位寄存器输出的栅极驱动信号。在所述驱动信号输出控制节点为有效电平(例如，高电平)时，所述移位寄存器的输出模块输出所述栅极驱动信号的有效电平(例如，高电平)。
作为示例，在第一开关SW1、第二开关SW2、第三开关SW3、第四开关SW4均为同一类型的TFT的情况下，所述第一控制端Con1可以与所述驱动信号输出控制节点CON连接，所述驱动信号输出控制节点CON可以与反相器的输入端连接，所述反相器将从所述驱动信号输出控制节点CON输入的信号反相并输出，所述第二控制端Con2与所述反相器的输出端连接。
替换地，根据本实用新型实施例的保护电路还可以包括控制模块。图13是根据本实用新型实施例的控制模块的示意性框图。
所述控制模块可以包括输入模块、复位模块、以及反相器。所述输入模块接收上一级(即第n-1级)移位寄存器输出的栅极驱动信号，所述复位模块接收下一级(即第n+1级)移位寄存器输出的栅极驱动信号。所述输入模块和所述复位模块可以与图12中所示的输入模块和复位模块相同，在此不再赘述。需要保证，图13中控制电路的第一控制端Con1的电平与图12中移位寄存器的驱动信号输出控制节点CON的电平相同。
作为示例，所述驱动信号输出控制节点CON处于高电平，所述栅线信号输出端输出栅极驱动信号的高电平，所述第一控制端Con1处于高电平。
具体地，例如，第一开关SW1和第二开关SW2为N型TFT，第三开关SW3和第四开关SW4也为N型TFT，第一控制端Con1和第二控制端Con2的信号反相，在第一控制端Con1为高电平时第二控制端Con2为低电平，第一开关SW1和第二开关SW2导通，第三开关SW3和第四开关SW4截止。
具体地，再例如，第一开关SW1和第二开关SW2为N型TFT，第三开关SW3和第四开关SW4为P型TFT，第一控制端Con1和第二控制端Con2为同一控制端，在此情况下，可以省略图13中所示的反相器。第一开关SW1和第二开关SW2导通，并且在第一开关SW1的第二端输出所述第一电压源 的第一电源高电压，并且在第二开关SW2的第二端输出所述第一电压源的第一电源低电压，第三开关SW3和第四开关SW4截止。
上面以栅极驱动信号的高电压为有效驱动电压为例描述了本实用新型实施例，然而应了解本实用新型实施例不限于此，所述栅极驱动信号的有效驱动电压可以为低电压。
根据本实用新型实施例，通过分别对GOA单元输出的栅极驱动信号的高电压和低电压进行防护，可以使得栅极驱动信号的高电平在预定高电平范围内并且使得栅极驱动信号的低电平在预定低电平范围内，从而不仅可以避免由于EDS或EOS在栅极驱动信号上产生电压冲击导致像素电路中TFT损坏，而且还可以消除由于EDS或EOS造成栅极驱动信号畸变导致显示面板显示异常的不利影响。
本实用新型实施例还提供了一种阵列基板，包括上述任一所述的阵列基板行驱动GOA单元的保护电路。
在上面详细描述了本实用新型的各个实施例。然而，本领域技术人员应该理解，在不脱离本实用新型的原理和精神的情况下，可对这些实施例进行各种修改，组合或子组合，并且这样的修改应落入本实用新型的范围内。
本申请要求2015年09月08日提交的申请号为201520692483.6且实用新型名称为“阵列基板行驱动单元的保护电路和阵列基板”的中国优先申请的优先权，通过引用将其全部内容并入于此。

Claims (13)

  1. 一种阵列基板行驱动GOA单元的保护电路，其与GOA单元的栅线信号输出端连接，其特征在于，所述保护电路包括：
    第一电压选通模块，其输入端与第一电压源的输出端连接，并且被配置为在所述栅线信号输出端应输出栅极驱动信号的有效驱动电压时，在其输出端输出所述第一电压源的输出端的输出电压；
    第一保护模块，其输入端与所述第一电压选通模块的输出端连接，并且其输出端与栅线连接；
    其中，在所述第一电压源的输出端的输出电压与所述栅线信号输出端的当前输出电压满足第一预定条件的情况下，所述第一保护模块将所述第一电压源的输出端的输出电压输出作为调整后的栅极驱动信号。
  2. 如权利要求1所述的保护电路，其特征在于，
    所述栅极驱动信号的有效驱动电压为高电压，
    所述第一电压源的输出端包括第一输出端，所述第一输出端的输出电压为第一电源高电压，
    所述第一电压选通模块的输入端包括第一输入端，所述第一输入端与所述第一电压源的第一输出端连接，所述第一电压选通模块的输出端包括第一输出端，
    所述第一保护模块的输入端包括第一输入端，所述第一保护模块的第一输入端与所述第一电压选通模块的第一输出端连接，
    其中，在所述栅线信号输出端应输出栅极驱动信号的高电压时，所述第一电压选通模块的第一输出端输出所述第一电源高电压，并且在所述栅线信号输出端的当前输出电压高出所述第一电源高电压的情况下，所述第一保护模块将所述栅线信号输出端的当前输出电压下拉至所述第一电源高电压，并且所述第一保护模块的输出端输出所述第一电源高电压作为调整后的栅极驱动信号。
  3. 如权利要求2所述的保护电路，其特征在于，
    所述第一电压源的输出端还包括第二输出端，所述第二输出端的输出电压为第一电源低电压，
    所述第一电压选通模块的输入端还包括第二输入端，所述第二输入端与 所述第一电压源的第二输出端连接，所述第一电压选通模块的输出端还包括第二输出端，
    所述第一保护模块的输入端还包括第二输入端，所述第一保护模块的第二输入端与所述第一电压选通模块的第二输出端连接，
    其中，在所述栅线信号输出端应输出栅极驱动信号的高电压时，所述第一电压选通模块的第二输出端输出所述第一电源低电压，并且在所述栅线信号输出端的当前输出电压低于所述第一电源低电压的情况下，所述第一保护模块将所述栅线信号输出端的当前输出电压上拉至所述第一电源低电压，并且所述第一保护模块的输出端输出所述第一电源低电压作为调整后的栅极驱动信号。
  4. 如权利要求1所述的保护电路，其特征在于，所述保护电路还包括：
    第二电压选通模块，其输入端与第二电压源的输出端连接，并且被配置为在所述栅线信号输出端应输出栅极驱动信号的非有效驱动电压时，在其输出端输出所述第二电压源的输出端的输出电压；
    第二保护模块，其输入端与所述第二电压选通模块的输出端连接，并且其输出端与所述栅线连接；
    其中，在所述第二电压源的输出端的输出电压与所述栅线信号输出端的当前输出电压满足第二预定条件的情况下，所述第二保护模块将所述第二电压源的输出端的输出电压输出作为调整后的栅极驱动信号。
  5. 如权利要求4所述的保护电路，其特征在于，
    所述栅极驱动信号的非有效驱动电压为低电压，
    所述第二电压源的输出端包括第一输出端，所述第一输出端的输出电压为第二电源高电压，
    所述第二电压选通模块的输入端包括第一输入端，所述第二电压选通模块的第一输入端与所述第二电压源的第一输出端连接，所述第二电压选通模块的输出端包括第一输出端，
    所述第二保护模块的输入端包括第一输入端，所述第二保护模块的第一输入端与所述第二电压选通模块的第一输出端连接，
    其中，在所述栅线信号输出端应输出栅极驱动信号的低电压时，所述第二电压选通模块的第一输出端输出所述第二电源高电压，并且在所述栅线信号输出端的当前输出电压高出所述第二电源高电压的情况下，所述第二保护 模块将所述栅线信号输出端的当前输出电压下拉至所述第二电源高电压并输出所述第二电源高电压作为调整后的栅极驱动信号。
  6. 如权利要求5所述的保护电路，其特征在于，
    所述第二电压源的输出端还包括第二输出端，所述第二输出端的输出电压为第二电源低电压，
    所述第二电压选通模块的输入端还包括第二输入端，所述第二电压选通模块的第二输入端与所述第二电压源的第二输出端连接，所述第二电压选通模块的输出端包括第一输出端，
    所述第二保护模块的输入端还包括第二输入端，所述第二保护模块的第二输入端与所述第二电压选通模块的第二输出端连接，
    其中，在所述栅线信号输出端应输出栅极驱动信号的低电压时，所述第二电压选通模块的第二输出端输出所述第二电源低电压，并且在所述栅线信号输出端的当前输出电压低于所述第二电源低电压的情况下，所述第二保护模块将所述栅线信号输出端的当前输出电压上拉至所述第二电源低电压并输出所述第二电源低电压作为调整后的栅极驱动信号。
  7. 如权利要求3所述的保护电路，其特征在于，
    所述栅线信号输出端为所述GOA单元中的移位寄存器的输出端，所述移位寄存器包括输入模块、输出模块和复位模块，所述输入模块和输出模块之间的连接点为驱动信号输出控制节点，
    所述第一电压选通模块包括第一开关和第二开关，所述第一开关的第一端与所述第一电压源的第一输出端连接，所述第一开关的第二端为所述第一电压选通模块的第一输出端，所述第一开关的第三端为控制端，所述第二开关的第一端与所述第一电压源的第二输出端连接，所述第二开关的第二端为所述第一电压选通模块的第二输出端，所述第二开关的第三端为控制端，
    所述第一开关和第二开关的第三端与所述驱动信号输出控制节点连接，或者所述第一开关和第二开关的第三端与另一节点连接，所述另一节点处的电平与所述驱动信号输出控制节点处的电平相同，
    在所述栅线信号输出端输出栅极驱动信号的高电平时所述驱动信号输出控制节点处于有效电平，使得第一开关和第二开关导通，在第一开关的第二端输出所述第一电压源的第一电源高电压，并且在第二开关的第二端输出所述第一电压源的第一电源低电压。
  8. 如权利要求6所述的保护电路，其特征在于，
    所述栅线信号输出端为所述GOA单元中的移位寄存器的输出端，所述移位寄存器包括输入模块、输出模块和复位模块，所述输入模块和输出模块之间的连接点为驱动信号输出控制节点，
    所述第二电压选通模块包括第三开关和第四开关，所述第三开关的第一端与所述第二电压源的第一输出端连接，所述第三开关的第二端为所述第二电压选通模块的第一输出端，所述第三开关的第三端为控制端，所述第四开关的第一端与所述第二电压源的第二输出端连接，所述第四开关的第二端为所述第二电压选通模块的第二输出端，所述第四开关的第三端为控制端，
    所述第三开关和第四开关的第三端与所述驱动信号输出控制节点连接，或者所述第三开关和第四开关的第三端与另一节点连接，所述另一节点处的电平与所述驱动信号输出控制节点处的电平相同，
    在所述栅线信号输出端输出栅极驱动信号的低电平时所述驱动信号输出控制节点处于非有效电平，使得第三开关和第四开关导通，在第三开关的第二端输出所述第二电压源的第二电源高电压，并且在第四开关的第二端输出所述第二电压源的第二电源低电压。
  9. 如权利要求3所述的保护电路，其特征在于，
    所述第一保护模块包括第一电阻、第一二极管、第二二极管；
    所述第一电阻连接在所述栅线信号输出端与所述第一保护模块的输出端之间，所述第一二极管的阳极和阴极分别连接所述第一保护模块的输出端和所述第一电压选通模块的第一输出端，所述第二二极管的阳极和阴极分别连接所述第一电压选通模块的第二输出端和所述第一保护模块的输出端。
  10. 如权利要求6所述的保护电路，其特征在于，
    所述第二保护模块包括第三二极管、第四二极管；
    所述第三二极管的阳极和阴极分别连接所述第二保护模块的输出端和所述第二电压选通模块的第一输出端，所述第四二极管的阳极和阴极分别连接所述第二电压选通模块的第二输出端和所述第二保护模块的输出端。
  11. 如权利要求3所述的保护电路，其特征在于，
    所述第一保护模块包括第一电阻、第一压敏电阻或高分子聚合物器件、第二压敏电阻或高分子聚合物器件；
    所述第一电阻连接在所述栅线信号输出端与所述第一保护模块的输出端 之间，所述第一压敏电阻或高分子聚合物器件连接所述第一保护模块的输出端和所述第一电压选通模块的第一输出端之间，所述第二压敏电阻或高分子聚合物器件连接所述第一电压选通模块的第二输出端和所述第一保护模块的输出端之间。
  12. 如权利要求6所述的保护电路，其特征在于，
    所述第二保护模块包括第三压敏电阻或高分子聚合物器件、第四压敏电阻或高分子聚合物器件；
    所述第三压敏电阻或高分子聚合物器件连接在所述第二保护模块的输出端和所述第二电压选通模块的第一输出端之间，所述第四压敏电阻或高分子聚合物器件连接在所述第二电压选通模块的第二输出端和所述第二保护模块的输出端之间。
  13. 一种阵列基板，其特征在于，包括如权利要求1-12任一所述的阵列基板行驱动GOA单元的保护电路。
PCT/CN2016/075339 2015-09-08 2016-03-02 阵列基板行驱动单元的保护电路和阵列基板 WO2017041457A1 (zh)

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