WO2017036095A1 - 一种阵列基板、显示器件和可穿戴设备 - Google Patents

一种阵列基板、显示器件和可穿戴设备 Download PDF

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Publication number
WO2017036095A1
WO2017036095A1 PCT/CN2016/073793 CN2016073793W WO2017036095A1 WO 2017036095 A1 WO2017036095 A1 WO 2017036095A1 CN 2016073793 W CN2016073793 W CN 2016073793W WO 2017036095 A1 WO2017036095 A1 WO 2017036095A1
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Prior art keywords
signal lines
array substrate
display area
signal line
substrate according
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PCT/CN2016/073793
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English (en)
French (fr)
Inventor
李文波
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京东方科技集团股份有限公司
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Priority to US15/308,761 priority Critical patent/US10256253B2/en
Publication of WO2017036095A1 publication Critical patent/WO2017036095A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/56—Substrates having a particular shape, e.g. non-rectangular
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/02—Visual time or date indication means by selecting desired characters out of a number of characters or by selecting indicating elements the position of which represent the time, e.g. by using multiplexing techniques
    • G04G9/06—Visual time or date indication means by selecting desired characters out of a number of characters or by selecting indicating elements the position of which represent the time, e.g. by using multiplexing techniques using light valves, e.g. liquid crystals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display device, and a wearable device.
  • the technological innovation in the field of liquid crystal display is inseparable from the subversive creation of people's various needs of life and the insatiable satisfaction of developers.
  • wearable display technology is changing with each passing day, and wearable smart watches have sprung up.
  • the existing dial design of a wearable smart watch is generally a rectangular design.
  • the wearable smart watch also has a circular display dial design, but its pixel structure is also a conventional rectangular pixel design.
  • the present disclosure provides an array substrate, a display device, and a wearable device to solve the technical problem of a pixel structure that is not specifically designed for circular display in the prior art.
  • an array substrate comprising: a base substrate having a circular or elliptical horizontal cross section.
  • the base substrate includes a display area and a non-display area.
  • the display area is provided with a plurality of first signal lines, a plurality of second signal lines, and a corresponding second signal line among the corresponding first signal lines and the plurality of second signal lines among the plurality of first signal lines
  • a connection lead connected to the first signal line and the second signal line is disposed in the non-display area.
  • Each of the first signal lines includes: a first portion and a second portion, the first portion is An arc or elliptical arc, the second portion for connecting the first portion to the connecting lead.
  • the first portions of the plurality of first signal lines are concentrically distributed, and each of the second signal lines extends from a point on an outer edge of the display region toward a central region of the base substrate.
  • the first portions of the plurality of first signal lines are equally spaced, or the first portion of the plurality of first signal lines are distributed in a direction extending from a center to an edge of the base substrate The density gradually increases.
  • first portion and the second portion of the plurality of first signal lines are disposed in the same material, and the second portion of the first signal line passes through other ones located on a side thereof adjacent to the non-display area An arc on the arc of the first signal line or an elliptical arc is connected to the connecting lead.
  • the first portion of the other first signal lines is an arc or elliptical arc having an opening, except for the first portion of the first signal line that is furthest from the non-display area.
  • the positions of the circular arc openings or the elliptical arc openings of the first portion of the plurality of first signal lines are correspondingly disposed.
  • the first portion and the second portion of the plurality of first signal lines are insulated from each other and connected through the via holes.
  • each of the plurality of second signal lines extends from a point on an outer edge of the display area toward a center of the base substrate.
  • the plurality of second signal lines are evenly distributed.
  • the area of the pixel electrode gradually increases in a direction extending from the center to the edge of the base substrate.
  • the plurality of pixel electrodes have a shape of a circle, an ellipse or a quadrangle.
  • the quadrilateral when the shape of the plurality of pixel electrodes is a quadrilateral, the quadrilateral includes opposite first and third sides and opposite second and fourth sides, wherein the first side and the third side It is an arc and is concentrically arranged with the first signal line adjacent thereto; the second side and the fourth side are straight lines and are parallel to the second signal line adjacent thereto.
  • the non-display area is located at a central area of the array substrate, and the display area is located at a periphery of the non-display area.
  • the non-display area is located at an edge area of the array substrate, and the display area is surrounded by the non-display area.
  • the present disclosure also provides a display device including the above array substrate.
  • the present disclosure also provides a wearable device including the above display device.
  • One of the signal lines of the array substrate is designed in the shape of a circular arc or an elliptical arc, and the other signal line is designed to be diverging outward from the central area of the base substrate, so as to be particularly suitable for a circular or elliptical display device.
  • FIG. 1 is a schematic structural view of an array substrate according to Embodiment 1 of the present disclosure.
  • FIG. 2 is a schematic structural view of an array substrate according to Embodiment 2 of the present disclosure.
  • FIG. 3 is a schematic structural diagram of an array substrate according to Embodiment 3 of the present disclosure.
  • FIG. 4 is a schematic structural view of an array substrate according to Embodiment 4 of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an array substrate according to Embodiment 5 of the present disclosure.
  • FIG. 6 is a schematic structural diagram of an array substrate according to Embodiment 6 of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an array substrate according to Embodiment 7 of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present disclosure.
  • the array substrate includes a base substrate having a circular cross section.
  • the base substrate includes a display area 110 and a non-display area 120.
  • the non-display area 120 is located in a central area of the base substrate.
  • the display area 110 is located at the periphery of the non-display area 120.
  • this design can realize a frameless design of the display device having the array substrate.
  • the arrangement of the display area 110 and the non-display area 120 shown in FIG. 1 is merely exemplary and not limiting.
  • the display area 110 and the non-display area 120 may also be arranged in other manners as needed, as described in detail in the various embodiments below.
  • the display region 110 is provided with a plurality of first signal lines 111, a plurality of second signal lines 112, and a thin film transistor located in a pixel region defined by the intersection of the first signal line 111 and the second signal line 112 ( TFT) 113 and pixel electrode 114.
  • the first signal line 111 is a data line
  • the second signal line 112 is a gate line.
  • Each of the pixel regions defined by the intersection of the first signal line (data line) 111 and the second signal line (gate line) 112 has a thin film transistor 113 and a pixel electrode 114.
  • the thin film transistor 113 is located at the first signal line The vicinity of the intersection of the (data line) 111 and the second signal line (gate line) 112.
  • a gate electrode of the thin film transistor 113 is connected to the second signal line (gate line) 112, a source electrode of the thin film transistor 113 is connected to the first signal line (data line) 111, and the thin film transistor The drain electrode of 113 is connected to the pixel electrode 114.
  • a connection lead (not shown) connected to the first signal line 111 and the second signal line 112 is disposed in the non-display area 120. The connection lead is for connecting the first signal line 111 and the second signal line 112 to the driving chip.
  • Each of the first signal lines 111 includes a first portion 1111 and a second portion 1112.
  • the first portion 1111 is an arc, and the first portions 1111 of the plurality of first signal lines 111 are concentrically distributed.
  • the second portion 1112 is a straight line for connecting the first portion 1111 to the connecting lead. Since the horizontal section of the base substrate is also a circular shape, optionally, the first portion 1111 of the plurality of first signal lines 111 is also concentrically arranged with the horizontal section of the base substrate, so that the area of the base substrate can be maximized.
  • the ground is used.
  • the first portion 1111 and the second portion 1112 of the first signal line 111 are disposed in the same layer with the same material, so that it can be formed by one patterning process to save cost.
  • the first signal line 111 is usually made of a metal material.
  • the metal material is, for example, copper, aluminum, or other suitable alloy material or the like.
  • the first signal line 111 farthest from the non-display area 120 (the first signal line of the outermost circle in this embodiment)
  • the first portion 1111 of 111) is a complete circular arc (i.e., a full circle), and the first portions 1111 of the other first signal lines 111 are arcs having an opening.
  • the possibility that the first signal line farthest from the non-display area is also an arc having an opening is not excluded.
  • the second portion 1112 of the other first signal lines 111 passes through other first signals located on a side thereof adjacent to the non-display area 120, except for the first signal line 111 closest to the non-display area.
  • An opening in the arc of the line 111 is connected to the connecting lead.
  • the positions of the circular arc openings of the first portion 1111 of the plurality of first signal lines 111 are correspondingly arranged to increase the aperture ratio.
  • each of the second signal lines 112 extends from a point on the outer edge of the display area 110 toward a center of the base substrate, but the plurality of second signal lines 112 do not intersect.
  • the outer edge of the display area 110 is circular, and the second signal line 112 is a part of the radius of the circle, as shown in FIG.
  • the first portions 1111 (circular arc portions) of the plurality of first signal lines 111 are equally spaced.
  • the plurality of second signal lines 112 are evenly distributed in the display area 110.
  • the equally spaced distribution of the first portion 1111 (circular arc portion) of the plurality of first signal lines 111 and the uniform distribution of the plurality of second signal lines 112 as shown in FIG. 1 are merely exemplary and not limiting. Those skilled in the art can also appropriately modify them into non-equally spaced distributions and non-uniform distributions according to actual needs.
  • a plurality of pixel electrodes 114 are included in a region defined by two adjacent second signal lines 112. As shown in FIG. 1, the area of the plurality of pixel electrodes 114 gradually increases in a direction extending from the center to the edge of the base substrate. Of course, the area of the plurality of pixel electrodes 114 may also be substantially the same or gradually decreased according to actual needs.
  • the shape of the pixel electrode 114 is a quadrangle.
  • the quadrilateral includes opposite first and third sides and opposite second and fourth sides.
  • the first side and the third side are arcs, and are concentrically arranged with the first signal line 111 adjacent thereto.
  • the second side and the fourth side are straight lines and are parallel to the second signal line 112 adjacent thereto.
  • the pixel electrode 114 of such a shape can maximize the aperture ratio of the pixel region.
  • the design includes a data line having a circular arc shape, a gate line having a diverging shape outward from a central region of the base substrate, and a pixel electrode having a shape matching with the data line and the gate line. It is convenient to apply to circular display devices.
  • FIG. 2 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present disclosure. It should be noted that the difference between the second embodiment and the first embodiment is that the first signal line 111 is a gate line, and the second signal line 112 is a data line.
  • the data lines are circular arcs, and the gate lines are straight lines.
  • the gate lines are arc-shaped, and the data lines are straight lines.
  • FIG. 3 is a schematic structural diagram of an array substrate according to Embodiment 3 of the present disclosure.
  • the difference between the third embodiment and the first embodiment is that the display area of the base substrate is The domain 110 is located in a central region of the base substrate while the non-display region 120 is located at the periphery of the display region 110.
  • the non-display area of the base substrate is located in the central area while the display area is located on the periphery of the non-display area.
  • the first portion 1111 of the first signal line 111 (the first signal line 111 which is the innermost circle in the embodiment) farthest from the non-display area 120 is a complete arc (ie, The first portion 1111 of the other first signal lines 111 is an arc having an opening, except for one full circle.
  • the second portion 1112 of the other first signal lines 111 passes through other first signals located on a side thereof adjacent to the non-display area 120, except for the first signal line 111 closest to the non-display area. An opening in the arc of the line 111 is connected to the connecting lead.
  • An advantage of this embodiment is that the central area of the array substrate can also display content.
  • FIG. 4 is a schematic structural diagram of an array substrate according to Embodiment 4 of the present disclosure. It should be noted that the difference between the fourth embodiment and the first embodiment is that the horizontal cross section of the base substrate is elliptical. At the same time, the first portion 1111 of the first signal line 111 is an elliptical arc, and the first portions 1111 of the plurality of first signal lines 111 are concentrically distributed. Since the horizontal section of the base substrate is also an elliptical shape, optionally, the first portion 1111 of the plurality of first signal lines 111 is also concentrically disposed with the horizontal section of the base substrate, so that the area of the base substrate can be maximized. The ground is used.
  • the first portion 1111 and the second portion 1112 of the first signal line 111 are disposed in the same layer with the same material, so that it can be formed by one patterning process to save cost.
  • the first signal line 111 is usually made of a metal material.
  • the first signal line 111 farthest from the non-display area 120 (the first signal line of the outermost circle in this embodiment)
  • the first portion 1111 of 111) is a complete elliptical arc (i.e., a full ellipse), and the first portions 1111 of the other first signal lines 111 are elliptical arcs having openings.
  • the first signal line that is furthest from the non-display area is also an elliptical arc with an opening.
  • the second portion 1112 of the first signal line 111 is connected to the connection lead through an opening on an elliptical arc of the other first signal line 111 on the side close to the non-display area 120.
  • the positions of the elliptical arc openings of the first portion 1111 of the plurality of first signal lines 111 are correspondingly arranged to increase the aperture ratio.
  • FIG. 5 is a schematic structural diagram of an array substrate according to Embodiment 5 of the present disclosure. It should be noted that the fifth embodiment differs from the first embodiment in that the first portion 1111 and the second portion 1112 of the first signal line 111 are insulated from each other and connected through via holes. Differently, in the first embodiment, the first portion 1111 and the second portion 1112 of the first signal line 111 are disposed in the same material.
  • the advantage that the first portion 1111 and the second portion 1112 are disposed in different layers is that all of the first portions 1111 of the first signal lines 111 do not need to be designed as circular arcs with openings, and thus can be designed as a full circle.
  • the second portion 1112 can be disposed in the same material as the gate line 112, and is formed by one patterning process to save cost.
  • FIG. 6 is a schematic structural diagram of an array substrate according to Embodiment 6 of the present disclosure. It is to be noted that the difference between the sixth embodiment and the first embodiment is that the distribution density of the first portions 1111 of the plurality of first signal lines 111 gradually increases in a direction extending from the center to the edge of the base substrate, that is, The interval between adjacent first portions 1111 is getting smaller and smaller in the direction extending from the center to the edge of the base substrate. In contrast to this, in the first embodiment, the first portions 1111 of the plurality of first signal lines 111 are equally spaced.
  • the distribution density of the first portion 1111 of the plurality of first signal lines 111 gradually increases. The increase is made, so that the area of each pixel electrode 114 can be designed to be the same.
  • FIG. 7 is a schematic structural diagram of an array substrate according to Embodiment 7 of the present disclosure. It should be noted that the difference between the seventh embodiment and the first embodiment is that the shape of the pixel electrode 114 is elliptical.
  • the shape of the pixel electrode 114 may also be circular.
  • the second signal line 112 is extended from a point on the outer edge of the display region 110 toward the center of the base substrate, that is, the extension of the second signal line 112 is over the substrate. Center of the heart. In some other embodiments of the present disclosure, the second signal line 112 is formed by a point on the outer edge of the display region 110 toward the central region of the substrate substrate, but the extension line is not the center of the substrate.
  • the present disclosure also provides a display device comprising the array substrate of any of the above embodiments.
  • the present disclosure also provides a wearable device including the above display device.
  • the wearable device may be a smart watch, a wristband or the like.

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Abstract

一种阵列基板包括：水平截面呈圆形或椭圆形的衬底基板。衬底基板包括显示区域（110）和非显示区域（120）。显示区域（110）中设置有多条第一信号线（111）、多条第二信号线（112）以及位于由多条第一信号线（111）当中相应的第一信号线（111）和多条第二信号线（112）当中相应的第二信号线（112）交叉限定出的多个像素区域中的多个薄膜晶体管（113）和多个像素电极（114）。非显示区域（120）中设置有与第一信号线（111）和第二信号线（112）连接的连接引线。每一条第一信号线（111）包括：第一部分（1111）和第二部分（1112），第一部分（1111）为圆弧或椭圆弧，第二部分（1112）用于将第一部分（1111）连接至连接引线。多条第一信号线（111）的第一部分（1111）同心分布，每一条第二信号线（112）从显示区域（110）外边缘上的一点向衬底基板的中心区域延伸而成。该阵列基板特别适用于圆形或椭圆形显示器件。

Description

一种阵列基板、显示器件和可穿戴设备
相关申请的交叉参考
本申请主张在2015年9月6日在中国提交的中国专利申请号No.201510561286.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，尤其涉及一种阵列基板、显示器件和可穿戴设备。
背景技术
液晶显示领域的技术革新，离不开人们对生活各式各样的需求满足以及研发者对产品永不满足的颠覆性创造。目前，穿戴式显示技术日新月异，穿戴式智能手表如雨后春笋般出现。然而，穿戴式智能手表的现有的表盘设计，一般为矩形设计方案。另外，穿戴式智能手表也有圆形显示表盘的设计方案，但是其像素结构同样是常规的矩形像素设计。
发明内容
(一)要解决的技术问题
有鉴于此，本公开文本提供一种阵列基板、显示器件和可穿戴设备，以解决现有技术中没有专门针对圆形显示而设计的像素结构的技术问题。
(二)技术方案
为解决上述技术问题，根据本公开文本的第一方面，提供了一种阵列基板，包括：水平截面呈圆形或椭圆形的衬底基板。所述衬底基板包括显示区域和非显示区域。所述显示区域中设置有多条第一信号线、多条第二信号线以及位于由多条第一信号线当中相应的第一信号线和多条第二信号线当中相应的第二信号线交叉限定出的多个像素区域中的多个薄膜晶体管和多个像素电极。所述非显示区域中设置有与所述第一信号线和第二信号线连接的连接引线。每一所述第一信号线都包括：第一部分和第二部分，所述第一部分为 圆弧或椭圆弧，所述第二部分用于将所述第一部分连接至所述连接引线。所述多条第一信号线的第一部分同心分布，每一所述第二信号线从所述显示区域外边缘上的一点向所述衬底基板的中心区域延伸而成。
可选地，所述多条第一信号线的第一部分等间隔分布，或者，在从所述衬底基板的中心向边缘延伸的方向上，所述多条第一信号线的第一部分的分布密度逐渐增大。
可选地，所述多条第一信号线的第一部分和第二部分同层同材料设置，所述第一信号线的第二部分穿过位于其靠近所述非显示区域的一侧的其他第一信号线的圆弧或椭圆弧上的开口与所述连接引线连接。
可选地，除距离所述非显示区域最远的第一信号线的第一部分之外，其他第一信号线的第一部分均为具有开口的圆弧或椭圆弧。
可选地，所述多条第一信号线的第一部分的圆弧开口或椭圆弧开口的位置对应设置。
可选地，所述多条第一信号线的第一部分和第二部分异层绝缘设置，并通过过孔连接。
可选地，每一所述多条第二信号线从所述显示区域外边缘上的一点向所述衬底基板的圆心方向延伸而成。
可选地，所述多条第二信号线均匀分布。
可选地，由相邻两条第二信号线限定的各个区域中，在从所述衬底基板的中心向边缘延伸的方向上，所述像素电极的面积逐渐增大。
可选地，所述多个像素电极的形状为圆形、椭圆形或四边形。
可选地，当所述多个像素电极的形状为四边形时，所述四边形包括相对的第一边和第三边以及相对的第二边和第四边，其中，第一边和第三边为弧线，且和与其相邻的第一信号线同心设置；第二边和第四边为直线，且和与其相邻的第二信号线平行。
可选地，所述非显示区域位于所述阵列基板的中心区域，所述显示区域位于所述非显示区域外围。
可选地，所述非显示区域位于所述阵列基板的边缘区域，所述显示区域被所述非显示区域包围。
根据本公开文本的第二方面，本公开文本还提供了一种显示器件，包括上述阵列基板。
根据本公开文本的第三方面，本公开文本还提供了一种可穿戴设备，包括上述显示器件。
(三)有益效果
本公开文本实施例至少具有如下有益效果：
阵列基板的其中一条信号线呈圆弧或椭圆弧形状设计，而另一条信号线呈从衬底基板的中心区域向外发散形状设计，以特别适用于圆形或椭圆形显示器件。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开文本实施例一的阵列基板的结构示意图；
图2为本公开文本实施例二的阵列基板的结构示意图；
图3为本公开文本实施例三的阵列基板的结构示意图；
图4为本公开文本实施例四的阵列基板的结构示意图；
图5为本公开文本实施例五的阵列基板的结构示意图；
图6为本公开文本实施例六的阵列基板的结构示意图；以及
图7为本公开文本实施例七的阵列基板的结构示意图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整 地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
下面将结合附图和实施例，对本公开文本的具体实施方式作进一步详细描述。以下实施例用于说明本公开文本，但不用来限制本公开文本的范围。
实施例一
请参考图1，图1为本公开文本实施例一的阵列基板的结构示意图。该阵列基板包括：水平截面呈圆形的衬底基板。所述衬底基板包括显示区域110和非显示区域120。所述非显示区域120位于所述衬底基板的中心区域。所述显示区域110位于所述非显示区域120的外围。很明显，该种设计可以使得具有该阵列基板的显示器件实现无边框设计。当然，图1所示的显示区域110和非显示区域120的布置仅是示例性的而非限定性的。例如，显示区域110和非显示区域120还可以根据需要被布置成其他方式，如下面各个实施例中详细描述的一样。
所述显示区域110中设置有多条第一信号线111、多条第二信号线112以及位于由所述第一信号线111和第二信号线112交叉限定出的像素区域中的薄膜晶体管(TFT)113和像素电极114。本实施例中，所述第一信号线111为数据线，所述第二信号线112为栅极线。其中，由所述第一信号线(数据线)111和第二信号线(栅极线)112交叉限定出的每一像素区域中均具有一薄膜晶体管113和一像素电极114。所述薄膜晶体管113位于所述第一信号线 (数据线)111和第二信号线(栅极线)112的交叉区域附近。所述薄膜晶体管113的栅电极与所述第二信号线(栅极线)112连接，所述薄膜晶体管113的源电极与所述第一信号线(数据线)111连接，而所述薄膜晶体管113的漏电极与像素电极114连接。所述非显示区域120中设置有与所述第一信号线111和第二信号线112连接的连接引线(图中未示出)。该连接引线用于将第一信号线111和第二信号线112连接至驱动芯片。
每一所述第一信号线111包括：第一部分1111和第二部分1112。所述第一部分1111为圆弧，并且所述多条第一信号线111的第一部分1111同心分布。所述第二部分1112为直线，用于将所述第一部分1111连接至所述连接引线。由于衬底基板的水平截面也是一圆形，可选地，所述多条第一信号线111的第一部分1111也与衬底基板的水平截面同心设置，从而使得衬底基板的面积可以最大程度地被利用。
本实施例中，所述第一信号线111的第一部分1111和第二部分1112同层同材料设置，从而可以采用一次构图工艺形成，以节省成本。所述第一信号线111通常采用金属材料制成。金属材料例如采用铜、铝、或其他合适的合金材料等。
为避免多个第一信号线111之间相互交叠，本实施例中，除距离所述非显示区域120最远的第一信号线111(本实施例中为最外圈的第一信号线111)的第一部分1111为一完整的圆弧(即为一个整圆)之外，其他第一信号线111的第一部分1111均为具有开口(opening)的圆弧。当然，在本公开文本的其他实施例中，也不排除距离所述非显示区域最远的第一信号线也为具有开口的圆弧的可能。除最靠近所述非显示区域的第一信号线111之外，其他所述第一信号线111的第二部分1112均穿过位于其靠近所述非显示区域120的一侧的其他第一信号线111的圆弧上的开口与所述连接引线连接。所述多个第一信号线111的第一部分1111的圆弧开口的位置对应设置，以提高开口率。
本实施例中，每一所述第二信号线112由所述显示区域110外边缘上的一点向所述衬底基板的圆心延伸而成，但所述多条第二信号线112并不相交。所述显示区域110的外边缘呈圆形，所述第二信号线112为该圆形的半径的一部分，如图1所示。
本实施例中，所述多条第一信号线111的第一部分1111(圆弧部分)等间隔分布。所述多条第二信号线112在所述显示区域110均匀分布。然而，如图1所示的多条第一信号线111的第一部分1111(圆弧部分)的等间隔分布和多条第二信号线112的均匀分布都仅是示例性的而非限定性的，根据实际需要，本领域技术人员还可将它们适当修改为非等间隔分布和非均匀分布。相邻两条第二信号线112限定的区域中包括多个像素电极114。如图1所示，在由所述衬底基板的中心向边缘延伸的方向上，所述多个像素电极114的面积逐渐增大。当然，根据实际需要，所述多个像素电极114的面积还可以是基本上相同的或者逐渐减小。
本实施例中，所述像素电极114的形状为四边形。其中，所述四边形包括相对的第一边和第三边以及相对的第二边和第四边。其中，第一边和第三边为弧线，且和与其相邻的第一信号线111同心设置。第二边和第四边为直线，且和与其相邻的第二信号线112平行。该种形状的像素电极114，能够最大程度地提高像素区域的开口率。
上述实施例提供的阵列基板中，设计包括呈圆弧形状的数据线、由衬底基板的中心区域向外呈发散形状的栅极线、以及与数据线和栅极线形状配合的像素电极，以方便地适用于圆形显示器件。
实施例二
接下来，请参考图2，图2为本公开文本实施例二的阵列基板的结构示意图。值得注意的是，实施例二与实施例一的区别在于：所述第一信号线111为栅极线，而所述第二信号线112为数据线。
也就是说，实施例一中，数据线为圆弧形，栅极线为直线。与此不同的是，实施例二中，栅极线为圆弧形，数据线为直线。
需要注意的是，在实施例二中，省略了与图1中所示的实施例一的特征在实质上相同的特征的描述。也就是说，仅仅描述了涉及实施例一和实施例二之间的差异，而相同部分可以参考实施例一中的相应描述，在此不再赘述。
实施例三
接下来，请参考图3，图3为本公开文本实施例三的阵列基板的结构示意图。值得注意的是，实施例三与实施例一的区别在于：衬底基板的显示区 域110位于所述衬底基板的中心区域，同时非显示区域120位于显示区域110的外围。与此不同的是，在实施例一中，衬底基板的非显示区域位于中心区域，同时显示区域位于非显示区域外围。
本实施例中，除距离所述非显示区域120最远的第一信号线111(本实施例中为最内圈的第一信号线111)的第一部分1111为一完整的圆弧(即为一个整圆)之外，其他第一信号线111的第一部分1111均为具有开口的圆弧。除最靠近所述非显示区域的第一信号线111之外，其他所述第一信号线111的第二部分1112均穿过位于其靠近所述非显示区域120的一侧的其他第一信号线111的圆弧上的开口与所述连接引线连接。
本实施例的优点在于：阵列基板的中心区域也可以显示内容。
需要注意的是，在实施例三中，省略了与图1中所示的实施例一的特征在实质上相同的特征的描述。也就是说，仅仅描述了涉及实施例一和实施例三之间的差异，而相同部分可以参考实施例一中的相应描述，在此不再赘述。
实施例四
接下来，请参考图4，图4为本公开文本实施例四的阵列基板的结构示意图。值得注意的是，实施例四与实施例一的区别在于：衬底基板的水平截面呈椭圆形。同时，第一信号线111的第一部分1111为椭圆弧，所述多条第一信号线111的第一部分1111同心分布。由于衬底基板的水平截面也是一椭圆形，可选地，所述多条第一信号线111的第一部分1111也与衬底基板的水平截面同心设置，从而使得衬底基板的面积可以最大程度地被利用。
本实施例中，所述第一信号线111的第一部分1111和第二部分1112同层同材料设置，从而可以采用一次构图工艺形成，以节省成本。所述第一信号线111通常采用金属材料制成。
为避免多个第一信号线111之间相互交叠，本实施例中，除距离所述非显示区域120最远的第一信号线111(本实施例中为最外圈的第一信号线111)的第一部分1111为一完整的椭圆弧(即为一个整椭圆)之外，其他第一信号线111的第一部分1111均为具有开口的椭圆弧。当然，在本公开文本的其他实施例中，也不排除距离所述非显示区域最远的第一信号线也为具有开口的椭圆弧的可能。除最靠近所述非显示区域的第一信号线111之外，其他所述 第一信号线111的第二部分1112均穿过位于其靠近所述非显示区域120的一侧的其他第一信号线111的椭圆弧上的开口与所述连接引线连接。所述多个第一信号线111的第一部分1111的椭圆弧开口的位置对应设置，以提高开口率。
需要注意的是，在实施例四中，省略了与图1中所示的实施例一的特征在实质上相同的特征的描述。也就是说，仅仅描述了涉及实施例一和实施例四之间的差异，而相同部分可以参考实施例一中的相应描述，在此不再赘述。
实施例五
接下来，请参考图5，图5为本公开文本实施例五的阵列基板的结构示意图。值得注意的是，实施例五与实施例一的区别在于：第一信号线111的第一部分1111和第二部分1112异层绝缘设置，并通过过孔连接。与此不同的是，在实施例一中，所述第一信号线111的第一部分1111和第二部分1112同层同材料设置。
这里，第一部分1111和第二部分1112异层设置的优点在于：所有第一信号线111的第一部分1111均无须设计成有开口的圆弧，因此都可以设计为整圆。
本实施例中，第二部分1112可以与栅极线112同层同材料设置，通过一次构图工艺形成，以节省成本。
需要注意的是，在实施例五中，省略了与图1中所示的实施例一的特征在实质上相同的特征的描述。也就是说，仅仅描述了涉及实施例一和实施例五之间的差异，而相同部分可以参考实施例一中的相应描述，在此不再赘述。
实施例六
接下来，请参考图6，图6为本公开文本实施例六的阵列基板的结构示意图。值得注意的是，实施例六与实施例一的区别在于：在由衬底基板的中心向边缘延伸的方向上，多个第一信号线111的第一部分1111的分布密度逐渐增大，即，在由衬底基板的中心向边缘延伸的方向上，相邻第一部分1111之间的间隔越来越小。与此不同的是，在实施例一中，多个第一信号线111的第一部分1111是等间隔分布。
本实施例中，由于多个第一信号线111的第一部分1111的分布密度逐渐 增大，因此可以将每一像素电极114的面积设计成相同。
需要注意的是，在实施例六中，省略了与图1中所示的实施例一的特征在实质上相同的特征的描述。也就是说，仅仅描述了涉及实施例一和实施例六之间的差异，而相同部分可以参考实施例一中的相应描述，在此不再赘述。
实施例七
接下来，请参考图7，图7为本公开文本实施例七的阵列基板的结构示意图。值得注意的是，实施例七与实施例一的区别在于：像素电极114的形状为椭圆形。
在本公开文本的其他一些实施例中，像素电极114的形状也可以为圆形。
需要注意的是，在实施例七中，省略了与图1中所示的实施例一的特征在实质上相同的特征的描述。也就是说，仅仅描述了涉及实施例一和实施例七之间的差异，而相同部分可以参考实施例一中的相应描述，在此不再赘述。
其他变形例
在上述各个实施例中，第二信号线112是由显示区域110外边缘上的一点向衬底基板的圆心延伸而成，也就是说，第二信号线112的延长线是过衬底基板的圆心的。在本公开文本的其他一些实施例中，第二信号线112是由显示区域110外边缘上的一点向衬底基板的中心区域延伸而成，但是其延长线并不过衬底基板的圆心。
在本公开文本的其他一些实施例中，上述各个实施例中的特征可以任意组合，在此不再一一描述。
本公开文本还提供一种显示器件，包括上述任一实施例中的阵列基板。
本公开文本还提供一种可穿戴设备，包括上述显示器件。所述可穿戴设备可以为智能手表、腕带等。
以上所述是本公开文本的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开文本的保护范围。

Claims (15)

  1. 一种阵列基板，包括：水平截面呈圆形或椭圆形的衬底基板，
    其中，所述衬底基板包括显示区域和非显示区域，
    其中，所述显示区域中设置有多条第一信号线、多条第二信号线以及位于由多条第一信号线当中相应的第一信号线和多条第二信号线当中相应的第二信号线交叉限定出的多个像素区域中的多个薄膜晶体管和多个像素电极，
    其中，所述非显示区域中设置有与所述第一信号线和第二信号线连接的连接引线，
    其中，每一所述第一信号线都包括：第一部分和第二部分，所述第一部分为圆弧或椭圆弧，所述第二部分用于将所述第一部分连接至所述连接引线，
    其中，所述多条第一信号线的第一部分同心分布，每一所述第二信号线从所述显示区域外边缘上的一点向所述衬底基板的中心区域延伸而成。
  2. 根据权利要求1所述的阵列基板，其中，所述多条第一信号线的第一部分等间隔分布，或者，在从所述衬底基板的中心向边缘延伸的方向上，所述多条第一信号线的第一部分的分布密度逐渐增大。
  3. 根据权利要求1或2所述的阵列基板，其中，所述多条第一信号线的第一部分和第二部分同层同材料设置，所述第一信号线的第二部分穿过位于其靠近所述非显示区域的一侧的其他第一信号线的圆弧或椭圆弧上的开口与所述连接引线连接。
  4. 根据权利要求3所述的阵列基板，其中，除距离所述非显示区域最远的第一信号线的第一部分之外，其他第一信号线的第一部分均为具有开口的圆弧或椭圆弧。
  5. 根据权利要求3或4所述的阵列基板，其中，所述多条第一信号线的第一部分的圆弧开口或椭圆弧开口的位置对应设置。
  6. 根据权利要求1或2所述的阵列基板，其中，所述多条第一信号线的第一部分和第二部分异层绝缘设置，并通过过孔连接。
  7. 根据权利要求1至6中任一项所述的阵列基板，其中，每一所述多条第二信号线从所述显示区域外边缘上的一点向所述衬底基板的圆心方向延伸 而成。
  8. 根据权利要求1至7中任一项所述的阵列基板，其中，所述多条第二信号线均匀分布。
  9. 根据权利要求8所述的阵列基板，其中，由相邻两条第二信号线限定的各个区域中，在从所述衬底基板的中心向边缘延伸的方向上，所述像素电极的面积逐渐增大。
  10. 根据权利要求1所述的阵列基板，其中，所述多个像素电极的形状为圆形、椭圆形或四边形。
  11. 根据权利要求10所述的阵列基板，其中，当所述多个像素电极的形状为四边形时，所述四边形包括相对的第一边和第三边以及相对的第二边和第四边，其中，第一边和第三边为弧线，且和与其相邻的第一信号线同心设置；其中，第二边和第四边为直线，且和与其相邻的第二信号线平行。
  12. 根据权利要求1至11中任一项所述的阵列基板，其中，所述非显示区域位于所述阵列基板的中心区域，所述显示区域位于所述非显示区域外围。
  13. 根据权利要求1至11中任一项所述的阵列基板，其中，所述非显示区域位于所述阵列基板的边缘区域，所述显示区域被所述非显示区域包围。
  14. 一种显示器件，包括如权利要求1-13中任一项所述的阵列基板。
  15. 一种可穿戴设备，包括如权利要求14所述的显示器件。
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CN105487314A (zh) 2016-01-07 2016-04-13 京东方科技集团股份有限公司 一种阵列基板和显示装置
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