WO2017031978A1 - Cpu互连装置、系统及其控制方法、控制装置 - Google Patents

Cpu互连装置、系统及其控制方法、控制装置 Download PDF

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Publication number
WO2017031978A1
WO2017031978A1 PCT/CN2016/076267 CN2016076267W WO2017031978A1 WO 2017031978 A1 WO2017031978 A1 WO 2017031978A1 CN 2016076267 W CN2016076267 W CN 2016076267W WO 2017031978 A1 WO2017031978 A1 WO 2017031978A1
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Prior art keywords
cpu
topology
terminal
state
change indication
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PCT/CN2016/076267
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English (en)
French (fr)
Inventor
廖德甫
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP16838241.4A priority Critical patent/EP3285173A4/en
Publication of WO2017031978A1 publication Critical patent/WO2017031978A1/zh
Priority to US15/903,032 priority patent/US20180181536A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a CPU interconnection device, a system, a control method thereof, and a control device.
  • the Quick Path Interconnect (QPI) technology connects the central processing units (CPUs) of multiple nodes to each other, so that multiple nodes that work independently can be combined into one whole (ie, composed).
  • a partition and the combined entity as an executive body to undertake the work on the original nodes, improve the data capacity and processing capacity of each node.
  • an embodiment of the present invention provides a CPU interconnection device, a system, a control method thereof, and a control device.
  • the technical solution is as follows:
  • an embodiment of the present invention provides a CPU interconnection apparatus, including: at least one switching circuit, each switching circuit includes two strobe units and a first intermediate line, and each strobe unit includes a first terminal And the second terminal, the first terminal is connected to the second terminal when the gating unit is in the first state, and the first terminal is in the second state when the gating cell is in the second state One terminal is disconnected from the second terminal, and the two first terminals of each of the switching circuits are respectively used to connect two CPUs in the first node, and the two of the switching circuits are respectively The two terminals are respectively connected to both ends of the first intermediate line, or the two second terminals of each of the switching circuits are respectively used to connect two CPUs in the second node.
  • the gating unit further includes a third terminal, where the first terminal is disconnected from the third terminal when the gating unit is in the first state The first terminal is connected to the third terminal when the gating unit is in the second state, and two of the second terminals of each of the switching circuits are respectively associated with two of the first intermediate lines End connections, two third terminals of each of the switching circuits are respectively used to connect two CPUs in the second node.
  • the device includes a second intermediate line, and the third terminal of the switching circuit is connected to the CPU in the second node by using the second intermediate line.
  • the third terminal of the circuit is connected.
  • the third terminal of the switching circuit is connected to the third terminal of the switching circuit connected to the CPU in the second node by a processing unit in the NC.
  • the gating unit is a switch circuit, an electronic switch, a gate, a selector, or a distributor.
  • an embodiment of the present invention provides a CPU interconnection system, including multiple nodes, where the multiple nodes include a first node and a second node, and each node includes multiple directly connected CPUs,
  • the CPU interconnect system also includes CPU interconnects as previously described.
  • an embodiment of the present invention provides a CPU interconnection control method, which is applicable to a CPU interconnection system, where the CPU interconnection system includes a plurality of nodes, and the plurality of nodes includes a first node and a second node.
  • Each node includes a plurality of directly connected CPUs, the CPU interconnection system further comprising a CPU interconnection device, the CPU interconnection device comprising: at least one switching circuit, each switching circuit comprising two gate units and one a first intermediate line, each of the gating units includes a first terminal and a second terminal, and the two first terminals of each of the switching circuits are respectively used to connect two CPUs in the first node, each of the Two of the second terminals of the switching circuit are respectively connected to both ends of the first intermediate line, or two second terminals of each of the switching circuits are respectively used for connection
  • the two CPUs in the second node the method includes:
  • the first terminal of the gating unit is controlled to be connected to the second terminal, and when the state of the gating cell is the second state The first terminal is controlled to be disconnected from the second terminal.
  • the gating unit further includes a third terminal, and the two second terminals of each of the switching circuits are respectively connected to two ends of the first intermediate line, and each The two third terminals of the switching circuit are respectively used to connect two CPUs in the second node, and the method further includes:
  • the first terminal is connected to the third terminal.
  • the acquiring a topology change indication signal includes:
  • topology change indication signal includes the topology change indication information
  • the topology change indication information includes a changed number of system partition CPUs or a changed system application scenario
  • the system application scenario Process scenarios or online transaction processing scenarios for online analysis.
  • the acquiring a topology change indication signal includes:
  • system monitoring information including at least one of a load and a delay of the CPU
  • topology change indication signal Generating the topology change indication signal according to the system monitoring information, where the topology change indication signal includes topology change indication information, where the topology change indication information includes at least one of a CPU with excessive load and a CPU with excessive delay.
  • determining the state of the gating unit according to the topology change indication signal includes:
  • the state of the gating unit is determined according to the topology of the transformed CPU interconnect system.
  • the determining, according to the topology change indication signal, a topology of the transformed CPU interconnection system including:
  • the determining, according to the topology change indication signal, a topology of the transformed CPU interconnection system including:
  • Determining a topology change according to the topology change indication signal includes connecting a line between the two CPUs or disconnecting a line between the two CPUs;
  • the determining the topology change according to the topology change indication signal includes:
  • Determining that the CPU with excessive load or excessive delay is determined when the topology change indication signal includes a CPU with excessive load or a CPU with excessive delay;
  • connection between the determined CPU and the CPU in the second node is changed to a connection with the CPU in the first node, and the determined CPU is in the first node.
  • the determining the topology of the transformed CPU interconnection system includes:
  • connection set C1 comprising a direct connection between two CPUs
  • connection set C2 comprising a first intermediate line, a second intermediate line, a connection between the CPU and the gating unit or A connection between the CPU and the processing unit
  • the C3 connection set including a pseudo direct connection, which is a connection established by the two CPUs through the first intermediate line or the second intermediate line.
  • determining the state of the gating unit according to the topology of the transformed CPU interconnection system includes:
  • an embodiment of the present invention provides a CPU interconnection control apparatus, which is applicable to a CPU interconnection system, where the CPU interconnection system includes a plurality of nodes, and the plurality of nodes includes a first node and a second node.
  • Each node includes a plurality of directly connected CPUs, the CPU interconnection system further comprising a CPU interconnection device, the CPU interconnection device comprising: at least one switching circuit, each switching circuit comprising two gate units and one a first intermediate line, each of the gating units includes a first terminal and a second terminal, and the two first terminals of each of the switching circuits are respectively used to connect two CPUs in the first node, each of the Two of the second terminals of the switching circuit are respectively connected to two ends of the first intermediate line, or two second terminals of each of the switching circuits are respectively used to connect two CPUs in the second node,
  • the device includes:
  • An acquiring module configured to acquire a topology change indication signal
  • a determining module configured to determine a state of the gating unit according to the topology change indication signal, where the state includes a first state and a second state;
  • control module configured to: when the state of the gating cell is the first state, control the first terminal of the gating cell to be connected to the second terminal, when the state of the gating cell is In the second state, the first terminal is controlled to be disconnected from the second terminal.
  • the gating unit further includes a third terminal, and the two second terminals of each of the switching circuits are respectively connected to two ends of the first intermediate line, and each The two third terminals of the switching circuit are respectively used to connect two CPUs in the second node, and the control module is further configured to:
  • the first terminal is connected to the third terminal.
  • the acquiring module is specifically configured to:
  • topology change indication signal includes the topology change indication information
  • the topology change indication information includes a changed number of system partition CPUs or a changed system application scenario
  • the system application scenario Process scenarios or online transaction processing scenarios for online analysis.
  • the acquiring module includes:
  • a first acquiring submodule configured to acquire system monitoring information, where the system monitoring information includes a CPU At least one of a load and a delay;
  • Generating a submodule configured to generate the topology change indication signal according to the system monitoring information, where the topology change indication signal includes topology change indication information, where the topology change indication information includes a CPU with excessive load and a CPU with excessive delay At least one of them.
  • the determining module includes:
  • a second obtaining submodule configured to determine a topology of the transformed CPU interconnection system according to the topology change indication signal
  • a first determining submodule configured to determine a state of the gating unit according to the transformed topology of the CPU interconnect system.
  • the second acquiring sub-module is specifically configured to:
  • the second acquiring sub-module is specifically configured to:
  • Determining a topology change according to the topology change indication signal includes connecting a line between the two CPUs or disconnecting a line between the two CPUs;
  • the second acquiring sub-module is specifically configured to:
  • Determining that the CPU with excessive load or excessive delay is determined when the topology change indication signal includes a CPU with excessive load or a CPU with excessive delay;
  • connection between the determined CPU and the CPU in the second node is changed to a connection with the CPU in the first node, and the determined CPU is in the first node.
  • the second acquiring sub-module is specifically configured to:
  • connection set C1 includes a direct connection between two CPUs, the connection set C2 including a first intermediate line, a second intermediate line, a CPU and a gating unit An inter-connection or a connection between a CPU and a processing unit, the C3 connection set including a pseudo-direct connection, which is a connection established by the two CPUs through the first intermediate line or the second intermediate line.
  • the first determining submodule is specifically configured to:
  • the two gate units in the CPU interconnection device communicate the first terminal and the second terminal in the first state, and the two second terminals are connected through the first intermediate line to implement CPU interconnection in the first node, or Two second terminals are respectively used to connect two CPUs in the second node to implement CPU interconnection between the first node and the second node, and when in the second state, disconnect the first terminal and the second terminal Terminals, therefore, by switching between the first state and the second state, the CPUs in the nodes or between the nodes can be interconnected and disconnected, so that the topology of the CPU interconnection system conforms to different characteristics and scene requirements, and the CPU interconnection system is improved. CPU processing performance.
  • FIG. 1a is a schematic structural diagram of a CPU interconnection device according to an embodiment of the present invention.
  • FIG. 1b is a schematic structural diagram of another CPU interconnection device according to an embodiment of the present invention.
  • 1c is a schematic structural diagram of another CPU interconnection apparatus according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a CPU interconnection system according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a CPU interconnection system according to an embodiment of the present invention.
  • 3b is a schematic structural diagram of a CPU interconnection system according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another CPU interconnection system according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another CPU interconnection system according to an embodiment of the present invention.
  • FIG. 5b is a schematic structural diagram of another CPU interconnection system according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a CPU interconnection control method according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of another CPU interconnection control method according to an embodiment of the present invention.
  • FIG. 8 is a topological structural diagram of an embodiment of the present invention.
  • FIG. 9 is another topological structural diagram provided by an embodiment of the present invention.
  • FIG. 10a is another topology diagram provided by an embodiment of the present invention.
  • FIG. 10b is another topology diagram provided by an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a CPU interconnection control apparatus according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a CPU interconnection control apparatus according to an embodiment of the present invention.
  • the CPU interconnection apparatus 10 includes: at least one switching circuit 11, each switching circuit 11 includes two gate units 110 and a first intermediate line. 120, each of the gating cells 110 includes a first terminal 111 and a second terminal 112.
  • the first terminal 111 When the gating cell 110 is in the first state, the first terminal 111 is connected to the second terminal 112, and when the gating cell 110 is in the second state, The first terminal 111 is disconnected from the second terminal 112, and the two first terminals 111 of each switching circuit 11 are respectively used to connect two CPUs in the first node 20 (such as CPU0 and CPU3 in the figure), each switching circuit The two second terminals 112 of the 11 are respectively connected to both ends of the first intermediate line 120.
  • FIG. 1b is a schematic structural diagram of another CPU interconnection apparatus according to an embodiment of the present invention. Compared with the apparatus provided in FIG. 1a, two second terminals 112 of each switching circuit 11 are respectively connected to the second node. Two CPUs.
  • the two gate units in the CPU interconnection device communicate the first terminal and the second terminal in the first state, and the two second terminals are connected through the first intermediate line to implement the first node.
  • CPU interconnection, or two second terminals are respectively used to connect two CPUs in the second node to realize CPU interconnection between the first node and the second node, and when in the second state, disconnect The first terminal and the second terminal are thus switchable in the first state and the second state
  • the CPU interconnects and disconnects between nodes or between nodes so that the topology of the CPU interconnect system conforms to different characteristics and scenarios, and improves the processing performance of the CPU in the CPU interconnect system.
  • FIG. 1c is a schematic structural diagram of another CPU interconnection device according to an embodiment of the present invention.
  • the gating unit 110 further includes a third terminal 113.
  • the first terminal 111 is disconnected from the third terminal 113.
  • the gate unit 110 is in the second state, the first terminal 111 is connected to the third terminal 113, and the two second terminals 112 of each switching circuit 11 are respectively associated with the first intermediate portion.
  • the two ends of the line 120 are connected, and the two third terminals 113 of each switching circuit 11 are respectively used to connect two CPUs in the second node 30.
  • the embodiment of the present invention further provides another CPU interconnection device.
  • the device may further include a second intermediate circuit, and the third terminal of the switching circuit passes through the second intermediate line.
  • the third terminal of the switching circuit connected to the CPU in the second node is connected.
  • the embodiment of the present invention further provides another CPU interconnection device.
  • the third terminal of the switching circuit passes through a node controller (English Node Controller, referred to as NC) for processing.
  • NC English Node Controller
  • the unit is connected to a third terminal of the switching circuit connected to the CPU in the second node.
  • the embodiment of the present invention further provides another CPU interconnection device.
  • the gating unit is a switch circuit, an electronic switch, a gate, a selector, a distributor, or has Hardware logic for similar functions.
  • the gating unit may also be a combination of at least two of the above components.
  • the switching circuit can be implemented by using a hardware chip, a circuit device, a combination circuit or a logic circuit with a path selection function (for example, using an existing circuit in the NC), and the specific implementation or combination manner is not limited in the present invention, but Such implementations are within the scope of the present invention.
  • FIG. 2 is a schematic structural diagram of a CPU interconnection system according to an embodiment of the present invention.
  • the system includes multiple nodes, and multiple nodes include a first node 21 and a second node 22, and each node 20 includes multiple direct connections.
  • the CPU, CPU interconnect system also includes the CPU interconnect device 10 as shown in Figures 1a, 1b or 1c (illustrated by 1c in the figure).
  • two gate units in the CPU interconnection device of the CPU interconnection system connect the first terminal and the second terminal in the first state, and the two second terminals are connected through the first intermediate line.
  • the CPUs in the first node are interconnected, or the two second terminals are respectively used to connect two CPUs in the second node to implement CPU interconnection between the first node and the second node, and when in the second state
  • the first terminal and the second terminal are disconnected, so the first state and the second state are passed
  • the CPU can be interconnected and disconnected within the node or between the nodes, so that the topology of the CPU interconnect system conforms to different characteristics and scenarios, and the processing performance of the CPU in the CPU interconnect system is improved.
  • the embodiment of the present invention further provides another CPU interconnection system.
  • each node in the system includes an even number of CPUs, and the number of gate units in the CPU interconnection system and the CPU The number is equal, each CPU is connected to the first terminal of one gating unit, and the gating unit connected to each CPU is different.
  • the CPU interconnection system may further include a gating unit that is smaller than the number of CPUs.
  • FIG. 3a is a schematic structural diagram of a CPU interconnection system according to an embodiment of the present invention.
  • the system includes two nodes and two NC0s, wherein the first node includes CPUs 0 to 3, and CPU0 and CPU1.
  • CPU3 and CPU2 are connected end to end in a circle.
  • the second node includes CPUs 4 to 7, and CPU4, CPU5, CPU7, and CPU6 are connected end to end in a circle.
  • NC0 is connected to CPU0, CPU3, CPU6, and CPU5, and NC2 and CPU2 respectively.
  • CPU1, CPU4 and CPU7 are connected, and the above CPU and NC form an 8P partition.
  • the NC0 includes a processing unit S1, and the processing unit S1 is configured to perform data receiving, verifying, parsing, and routing processing, and can implement the CPU.
  • the CPU 3 is connected to the processing unit S1 or via the first intermediate line S0.
  • the first intermediate line S0 is a line in the NC.
  • the system includes two nodes and a CPU interconnection device.
  • the first node includes CPUs 0 to 3, and CPU0 and CPU1.
  • the CPU 3 and the CPU 2 are connected end to end in a circle
  • the second node includes the CPUs 4 to 7, and the CPU 4, the CPU 5, the CPU 7, and the CPU 6 are connected end to end in a circle.
  • the CPU interconnection device includes a switching circuit including a gating unit A1, A2 and a first intermediate line a2 for respectively connecting the CPU 0 and the CPU 3 through the first intermediate line a2 or through the second intermediate The line (such as a1) is connected to the CPU of the second node.
  • a2 is a second intermediate line
  • the third terminal of the switching unit A1 in the switching circuit is connected to the third terminal of the switching circuit connected to the CPU 5 in the second node through the second intermediate line a2.
  • FIG. 5a and 5b are schematic structural diagrams of another CPU interconnection system according to an embodiment of the present invention.
  • the main difference between the system and the system provided in FIG. 4 is that multiple CPU connections between CPUs or nodes in a node may pass through multiple modules.
  • Line implementation, see Figure 5a the system includes multiple 4 nodes (Node0 ⁇ 3), there are four lines between any two nodes, the internal structure of each node is shown in Figure 5b, including 4 CPU (CPU0 ⁇ 3), there is a path between any two CPUs, and each CPU is connected to three other nodes through three lines.
  • FIG. 6 is a flowchart of a CPU interconnection control method according to an embodiment of the present disclosure, which is applicable to the CPU interconnection system shown in FIG. 2, where the CPU interconnection system includes multiple nodes, and multiple nodes include a first node and a second node, each node comprising a plurality of directly connected CPUs, the CPU interconnection system further comprising a CPU interconnection device, the CPU interconnection device comprising: at least one switching circuit, each switching circuit comprising two gate units and one a first intermediate line, each of the gating cells includes a first terminal and a second terminal, and the two first terminals of each switching circuit are respectively used to connect two CPUs in the first node, two of each switching circuit The two terminals are respectively connected to the two ends of the first intermediate line, or the two second terminals of each switching circuit are respectively used to connect two CPUs in the second node.
  • the method includes:
  • Step 101 Acquire a topology change indication signal.
  • the topology change indication signal can be either user input or automatically generated by the system.
  • Step 102 Determine a state of the gating unit according to the topology change indication signal, where the state includes the first state and the second state.
  • Step 103 When the state of the gating cell is the first state, the first terminal of the control gating cell is connected to the second terminal, and when the state of the gating cell is the second state, the first terminal and the second terminal are controlled to be disconnected.
  • the invention determines the state of the gating unit by the acquired topology change indication signal, the state includes a first state and a second state, and when the state of the gating cell is the first state, controlling the first terminal and the second terminal of the gating cell Connecting, when the state of the gating unit is the second state, controlling the first terminal to be disconnected from the second terminal, thereby implementing intelligently selecting a path between the CPUs according to the topology change indication, so that the topology of the CPU interconnection system conforms to current requirements, and improving The processing performance of the CPU in the CPU interconnect system.
  • FIG. 7 is a flowchart of another CPU interconnection control method according to an embodiment of the present invention.
  • the method includes:
  • Step 201 Acquire a topology change indication signal, where the topology change indication signal is used to indicate a topology change of the CPU interconnection system.
  • acquiring a topology change indication signal includes:
  • the topology change indication signal includes a topology change indication information
  • the topology change indication information includes a changed number of system partition CPUs (such as four) or a changed system application scenario.
  • the topology change indication information is not limited to the above-listed forms, and for example, it may also directly indicate a priority intra-node connection or an inter-node connection.
  • acquiring a topology change indication signal includes:
  • system monitoring information includes at least one of a load and a delay of the CPU
  • the topology change indication signal is generated according to the system monitoring information, and the topology change indication signal includes topology change indication information, where the topology change indication information includes at least one of a CPU with excessive load and a CPU with excessive delay.
  • the generating the topology change indication signal according to the system monitoring information may include: comparing the magnitude of the load and the preset load threshold in the system monitoring information, and the delay of the system monitoring information and the preset delay threshold; when the system monitoring information A topology change indication signal is generated when the medium load is greater than the preset load threshold or the delay is greater than the preset delay threshold.
  • the system monitoring information can be obtained by using an existing performance detecting device or circuit, and is not described here.
  • Step 202 Determine a state of the gating unit according to the topology change indication signal, where the state includes the first state and the second state.
  • step 202 may include:
  • the state of the gating cell is determined according to the topology of the transformed CPU interconnect system.
  • determining the topology of the transformed CPU interconnection system according to the topology change indication signal may be implemented in the following manner:
  • Step 1 Obtain the correspondence between the topology change indication signal and the topology.
  • the corresponding topology structure can be designed according to the topology change indication signal in advance.
  • the mapping between the topology change indication signal and the topology includes, but is not limited to, the correspondence between the system partition CPU number change and the topology, the corresponding relationship between the system application scenario and the topology, and the corresponding relationship between the load being too high and the topology. And the relationship between the delay is too large and the topology.
  • system partition CPU number change indication and topology correspondence can be set as follows:
  • FIGS. 3a and 3b when CPUs (such as CPU0 and CPU3) are connected by a processing unit, an 8P partition is formed, the topology of which is shown in FIG. 3a; when the CPUs are connected by the first intermediate line, The two 4P partitions are formed, and the topology is simplified as shown in FIG. Therefore, the corresponding relationship between the topology change indication and the topology may be as follows: when the topology change indication information includes the number of system partition CPUs is 8, the corresponding topology is as shown in FIG. 3a; and the topology change indication information includes the number of system partition CPUs is 4 The corresponding topology is shown in Figure 8.
  • the corresponding topology is as shown in FIG. 9; when the topology change indication information includes the number of CPUs of the system partition is 4, the corresponding topology is as shown in FIG. 8 is shown.
  • the corresponding topology is as shown in FIG. 5a and FIG. 5b; and the system application scenario included in the topology change indication information is an online transaction processing.
  • the corresponding topology is shown in Figures 10a and 10b.
  • Step 2 Determine the topology of the transformed CPU interconnection system according to the correspondence between the topology change indication signal and the topology, and the topology of the transformed CPU interconnection system corresponds to the topology change indication signal.
  • determining the topology of the transformed CPU interconnection system according to the topology change indication signal may also be implemented in the following manner:
  • Step 1 Determine the topology change according to the topology change indication signal.
  • the topology change includes connecting the line between the two CPUs or disconnecting the line between the two CPUs.
  • Step 1 may include: when the topology change indication signal includes a CPU with excessive load or an excessively delayed CPU, determine a CPU with excessive load or excessive delay; and determine the CPU and the CPU in the second node. The connection between the two is changed to the connection with the CPU in the first node, and the determined CPU is in the first node.
  • Step 2 Determine the topology of the transformed CPU interconnection system according to the topology and topology changes of the CPU interconnection system before the transformation.
  • step 202 may further include: acquiring a topology of the CPU interconnection system before the transformation.
  • FIG 3a the topology before the transformation is shown in Figure 3a.
  • the topology change indication signal includes excessive delay and the delay is too large for the first node CPU0 and CPU1
  • the delay of the first node CPU0 and CPU1 needs to be reduced; specifically, the connection lines of CPU0 and CPU3, CPU1 and CPU2 in the node may be increased.
  • the transformed topology determined according to this scheme is shown in Figure 8.
  • the topology before the transformation is as shown in FIG. 9.
  • the topology change indication signal includes excessive delay and the delay is too large for the first node CPU0 and CPU1
  • the delay of the first node CPU0 and CPU1 needs to be reduced; specifically, the connection lines of CPU0 and CPU3, CPU1 and CPU2 in the node may be increased.
  • the transformed topology determined according to this scheme is shown in Figure 8.
  • FIG. 5a the topology before the transformation is shown in Figures 5a and 5b.
  • the topology change indication signal includes the load being too high and the load is too high for the first node CPU0 and CPU1
  • the load of the first node CPU0 and CPU1 needs to be reduced; specifically, the CPU0 can be lowered by connecting the CPU0 with other CPUs.
  • Load such as increasing the line between CPU0 and other CPUs in the node to two
  • the transformed topology determined according to this scheme is shown in Figures 10a and 10b.
  • determining a topology of the transformed CPU interconnection system includes:
  • connection set C1 includes a direct connection between two CPUs
  • connection set C2 includes a first intermediate line, a second intermediate line, a connection between the CPU and the gating unit, or a CPU and a processing unit
  • the connection between the C3 connection sets includes a pseudo direct connection
  • the pseudo direct connection is a connection established by the two CPUs through the first intermediate line or the second intermediate line.
  • connection set C1 is a direct connection between two CPUs, and can be represented by two CPUs, for example, (CPU0, CPU1).
  • a node number can be added before the CPU, such as (node1CPU0) , node2CPU1).
  • the connection set C2 includes a first or second intermediate line, a connection between the CPU and the gating unit, or a CPU and a node connector, and may use a gating unit at both ends of the first or second intermediate line, or a CPU at both ends of the line and Gating unit table
  • a node number can be added before the CPU and the gating unit.
  • the C3 connection set includes a pseudo-direct connection, which can be represented by two CPUs connected by the pseudo-direct connection and two gate units in the middle, for example (CPU0, A1, A2, CPU1), also for a multi-node system, The node number can be added before the CPU and the gating unit.
  • the pseudo-direct connection only needs to perform hardware layer or physical layer signal or data forwarding, and does not need to perform data processing of two layers or more: receiving, verifying, parsing, exchanging, reorganizing, routing, and the like.
  • the topology of the transformed CPU interconnect system is determined, that is, the connection sets C1, C2, and C3 are determined.
  • determining the state of the gating unit according to the topology of the transformed CPU interconnection system includes:
  • the state of the gating is determined according to the first intermediate line or the second intermediate line that the gating unit is connected to.
  • Step 203 When the state of the gating unit is the first state, the first terminal of the control gating unit is connected to the second terminal, and the first terminal is controlled to be disconnected from the third terminal; when the state of the gating cell is the second state, The first terminal is controlled to be disconnected from the second terminal, and the first terminal is connected to the third terminal.
  • the gating unit further includes a third terminal, and the two second terminals of each switching circuit are respectively connected to the two ends of the first intermediate circuit, and the two third terminals of each switching circuit are respectively connected to the second node.
  • the two CPUs are respectively connected to the two ends of the first intermediate circuit, and the two third terminals of each switching circuit are respectively connected to the second node.
  • the corresponding control signal is determined according to the state of the gating unit, and the determined control signal is sent to the gating unit.
  • control signal may comprise a binary number of 0 or 1.
  • control signal may be a single signal such as 0 or 1, or a combination of multiple signals.
  • control signal can also be a single signal or a combination of signals (eg, non-operational).
  • the CPU interconnection control method provided by the present invention is mainly applied to various scenarios in which CPU connection adjustment is required, and the topology of the CPU interconnection is adjusted, thereby greatly improving the performance of the CPU interconnection. For example, when the CPU delay and load are high, by increasing the CPU connection between nodes, the number of hops of data transmission between nodes is reduced, thereby reducing the amount of data transferred, thereby greatly improving the processing performance of the CPU.
  • FIG. 11 is a schematic structural diagram of a CPU interconnection control apparatus according to an embodiment of the present disclosure, which is applicable to the CPU interconnection system shown in FIG. 2, where the CPU interconnection system includes multiple nodes, and multiple nodes include a first node and a second node, each node comprising a plurality of directly connected CPUs, the CPU interconnection system further comprising a CPU interconnection device, the CPU interconnection device comprising: at least one switching circuit, each switching circuit comprising two gate units and one a first intermediate line, each of the gating cells includes a first terminal and a second terminal, and the two first terminals of each switching circuit are respectively used to connect two CPUs in the first node, two of each switching circuit The two terminals are respectively connected to the two ends of the first intermediate line, or the two second terminals of each switching circuit are respectively used to connect two CPUs in the second node.
  • the device includes:
  • the obtaining module 301 is configured to acquire a topology change indication signal.
  • the determining module 302 is configured to determine a state of the gating unit according to the topology change indication signal, where the state includes the first state and the second state;
  • the control module 303 is configured to: when the state of the gating cell is the first state, the first terminal of the control gating cell is connected to the second terminal, and when the state of the gating cell is the second state, the first terminal and the second terminal are controlled. disconnect.
  • the invention determines the state of the gating unit by the acquired topology change indication signal, the state includes a first state and a second state, and when the state of the gating cell is the first state, controlling the first terminal and the second terminal of the gating cell Connecting, when the state of the gating unit is the second state, controlling the first terminal to be disconnected from the second terminal, thereby implementing intelligently selecting a path between the CPUs according to the topology change indication, so that the topology of the CPU interconnection system conforms to current requirements, and improving The processing performance of the CPU in the CPU interconnect system.
  • FIG. 12 is a schematic structural diagram of a CPU interconnection control apparatus according to an embodiment of the present invention, which is applicable to the foregoing CPU interconnection system.
  • the apparatus includes:
  • the obtaining module 401 is configured to acquire a topology change indication signal.
  • a determining module 402 configured to determine a state of the gating unit according to the topology change indication signal, where the state includes the first state and the second state;
  • the control module 403 is configured to: when the state of the gating cell is the first state, the first terminal of the control gating cell is connected to the second terminal, and when the state of the gating cell is the second state, the first end is controlled. The sub is disconnected from the second terminal.
  • the gating unit further includes a third terminal, wherein the two second terminals of each switching circuit are respectively connected to the two ends of the first intermediate circuit, and the two third terminals of each switching circuit are respectively used to connect the second node
  • the two CPUs inside, the control module 403, are also used to:
  • the first terminal When the state of the gating cell is the first state, the first terminal is controlled to be disconnected from the third terminal, and when the state of the gating cell is the second state, the first terminal is controlled to be connected to the third terminal.
  • the obtaining module 401 is specifically configured to:
  • the topology change indication signal is received by the user, and the topology change indication signal includes the topology change indication information, where the topology change indication information includes the changed system partition CPU number or the changed system application scenario.
  • the obtaining module 401 includes:
  • the first obtaining submodule 4011 is configured to acquire system monitoring information, where the system monitoring information includes at least one of a load and a delay of the CPU;
  • the generating sub-module 4012 is configured to generate a topology change indication signal according to the system monitoring information, where the topology change indication signal includes topology change indication information, where the topology change indication information includes at least one of a CPU with excessive load and a CPU with excessive delay.
  • the determining module 402 includes:
  • a second obtaining submodule 4021 configured to determine a topology of the transformed CPU interconnection system according to the topology change indication signal
  • the first determining submodule 4022 is configured to determine a state of the gating unit according to a topology of the transformed CPU interconnect system.
  • the second obtaining submodule 4021 is specifically configured to:
  • the topology of the transformed CPU interconnection system is determined according to the correspondence between the topology change indication signal and the topology, and the topology of the transformed CPU interconnection system corresponds to the topology change indication signal.
  • the second obtaining submodule 4021 is specifically configured to:
  • the topology change is determined according to the topology change indication signal, and the topology change includes connecting a line between the two CPUs or disconnecting a line between the two CPUs;
  • the topology of the transformed CPU interconnect system is determined according to the topology and topology changes of the CPU interconnect system before the transformation.
  • the topology of the CPU interconnection system before the transformation may be acquired in advance, or may be obtained by the determining module 402. Therefore, in this implementation, the determining module 402 may further include: a second obtaining sub-module 4021, configured to acquire a topology of the CPU interconnection system before the transformation.
  • the second obtaining submodule 4021 is specifically configured to:
  • connection between the determined CPU and the CPU in the second node is changed to the connection with the CPU in the first node, and the determined CPU is in the first node.
  • the second obtaining submodule 4021 is specifically configured to:
  • connection set C1 includes a direct connection between two CPUs
  • connection set C2 includes a first intermediate line, a second intermediate line, a connection between the CPU and the gating unit, or a CPU and a processing unit
  • the connection between the C3 connection sets includes a pseudo direct connection
  • the pseudo direct connection is a connection established by the two CPUs through the first intermediate line or the second intermediate line.
  • first determining submodule 4022 is specifically configured to:
  • the state of the gating is determined according to the first intermediate line or the second intermediate line that the gating unit is connected to.
  • the CPU interconnection control device provided by the foregoing embodiment is only illustrated by the division of the foregoing functional modules when performing CPU interconnection. In actual applications, the foregoing functions may be assigned different functions according to requirements. The module is completed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.
  • the embodiment of the CPU interconnection control device and the CPU interconnection control method provided by the foregoing embodiments are in the same concept, and the specific implementation process is described in detail in the method embodiment, and details are not described herein again.

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Abstract

一种CPU互连装置、系统及其控制方法、控制装置，属于电子技术领域。所述CPU互连装置包括：至少一个切换电路（11），每个切换电路包括两个选通单元（110）和一条第一中间线路（120），每个选通单元（110）包括第一端子（111）和第二端子（112），当所述选通单元（110）处于第一状态时，所述第一端子（111）与所述第二端子（112）连接，当所述选通单元（110）处于第二状态时，所述第一端子（111）与所述第二端子（112）断开，每个所述切换电路（11）的两个所述第一端子（111）分别用于连接第一节点（20）内的两个CPU，每个所述切换电路（11）的两个所述第二端子（112）分别与第一中间线路（120）的两端连接，或者每个所述切换电路（11）的两个第二端子（112）分别用于连接第二节点（30）内的两个CPU。

Description

CPU互连装置、系统及其控制方法、控制装置
本申请要求于2015年08月25日提交中国专利局、申请号为201510526313.5、发明名称为“CPU互连装置、系统及其控制方法、控制装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子技术领域，特别涉及一种CPU互连装置、系统及其控制方法、控制装置。
背景技术
快速互联通道(英文Quick Path Interconnect，简称QPI)技术将多个节点中的中央处理器(英文Central Processing Unit，简称CPU)相互连接，使得原本独立工作的多个节点可以联合成一个整体(即组成一个分区)，并将所联合成的整体作为一个执行主体来承担原来各个节点上的工作，提高了各个节点的数据承载量和处理能力。
现有技术中，由于CPU的端子数量有限，在实际应用中往往不能做到一个分区中的每个CPU都与其他的CPU两两相连，所以在进行拓扑搭建时，将一个CPU与其他CPU进行连接，会选择性地将该CPU与其他CPU中的几个进行连接，而由于在将一个CPU与其他CPU中的几个进行连接存在多种连接方式，所以对于多个节点的CPU互连而言，可以通过选择不同的连接方式搭建出多种拓扑结构。但由于拓扑结构在搭建完成后是固定不变的，因而无法实现系统多样化的需求。
发明内容
为了解决现有技术的问题，本发明实施例提供了一种CPU互连装置、系统及其控制方法、控制装置。所述技术方案如下：
第一方面，本发明实施例提供了一种CPU互连装置，包括：至少一个切换电路，每个切换电路包括两个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，当所述选通单元处于第一状态时，所述第一端子与所述第二端子连接，当所述选通单元处于第二状态时，所述第 一端子与所述第二端子断开，每个所述切换电路的两个所述第一端子分别用于连接第一节点内的两个CPU，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，或者每个所述切换电路的两个第二端子分别用于连接第二节点内的两个CPU。
在本发明实施例的一种实现方式中，所述选通单元还包括第三端子，当所述选通单元处于所述第一状态时，所述第一端子与所述第三端子断开，当所述选通单元处于所述第二状态时，所述第一端子与所述第三端子连接，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，每个所述切换电路的两个第三端子分别用于连接所述第二节点内的两个CPU。
在本发明实施例的另一种实现方式中，所述装置包括第二中间线路，所述切换电路的第三端子通过所述第二中间线路与所述第二节点内的CPU所连的切换电路的第三端子连接。
在本发明实施例的另一种实现方式中，所述切换电路的第三端子通过NC中的处理单元与所述第二节点内的CPU所连的切换电路的第三端子连接。
在本发明实施例的另一种实现方式中，所述选通单元为开关电路、电子开关、选通器、选择器或者分配器。
第二方面，本发明实施例提供了一种CPU互连系统，包括多个节点，所述多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，所述CPU互连系统还包括如前所述的CPU互连装置。
第三方面，本发明实施例提供了一种CPU互连控制方法，适用于CPU互连系统，所述CPU互连系统包括多个节点，所述多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，所述CPU互连系统还包括CPU互连装置，所述CPU互连装置包括：至少一个切换电路，每个切换电路包括两个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，每个所述切换电路的两个所述第一端子分别用于连接第一节点内的两个CPU，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，或者每个所述切换电路的两个第二端子分别用于连接所 述第二节点内的两个CPU，所述方法包括：
获取拓扑变化指示信号；
根据所述拓扑变化指示信号确定选通单元的状态，所述状态包括第一状态和第二状态；
当所述选通单元的状态为所述第一状态时，控制所述选通单元的所述第一端子与所述第二端子连接，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第二端子断开。
在本发明实施例的一种实现方式中，所述选通单元还包括第三端子，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，每个所述切换电路的两个第三端子分别用于连接所述第二节点内的两个CPU，所述方法还包括：
当所述选通单元的状态为所述第一状态时，控制所述第一端子与所述第三端子断开，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第三端子连接。
在本发明实施例的另一种实现方式中，所述获取拓扑变化指示信号，包括：
接收用户输入的拓扑变化指示信号，所述拓扑变化指示信号包括所述拓扑变化指示信息，所述拓扑变化指示信息包括变化后的系统分区CPU数量或变化后的系统应用场景，所述系统应用场景为联机分析处理场景或者联机事务处理场景。
在本发明实施例的另一种实现方式中，所述获取拓扑变化指示信号，包括：
获取系统监测信息，所述系统监测信息包括CPU的负载和延迟中的至少一个；
根据所述系统监测信息生成所述拓扑变化指示信号，所述拓扑变化指示信号包括拓扑变化指示信息，所述拓扑变化指示信息包括负载过高的CPU和延迟过大的CPU中的至少一个。
在本发明实施例的另一种实现方式中，所述根据所述拓扑变化指示信号确定选通单元的状态，包括：
根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑；
根据变换后的所述CPU互连系统的拓扑确定选通单元的状态。
在本发明实施例的另一种实现方式中，所述根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑，包括：
获取拓扑变化指示信号与拓扑的对应关系；
根据所述拓扑变化指示信号与拓扑的对应关系，确定变换后的所述CPU互连系统的拓扑，所述变换后的所述CPU互连系统的拓扑与拓扑变化指示信号相对应。
在本发明实施例的另一种实现方式中，所述根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑，包括：
根据所述拓扑变化指示信号确定拓扑变化，所述拓扑变化包括连通两CPU之间的线路或者断开两CPU之间的线路；
根据变换前的所述CPU互连系统的拓扑和所述拓扑变化，确定变换后的所述CPU互连系统的拓扑。
在本发明实施例的另一种实现方式中，所述根据所述拓扑变化指示信号确定拓扑变化，包括：
当所述拓扑变化指示信号包括负载过高的CPU或延迟过大的CPU时，确定所述负载过高或延迟过大的CPU；
将确定出的CPU与所述第二节点中的CPU之间的连接，改为与所述第一节点内的CPU之间的连接，所述确定出的CPU处于所述第一节点内。
在本发明实施例的另一种实现方式中，所述确定变换后的所述CPU互连系统的拓扑，包括：
确定连接集C1、C2和C3，所述连接集C1包括两个CPU间的直连连接，所述连接集C2包括第一中间线路、第二中间线路、CPU与选通单元之间的连接或者CPU与处理单元之间的连接，所述C3连接集包括伪直连连接，所述伪直连连接是两CPU通过第一中间线路或第二中间线路建立的连接。
在本发明实施例的另一种实现方式中，所述根据变换后的所述CPU互连系统的拓扑确定选通单元的状态，包括：
获取变换后的所述CPU互连系统的拓扑中的连接集C2和C3；
根据所述连接集C2和C3确定每个选通单元所连通的第一中间线路或者第二中间线路；
根据所述选通单元所连通的第一中间线路或者第二中间线路确定所述 选通的状态。
第四方面，本发明实施例提供了一种CPU互连控制装置，适用于CPU互连系统，所述CPU互连系统包括多个节点，所述多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，所述CPU互连系统还包括CPU互连装置，所述CPU互连装置包括：至少一个切换电路，每个切换电路包括两个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，每个所述切换电路的两个所述第一端子分别用于连接第一节点内的两个CPU，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，或者每个所述切换电路的两个第二端子分别用于连接所述第二节点内的两个CPU，所述装置包括：
获取模块，用于获取拓扑变化指示信号；
确定模块，用于根据所述拓扑变化指示信号确定选通单元的状态，所述状态包括第一状态和第二状态；
控制模块，用于当所述选通单元的状态为所述第一状态时，控制所述选通单元的所述第一端子与所述第二端子连接，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第二端子断开。
在本发明实施例的一种实现方式中，所述选通单元还包括第三端子，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，每个所述切换电路的两个第三端子分别用于连接所述第二节点内的两个CPU，所述控制模块，还用于：
当所述选通单元的状态为所述第一状态时，控制所述第一端子与所述第三端子断开，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第三端子连接。
在本发明实施例的另一种实现方式中，所述获取模块，具体用于：
接收用户输入的拓扑变化指示信号，所述拓扑变化指示信号包括所述拓扑变化指示信息，所述拓扑变化指示信息包括变化后的系统分区CPU数量或变化后的系统应用场景，所述系统应用场景为联机分析处理场景或者联机事务处理场景。
在本发明实施例的另一种实现方式中，所述获取模块，包括：
第一获取子模块，用于获取系统监测信息，所述系统监测信息包括CPU 的负载和延迟中的至少一个；
生成子模块，用于根据所述系统监测信息生成所述拓扑变化指示信号，所述拓扑变化指示信号包括拓扑变化指示信息，所述拓扑变化指示信息包括负载过高的CPU和延迟过大的CPU中的至少一个。
在本发明实施例的另一种实现方式中，所述确定模块，包括：
第二获取子模块，用于根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑；
第一确定子模块，用于根据变换后的所述CPU互连系统的拓扑确定选通单元的状态。
在本发明实施例的另一种实现方式中，所述第二获取子模块，具体用于：
获取拓扑变化指示信号与拓扑的对应关系；
根据所述拓扑变化指示信号与拓扑的对应关系，确定变换后的所述CPU互连系统的拓扑，所述变换后的所述CPU互连系统的拓扑与拓扑变化指示信号相对应。
在本发明实施例的另一种实现方式中，所述第二获取子模块，具体用于：
根据所述拓扑变化指示信号确定拓扑变化，所述拓扑变化包括连通两CPU之间的线路或者断开两CPU之间的线路；
根据变换前的所述CPU互连系统的拓扑和所述拓扑变化，确定变换后的所述CPU互连系统的拓扑。
在本发明实施例的另一种实现方式中，所述第二获取子模块，具体用于：
当所述拓扑变化指示信号包括负载过高的CPU或延迟过大的CPU时，确定所述负载过高或延迟过大的CPU；
将确定出的CPU与所述第二节点中的CPU之间的连接，改为与所述第一节点内的CPU之间的连接，所述确定出的CPU处于所述第一节点内。
在本发明实施例的另一种实现方式中，所述第二获取子模块，具体用于：
确定连接集C1、C2和C3，所述连接集C1包括两个CPU间的直连连接，所述连接集C2包括第一中间线路、第二中间线路、CPU与选通单元之 间的连接或者CPU与处理单元之间的连接，所述C3连接集包括伪直连连接，所述伪直连连接是两CPU通过第一中间线路或第二中间线路建立的连接。
在本发明实施例的另一种实现方式中，所述第一确定子模块，具体用于：
获取变换后的所述CPU互连系统的拓扑中的连接集C2和C3；
根据所述连接集C2和C3确定每个选通单元所连通的第一中间线路或者第二中间线路；
根据所述选通单元所连通的第一中间线路或者第二中间线路确定所述选通的状态。
本发明实施例提供的技术方案带来的有益效果是：
CPU互连装置中的两个选通单元在第一状态下，连通第一端子和第二端子，两个第二端子通过第一中间线路连接，实现第一节点内的CPU互连，或者，两个第二端子分别用于连接第二节点内的两个CPU，实现第一节点与第二节点间的CPU互连，而当处在第二状态下时，断开第一端子和第二端子，因此通过在第一状态和第二状态下的切换，可以节点内或节点间CPU互连与断开，使得CPU互连系统的拓扑符合不同特性、场景需求，提高了CPU互连系统中CPU的处理性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a是本发明实施例提供的一种CPU互连装置的结构示意图；
图1b是本发明实施例提供的另一种CPU互连装置的结构示意图；
图1c是本发明实施例提供的另一种CPU互连装置的结构示意图；
图2是本发明实施例提供的一种CPU互连系统的结构示意图；
图3a是本发明实施例提供的一种CPU互连系统的结构示意图；
图3b是本发明实施例提供的一种CPU互连系统的结构示意图；
图4是本发明实施例提供的另一种CPU互连系统的结构示意图；
图5a是本发明实施例提供的另一种CPU互连系统的结构示意图；
图5b是本发明实施例提供的另一种CPU互连系统的结构示意图；
图6是本发明实施例提供的一种CPU互连控制方法的流程图；
图7是本发明实施例提供的另一种CPU互连控制方法的流程图；
图8是本发明实施例提供的一种拓扑结构图；
图9是本发明实施例提供的另一种拓扑结构图；
图10a是本发明实施例提供的另一种拓扑结构图；
图10b是本发明实施例提供的另一种拓扑结构图；
图11是本发明实施例提供的一种CPU互连控制装置的结构示意图；
图12是本发明实施例提供的一种CPU互连控制装置的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
图1a是本发明实施例提供的一种CPU互连装置的结构示意图，CPU互连装置10包括：至少一个切换电路11，每个切换电路11包括两个选通单元110和一条第一中间线路120，每个选通单元110包括第一端子111和第二端子112，当选通单元110处于第一状态时，第一端子111与第二端子112连接，当选通单元110处于第二状态时，第一端子111与第二端子112断开，每个切换电路11的两个第一端子111分别用于连接第一节点20内的两个CPU(如图中CPU0和CPU3)，每个切换电路11的两个第二端子112分别与第一中间线路120的两端连接。
图1b是本发明实施例提供的另一种CPU互连装置的结构示意图，与图1a提供的装置相比，每个切换电路11的两个第二端子112分别用于连接第二节点内的两个CPU。
本发明实施例中，CPU互连装置中的两个选通单元在第一状态下，连通第一端子和第二端子，两个第二端子通过第一中间线路连接，实现第一节点内的CPU互连，或者，两个第二端子分别用于连接第二节点内的两个CPU，实现第一节点与第二节点间的CPU互连，而当处在第二状态下时，断开第一端子和第二端子，因此通过在第一状态和第二状态下的切换，可 以节点内或节点间CPU互连与断开，使得CPU互连系统的拓扑符合不同特性、场景需求，提高了CPU互连系统中CPU的处理性能。
图1c是本发明实施例提供的另一种CPU互连装置的结构示意图，与图1a提供的装置相比，选通单元110还包括第三端子113，当选通单元110处于第一状态时，第一端子111与第三端子113断开，当选通单元110处于第二状态时，第一端子111与第三端子113连接，每个切换电路11的两个第二端子112分别与第一中间线路120的两端连接，每个切换电路11的两个第三端子113分别用于连接第二节点30内的两个CPU。
本发明实施例还提供了另一种CPU互连装置，与图1a、1b或1c提供的装置相比，该装置还可以包括第二中间线路，切换电路的第三端子通过第二中间线路与第二节点内的CPU所连的切换电路的第三端子连接。
本发明实施例还提供了另一种CPU互连装置，与图1a、1b或1c提供的装置相比，该切换电路的第三端子通过节点控制器(英文Node Controller，简称NC)中的处理单元与第二节点内的CPU所连的切换电路的第三端子连接。
本发明实施例还提供了另一种CPU互连装置，与图1a、1b或1c提供的装置相比，选通单元为开关电路、电子开关、选通器、选择器、分配器、或具有类似功能的硬件逻辑。选通单元还可以是上述元器件中至少两个的组合。开关电路可以采用具有通路选择功能的硬件芯片、电路器件、组合电路或者逻辑电路实现(如采用NC中的已有电路实现)，在本发明中对此具体实现或组合的方式不做限定，但此类实现方式均在本发明涵盖范围内。
图2是本发明实施例提供的一种CPU互连系统的结构示意图，该系统包括多个节点，多个节点包括第一节点21和第二节点22，每个节点20包括多个直连连接的CPU，CPU互连系统还包括如图1a、1b或1c(图中以1c为例)所示的CPU互连装置10。
本发明实施例中，CPU互连系统的CPU互连装置中的两个选通单元在第一状态下，连通第一端子和第二端子，两个第二端子通过第一中间线路连接，实现第一节点内的CPU互连，或者，两个第二端子分别用于连接第二节点内的两个CPU，实现第一节点与第二节点间的CPU互连，而当处在第二状态下时，断开第一端子和第二端子，因此通过在第一状态和第二状 态下的切换，可以节点内或节点间CPU互连与断开，使得CPU互连系统的拓扑符合不同特性、场景需求，提高了CPU互连系统中CPU的处理性能。
本发明实施例还提供了另一种CPU互连系统，与图2提供的CPU互连系统相比，该系统中每个节点包括偶数个CPU，且CPU互连系统中选通单元的数量与CPU数量相等，每个CPU分别与一个选通单元的第一端子连接，且每个CPU连接的选通单元不同。当然，在本发明实施例中，CPU互连系统还可以包括比CPU数量少的选通单元。
下面通过举例对本发明实施例提供的CPU互连系统进行说明：
图3a是本发明实施例提供的一种CPU互连系统的结构示意图，参见图3a，该系统中包括两个节点和两个NC0，其中，第一节点包括CPU0～3，且CPU0、CPU1、CPU3、CPU2首尾相连围成一圈，同样第二节点包括CPU4～7，且CPU4、CPU5、CPU7、CPU6首尾相连围成一圈，NC0分别与CPU0、CPU3、CPU6和CPU5连接，NC2分别与CPU2、CPU1、CPU4和CPU7连接，上述CPU和NC组成一个8P的分区。
具体地，下面对NC内部结构进行说明，以NC0为例，具体如图3b所示，NC0包括处理单元S1，处理单元S1用于进行数据接收、校验、解析和路由处理，可以实现CPU之间的连通与断开；NC0还包括CPU互连装置，CPU互连装置包括切换电路，切换电路包括选通单元S2、S3和第一中间线路S0，选通单元S2和S3用于使CPU0和CPU3通过处理单元S1连通，或者通过第一中间线路S0连通。其中，第一中间线路S0为NC中的线路。
图4是本发明实施例提供的另一种CPU互连系统的结构示意图，参见图4，该系统中包括两个节点以及CPU互连装置，第一节点包括CPU0～3，且CPU0、CPU1、CPU3、CPU2首尾相连围成一圈，同样第二节点包括CPU4～7，且CPU4、CPU5、CPU7、CPU6首尾相连围成一圈。CPU互连装置包括切换电路，切换电路包括选通单元A1、A2和第一中间线路a2，选通单元A1和A2分别用于使CPU0和CPU3通过第一中间线路a2连通，或者通过第二中间线路(如a1)连接到第二节点的CPU上。
其中，a2为一条第二中间线路，切换电路中选通单元A1的第三端子通过第二中间线路a2与第二节点内的CPU5所连的切换电路的第三端子连接。
图5a和5b是本发明实施例提供的另一种CPU互连系统的结构示意图，该系统与图4提供的系统的主要区别在于，节点内CPU间或者节点间的CPU间连接可以通过多条线路实现，参见图5a，该系统中包括多个4个节点(Node0～3)，任意两个节点之间有四条线路连接，每个节点的内部结构如图5b所示，其中包括4个CPU(CPU0～3)，任意两个CPU之间有一条通路，每个CPU通过三条线路与另外三个节点连接。
需要说明的是，以上应用场景中CPU及其他元器件的数量仅为举例，本发明对此不作限制。
图6是本发明实施例提供的一种CPU互连控制方法的流程图，适用于前述图2所示的CPU互连系统，CPU互连系统包括多个节点，多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，CPU互连系统还包括CPU互连装置，CPU互连装置包括：至少一个切换电路，每个切换电路包括两个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，每个切换电路的两个第一端子分别用于连接第一节点内的两个CPU，每个切换电路的两个第二端子分别与第一中间线路的两端连接，或者每个切换电路的两个第二端子分别用于连接第二节点内的两个CPU，参见图6，该方法包括：
步骤101：获取拓扑变化指示信号。
拓扑变化指示信号既可以是用户输入的，也可以是系统自动生成的。
步骤102：根据拓扑变化指示信号确定选通单元的状态，状态包括第一状态和第二状态。
步骤103：当选通单元的状态为第一状态时，控制选通单元的第一端子与第二端子连接，当选通单元的状态为第二状态时，控制第一端子与第二端子断开。
本发明通过获取到的拓扑变化指示信号确定选通单元的状态，状态包括第一状态和第二状态，当选通单元的状态为第一状态时，控制选通单元的第一端子与第二端子连接，当选通单元的状态为第二状态时，控制第一端子与第二端子断开，从而实现根据拓扑变化指示智能化选择CPU间的通路，使得CPU互连系统的拓扑符合当前需求，提高了CPU互连系统中CPU的处理性能。
图7是本发明实施例提供的另一种CPU互连控制方法的流程图，适用 于前文的CPU互连系统，参见图7，该方法包括：
步骤201：获取拓扑变化指示信号，拓扑变化指示信号用于指示进行CPU互连系统的拓扑变化。
在本发明实施例的一种实现方式中，获取拓扑变化指示信号，包括：
接收用户输入的拓扑变化指示信号，拓扑变化指示信号包括拓扑变化指示信息，拓扑变化指示信息包括变化后的系统分区CPU数量(如4个)或变化后的系统应用场景。当然拓扑变化指示信息不限于上述所列举的形式，例如还可以是直接指示优先节点内连接或节点间连接。
在本发明实施例的另一种实现方式中，获取拓扑变化指示信号，包括：
获取系统监测信息，系统监测信息包括CPU的负载和延迟中的至少一个；
根据系统监测信息生成拓扑变化指示信号，拓扑变化指示信号包括拓扑变化指示信息，拓扑变化指示信息包括负载过高的CPU和延迟过大的CPU中的至少一个。
其中，根据系统监测信息生成拓扑变化指示信号可以包括：比较系统监测信息中的负载与预设负载阀值的大小，以及系统监测信息中的延迟与预设延迟阀值的大小；当系统监测信息中负载大于预设负载阀值或者延迟大于预设延迟阀值时，生成拓扑变化指示信号。其中，系统监测信息的获取可以采用现有的性能检测装置或电路实现，这里不做赘述。
步骤202：根据拓扑变化指示信号确定选通单元的状态，状态包括第一状态和第二状态。
具体地，步骤202可以包括：
根据拓扑变化指示信号确定变换后的CPU互连系统的拓扑；
根据变换后的CPU互连系统的拓扑确定选通单元的状态。
在本发明实施例的一种实现方式中，根据拓扑变化指示信号确定变换后的CPU互连系统的拓扑可以采用下述方式实现：
步骤一：获取拓扑变化指示信号与拓扑的对应关系。
由于对于一个系统而言，其中CPU等元件的布置是固定的，因此可以事先根据拓扑变化指示信号设计出对应的拓扑结构。具体地，拓扑变化指示信号与拓扑的对应关系包括但不限于：系统分区CPU数量变化与拓扑的对应关系，系统应用场景与拓扑的对应关系，负载过高与拓扑的对应关系 及延迟过大与拓扑的对应关系。
下面通过举例对上述拓扑变化指示与拓扑的对应关系进行说明：
例如，系统分区CPU数量变化指示与拓扑的对应关系可以按如下方式设置：
以图3a和3b为例，当CPU之间(如CPU0和CPU3)通过处理单元连接时，构成一个8P的分区，其拓扑如图3a所示；当CPU之间通过第一中间线路连接时，构成两个4P的分区，其拓扑简化如图8所示。因此，上述拓扑变化指示与拓扑的对应关系可以如下：当拓扑变化指示信息包括系统分区CPU数量为8时，其对应的拓扑如图3a所示；当拓扑变化指示信息包括系统分区CPU数量为4时，其对应的拓扑如图8所示。
以图4为例，当拓扑变化指示信息包括系统分区CPU数量为8时，其对应的拓扑如图9所示；当拓扑变化指示信息包括系统分区CPU数量为4时，其对应的拓扑如图8所示。
以图5a为例，当拓扑变化指示信息包括的系统应用场景为联机分析处理OLAP场景时，其对应的拓扑如图5a和5b所示；当拓扑变化指示信息包括的系统应用场景为联机事务处理OLTP场景时，其对应的拓扑如图10a和10b所示。
步骤二：根据拓扑变化指示信号与拓扑的对应关系，确定变换后的CPU互连系统的拓扑，变换后的CPU互连系统的拓扑与拓扑变化指示信号相对应。
在本发明实施例的另一种实现方式中，根据拓扑变化指示信号确定变换后的CPU互连系统的拓扑还可以采用下述方式实现：
步骤一：根据拓扑变化指示信号确定拓扑变化，拓扑变化包括连通两CPU之间的线路或者断开两CPU之间的线路。
其中，步骤一可以包括：当拓扑变化指示信号包括负载过高的CPU或延迟过大的CPU时，确定负载过高或延迟过大的CPU；将确定出的CPU与第二节点中的CPU之间的连接，改为与第一节点内的CPU之间的连接，确定出的CPU处于第一节点内。
步骤二：根据变换前的CPU互连系统的拓扑和拓扑变化，确定变换后的CPU互连系统的拓扑。
其中，变换前的CPU互连系统的拓扑可能是在步骤201之前获取到的， 也可以是在步骤一前获取到的。因此，在这种实现方式中，步骤202还可以包括：获取变换前的CPU互连系统的拓扑。
下面通过举例对上述拓扑变化进行说明：
以图3a为例，变换前的拓扑如图3a所示。当拓扑变化指示信号包括延迟过大，延迟过大的为第一节点CPU0和CPU1时，需要降低第一节点CPU0和CPU1的延迟；具体可以通过增加节点内CPU0和CPU3、CPU1和CPU2的连接线路来降低两种延迟，按照此方案确定出的变换后的拓扑如图8所示。
以图4为例，变换前的拓扑如图9所示。当拓扑变化指示信号包括延迟过大，延迟过大的为第一节点CPU0和CPU1时，需要降低第一节点CPU0和CPU1的延迟；具体可以通过增加节点内CPU0和CPU3、CPU1和CPU2的连接线路来降低两种延迟，按照此方案确定出的变换后的拓扑如图8所示。
以图5a为例，变换前的拓扑如图5a和5b所示。当拓扑变化指示信号包括负载过高，负载过高大的为第一节点CPU0和CPU1时，需要降低第一节点CPU0和CPU1的负载；具体可以通过增加节点内CPU0与其他CPU的连接线路来降低其负载，如将CPU0与节点内其他CPU之间的线路增加至两条，按照此方案确定出的变换后的拓扑如图10a和10b所示。
在上述方案中，拓扑是采用图示方式表示的，但是对于处理器或者控制器而言，为了降低其处理复杂度，可以采用下述方式连接集的方式表示拓扑。具体地，在上述两种实现方式中，确定变换后的CPU互连系统的拓扑包括：
确定连接集C1、C2和C3，连接集C1包括两个CPU间的直连连接，连接集C2包括第一中间线路、第二中间线路、CPU与选通单元之间的连接或者CPU与处理单元之间的连接，C3连接集包括伪直连连接，伪直连连接是两CPU通过第一中间线路或第二中间线路建立的连接。
具体地，连接集C1为两个CPU间的直连连接，可以采用两个CPU来表示，例如(CPU0，CPU1)，对于多节点系统而言，可以在CPU前加上节点号，如(node1CPU0，node2CPU1)。连接集C2为包括第一或者第二中间线路、CPU与选通单元之间的连接或者CPU与节点连接器，可以采用第一或者第二中间线路两端的选通单元、或者线路两端的CPU与选通单元表 示，例如(A1，A2)、(CPU0、A1)，同样对于多节点系统而言，可以在CPU和选通单元前加上节点号。C3连接集包括伪直连连接，可以采用该伪直连连接连通的两个CPU及中间的两个选通单元表示，例如(CPU0，A1，A2，CPU1)，同样对于多节点系统而言，可以在CPU和选通单元前加上节点号。在本发明实施例中，伪直连连接只需进行硬件层或物理层信号或数据转发，而不需要进行二层及以上的数据处理：接收、校验、解析、交换、重组、路由等。
在前述步骤中，确定变换后的CPU互连系统的拓扑，即包括确定连接集C1、C2和C3。
在本发明实施例中，根据变换后的CPU互连系统的拓扑确定选通单元的状态，包括：
获取变换后的CPU互连系统的拓扑中的连接集C2和C3；
根据连接集C2和C3确定每个选通单元所连通的第一中间线路或者第二中间线路；
根据选通单元所连通的第一中间线路或者第二中间线路确定选通的状态。
以图3a为例，当选通单元连接第一中间线路S0时，确定选通单元为第一状态。
步骤203：当选通单元的状态为第一状态时，控制选通单元的第一端子与第二端子连接，控制第一端子与第三端子断开；当选通单元的状态为第二状态时，控制第一端子与第二端子断开，控制第一端子与第三端子连接。
其中，选通单元还包括第三端子，每个切换电路的两个第二端子分别与第一中间线路的两端连接，每个切换电路的两个第三端子分别用于连接第二节点内的两个CPU。
具体控制时，根据选通单元的状态确定对应的控制信号，将确定出的控制信号发送给选通单元。
具体地，控制信号可以包括二进制数0或者1。在本发明实施例中，控制信号可能是一个单一的信号例如0或者1，也可以是多个信号的组合。此外，控制信号还可以是单个信号或者组合经过运算(如非运算)后的信号。
本发明所提供的CPU互连控制方法主要应用于需要进行CPU连接调整的各种场景中，通过CPU互连的拓扑调整，从而大大改善CPU互连的性能， 例如在CPU延迟和负载较高时，通过增加节点间的CPU连接，减少数据在节点间CPU传输的跳数，从而减少了传输数据量，从而很大程度提高了CPU的处理性能。
图11是本发明实施例提供的一种CPU互连控制装置的结构示意图，适用于前述图2所示的CPU互连系统，CPU互连系统包括多个节点，多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，CPU互连系统还包括CPU互连装置，CPU互连装置包括：至少一个切换电路，每个切换电路包括两个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，每个切换电路的两个第一端子分别用于连接第一节点内的两个CPU，每个切换电路的两个第二端子分别与第一中间线路的两端连接，或者每个切换电路的两个第二端子分别用于连接第二节点内的两个CPU，参见图11，该装置包括：
获取模块301，用于获取拓扑变化指示信号；
确定模块302，用于根据拓扑变化指示信号确定选通单元的状态，状态包括第一状态和第二状态；
控制模块303，用于当选通单元的状态为第一状态时，控制选通单元的第一端子与第二端子连接，当选通单元的状态为第二状态时，控制第一端子与第二端子断开。
本发明通过获取到的拓扑变化指示信号确定选通单元的状态，状态包括第一状态和第二状态，当选通单元的状态为第一状态时，控制选通单元的第一端子与第二端子连接，当选通单元的状态为第二状态时，控制第一端子与第二端子断开，从而实现根据拓扑变化指示智能化选择CPU间的通路，使得CPU互连系统的拓扑符合当前需求，提高了CPU互连系统中CPU的处理性能。
图12是本发明实施例提供的一种CPU互连控制装置的结构示意图，适用于前文的CPU互连系统，参见图12，该装置包括：
获取模块401，用于获取拓扑变化指示信号；
确定模块402，用于根据拓扑变化指示信号确定选通单元的状态，状态包括第一状态和第二状态；
控制模块403，用于当选通单元的状态为第一状态时，控制选通单元的第一端子与第二端子连接，当选通单元的状态为第二状态时，控制第一端 子与第二端子断开。
进一步地，选通单元还包括第三端子，每个切换电路的两个第二端子分别与第一中间线路的两端连接，每个切换电路的两个第三端子分别用于连接第二节点内的两个CPU，控制模块403，还用于：
当选通单元的状态为第一状态时，控制第一端子与第三端子断开，当选通单元的状态为第二状态时，控制第一端子与第三端子连接。
在一种实现方式中，获取模块401，具体用于：
接收用户输入的拓扑变化指示信号，拓扑变化指示信号包括拓扑变化指示信息，拓扑变化指示信息包括变化后的系统分区CPU数量或变化后的系统应用场景。
在另一种实现方式中，获取模块401，包括：
第一获取子模块4011，用于获取系统监测信息，系统监测信息包括CPU的负载和延迟中的至少一个；
生成子模块4012，用于根据系统监测信息生成拓扑变化指示信号，拓扑变化指示信号包括拓扑变化指示信息，拓扑变化指示信息包括负载过高的CPU和延迟过大的CPU中的至少一个。
在本发明实施例的一种实现方式中，确定模块402，包括：
第二获取子模块4021，用于根据拓扑变化指示信号确定变换后的CPU互连系统的拓扑；
第一确定子模块4022，用于根据变换后的CPU互连系统的拓扑确定选通单元的状态。
在本发明实施例的一种实现方式中，第二获取子模块4021，具体用于：
获取拓扑变化指示信号与拓扑的对应关系；
根据拓扑变化指示信号与拓扑的对应关系，确定变换后的CPU互连系统的拓扑，变换后的CPU互连系统的拓扑与拓扑变化指示信号相对应。
在本发明实施例的另一种实现方式中，第二获取子模块4021，具体用于：
根据拓扑变化指示信号确定拓扑变化，拓扑变化包括连通两CPU之间的线路或者断开两CPU之间的线路；
根据变换前的CPU互连系统的拓扑和拓扑变化，确定变换后的CPU互连系统的拓扑。
其中，变换前的CPU互连系统的拓扑可能是事先获取到的，也可以是确定模块402获取到的。因此，在这种实现方式中，确定模块402还可以包括：第二获取子模块4021，用于获取变换前的CPU互连系统的拓扑。
具体地，第二获取子模块4021，具体用于：
当拓扑变化指示信号包括负载过高的CPU或延迟过大的CPU时，确定负载过高或延迟过大的CPU；
将确定出的CPU与第二节点中的CPU之间的连接，改为与第一节点内的CPU之间的连接，确定出的CPU处于第一节点内。
在本发明实施例中，第二获取子模块4021，具体用于：
确定连接集C1、C2和C3，连接集C1包括两个CPU间的直连连接，连接集C2包括第一中间线路、第二中间线路、CPU与选通单元之间的连接或者CPU与处理单元之间的连接，C3连接集包括伪直连连接，伪直连连接是两CPU通过第一中间线路或第二中间线路建立的连接。
进一步地，第一确定子模块4022，具体用于：
获取变换后的CPU互连系统的拓扑中的连接集C2和C3；
根据连接集C2和C3确定每个选通单元所连通的第一中间线路或者第二中间线路；
根据选通单元所连通的第一中间线路或者第二中间线路确定选通的状态。
关于上述实施例中的装置，其中各个模块执行操作的具体方式已经在有关该方法的实施例中进行了详细描述，此处将不做详细阐述说明。
需要说明的是：上述实施例提供的CPU互连控制装置在进行CPU互连时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的CPU互连控制装置与CPU互连控制方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存 储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (26)

  1. 一种CPU互连装置，其特征在于，包括：至少一个切换电路，每个切换电路包括两个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，当所述选通单元处于第一状态时，所述第一端子与所述第二端子连接，当所述选通单元处于第二状态时，所述第一端子与所述第二端子断开，每个所述切换电路的两个所述第一端子分别用于连接第一节点内的两个CPU，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，或者每个所述切换电路的两个第二端子分别用于连接第二节点内的两个CPU。
  2. 根据权利要求1所述的装置，其特征在于，所述选通单元还包括第三端子，当所述选通单元处于所述第一状态时，所述第一端子与所述第三端子断开，当所述选通单元处于所述第二状态时，所述第一端子与所述第三端子连接，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，每个所述切换电路的两个第三端子分别用于连接所述第二节点内的两个CPU。
  3. 根据权利要求2所述的装置，其特征在于，所述装置包括第二中间线路，所述切换电路的第三端子通过所述第二中间线路与所述第二节点内的CPU所连的切换电路的第三端子连接。
  4. 根据权利要求2所述的装置，其特征在于，所述切换电路的第三端子通过NC中的处理单元与所述第二节点内的CPU所连的切换电路的第三端子连接。
  5. 根据权利要求2所述的装置，其特征在于，所述选通单元为开关电路、电子开关、选通器、选择器或者分配器。
  6. 一种CPU互连系统，包括多个节点，所述多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，其特征在于，所述CPU互连系统还包括如权利要求1-5任一项所述的CPU互连装置。
  7. 一种CPU互连控制方法，适用于CPU互连系统，所述CPU互连系统包括多个节点，所述多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，其特征在于，所述CPU互连系统还包括CPU互连装置，所述CPU互连装置包括：至少一个切换电路，每个切换电路包括两 个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，每个所述切换电路的两个所述第一端子分别用于连接第一节点内的两个CPU，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，或者每个所述切换电路的两个第二端子分别用于连接所述第二节点内的两个CPU，所述方法包括：
    获取拓扑变化指示信号；
    根据所述拓扑变化指示信号确定选通单元的状态，所述状态包括第一状态和第二状态；
    当所述选通单元的状态为所述第一状态时，控制所述选通单元的所述第一端子与所述第二端子连接，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第二端子断开。
  8. 根据权利要求7所述的方法，其特征在于，所述选通单元还包括第三端子，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，每个所述切换电路的两个第三端子分别用于连接所述第二节点内的两个CPU，所述方法还包括：
    当所述选通单元的状态为所述第一状态时，控制所述第一端子与所述第三端子断开，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第三端子连接。
  9. 根据权利要求7或8所述的方法，其特征在于，所述获取拓扑变化指示信号，包括：
    接收用户输入的拓扑变化指示信号，所述拓扑变化指示信号包括所述拓扑变化指示信息，所述拓扑变化指示信息包括变化后的系统分区CPU数量或变化后的系统应用场景，所述系统应用场景为联机分析处理场景或者联机事务处理场景。
  10. 根据权利要求7或8所述的方法，其特征在于，所述获取拓扑变化指示信号，包括：
    获取系统监测信息，所述系统监测信息包括CPU的负载和延迟中的至少一个；
    根据所述系统监测信息生成所述拓扑变化指示信号，所述拓扑变化指示信号包括拓扑变化指示信息，所述拓扑变化指示信息包括负载过高的CPU和延迟过大的CPU中的至少一个。
  11. 根据权利要求7或8所述的方法，其特征在于，所述根据所述拓扑变化指示信号确定选通单元的状态，包括：
    根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑；
    根据变换后的所述CPU互连系统的拓扑确定选通单元的状态。
  12. 根据权利要求11所述的方法，其特征在于，所述根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑，包括：
    获取拓扑变化指示信号与拓扑的对应关系；
    根据所述拓扑变化指示信号与拓扑的对应关系，确定变换后的所述CPU互连系统的拓扑，所述变换后的所述CPU互连系统的拓扑与拓扑变化指示信号相对应。
  13. 根据权利要求11所述的方法，其特征在于，所述根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑，包括：
    根据所述拓扑变化指示信号确定拓扑变化，所述拓扑变化包括连通两CPU之间的线路或者断开两CPU之间的线路；
    根据变换前的所述CPU互连系统的拓扑和所述拓扑变化，确定变换后的所述CPU互连系统的拓扑。
  14. 根据权利要求13所述的方法，其特征在于，所述根据所述拓扑变化指示信号确定拓扑变化，包括：
    当所述拓扑变化指示信号包括负载过高的CPU或延迟过大的CPU时，确定所述负载过高或延迟过大的CPU；
    将确定出的CPU与所述第二节点中的CPU之间的连接，改为与所述第一节点内的CPU之间的连接，所述确定出的CPU处于所述第一节点内。
  15. 根据权利要求12-14任一项所述的方法，其特征在于，所述确定变换后的所述CPU互连系统的拓扑，包括：
    确定连接集C1、C2和C3，所述连接集C1包括两个CPU间的直连连接，所述连接集C2包括第一中间线路、第二中间线路、CPU与选通单元之间的连接或者CPU与处理单元之间的连接，所述C3连接集包括伪直连连接，所述伪直连连接是两CPU通过第一中间线路或第二中间线路建立的连接。
  16. 根据权利要求15所述的方法，其特征在于，所述根据变换后的所述CPU互连系统的拓扑确定选通单元的状态，包括：
    获取变换后的所述CPU互连系统的拓扑中的连接集C2和C3；
    根据所述连接集C2和C3确定每个选通单元所连通的第一中间线路或者第二中间线路；
    根据所述选通单元所连通的第一中间线路或者第二中间线路确定所述选通的状态。
  17. 一种CPU互连控制装置，适用于CPU互连系统，所述CPU互连系统包括多个节点，所述多个节点包括第一节点和第二节点，每个节点包括多个直连连接的CPU，其特征在于，所述CPU互连系统还包括CPU互连装置，所述CPU互连装置包括：至少一个切换电路，每个切换电路包括两个选通单元和一条第一中间线路，每个选通单元包括第一端子和第二端子，每个所述切换电路的两个所述第一端子分别用于连接第一节点内的两个CPU，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，或者每个所述切换电路的两个第二端子分别用于连接所述第二节点内的两个CPU，所述装置包括：
    获取模块，用于获取拓扑变化指示信号；
    确定模块，用于根据所述拓扑变化指示信号确定选通单元的状态，所述状态包括第一状态和第二状态；
    控制模块，用于当所述选通单元的状态为所述第一状态时，控制所述选通单元的所述第一端子与所述第二端子连接，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第二端子断开。
  18. 根据权利要求17所述的装置，其特征在于，所述选通单元还包括第三端子，每个所述切换电路的两个所述第二端子分别与第一中间线路的两端连接，每个所述切换电路的两个第三端子分别用于连接所述第二节点内的两个CPU，所述控制模块，还用于：
    当所述选通单元的状态为所述第一状态时，控制所述第一端子与所述第三端子断开，当所述选通单元的状态为所述第二状态时，控制所述第一端子与所述第三端子连接。
  19. 根据权利要求17或18所述的装置，其特征在于，所述获取模块，具体用于：
    接收用户输入的拓扑变化指示信号，所述拓扑变化指示信号包括所述拓扑变化指示信息，所述拓扑变化指示信息包括变化后的系统分区CPU数 量或变化后的系统应用场景，所述系统应用场景为联机分析处理场景或者联机事务处理场景。
  20. 根据权利要求17或18所述的装置，其特征在于，所述获取模块，包括：
    第一获取子模块，用于获取系统监测信息，所述系统监测信息包括CPU的负载和延迟中的至少一个；
    生成子模块，用于根据所述系统监测信息生成所述拓扑变化指示信号，所述拓扑变化指示信号包括拓扑变化指示信息，所述拓扑变化指示信息包括负载过高的CPU和延迟过大的CPU中的至少一个。
  21. 根据权利要求17或18所述的装置，其特征在于，所述确定模块，包括：
    第二获取子模块，用于根据所述拓扑变化指示信号确定变换后的所述CPU互连系统的拓扑；
    第一确定子模块，用于根据变换后的所述CPU互连系统的拓扑确定选通单元的状态。
  22. 根据权利要求21所述的装置，其特征在于，所述第二获取子模块，具体用于：
    获取拓扑变化指示信号与拓扑的对应关系；
    根据所述拓扑变化指示信号与拓扑的对应关系，确定变换后的所述CPU互连系统的拓扑，所述变换后的所述CPU互连系统的拓扑与拓扑变化指示信号相对应。
  23. 根据权利要求21所述的装置，其特征在于，所述第二获取子模块，具体用于：
    根据所述拓扑变化指示信号确定拓扑变化，所述拓扑变化包括连通两CPU之间的线路或者断开两CPU之间的线路；
    根据变换前的所述CPU互连系统的拓扑和所述拓扑变化，确定变换后的所述CPU互连系统的拓扑。
  24. 根据权利要求23所述的装置，其特征在于，所述第二获取子模块，具体用于：
    当所述拓扑变化指示信号包括负载过高的CPU或延迟过大的CPU时，确定所述负载过高或延迟过大的CPU；
    将确定出的CPU与所述第二节点中的CPU之间的连接，改为与所述第一节点内的CPU之间的连接，所述确定出的CPU处于所述第一节点内。
  25. 根据权利要求22-24任一项所述的装置，其特征在于，所述第二获取子模块，具体用于：
    确定连接集C1、C2和C3，所述连接集C1包括两个CPU间的直连连接，所述连接集C2包括第一中间线路、第二中间线路、CPU与选通单元之间的连接或者CPU与处理单元之间的连接，所述C3连接集包括伪直连连接，所述伪直连连接是两CPU通过第一中间线路或第二中间线路建立的连接。
  26. 根据权利要求25所述的装置，其特征在于，所述第一确定子模块，具体用于：
    获取变换后的所述CPU互连系统的拓扑中的连接集C2和C3；
    根据所述连接集C2和C3确定每个选通单元所连通的第一中间线路或者第二中间线路；
    根据所述选通单元所连通的第一中间线路或者第二中间线路确定所述选通的状态。
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