WO2017016013A1 - 一种栅极驱动电路及液晶显示器 - Google Patents

一种栅极驱动电路及液晶显示器 Download PDF

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Publication number
WO2017016013A1
WO2017016013A1 PCT/CN2015/087819 CN2015087819W WO2017016013A1 WO 2017016013 A1 WO2017016013 A1 WO 2017016013A1 CN 2015087819 W CN2015087819 W CN 2015087819W WO 2017016013 A1 WO2017016013 A1 WO 2017016013A1
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Prior art keywords
sub
gate
field effect
effect transistor
gate driving
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PCT/CN2015/087819
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English (en)
French (fr)
Inventor
张先明
曹丹
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深圳市华星光电技术有限公司
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Priority to US14/787,541 priority Critical patent/US9824657B2/en
Publication of WO2017016013A1 publication Critical patent/WO2017016013A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a gate driving circuit and a liquid crystal display.
  • the display of the liquid crystal display is realized by a driving circuit.
  • the liquid crystal display includes a gate driving circuit, a source driving circuit, and a pixel region.
  • the gate driving circuit generates a gate driving voltage by using a gate pulse modulator (GPM) method, and only one gate driving voltage can be generated in this manner.
  • GPM gate pulse modulator
  • the GPM method cannot generate a plurality of gate driving voltages, which affects the display effect of the liquid crystal display.
  • Embodiments of the present invention provide a gate driving circuit and a liquid crystal display, which can generate a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • a first aspect of the embodiments of the present invention provides a gate driving circuit, including:
  • control circuit comprising at least one sub-control circuit, an input of each of the at least one sub-control circuit being connected to an output of the gate pulse modulator, each of the sub-controls The output of the circuit is connected to a power source;
  • the power source outputs a level signal to each of the sub-control circuits, and each of the sub-control circuits controls the communication between each of the sub-control circuits and the gate pulse modulator according to the level signal to control
  • the gate driving circuit outputs at least one gate driving voltage.
  • each of the sub-control circuits of the at least one sub-control circuit comprises a first voltage dividing resistor and a first field effect transistor.
  • the input end of the first voltage dividing resistor is connected to the output end of the gate pulse modulator, and the output end of the first voltage dividing resistor is connected to the drain of the first field effect transistor.
  • the source of the first field effect transistor is grounded, and the gate of the first field effect transistor is connected to a power source.
  • the first field effect transistor is an N-channel depletion field effect transistor.
  • the first FET when the level signal output by the power source to each of the sub-control circuits is greater than or equal to a conduction threshold of the first FET, the first FET is in an on state, a first voltage dividing resistor connected to the gate pulse modulator; when the level signal output by the power source to each of the sub-control circuits is smaller than a conduction threshold of the first FET, The first field effect transistor is in an off state, and the first voltage dividing resistor is disconnected from the gate pulse modulator.
  • each of the sub-control circuits of the at least one sub-control circuit further comprises a second field effect transistor and a second voltage dividing resistor.
  • the input end of the first voltage dividing resistor is connected to the output end of the gate pulse modulator, and the output end of the first voltage dividing resistor is connected to the drain of the second field effect transistor.
  • a source of the second field effect transistor is grounded, a gate of the second field effect transistor is connected to a drain of the first field effect transistor, and a source of the first field effect transistor is grounded, the first field
  • the gate of the effect transistor is connected to the power source, the output of the second voltage dividing resistor is connected to the drain of the first field effect transistor, and the input of the second voltage dividing resistor is connected to the power source.
  • the first field effect transistor and the second field effect transistor are N-channel depletion field effect transistors.
  • the power source outputs a constant voltage to the second voltage dividing resistor, and the constant voltage is greater than or equal to a conduction threshold of the second field effect transistor.
  • the first FET when the level signal of each of the sub-control circuits is greater than or equal to a conduction threshold of the first FET, the first FET is in an on state, and the second FET In an off state, the first voltage dividing resistor is disconnected from the gate pulse modulator; when the level signal of each of the sub-control circuits is less than a conduction threshold of the first FET, The first field effect transistor is in an off state, the second field effect transistor is in an on state, and the first voltage dividing resistor is in communication with the gate pulse modulator.
  • the power source outputs the same level signal to each of the sub-control circuits.
  • a second aspect of the embodiments of the present invention provides a liquid crystal display comprising the gate driving circuit provided by the first aspect.
  • each sub-control circuit controls the connection between each of the sub-control circuits and the gate pulse modulator according to a level signal of the power supply output to control
  • the gate driving circuit outputs a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another gate driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a circuit diagram of another gate driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display according to an embodiment of the present invention.
  • the gate driving circuit includes a gate pulse modulator 1, a control circuit 2, and a power source 3.
  • the control circuit 2 includes N sub-control circuits, such as sub-control circuit 21, ..., sub-control circuit 2N, etc., wherein N is a positive integer greater than or equal to 1, and each sub-control circuit is connected in the same manner.
  • N is a positive integer greater than or equal to 1
  • the input end of the sub-control circuit 21 is connected to the output of the gate pulse modulator 1, the output of the sub-control circuit 21 is connected to the power supply 3;
  • the power source 3 outputs a level signal to the sub-control circuit 21, and the sub-control circuit 21 controls the communication between the sub-control circuit 21 and the gate pulse modulator 1 according to the level signal to control the
  • the gate drive circuit outputs at least one gate drive voltage.
  • the liquid crystal display includes a gate driving circuit that can generate a gate driving voltage required for the liquid crystal display.
  • the gate driving circuit comprises a gate pulse modulator 1 which is an implementation of a conventional gate driving circuit, and the input is high by the gate pulse modulator 1 The level voltage, which in turn produces a gate drive voltage.
  • a plurality of gate drive voltages can be generated by the control circuit 2 being coupled to the output of the gate pulse modulator 1.
  • each of the sub-control circuits controls the communication between each of the sub-control circuits and the gate pulse modulator 1 according to the level signal of the power output to control the gate drive circuit to output a plurality of gate drives. Voltage.
  • each sub-control circuit controls the connection between each of the sub-control circuits and the gate pulse modulator according to a level signal of the power supply output to control
  • the gate driving circuit outputs a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • the gate driving circuit includes a gate pulse modulator 1, a control circuit 2, and a power source 3.
  • the control circuit 2 includes N sub-control circuits, such as sub-control circuit 21, ..., sub-control circuit 2N, etc., wherein N is a positive integer greater than or equal to 1, and each sub-control circuit includes a first sub-
  • the voltage resistance and the first field effect transistor, such as the sub-control circuit 21, include a first voltage dividing resistor 211 and a first field effect transistor 212, and each of the sub-control circuits is connected in the same manner, and then for the sub-control circuit 21 for a detailed introduction.
  • An input end of the first voltage dividing resistor 211 is connected to an output end of the gate pulse modulator 1 , and an output end of the first voltage dividing resistor 211 is connected to a drain of the first field effect transistor 212 .
  • the source of the first FET 212 is grounded, and the gate of the first FET 212 is connected to the power source 3.
  • the first field effect transistor 212 is an N-channel depletion field effect transistor. Specifically, when the power source 3 When the level signal outputted to the sub-control circuit 21 is greater than or equal to the conduction threshold of the first FET 212, the first FET 212 is in an on state, and the first voltage dividing resistor 211 is The gate pulse modulator 1 is connected; when the level signal output by the power source 3 to the sub-control circuit 21 is smaller than the conduction threshold of the first field effect transistor 212, the first field effect transistor 212 In the off state, the first voltage dividing resistor 211 is disconnected from the gate pulse modulator 1.
  • the liquid crystal display includes a gate driving circuit that can generate a gate driving voltage required for the liquid crystal display.
  • the gate driving circuit comprises a gate pulse modulator 1 which is an implementation of a conventional gate driving circuit, and the input is high by the gate pulse modulator 1
  • the level voltage which in turn produces a gate drive voltage.
  • a plurality of gate drive voltages can be generated by the control circuit 2 being coupled to the output of the gate pulse modulator 1.
  • the level signals output by the power source to each of the sub-control circuits are the same, and the first voltage dividing resistor of each of the sub-control circuits is simultaneously disconnected and connected with the gate pulse modulator 1 to generate two Kind of gate drive voltage.
  • the power source 3 may output different level signals to the N sub-control circuits included in the control circuit, and may control the first voltage dividing resistors in the different sub-control circuits to be disconnected from the gate pulse modulator 1 Opening and connecting, thereby controlling the gate driving circuit to output a plurality of driving voltages.
  • each sub-control circuit controls the connection between each of the sub-control circuits and the gate pulse modulator according to a level signal of the power supply output to control
  • the gate driving circuit outputs a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • FIG. 3 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.
  • the gate driving circuit includes a gate pulse modulator 1 and a control circuit 2.
  • the control circuit 2 includes three sub-control circuits, specifically including: first sub-control circuits MOS1 and R21, second sub-control circuits MOS2 and R22, and third sub-control circuits MOS3 and R23, wherein the MOS1 Both MOS2 and MOS3 are N-channel depletion field effect transistors.
  • the gate pulse modulator 1 is an implementation of a conventional gate driving circuit, and generates a gate driving voltage V13 by inputting a high level voltage V11 to the entire gate pulse modulator 1 and
  • the size of the V13 is determined according to the voltage dividing resistors R11 and R12. Therefore, in the embodiment of the present invention, the gate driving voltage V13 is changed by changing the voltage dividing resistance of the entire gate driving circuit.
  • a common node of R11 and R12 in the gate pulse modulator 1 is selected as an output terminal of the gate pulse modulator 1.
  • the input terminals of R21, R22 and R23 are connected to the common node of R11 and R12, the output of R21 is connected to the D pole of MOS1, the S pole of MOS1 is grounded, and the G pole of MOS1 is connected to V21.
  • the output of R22 is connected to the D pole of MOS2, the S pole of MOS2 is grounded, and the G pole of MOS2 is connected to V22.
  • the output of R23 is connected to the D pole of MOS3, the S pole of MOS3 is grounded, and the G pole of MOS3 is connected to V23.
  • V21, V22, V23 are level signals input to the corresponding FET.
  • the turn-on threshold is in the range of 3V to 6V, assuming that the turn-on threshold of MOS1, MOS2, and MOS3 is 3V.
  • V21 is 3.3V
  • V22 is 0V
  • V23 is 0V
  • MOS1 is turned on
  • MOS2 is turned off
  • MOS3 is turned off, that is, R21 is grounded, and R22 and R23 are turned off. Therefore, R21 is connected to the gate pulse modulator 1.
  • a gate driving voltage V13 can be generated.
  • V21 is 3.3V
  • V22 is 3.3V
  • V23 is 0V
  • MOS1 is turned on
  • MOS2 is turned on
  • MOS3 is turned off, that is, R21 is grounded, R22 is grounded, and R23 is turned off. Therefore, R21 and R22 and the gate pulse are turned off.
  • the modulator 1 is connected to generate a second gate drive voltage V13.
  • the above is only one possible solution, and will not be enumerated here. It can be understood that the gate driving circuit can also set different level signals for V21, V22, V23, thereby generating different gate driving. Voltage V13.
  • each sub-control circuit controls the connection between each of the sub-control circuits and the gate pulse modulator according to a level signal of the power supply output to control
  • the gate driving circuit outputs a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • the gate driving circuit includes a gate pulse modulator 1, a control circuit 2, and a power source 3.
  • the control circuit 2 includes N sub-control circuits, such as sub-control circuit 21, ..., sub-control circuit 2N, etc., wherein N is a positive integer greater than or equal to 1, and each sub-control circuit includes a first sub- a voltage resistor, a first field effect transistor, a second field effect transistor, and a second voltage dividing resistor, such as the sub-control circuit 21, including a first voltage dividing resistor 211, a first field effect transistor 212, a second field effect transistor 213, and Second point
  • the voltage resistors 214 are connected in the same manner for each of the sub-control circuits, and the sub-control circuit 21 will be described in detail next.
  • An input end of the first voltage dividing resistor 211 is connected to an output end of the gate pulse modulator 1 , and an output end of the first voltage dividing resistor 211 is connected to a drain of the second field effect transistor 213 .
  • the source of the second FET 213 is grounded, the gate of the second FET 213 is connected to the drain of the first FET 212, and the source of the first FET 212 is grounded.
  • the gate of the first field effect transistor 212 is connected to the power source 3
  • the output end of the second voltage dividing resistor 214 is connected to the drain of the first field effect transistor 212, and the second voltage dividing resistor 214
  • the input is connected to the power supply 3.
  • the first field effect transistor 212 and the second field effect transistor 213 are N-channel depletion field effect transistors.
  • the power source 3 outputs a constant voltage to the second voltage dividing resistor 214, and the constant voltage is greater than or equal to a conduction threshold of the second field effect transistor 213.
  • the power source 3 outputs a level signal to the sub-control circuit 21, and when the level signal is greater than or equal to the conduction threshold of the first FET 212, the first FET 212 is in a conducting state. At this time, the gate of the second field effect transistor 213 is equivalent to ground, and therefore, the second field effect transistor 213 is in an off state, the first voltage dividing resistor 211 and the gate pulse modulator 1 Disconnected; when the level signal is less than the conduction threshold of the first FET 212, the first FET 212 is in an off state, at which time, the gate of the second FET 213 Corresponding to connecting the constant voltage, since the constant voltage is greater than or equal to the conduction threshold of the second field effect transistor 213, the second field effect transistor 213 is in an on state, and the first voltage dividing resistor 211 is The gate pulse modulator 1 is in communication.
  • the liquid crystal display includes a gate driving circuit that can generate a gate driving voltage required for the liquid crystal display.
  • the gate driving circuit comprises a gate pulse modulator 1 which is an implementation of a conventional gate driving circuit, and the input is high by the gate pulse modulator 1
  • the level voltage which in turn produces a gate drive voltage.
  • a plurality of gate drive voltages can be generated by the control circuit 2 being coupled to the output of the gate pulse modulator 1.
  • the level signals output by the power source to each of the sub-control circuits are the same, and the first voltage dividing resistor of each of the sub-control circuits is simultaneously disconnected and connected with the gate pulse modulator 1 to generate two Kind of gate drive voltage.
  • the power source 3 can output different level signals to the N sub-control circuits included in the control circuit, and can control the first voltage dividing resistor and the different sub-control circuit.
  • the gate pulse modulator 1 is turned off and connected to control the gate drive circuit to output a plurality of driving voltages.
  • each sub-control circuit controls the connection between each of the sub-control circuits and the gate pulse modulator according to a level signal of the power supply output to control
  • the gate driving circuit outputs a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • FIG. 5 a circuit diagram of another gate driving circuit according to an embodiment of the present invention is provided.
  • the gate driving circuit includes a gate pulse modulator 1 and a control circuit 2.
  • the control circuit 2 includes a sub-control circuit, and specifically includes: a first voltage dividing resistor R25, a first field effect transistor MOS4, a second field effect transistor MOS5, and a second voltage dividing resistor R24, wherein the MOS4 MOS5 is an N-channel depletion field effect transistor.
  • the gate pulse modulator 1 is an implementation of a conventional gate driving circuit. By inputting a high level voltage V11 to the entire gate pulse modulator 1, a gate driving voltage V13 is generated, and the V13 is generated. The size is determined based on the voltage dividing resistors R11 and R12. Therefore, in the embodiment of the present invention, the gate driving voltage V13 is changed by changing the voltage dividing resistance of the entire gate driving circuit. A common node of R11 and R12 in the gate pulse modulator 1 is selected as an output terminal of the gate pulse modulator 1.
  • the input of R25 is connected to the common node of R11 and R12, the output of R25 is connected to the D pole of MOS5, the S pole of MOS5 is grounded, the G pole of MOS5 is connected to the D pole of MOS4, the S pole of MOS4 is grounded, MOS4 The G pole is connected to V24, the output of R24 is connected to the D pole of MOS4, and the input of R24 is connected to V25.
  • V24 is a level signal input to MOS4, and V25 is a constant voltage.
  • the turn-on threshold is in the range of 3V to 6V, assuming that the turn-on threshold of MOS4 and MOS5 is 3V and V25 is 3.3V.
  • V24 is 3.3V
  • MOS4 is turned on, that is, R24 is grounded, and the D-pole voltage of MOS4 is 0V, so that MOS5 cannot be turned on, and is in an off state. Therefore, R25 is disconnected from the gate pulse modulator 1 to generate A gate drive voltage is used.
  • V24 is 0V, it is cut off, that is, R24 is disconnected, and the MOS4D pole voltage is 3.3V, which makes MOS5 turn on. Therefore, R25 is in communication with the gate pulse modulator 1 to generate another gate drive voltage. Therefore, the gate driving circuit can set different level signals to V24, thereby generating different gate driving voltages.
  • each sub-control circuit controls the connection between each of the sub-control circuits and the gate pulse modulator according to a level signal of the power supply output to control
  • the gate driving circuit outputs a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display according to an embodiment of the present invention.
  • the liquid crystal display of the embodiment of the present invention may include a gate driving circuit 61, a source driving circuit 62, and a pixel region 63.
  • the gate driving circuit 61 includes a gate pulse modulator 611 and a control circuit 612.
  • the control circuit 622 includes at least one sub-control circuit, and an input end of each of the at least one sub-control circuit is connected to an output end of the gate pulse modulator 611, and each of the sub-control circuits The output is connected to the power supply;
  • the power source outputs a level signal to each of the sub-control circuits, and each of the sub-control circuits controls the communication between each of the sub-control circuits and the gate pulse modulator 611 according to the level signal,
  • the gate drive circuit 61 is controlled to output at least one gate drive voltage.
  • the liquid crystal display includes a gate driving circuit 61 that can generate a gate driving voltage required for the liquid crystal display.
  • the gate driving circuit 61 includes a gate pulse modulator 611, and the gate pulse modulator 611 can generate a gate driving voltage.
  • a plurality of gate drive voltages can be generated by the control circuit 613 being coupled to the output of the gate pulse modulator 611.
  • each of the sub-control circuits controls the communication between each of the sub-control circuits and the gate pulse modulator 611 according to the level signal of the power output to control the gate driving circuit 61 to output a plurality of gates. Drive voltage.
  • each sub-control circuit controls the connection between each of the sub-control circuits and the gate pulse modulator according to a level signal of the power supply output to control
  • the gate driving circuit outputs a plurality of gate driving voltages, thereby improving the display effect of the liquid crystal display.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

一种栅极驱动电路包括栅级脉冲调制器（1）和控制电路（2），控制电路（2）包括至少一个分控制电路（21～2N），至少一个分控制电路（21～2N）中的每一个分控制电路（21～2N）的输入端连接于栅极脉冲调制器（1）的输出端，每一个分控制电路（21～2N）的输出端连接至电源（3）；电源（3）向每一个分控制电路（21～2N）输出电平信号，每一个分控制电路（21～2N）根据电平信号控制每一个分控制电路（21～2N）与栅极脉冲调制器（1）的连通，以控制栅极驱动电路输出至少一个栅极驱动电压。采用该栅极驱动电路的液晶显示器，可产生多种栅极驱动电压，进而提高液晶显示器的显示效果。

Description

一种栅极驱动电路及液晶显示器
本申请要求于2015年7月24日提交中国专利局，申请号为201510444321.5、发明名称为“一种栅极驱动电路及液晶显示器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，尤其涉及一种栅极驱动电路及液晶显示器。
背景技术
目前，液晶显示装置的发展呈现出高集成度、低成本的发展趋势，液晶显示器(Liquid Crystal Display，LCD)的应用已经非常广泛，如电脑、电视等领域。液晶显示器的显示是通过驱动电路实现的。其中，液晶显示器包含栅极驱动电路、源极驱动电路和像素区域。现有的技术方案中，栅极驱动电路采用栅极脉冲调制器(gate pulse modulator，GPM)方式产生栅极驱动电压，并且这种方式只能产生一种栅极驱动电压。然而，对于特殊画面或者3D模式等需要多种栅极驱动电压的情况，GPM方法无法产生多种栅极驱动电压，影响了液晶显示器的显示效果。
发明内容
本发明实施例提供一种栅极驱动电路及液晶显示器，可产生多种栅极驱动电压，进而提高液晶显示器的显示效果。
本发明实施例第一方面提供了一种栅极驱动电路，包括：
控制电路，所述控制电路包括至少一个分控制电路，所述至少一个分控制电路中的每一个分控制电路的输入端连接于所述栅极脉冲调制器的输出端，所述每一个分控制电路的输出端连接至电源；
所述电源向所述每一个分控制电路输出电平信号，所述每一个分控制电路根据所述电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出至少一个栅极驱动电压。
其中，所述至少一个分控制电路的每一个分控制电路包括第一分压电阻和第一场效应管。
其中，所述第一分压电阻的输入端连接于所述栅极脉冲调制器的输出端，所述第一分压电阻的输出端与所述第一场效应管的漏极相连，所述第一场效应管的源极接地，所述第一场效应管的栅极连接至电源。
其中，所述第一场效应管为N沟道耗尽型场效应管。
其中，当所述电源向所述每一个分控制电路输出的所述电平信号大于等于所述第一场效应管的导通阈值时，所述第一场效应管处于导通状态，所述第一分压电阻与所述栅极脉冲调制器连通；当所述电源向所述每一个分控制电路输出的所述电平信号小于所述第一场效应管的导通阈值时，所述第一场效应管处于截止状态，所述第一分压电阻与所述栅极脉冲调制器断开。
其中，所述至少一个分控制电路的每一个分控制电路还包括第二场效应管和第二分压电阻。
其中，所述第一分压电阻的输入端连接于所述栅极脉冲调制器的输出端，所述第一分压电阻的输出端连接于所述第二场效应管的漏极，所述第二场效应管的源极接地，所述第二场效应管的栅极与所述第一场效应管的漏极连接，所述第一场效应管的源极接地，所述第一场效应管的栅极连接至电源，所述第二分压电阻的输出端连接于所述第一场效应管的漏极，所述第二分压电阻的输入端连接至电源。
其中，所述第一场效应管和第二场效应管为N沟道耗尽型场效应管。
其中，所述电源向所述第二分压电阻输出恒定电压，且所述恒定电压大于等于所述第二场效应管的导通阈值。
其中，当所述每一个分控制电路的所述电平信号大于等于所述第一场效应管的导通阈值时，所述第一场效应管处于导通状态，所述第二场效应管处于截止状态，所述第一分压电阻与所述栅极脉冲调制器断开；当所述每一个分控制电路的所述电平信号小于所述第一场效应管的导通阈值时，所述第一场效应管处于截止状态，所述第二场效应管处于导通状态，所述第一分压电阻与所述栅极脉冲调制器连通。
其中，所述电源向所述每一个分控制电路输出的电平信号相同。
本发明实施例第二方面提供了一种液晶显示器，包括第一方面提供的栅极驱动电路。
在本发明实施例中，通过设定多个分控制电路，并且每一个分控制电路根据电源输出的电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出多个栅极驱动电压，提高了液晶显示器的显示效果。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种栅极驱动电路的结构示意图；
图2是本发明实施例提供的另一种栅极驱动电路的结构示意图；
图3是本发明实施例提供的一种栅极驱动电路的电路图；
图4是本发明实施例提供的又一种栅极驱动电路的结构示意图；
图5是本发明实施例提供的另一种栅极驱动电路的电路图；
图6是本发明实施例提供的一种液晶显示器的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1，为本发明实施例提供了一种栅极驱动电路的结构示意图。如图1所示，所述栅极驱动电路包括栅极脉冲调制器1、控制电路2和电源3。其中，所述控制电路2包括N个分控制电路，如分控制电路21、……、分控制电路2N等，其中，N为大于等于1的正整数，且每一个分控制电路的连接方式相同，接下来针对所述分控制电路21进行详细介绍。
所述分控制电路21的输入端连接于所述栅极脉冲调制器1的输出端，所述分控制电路21的输出端连接至电源3；
所述电源3向所述分控制电路21输出电平信号，所述分控制电路21根据所述电平信号控制所述分控制电路21与所述栅极脉冲调制器1的连通，以控制所述栅极驱动电路输出至少一个栅极驱动电压。
需要说明的是，液晶显示器包括栅极驱动电路，所述栅极驱动电路可以产生液晶显示器所需的栅极驱动电压。其中，所述栅级驱动电路包括栅级脉冲调制器1，所述栅极脉冲调制器1是现有的一种栅极驱动电路的实现方式，通过对所述栅极脉冲调制器1输入高电平电压，进而产生一种栅极驱动电压。通过控制电路2与所述栅极脉冲调制器1的输出端连接，可产生多种栅极驱动电压。具体是每一个分控制电路根据电源输出的所述电平信号控制所述每一个分控制电路与所述栅极脉冲调制器1的连通，以控制所述栅极驱动电路输出多个栅极驱动电压。
在本发明实施例中，通过设定多个分控制电路，并且每一个分控制电路根据电源输出的电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出多个栅极驱动电压，提高了液晶显示器的显示效果。
请参见图2，为本发明实施例提供了另一种栅极驱动电路的结构示意图。如图2所示，所述栅极驱动电路包括栅极脉冲调制器1、控制电路2和电源3。其中，所述控制电路2包括N个分控制电路，如分控制电路21、……、分控制电路2N等，其中，N为大于等于1的正整数，且每一个分控制电路包括第一分压电阻和第一场效应管，如所述分控制电路21包括第一分压电阻211和第一场效应管212，且每一个分控制电路的连接方式相同，接下来针对所述分控制电路21进行详细介绍。
所述第一分压电阻211的输入端连接于所述栅极脉冲调制器1的输出端，所述第一分压电阻211的输出端与所述第一场效应管212的漏极相连，所述第一场效应管212的源极接地，所述第一场效应管212的栅极连接至电源3。
所述第一场效应管212为N沟道耗尽型场效应管。具体的，当所述电源3 向所述分控制电路21输出的电平信号大于等于所述第一场效应管212的导通阈值时，所述第一场效应管212处于导通状态，所述第一分压电阻211与所述栅极脉冲调制器1连通；当所述电源3向所述分控制电路21输出的电平信号小于所述第一场效应管212的导通阈值时，所述第一场效应管212处于截止状态，所述第一分压电阻211与所述栅极脉冲调制器1断开。
需要说明的是，液晶显示器包括栅极驱动电路，所述栅极驱动电路可以产生液晶显示器所需的栅极驱动电压。其中，所述栅级驱动电路包括栅级脉冲调制器1，所述栅极脉冲调制器1是现有的一种栅极驱动电路的实现方式，通过对所述栅极脉冲调制器1输入高电平电压，进而产生一种栅极驱动电压。通过控制电路2与所述栅极脉冲调制器1的输出端连接，可产生多种栅极驱动电压。具体的，所述电源向所述每一个分控制电路输出的电平信号相同，每一个分控制电路的第一分压电阻同时与所述栅极脉冲调制器1断开和连通，进行产生两种栅极驱动电压。或者，所述电源3可以向所述控制电路所包括的N个分控制电路输出不同的电平信号，可以控制不同分控制电路中的第一分压电阻与所述栅极脉冲调制器1断开和连通，进而控制所述栅极驱动电路输出多个驱动电压。
在本发明实施例中，通过设定多个分控制电路，并且每一个分控制电路根据电源输出的电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出多个栅极驱动电压，提高了液晶显示器的显示效果。
请参见图3，为本发明实施例提供了一种栅极驱动电路的电路图。如图3所示，是针对图2所示的栅极驱动电路的结构示意图所提供的一种栅极驱动电路的电路图。所述栅极驱动电路包括栅极脉冲调制器1、控制电路2。其中，所述控制电路2包括3个分控制电路，具体包括：第一分控制电路MOS1和R21、第二分控制电路MOS2和R22、第三分控制电路MOS3和R23，其中，所述MOS1、MOS2、MOS3均为N沟道耗尽型场效应管。
所述栅极脉冲调制器1是现有的一种栅极驱动电路的实现方式，通过对整个栅极脉冲调制器1输入高电平电压V11，进而产生栅极驱动电压V13，并且 所述V13的大小是根据所述分压电阻R11和R12所确定的。因此本发明实施例中采用通过改变整个栅极驱动电路的分压电阻进而改变栅极驱动电压V13。选择所述栅极脉冲调制器1中R11和R12的公共节点作为所述栅极脉冲调制器1的输出端。
R21、R22和R23的输入端连接于R11和R12的公共节点，R21的输出端与MOS1的D极相连，MOS1的S极接地，MOS1的G极连接至V21。R22的输出端与MOS2的D极相连，MOS2的S极接地，MOS2的G极连接至V22。R23的输出端与MOS3的D极相连，MOS3的S极接地，MOS3的G极连接至V23。其中，V21、V22、V23是对相应的场效应管所输入的电平信号。
标准的N沟道MOS管，导通阈值在3V～6V范围之内，假设MOS1、MOS2、MOS3的导通阈值为3V。当V21为3.3V、V22为0V、V23为0V时，则MOS1导通、MOS2截止和MOS3截止，即R21接地、R22和R23断开，因此，R21与所述栅极脉冲调制器1连通，可以产生一种栅极驱动电压V13。当V21为3.3V、V22为3.3V、V23为0V时，则MOS1导通、MOS2导通和MOS3截止，即R21接地、R22接地、R23断开，因此，R21和R22与所述栅极脉冲调制器1连通，可以产生第二种栅极驱动电压V13。以上仅为一种可行的方案，在此不再枚举，可以理解的是，所述栅极驱动电路还可以对V21、V22、V23设定不同的电平信号，进而产生不同的栅极驱动电压V13。
在本发明实施例中，通过设定多个分控制电路，并且每一个分控制电路根据电源输出的电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出多个栅极驱动电压，提高了液晶显示器的显示效果。
请参见图4，为本发明实施例提供了另一种栅极驱动电路的结构示意图。如图2所示，所述栅极驱动电路包括栅极脉冲调制器1、控制电路2和电源3。其中，所述控制电路2包括N个分控制电路，如分控制电路21、……、分控制电路2N等，其中，N为大于等于1的正整数，且每一个分控制电路包括第一分压电阻、第一场效应管、第二场效应管和第二分压电阻，如所述分控制电路21包括第一分压电阻211、第一场效应管212、第二场效应管213和第二分 压电阻214，且每一个分控制电路的连接方式相同，接下来针对所述分控制电路21进行详细介绍。
所述第一分压电阻211的输入端连接于所述栅极脉冲调制器1的输出端，所述第一分压电阻211的输出端连接于所述第二场效应管213的漏极，所述第二场效应管213的源极接地，所述第二场效应管213的栅极与所述第一场效应管212的漏极连接，所述第一场效应管212的源极接地，所述第一场效应管212的栅极连接至电源3，所述第二分压电阻214的输出端连接于所述第一场效应管212的漏极，所述第二分压电阻214的输入端连接至电源3。
所述第一场效应管212和第二场效应管213为N沟道耗尽型场效应管。所述电源3向所述第二分压电阻214输出恒定电压，且所述恒定电压大于等于所述第二场效应管213的导通阈值。
所述电源3向所述分控制电路21输出电平信号，当所述电平信号大于等于所述第一场效应管212的导通阈值时，所述第一场效应管212处于导通状态，这时，所述第二场效应管213的栅极相当于接地，因此，所述第二场效应管213处于截止状态，所述第一分压电阻211与所述栅极脉冲调制器1断开；当所述电平信号小于所述第一场效应管212的导通阈值时，所述第一场效应管212处于截止状态，这时，所述第二场效应管213的栅极相当于连接所述恒定电压，由于所述恒定电压大于等于所述第二场效应管213的导通阈值，所述第二场效应管213处于导通状态，所述第一分压电阻211与所述栅极脉冲调制器1连通。
需要说明的是，液晶显示器包括栅极驱动电路，所述栅极驱动电路可以产生液晶显示器所需的栅极驱动电压。其中，所述栅级驱动电路包括栅级脉冲调制器1，所述栅极脉冲调制器1是现有的一种栅极驱动电路的实现方式，通过对所述栅极脉冲调制器1输入高电平电压，进而产生一种栅极驱动电压。通过控制电路2与所述栅极脉冲调制器1的输出端连接，可产生多种栅极驱动电压。具体的，所述电源向所述每一个分控制电路输出的电平信号相同，每一个分控制电路的第一分压电阻同时与所述栅极脉冲调制器1断开和连通，进行产生两种栅极驱动电压。或者，所述电源3可以向所述控制电路所包括的N个分控制电路输出不同的电平信号，可以控制不同分控制电路中的第一分压电阻与所 述栅极脉冲调制器1断开和连通，进而控制所述栅极驱动电路输出多个驱动电压。
在本发明实施例中，通过设定多个分控制电路，并且每一个分控制电路根据电源输出的电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出多个栅极驱动电压，提高了液晶显示器的显示效果。
请参见图5，为本发明实施例提供了另一种栅极驱动电路的电路图。如图5所示，是针对图4所示的栅极驱动电路的结构示意图所提供的一种栅极驱动电路的电路图。所述栅极驱动电路包括栅极脉冲调制器1、控制电路2。其中，所述控制电路2包括1个分控制电路，具体包括：第一分压电阻R25、第一场效应管MOS4、第二场效应管MOS5、第二分压电阻R24，其中，所述MOS4、MOS5均为N沟道耗尽型场效应管。
所述栅极脉冲调制器1是现有的一种栅极驱动电路的实现方式，通过对整个栅极脉冲调制器1输入高电平电压V11，进而产生栅极驱动电压V13，并且所述V13的大小是根据所述分压电阻R11和R12所确定的。因此本发明实施例中采用通过改变整个栅极驱动电路的分压电阻进而改变栅极驱动电压V13。选择所述栅极脉冲调制器1中R11和R12的公共节点作为所述栅极脉冲调制器1的输出端。
R25的输入端连接于R11和R12的公共节点，R25的输出端与MOS5的D极相连，MOS5的S极接地，MOS5的G极连接至MOS4的D极相连，MOS4的S极接地，MOS4的G极连接至V24，R24的输出端连接于MOS4的D极，R24的输入端连接至V25。其中，V24是对MOS4输入的电平信号，V25是恒定电压。
标准的N沟道MOS管，导通阈值在3V～6V范围之内，假设MOS4、MOS5的导通阈值为3V，V25为3.3V时。当V24为3.3V时，则MOS4导通，即R24接地，MOS4的D极电压为0V，使得MOS5无法导通，处于截止状态，因此，R25与所述栅极脉冲调制器1断开，产生了一种栅极驱动电压。当V24为0V时，则截止，即R24断开，MOS4D极电压为3.3V，使得MOS5导通， 因此，R25与所述栅极脉冲调制器1连通，产生了另一种栅极驱动电压。因此，所述栅极驱动电路可以对V24设定不同的电平信号，进而产生不同的栅极驱动电压。
在本发明实施例中，通过设定多个分控制电路，并且每一个分控制电路根据电源输出的电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出多个栅极驱动电压，提高了液晶显示器的显示效果。
请参见图6，为本发明实施例提供了一种液晶显示器的结构示意图。如图6所示，本发明实施例的所述液晶显示器可以包括：栅极驱动电路61、源极驱动电路62和像素区域63。其中，所述栅极驱动电路61包括栅极脉冲调制器611和控制电路612。
所述控制电路622包括至少一个分控制电路，所述至少一个分控制电路中的每一个分控制电路的输入端连接于所述栅极脉冲调制器611的输出端，所述每一个分控制电路的输出端连接至电源；
所述电源向所述每一个分控制电路输出电平信号，所述每一个分控制电路根据所述电平信号控制所述每一个分控制电路与所述栅极脉冲调制器611的连通，以控制所述栅极驱动电路61输出至少一个栅极驱动电压。
需要说明的是，液晶显示器包括栅极驱动电路61，所述栅极驱动电路61可以产生液晶显示器所需的栅极驱动电压。其中，所述栅级驱动电路61包括栅级脉冲调制器611，所述栅极脉冲调制器611可产生一种栅极驱动电压。通过控制电路613与所述栅极脉冲调制器611的输出端连接，可产生多种栅极驱动电压。具体是每一个分控制电路根据电源输出的所述电平信号控制所述每一个分控制电路与所述栅极脉冲调制器611的连通，以控制所述栅极驱动电路61输出多个栅极驱动电压。
在本发明实施例中，通过设定多个分控制电路，并且每一个分控制电路根据电源输出的电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出多个栅极驱动电压，提高了液晶显示器的显示效果。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种栅极驱动电路，应用于液晶显示器，所述栅极驱动电路包括栅级脉冲调制器，其特征在于：
    所述栅极驱动电路还包括控制电路，所述控制电路包括至少一个分控制电路，所述至少一个分控制电路中的每一个分控制电路的输入端连接于所述栅极脉冲调制器的输出端，所述每一个分控制电路的输出端连接至电源；
    所述电源向所述每一个分控制电路输出电平信号，所述每一个分控制电路根据所述电平信号控制所述每一个分控制电路与所述栅极脉冲调制器的连通，以控制所述栅极驱动电路输出至少一个栅极驱动电压。
  2. 根据权利要求1所述的栅极驱动电路，其特征在于，所述至少一个分控制电路的每一个分控制电路包括第一分压电阻和第一场效应管。
  3. 根据权利要求2所述的栅极驱动电路，其特征在于，所述第一分压电阻的输入端连接于所述栅极脉冲调制器的输出端，所述第一分压电阻的输出端与所述第一场效应管的漏极相连，所述第一场效应管的源极接地，所述第一场效应管的栅极连接至电源。
  4. 根据权利要求3所述的栅极驱动电路，其特征在于，所述第一场效应管为N沟道耗尽型场效应管。
    其中，当所述电源向所述每一个分控制电路输出的所述电平信号大于等于所述第一场效应管的导通阈值时，所述第一场效应管处于导通状态，所述第一分压电阻与所述栅极脉冲调制器连通；当所述电源向所述每一个分控制电路输出的所述电平信号小于所述第一场效应管的导通阈值时，所述第一场效应管处于截止状态，所述第一分压电阻与所述栅极脉冲调制器断开。
  5. 根据权利要求2所述的栅极驱动电路，其特征在于，所述至少一个分控制电路的每一个分控制电路还包括第二场效应管和第二分压电阻。
  6. 根据权利要求5所述的栅极驱动电路，其特征在于，所述第一分压电阻的输入端连接于所述栅极脉冲调制器的输出端，所述第一分压电阻的输出端连接于所述第二场效应管的漏极，所述第二场效应管的源极接地，所述第二场效应管的栅极与所述第一场效应管的漏极连接，所述第一场效应管的源极接地，所述第一场效应管的栅极连接至电源，所述第二分压电阻的输出端连接于所述第一场效应管的漏极，所述第二分压电阻的输入端连接至电源。
  7. 根据权利要求6所述的栅极驱动电路，其特征在于，所述第一场效应管和第二场效应管为N沟道耗尽型场效应管。
  8. 根据权利要求7所述的栅极驱动电路，其特征在于，所述电源向所述第二分压电阻输出恒定电压，且所述恒定电压大于等于所述第二场效应管的导通阈值。
    其中，当所述每一个分控制电路的所述电平信号大于等于所述第一场效应管的导通阈值时，所述第一场效应管处于导通状态，所述第二场效应管处于截止状态，所述第一分压电阻与所述栅极脉冲调制器断开；当所述每一个分控制电路的所述电平信号小于所述第一场效应管的导通阈值时，所述第一场效应管处于截止状态，所述第二场效应管处于导通状态，所述第一分压电阻与所述栅极脉冲调制器连通。
  9. 根据权利要求1-8任一项所述的栅极驱动电路，其特征在于，所述电源向所述每一个分控制电路输出的电平信号相同。
  10. 一种液晶显示器，其特征在于：所述液晶显示器包括上述1-9任意一项所述的栅极驱动电路。
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