WO2017028347A1 - 驱动电路以及液晶显示装置 - Google Patents

驱动电路以及液晶显示装置 Download PDF

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Publication number
WO2017028347A1
WO2017028347A1 PCT/CN2015/089263 CN2015089263W WO2017028347A1 WO 2017028347 A1 WO2017028347 A1 WO 2017028347A1 CN 2015089263 W CN2015089263 W CN 2015089263W WO 2017028347 A1 WO2017028347 A1 WO 2017028347A1
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Prior art keywords
diode
voltage
capacitor
fet
input
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PCT/CN2015/089263
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English (en)
French (fr)
Inventor
张先明
曹丹
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深圳市华星光电技术有限公司
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Priority to US14/905,805 priority Critical patent/US10115367B2/en
Publication of WO2017028347A1 publication Critical patent/WO2017028347A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a driving circuit and a liquid crystal display device.
  • the prior art provides a driving circuit including a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a first capacitor C1.
  • the anode of the first diode D1 is used for the input voltage VAA
  • the cathode of the first diode D1 is connected to the anode of the second diode D2
  • the cathode of the second diode D2 is connected to the cathode of the third diode D3.
  • the anode, the cathode of the third diode D3 is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is used for outputting the voltage VGH, and the first end of the first capacitor C1 is connected to the first diode D1 and a common end of the second diode D2, the second end of the first capacitor C1 is connected to the first end of the input voltage source V1, the second end of the input voltage source V1 is grounded, and the first end of the second capacitor C2 is connected to the second second a common end of the diode D2 and the third diode D3, the second end of the second capacitor C2 is grounded, and the first end of the third capacitor C3 is connected to the common end of the third diode D3 and the fourth diode D4, The second end of the third capacitor C3 is connected to the first end of the input voltage source V1, the first end of the fourth capacitor C4 is connected to the cathode of the fourth diode D4, and the second end
  • a technical problem to be solved by embodiments of the present invention is to provide a driving circuit and a liquid crystal display device capable of providing various output voltages.
  • the present invention provides a driving circuit including: a first diode, a second diode, a third diode, a fourth diode, a first capacitor, a second capacitor, and an adjustable voltage source, wherein
  • the adjustable voltage source includes a plurality of field effect transistors, an anode of the first diode is used for inputting a voltage, and a cathode of the first diode is connected to an anode of the second diode, the first a cathode of the diode is connected to the anode of the third diode, a cathode of the third diode is connected to an anode of the fourth diode, and a cathode of the fourth diode is used for output voltage a first end of the first capacitor is connected to a common end of the first diode and the second diode, and a second end of the first capacitor is connected to an output end of the adjustable voltage source,
  • the selected end of the adjustable voltage source is used to input
  • the adjustable voltage source includes a first FET, a second FET, and a third FET three FETs, and the gate of the first FET is used to input the first voltage a drain of the first FET is connected to a common end of the second end of the first capacitor and a second end of the second capacitor, and a source of the first FET is used to input a first selection a voltage, a gate of the second field effect transistor is used to input a second voltage, and a drain of the second field effect transistor is connected to a common end of the second end of the first capacitor and the second end of the second capacitor End, the source of the second FET is used to input a second selection voltage, the gate of the third FET is used to input a third voltage, and the drain of the third FET is connected to the A common end of the second end of the first capacitor and the second end of the second capacitor, the source of the third FET is used to input a third selection voltage.
  • the output voltage is 16 volts
  • the second selection voltage is a 3.3 volt Buck line voltage in a pulse width modulation chip.
  • the output voltage is 12 volts and the third selection voltage is a 1.2 volt Buck line voltage in a pulse width modulation chip, which is 3.3 volts.
  • the present invention provides a driving circuit including: a first diode, a second diode, a third diode, a fourth diode, a first capacitor, a second capacitor, and an adjustable voltage source, wherein An anode of the first diode is used for inputting a voltage, a cathode of the first diode is connected to an anode of the second diode, and a cathode of the second diode is connected to the third diode An anode of the tube, a cathode of the third diode is connected to an anode of the fourth diode, a cathode of the fourth diode is used for outputting a voltage, and a first end of the first capacitor is connected to the anode a common end of the first diode and the second diode, the first capacitor The second end is connected to the output end of the adjustable voltage source, and the selected end of the adjustable voltage source is used to input a selection voltage; when the input voltage is constant, the
  • the adjustable voltage source comprises a plurality of field effect transistors.
  • the adjustable voltage source includes a first FET, a second FET, and a third FET three FETs, and the gate of the first FET is used to input the first voltage a drain of the first FET is connected to a common end of the second end of the first capacitor and a second end of the second capacitor, and a source of the first FET is used to input a first selection a voltage, a gate of the second field effect transistor is used to input a second voltage, and a drain of the second field effect transistor is connected to a common end of the second end of the first capacitor and the second end of the second capacitor End, the source of the second FET is used to input a second selection voltage, the gate of the third FET is used to input a third voltage, and the drain of the third FET is connected to the A common end of the second end of the first capacitor and the second end of the second capacitor, the source of the third FET is used to input a third selection voltage.
  • the output voltage is 16 volts
  • the second selection voltage is a 3.3 volt Buck line voltage in a pulse width modulation chip.
  • the output voltage is 12 volts and the third selection voltage is a 1.2 volt Buck line voltage in a pulse width modulation chip, which is 3.3 volts.
  • the first capacitor and the second capacitor are both non-adjustable capacitors.
  • the present invention also provides a liquid crystal display panel, the liquid crystal display panel including a driving circuit, the driving circuit comprising: a first diode, a second diode, a third diode, a fourth diode, a first capacitor, a second capacitor, and an adjustable voltage source, wherein an anode of the first diode is used for inputting a voltage, and a cathode of the first diode is connected to an anode of the second diode a cathode of the second diode is connected to an anode of the third diode, a cathode of the third diode is connected to an anode of the fourth diode, and a cathode of the fourth diode is used for An output voltage, a first end of the first capacitor is connected to a common end of the first diode and the second diode, and a second end of the first capacitor is connected to an output of the adjustable voltage source The selected end of the adjustable voltage source is used to input a selection
  • the adjustable voltage source comprises a plurality of field effect transistors.
  • the adjustable voltage source includes a first FET, a second FET, and a third FET three FETs, and the gate of the first FET is used to input the first voltage
  • the first game a drain of the effect transistor is connected to a common end of the second end of the first capacitor and a second end of the second capacitor, a source of the first field effect transistor is used to input a first selection voltage, and the second a gate of the FET is used to input a second voltage, and a drain of the second FET is connected to a common end of the second end of the first capacitor and the second end of the second capacitor, the second a source of the FET is used to input a second selection voltage, a gate of the third FET is used to input a third voltage, and a drain of the third FET is connected to a second of the first capacitor And a common end of the second end of the second capacitor, the source of the third field effect transistor is used to input a third selection voltage.
  • the output voltage is 16 volts
  • the second selection voltage is a 3.3 volt Buck line voltage in a pulse width modulation chip.
  • the output voltage is 12 volts and the third selection voltage is a 1.2 volt Buck line voltage in a pulse width modulation chip, which is 3.3 volts.
  • the first capacitor and the second capacitor are both non-adjustable capacitors.
  • different voltages can be input through the adjustable voltage source, so that the output terminals can provide different output voltages to meet various user requirements.
  • different drive currents can be provided by adjusting the voltage. When a large current drive is required, the output voltage can be lowered, thereby improving the current drive capability.
  • FIG. 1 is a circuit diagram of an embodiment of a prior art driving circuit
  • FIG. 2 is a circuit diagram of an embodiment of a driving circuit of the present invention.
  • FIG. 3 is a circuit diagram of another embodiment of a drive circuit of the present invention.
  • FIG. 2 is a circuit diagram of an embodiment of a driving circuit of the present invention.
  • the driving circuit of this embodiment includes: a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first capacitor C1, a second capacitor C2, and an adjustable voltage source.
  • the anode of the first diode D1 is used for the input voltage
  • the cathode of the first diode D1 is connected to the anode of the second diode D2
  • the cathode of the second diode D2 is connected to the anode of the third diode D3.
  • the cathode of the third diode D3 is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is used for output voltage, and the first end of the first capacitor C1 is connected to the first diode D1 and the second At the common end of the diode D2, the second end of the first capacitor C1 is connected to the output end of the adjustable voltage source Vi, and the selected end of the adjustable voltage source Vi is used to input the selection voltage.
  • the adjustable voltage source Vi outputs a pulse width adjustment voltage having a different duty ratio.
  • the adjustable voltage source Vi is at a low level.
  • the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are all turned on.
  • the voltages V D1 , V D2 , V D3 , and V D4 output from one diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are both VAA.
  • the adjustable voltage source Vi is at a high level, the first diode D1 is turned off, and the second diode D2, the third diode D3, and the fourth diode D4 are both turned on, the first two The voltages V D1 , V D2 , V D3 , and V D4 output from the pole tube D1, the second diode D2, the third diode D3, and the fourth diode D4 are all Vi+VAA.
  • the adjustable voltage source Vi is at a low level.
  • the first diode D1 and the third diode D3 are turned on, and the second diode D2 and the fourth diode D4 are turned off.
  • the voltage V D1 of the output of one diode D1 is VAA
  • the voltages V D2 , V D3 , V D4 output by the second diode D2, the third diode D3 and the fourth diode D4 are all Vi+VAA .
  • the adjustable voltage source Vi is at a high level.
  • the first diode D1 and the third diode D3 are turned off, and the second diode D2 and the fourth diode D4 are turned on.
  • the voltage V D1 of the output of one diode D1 is Vi+VAA
  • the voltage V D2 of the output of the second diode D2 is Vi+VAA
  • the voltage V output by the third diode D3 and the fourth diode D4 D3 and V D4 are both 2Vi+VAA.
  • different voltages can be input through the adjustable voltage source, so that the output terminals can provide different output voltages to meet various user requirements.
  • different drive currents can be provided by adjusting the voltage. When a large current drive is required, the output voltage can be lowered, thereby improving the current drive capability.
  • FIG. 3 is a circuit diagram of another embodiment of the driving circuit of the present invention.
  • the driving circuit of this embodiment includes: a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first capacitor C1, a second capacitor C2, and a first field effect.
  • the first capacitor C1 and the second capacitor C2 are both adjustable capacitors.
  • the anode of the first diode D1 is used for input voltage
  • the cathode of the first diode D1 is connected to the anode of the second diode D2
  • the cathode of the second diode D2 is connected to the anode of the third diode D3
  • the cathode of the third diode D3 is connected to the anode of the fourth diode D4
  • the cathode of the fourth diode D4 is used for output voltage
  • the first end of the first capacitor C1 is connected to the first diode D1 and the second diode
  • the first end of the second capacitor C2 is connected to the common end of the third diode D3 and the fourth diode D4, and the second end of the first capacitor C1 is connected to the second end of the second capacitor C2.
  • the gate of the first field effect transistor M1 is used to input a first voltage, and the drain d1 of the first field effect transistor M1 is connected to the common end of the second end of the first capacitor C1 and the second end of the second capacitor C2, the first field The source s1 of the effect transistor M1 is used to input the first selection voltage LX1, the gate g2 of the second FET M2 is used to input the second voltage, and the drain d2 of the second FET M2 is connected to the first capacitor C1.
  • the drain d3 of the third field effect transistor M3 is connected to the second end of the first capacitor C1 and The common end of the second end of the second capacitor C2, the source s3 of the third field effect transistor M3 is used to input the third selection voltage LX3.
  • the first selection voltage LX1, the second selection voltage LX2, and the third selection voltage LX3 are pulse width adjustment voltages having different duty ratios.
  • the first selection voltage LX1 is at a low level, and at this time, the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are both turned on,
  • the voltages VD1, VD2, VD3, and VD4 output from one diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are all VAA.
  • the first selection voltage LX1 is at a high level, the first diode D1 is turned off, and the second diode D2, the third diode D3, and the fourth diode D4 are both turned on, the first two The voltages VD1, VD2, VD3, and VD4 output from the pole tube D1, the second diode D2, the third diode D3, and the fourth diode D4 are both LX1+VAA.
  • the first selection voltage LX1 is at a low level.
  • the first diode D1 and the third diode D3 are turned on, and the second diode D2 and the fourth diode D4 are turned off.
  • the voltage VD1 of the output of one diode D1 is VAA
  • the voltages VD2, VD3, and VD4 output by the second diode D2, the third diode D3, and the fourth diode D4 are both LX1+VAA.
  • the first selection voltage LX1 is at a high level.
  • the first diode D1 and the third diode D3 are turned off, and the second diode D2 and the fourth diode D4 are turned on.
  • the voltage VD1 of the output of one diode D1 is Vi+VAA
  • the voltage VD2 of the output of the second diode D2 is LX1+VAA
  • the second selection voltage LX2 is at a low level, at this time, the first diode D1, the second The diode D2, the third diode D3, and the fourth diode D4 are both turned on, and the voltages output by the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 VD1, VD2, VD3, and VD4 are all VAA.
  • the second selection voltage LX2 is at a high level, the first diode D1 is turned off, and the second diode D2, the third diode D3, and the fourth diode D4 are both turned on, the first two The voltages VD1, VD2, VD3, and VD4 output from the pole tube D1, the second diode D2, the third diode D3, and the fourth diode D4 are all LX2+VAA.
  • the second selection voltage LX2 is at a low level.
  • the first diode D1 and the third diode D3 are turned on, and the second diode D2 and the fourth diode D4 are turned off.
  • the voltage VD1 of the output of one diode D1 is VAA
  • the voltages VD2, VD3, and VD4 output by the second diode D2, the third diode D3, and the fourth diode D4 are both LX2+VAA.
  • the second selection voltage LX2 is at a high level.
  • the first diode D1 and the third diode D3 are turned off, and the second diode D2 and the fourth diode D4 are turned on.
  • the voltage VD1 of the output of one diode D1 is Vi+VAA
  • the voltage VD2 of the output of the second diode D2 is LX2+VAA
  • the third selection voltage LX3 is at a low level.
  • the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are both turned on.
  • the voltages VD1, VD2, VD3, and VD4 output from one diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are all VAA.
  • the third selection voltage LX3 is at a high level, the first diode D1 is turned off, and the second diode D2, the third diode D3, and the fourth diode D4 are both turned on, the first two The voltages VD1, VD2, VD3, and VD4 output from the pole tube D1, the second diode D2, the third diode D3, and the fourth diode D4 are both LX3+VAA.
  • the third selection voltage LX3 is at a low level, at this time, the first diode D1 and the first The three diodes D3 are turned on, the second diode D2 and the fourth diode D4 are turned off, and the voltage VD1 of the output of the first diode D1 is VAA, the second diode D2, the third diode D3, and the The voltages VD2, VD3, and VD4 output by the four diodes D4 are both LX3+VAA.
  • the third selection voltage LX3 is at a high level.
  • the first diode D1 and the third diode D3 are turned off, and the second diode D2 and the fourth diode D4 are turned on.
  • the voltage VD1 of the output of one diode D1 is LX3+VAA
  • the voltage VD2 of the output of the second diode D2 is LX3+VAA
  • the output voltage VGH when the first selection voltage LX1 is the BOOST voltage in the pulse width modulation chip, the output voltage VGH is 16 volts, and the second selection voltage LX2 is the 3.3 volt Buck line voltage in the pulse width modulation chip.
  • the output voltage VGH is 12 volts, and when the third selection voltage LX3 is a 1.2 volt Buck line voltage in the pulse width modulation chip, the output voltage VGH is 3.3 volts.
  • different voltages can be input through the adjustable voltage source, so that the output terminals can provide different output voltages to meet various user requirements.
  • different drive currents can be provided by adjusting the voltage. When a large current drive is required, the output voltage can be lowered, thereby improving the current drive capability.
  • the present invention also provides a liquid crystal display panel, which includes the driving circuit as shown in FIG. 2 and FIG. 3 .
  • a liquid crystal display panel which includes the driving circuit as shown in FIG. 2 and FIG. 3 .
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

Abstract

一种驱动电路以及液晶显示装置，所述驱动电路包括：第一二极管（D1）、第二二极管（D2）、第三二极管（D3）、第四二极管（D4）、第一电容（C1）、第二电容（C2）以及可调电压源（Vi），其中，第一二极管（D1）的阳极用于输入电压（VAA），第一二极管（D1）的阴极连接第二二极管（D2）的阳极，第二二极管（D2）的阴极连接第三二极管（D3）的阳极，第三二极管（D3）的阴极连接第四二极管（D4）的阳极，第四二极管（D4）的阴极用于输出电压（VGH），第一电容（C1）的第一端连接第一二极管（D1）与第二二极管（D2）的公共端，第一电容（C1）的第二端连接可调电压源（Vi）的输出端，可调电压源（Vi）的选择端用于输入选择电压（LX1，LX2，LX3）；在输入电压（VAA）不变时，所述选择电压（LX1，LX2，LX3）不同，输出电压（VGH）不同。上述方法能够提供多种输出电压（VGH），满足用户的使用要求。

Description

驱动电路以及液晶显示装置
本发明要求2015年08月19日递交的发明名称为“驱动电路以及液晶显示装置”的申请号201510511114.7的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种驱动电路以及液晶显示装置。
背景技术
如图1所示，现有技术提供了一种驱动电路，包括第一二极管D1、第二二极管D2、第三二极管D3、第四二极管D4、第一电容C1、第二电容C2、第三电容C3、第四电容C4以及输入电压源V1。其中，第一二极管D1的阳极用于输入电压VAA，第一二极管D1的阴极连接第二二极管D2的阳极，第二二极管D2的阴极连接第三二极管D3的阳极，第三二极管D3的阴极连接第四二极管D4的阳极，第四二极管D4的阴极用于输出电压VGH，第一电容C1的第一端连接第一二极管D1与第二二极管D2的公共端，第一电容C1的第二端连接输入电压源V1的第一端，输入电压源V1的第二端接地，第二电容C2的第一端连接第二二极管D2与第三二极管D3的公共端，第二电容C2的第二端接地，第三电容C3的第一端连接第三二极管D3与第四二极管D4的公共端，第三电容C3的第二端连接输入电压源V1的第一端，第四电容C4的第一端连接第四二极管D4的阴极，第四电容C4的第二端接地。
在理想状态下，输入电压VAA与输出电压VGH之间的关系为：VGHF＝VAA+2*V1，可以知道，输出电压VGH是固定的，不能满足使用的要求。
发明内容
本发明实施例所要解决的技术问题在于，提供一种驱动电路以及液晶显示装置，能够提供多种输出电压。
本发明提供了一种驱动电路，包括：第一二极管、第二二极管、第三二极管、第四二极管、第一电容、第二电容以及可调电压源，其中，所述可调电压源包括多个场效应管，所述第一二极管的阳极用于输入电压，所述第一二极管的阴极连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第四二极管的阳极，所述第四二极管的阴极用于输出电压，所述第一电容的第一端连接所述第一二极管与所述第二二极管的公共端，所述第一电容的第二端连接所述可调电压源的输出端，所述可调电压源的选择端用于输入选择电压；在所述输入电压不变时，所述选择电压不同，所述输出电压不同，其中，所述第一电容以及所述第二电容均是不可调电容。
可选地，所述可调电压源包括第一场效应管、第二场效应管以及第三场效应管三个场效应管，所述第一场效应管的栅极用于输入第一电压，所述第一场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第一场效应管的源极用于输入第一选择电压，所述第二场效应管的栅极用于输入第二电压，所述第二场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第二场效应管的源极用于输入第二选择电压，所述第三场效应管的栅极用于输入第三电压，所述第三场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第三场效应管的源极用于输入第三选择电压。
可选地，所述第一选择电压为脉冲宽度调制芯片中BOOST电压时，所述输出电压为16伏，所述第二选择电压为脉冲宽度调制芯片中的3.3伏的Buck线路电压时，所述输出电压为12伏，所述第三选择电压为脉冲宽度调制芯片中的1.2伏的Buck线路电压时，所述输出电压为3.3伏。
本发明提供了一种驱动电路，包括：第一二极管、第二二极管、第三二极管、第四二极管、第一电容、第二电容以及可调电压源，其中，所述第一二极管的阳极用于输入电压，所述第一二极管的阴极连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第四二极管的阳极，所述第四二极管的阴极用于输出电压，所述第一电容的第一端连接所述第一二极管与所述第二二极管的公共端，所述第一电容的 第二端连接所述可调电压源的输出端，所述可调电压源的选择端用于输入选择电压；在所述输入电压不变时，所述选择电压不同，所述输出电压不同。
可选地，所述可调电压源包括多个场效应管。
可选地，所述可调电压源包括第一场效应管、第二场效应管以及第三场效应管三个场效应管，所述第一场效应管的栅极用于输入第一电压，所述第一场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第一场效应管的源极用于输入第一选择电压，所述第二场效应管的栅极用于输入第二电压，所述第二场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第二场效应管的源极用于输入第二选择电压，所述第三场效应管的栅极用于输入第三电压，所述第三场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第三场效应管的源极用于输入第三选择电压。
可选地，所述第一选择电压为脉冲宽度调制芯片中BOOST电压时，所述输出电压为16伏，所述第二选择电压为脉冲宽度调制芯片中的3.3伏的Buck线路电压时，所述输出电压为12伏，所述第三选择电压为脉冲宽度调制芯片中的1.2伏的Buck线路电压时，所述输出电压为3.3伏。
可选地，所述第一电容以及所述第二电容均是不可调电容。
本发明还提供了一种液晶显示面板，所述液晶显示面板包括驱动电路，所述驱动电路包括：第一二极管、第二二极管、第三二极管、第四二极管、第一电容、第二电容以及可调电压源，其中，所述第一二极管的阳极用于输入电压，所述第一二极管的阴极连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第四二极管的阳极，所述第四二极管的阴极用于输出电压，所述第一电容的第一端连接所述第一二极管与所述第二二极管的公共端，所述第一电容的第二端连接所述可调电压源的输出端，所述可调电压源的选择端用于输入选择电压；在所述输入电压不变时，所述选择电压不同，所述输出电压不同。
可选地，所述可调电压源包括多个场效应管。
可选地，所述可调电压源包括第一场效应管、第二场效应管以及第三场效应管三个场效应管，所述第一场效应管的栅极用于输入第一电压，所述第一场 效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第一场效应管的源极用于输入第一选择电压，所述第二场效应管的栅极用于输入第二电压，所述第二场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第二场效应管的源极用于输入第二选择电压，所述第三场效应管的栅极用于输入第三电压，所述第三场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第三场效应管的源极用于输入第三选择电压。
可选地，所述第一选择电压为脉冲宽度调制芯片中BOOST电压时，所述输出电压为16伏，所述第二选择电压为脉冲宽度调制芯片中的3.3伏的Buck线路电压时，所述输出电压为12伏，所述第三选择电压为脉冲宽度调制芯片中的1.2伏的Buck线路电压时，所述输出电压为3.3伏。
可选地，所述第一电容以及所述第二电容均是不可调电容。
通过实施本发明实施例，能够通过可调电压源输入不同的电压，从而使得输出端能够提供不同的输出电压，满足用户的各种使用要求。而且，可通过调节电压，提供不同的驱动电流。当需要大电流驱动时，可以降低输出电压，从而提高电流驱动的能力。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术驱动电路一实施方式的电路图；
图2是本发明驱动电路一实施方式的电路图；
图3是本发明驱动电路另一实施方式的电路图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清 楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
请参阅图2，图2是本发明驱动电路一实施方式的电路图。本实施方式的驱动电路包括：第一二极管D1、第二二极管D2、第三二极管D3、第四二极管D4、第一电容C1、第二电容C2以及可调电压源Vi。其中，第一二极管D1的阳极用于输入电压，第一二极管D1的阴极连接第二二极管D2的阳极，第二二极管D2的阴极连接第三二极管D3的阳极，第三二极管D3的阴极连接第四二极管D4的阳极，第四二极管D4的阴极用于输出电压，第一电容C1的第一端连接第一二极管D1与第二二极管D2的公共端，第一电容C1的第二端连接可调电压源Vi的输出端，可调电压源Vi的选择端用于输入选择电压。当选择电压不同时，可调电压源Vi输出占空比不同的脉冲宽度调节电压。
在第一阶段，可调电压源Vi为低电平，此时，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为VAA。
在第二阶段，可调电压源Vi为高电平，第一二极管D1截止，第二二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为Vi+VAA。
在第三阶段，可调电压源Vi为低电平，此时，第一二极管D1以及第三二极管D3导通，第二二极管D2以及第四二极管D4截止，第一二极管D1的输出的电压VD1为VAA，第二二极管D2、第三二极管D3以及第四二极管D4 输出的电压VD2、VD3、VD4均为Vi+VAA。
在第四阶段，可调电压源Vi为高电平，此时，第一二极管D1以及第三二极管D3截止，第二二极管D2以及第四二极管D4导通，第一二极管D1的输出的电压VD1为Vi+VAA，第二二极管D2的输出的电压VD2为Vi+VAA，第三二极管D3以及第四二极管D4输出的电压VD3、VD4均为2Vi+VAA。
所以，输入电压VAA与输出电压VGH之间的关系为满足VGHF＝VAA+2*Vi，所以当选择电压不同时，可调电压源电压输出的电压Vi不同，输出电压VGH也不相同。
通过实施本发明实施例，能够通过可调电压源输入不同的电压，从而使得输出端能够提供不同的输出电压，满足用户的各种使用要求。而且，可通过调节电压，提供不同的驱动电流。当需要大电流驱动时，可以降低输出电压，从而提高电流驱动的能力。
请参阅图3，图3是本发明驱动电路另一实施方式的电路图。本实施方式的驱动电路包括：第一二极管D1、第二二极管D2、第三二极管D3、第四二极管D4、第一电容C1、第二电容C2、第一场效应管M1、第二场效应管M2以及第三场效应管M3。其中，第一电容C1以及第二电容C2均为不可以调电容。第一二极管D1的阳极用于输入电压，第一二极管D1的阴极连接第二二极管D2的阳极，第二二极管D2的阴极连接第三二极管D3的阳极，第三二极管D3的阴极连接第四二极管D4的阳极，第四二极管D4的阴极用于输出电压，第一电容C1的第一端连接第一二极管D1与第二二极管D2的公共端，第二电容C2的第一端连接第三二极管D3和第四二极管D4的公共端，第一电容C1的第二端连接第二电容C2的第二端。第一场效应管M1的栅极用于输入第一电压，第一场效应管M1的漏极d1连接第一电容C1的第二端与第二电容C2的第二端的公共端，第一场效应管M1的源极s1用于输入第一选择电压LX1，第二场效应管M2的栅极g2用于输入第二电压，第二场效应管M2的漏极d2连接第一电容C1的第二端与第二电容C2的第二端的公共端，第二场效应管M2的源极s2用于输入第二选择电压LX2，第三场效应管M3的栅极g3用于输入第三电压，第三场效应管M3的漏极d3连接第一电容C1的第二端与 第二电容C2的第二端的公共端，第三场效应管M3的源极s3用于输入第三选择电压LX3。其中，第一选择电压LX1，第二选择电压LX2以及第三选择电压LX3为占空比不同的脉冲宽度调节电压。
当向第一场效应管M1的栅极g1输入第一电压，而不向第二场效应管M2的栅极g2以及第三场效应管M3的栅极g3输入电压时，第一场效应管M1导通，所以，第一选择电压LX1向第一电容C1以及第二电容C2充电。具体的过程为：
在第一阶段，第一选择电压LX1为低电平，此时，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为VAA。
在第二阶段，第一选择电压LX1为高电平，第一二极管D1截止，第二二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为LX1+VAA。
在第三阶段，第一选择电压LX1为低电平，此时，第一二极管D1以及第三二极管D3导通，第二二极管D2以及第四二极管D4截止，第一二极管D1的输出的电压VD1为VAA，第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD2、VD3、VD4均为LX1+VAA。
在第四阶段，第一选择电压LX1为高电平，此时，第一二极管D1以及第三二极管D3截止，第二二极管D2以及第四二极管D4导通，第一二极管D1的输出的电压VD1为Vi+VAA，第二二极管D2的输出的电压VD2为LX1+VAA，第三二极管D3以及第四二极管D4输出的电压VD3、VD4均为2LX1+VAA。
当向第二场效应管M2的栅极g2输入第二电压，而不向第一场效应管M1的栅极g1以及第三场效应管M3的栅极g3输入电压时，第二场效应管M2导通，所以，第二选择电压LX2向第一电容C1以及第二电容C2充电。具体的过程为：
在第一阶段，第二选择电压LX2为低电平，此时，第一二极管D1、第二 二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为VAA。
在第二阶段，第二选择电压LX2为高电平，第一二极管D1截止，第二二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为LX2+VAA。
在第三阶段，第二选择电压LX2为低电平，此时，第一二极管D1以及第三二极管D3导通，第二二极管D2以及第四二极管D4截止，第一二极管D1的输出的电压VD1为VAA，第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD2、VD3、VD4均为LX2+VAA。
在第四阶段，第二选择电压LX2为高电平，此时，第一二极管D1以及第三二极管D3截止，第二二极管D2以及第四二极管D4导通，第一二极管D1的输出的电压VD1为Vi+VAA，第二二极管D2的输出的电压VD2为LX2+VAA，第三二极管D3以及第四二极管D4输出的电压VD3、VD4均为2LX2+VAA。
当向第三场效应管M3的栅极g3输入第三电压，而不向第一场效应管M1的栅极g1以及第二场效应管M2的栅极g2输入电压时，第三场效应管M2导通，所以，第三选择电压LX2向第一电容C1以及第二电容C2充电。具体的过程为：
在第一阶段，第三选择电压LX3为低电平，此时，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为VAA。
在第二阶段，第三选择电压LX3为高电平，第一二极管D1截止，第二二极管D2、第三二极管D3以及第四二极管D4均导通，第一二极管D1、第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD1、VD2、VD3、VD4均为LX3+VAA。
在第三阶段，第三选择电压LX3为低电平，此时，第一二极管D1以及第 三二极管D3导通，第二二极管D2以及第四二极管D4截止，第一二极管D1的输出的电压VD1为VAA，第二二极管D2、第三二极管D3以及第四二极管D4输出的电压VD2、VD3、VD4均为LX3+VAA。
在第四阶段，第三选择电压LX3为高电平，此时，第一二极管D1以及第三二极管D3截止，第二二极管D2以及第四二极管D4导通，第一二极管D1的输出的电压VD1为LX3+VAA，第二二极管D2的输出的电压VD2为LX3+VAA，第三二极管D3以及第四二极管D4输出的电压VD3、VD4均为2LX3+VAA。
所以，由上述可知，在输入电压VAA不变时，当选择电压不同，输出电压VGH也不相同。
在一具体的实施方式中，第一选择电压LX1为脉冲宽度调制芯片中BOOST电压时，输出电压VGH为16伏，第二选择电压LX2为脉冲宽度调制芯片中的3.3伏的Buck线路电压时，输出电压VGH为12伏，第三选择电压LX3为脉冲宽度调制芯片中的1.2伏的Buck线路电压时，输出电压VGH为3.3伏。
可以理解的是，上述的实施方式是以可调电压源为3个场效应管为例进行说明，在其它的实施方式中，场效应管的数量可以是4个或者更多，具体可根据需要进行设置。
通过实施本发明实施例，能够通过可调电压源输入不同的电压，从而使得输出端能够提供不同的输出电压，满足用户的各种使用要求。而且，可通过调节电压，提供不同的驱动电流。当需要大电流驱动时，可以降低输出电压，从而提高电流驱动的能力。
本发明还提供了一种液晶显示面板，所述面板包括如图2和图3所示的驱动电路，具体请参阅图2、图3以及相关描述，此处不再一一重复赘述。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。 其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (13)

  1. 一种驱动电路，其特征在于，包括：第一二极管、第二二极管、第三二极管、第四二极管、第一电容、第二电容以及可调电压源，其中，所述可调电压源包括多个场效应管，所述第一二极管的阳极用于输入电压，所述第一二极管的阴极连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第四二极管的阳极，所述第四二极管的阴极用于输出电压，所述第一电容的第一端连接所述第一二极管与所述第二二极管的公共端，所述第一电容的第二端连接所述可调电压源的输出端，所述可调电压源的选择端用于输入选择电压；在所述输入电压不变时，所述选择电压不同，所述输出电压不同，其中，所述第一电容以及所述第二电容均是不可调电容。
  2. 根据权利要求1所述的电路，其特征在于，所述可调电压源包括第一场效应管、第二场效应管以及第三场效应管三个场效应管，
    所述第一场效应管的栅极用于输入第一电压，所述第一场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第一场效应管的源极用于输入第一选择电压，
    所述第二场效应管的栅极用于输入第二电压，所述第二场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第二场效应管的源极用于输入第二选择电压，
    所述第三场效应管的栅极用于输入第三电压，所述第三场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第三场效应管的源极用于输入第三选择电压。
  3. 根据权利要求2所述的电路，其特征在于，所述第一选择电压为脉冲宽度调制芯片中BOOST电压时，所述输出电压为16伏，所述第二选择电压为脉冲宽度调制芯片中的3.3伏的Buck线路电压时，所述输出电压为12伏，所述第三选择电压为脉冲宽度调制芯片中的1.2伏的Buck线路电压时，所述输出电压为3.3伏。
  4. 一种驱动电路，其特征在于，包括：第一二极管、第二二极管、第三二极管、第四二极管、第一电容、第二电容以及可调电压源，其中，所述第一 二极管的阳极用于输入电压，所述第一二极管的阴极连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第四二极管的阳极，所述第四二极管的阴极用于输出电压，所述第一电容的第一端连接所述第一二极管与所述第二二极管的公共端，所述第一电容的第二端连接所述可调电压源的输出端，所述可调电压源的选择端用于输入选择电压；在所述输入电压不变时，所述选择电压不同，所述输出电压不同。
  5. 根据权利要求4所述的电路，其特征在于，所述可调电压源包括多个场效应管。
  6. 根据权利要求5所述的电路，其特征在于，所述可调电压源包括第一场效应管、第二场效应管以及第三场效应管三个场效应管，
    所述第一场效应管的栅极用于输入第一电压，所述第一场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第一场效应管的源极用于输入第一选择电压，
    所述第二场效应管的栅极用于输入第二电压，所述第二场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第二场效应管的源极用于输入第二选择电压，
    所述第三场效应管的栅极用于输入第三电压，所述第三场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第三场效应管的源极用于输入第三选择电压。
  7. 根据权利要求6所述的电路，其特征在于，所述第一选择电压为脉冲宽度调制芯片中BOOST电压时，所述输出电压为16伏，所述第二选择电压为脉冲宽度调制芯片中的3.3伏的Buck线路电压时，所述输出电压为12伏，所述第三选择电压为脉冲宽度调制芯片中的1.2伏的Buck线路电压时，所述输出电压为3.3伏。
  8. 根据权利要求4所述的电路，其特征在于，所述第一电容以及所述第二电容均是不可调电容。
  9. 一种液晶显示面板，其特征在于，所述液晶显示面板包括驱动电路，所述驱动电路包括：第一二极管、第二二极管、第三二极管、第四二极管、第一电容、第二电容以及可调电压源，其中，所述第一二极管的阳极用于输入电 压，所述第一二极管的阴极连接所述第二二极管的阳极，所述第二二极管的阴极连接所述第三二极管的阳极，所述第三二极管的阴极连接所述第四二极管的阳极，所述第四二极管的阴极用于输出电压，所述第一电容的第一端连接所述第一二极管与所述第二二极管的公共端，所述第一电容的第二端连接所述可调电压源的输出端，所述可调电压源的选择端用于输入选择电压；在所述输入电压不变时，所述选择电压不同，所述输出电压不同。
  10. 根据权利要求9所述的液晶显示面板，其特征在于，所述可调电压源包括多个场效应管。
  11. 根据权利要求10所述的液晶显示面板，其特征在于，所述可调电压源包括第一场效应管、第二场效应管以及第三场效应管三个场效应管，
    所述第一场效应管的栅极用于输入第一电压，所述第一场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第一场效应管的源极用于输入第一选择电压，
    所述第二场效应管的栅极用于输入第二电压，所述第二场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第二场效应管的源极用于输入第二选择电压，
    所述第三场效应管的栅极用于输入第三电压，所述第三场效应管的漏极连接所述第一电容的第二端与所述第二电容的第二端的公共端，所述第三场效应管的源极用于输入第三选择电压。
  12. 根据权利要求11所述的液晶显示面板，其特征在于，所述第一选择电压为脉冲宽度调制芯片中BOOST电压时，所述输出电压为16伏，所述第二选择电压为脉冲宽度调制芯片中的3.3伏的Buck线路电压时，所述输出电压为12伏，所述第三选择电压为脉冲宽度调制芯片中的1.2伏的Buck线路电压时，所述输出电压为3.3伏。
  13. 根据权利要求9所述的液晶显示面板，其特征在于，所述第一电容以及所述第二电容均是不可调电容。
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