WO2017008329A1 - 一种像素矩阵的外围补偿系统、方法和显示系统 - Google Patents

一种像素矩阵的外围补偿系统、方法和显示系统 Download PDF

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Publication number
WO2017008329A1
WO2017008329A1 PCT/CN2015/085084 CN2015085084W WO2017008329A1 WO 2017008329 A1 WO2017008329 A1 WO 2017008329A1 CN 2015085084 W CN2015085084 W CN 2015085084W WO 2017008329 A1 WO2017008329 A1 WO 2017008329A1
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Prior art keywords
signal
display
analog
correction
compensation
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English (en)
French (fr)
Inventor
林兴武
张盛东
冷传利
王翠翠
孟雪
张敏
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a peripheral compensation system, method, and display system for a pixel matrix.
  • OLED Organic Light-Emitting Diode
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the passive matrix driving method is low in cost, there is a crosstalk phenomenon and thus a high-resolution display cannot be realized.
  • the passive matrix driving current is large, which reduces the service life of the organic light emitting diode.
  • the active matrix driving method is to set a different number of transistors as current sources on each pixel unit of the pixel matrix, thereby avoiding crosstalk and realizing high resolution display, and the active matrix driving current is Smaller, lower power consumption, increasing the lifetime of organic light-emitting diodes.
  • One of the active matrix driven pixel units is a two-film Thin Film Transistor (TFT) structure including a driving transistor, a display switching transistor, a storage capacitor, and an organic light emitting diode.
  • the display switching transistor samples the signal from the display signal line in response to a signal from the display address line.
  • the storage capacitor stores the signal voltage of the sampled display signal line after the display switching transistor is turned off.
  • the drive transistor supplies an output current according to an input voltage retained by the storage capacitor during a given illumination period.
  • the organic light emitting diode emits light whose brightness is commensurate with the signal of the display signal line by the output current from the driving transistor.
  • the driving current I DS can be expressed as:
  • I DS 1/2 ⁇ n C ox W/L (V G - V OLED - V TH ) 2 (1)
  • I DS is the drain current flowing to the source of the drain of the driving transistor
  • ⁇ n is the effective mobility of the thin film field effect transistor
  • C ox is the gate capacitance per unit area of the thin film field effect transistor
  • W is the thin film field effect transistor Effective channel width
  • L is the effective channel length of the thin film field effect transistor
  • V G is the gate voltage of the thin film field effect transistor
  • V OLED is the bias voltage on the organic light emitting diode
  • V TH is the threshold of the thin film field effect transistor
  • the voltage, V OLED is related to the threshold voltage of the organic light emitting diode OLED.
  • the structure circuit of the two thin film field effect transistors of the active matrix driven pixel unit described above although the circuit is simple, the components therein will age over time, especially the driving transistor and the organic light emitting diode will age, directly The consequence is that the threshold voltages of the driving transistor and the organic light emitting diode will drift, and the threshold voltage drift of the driving transistor and the organic light emitting diode of each pixel unit in the pixel matrix is also different; in addition, the thin film field effect transistor is made of polysilicon material.
  • the threshold voltage V TH of the driving transistor of each pixel unit in the pixel matrix is made to have non-uniformity; in the above two cases, according to the formula (1), the driving current I DS changes at this time, so that This will result in unevenness in the display of the pixel matrix.
  • pixel unit internal compensation In view of the problem that the pixel matrix display unevenness caused by the threshold voltage drift and the non-uniformity of the driving transistor and the organic light emitting diode, two types of methods for compensating the threshold voltage are currently available: pixel unit internal compensation and peripheral compensation.
  • the compensation in the pixel unit is to provide a constant driving current for the organic light emitting diode through the complicated pixel unit circuit structure.
  • the circuit of this method is not only complicated, but also the circuit complexity further causes the aperture ratio and the yield of the pixel unit to decrease; the peripheral compensation phase A simpler pixel cell structure can be used, which is more suitable for industrial applications.
  • the present application provides a peripheral compensation system, method and display system for a pixel matrix, which realizes accurate peripheral compensation of pixel units.
  • the present application provides a peripheral compensation system for a pixel matrix, the pixel matrix 100 including N rows and M columns of pixel units 101, N rows of display address lines, and M columns of display signal lines, pixel units 101 and The respective display address lines and display signal lines are respectively connected, N and M are positive integers, and the peripheral compensation system comprises: a line scan driver 200 for transmitting a display address signal to the pixel matrix 100 by displaying the address line to be in one frame. Internally strobing each row of pixel units 101;
  • the compensator 400 includes a compensation information storage module 402 for storing compensation information, and the compensator 400 is configured to send a digital display compensation signal to the column driver 300.
  • the compensator 400 sends out The corresponding digital display compensation signal to compensate for the inaccuracy of the display of the image information of the pixel unit 101;
  • the column driver 300 includes a display signal generating module 301 for transmitting an analog display signal to the pixel matrix 100 for providing display data including image video information for the display signal line of the pixel unit 101; the display signal
  • the generating module 301 includes a first digital-to-analog conversion module 311 having a gamma correction function, a second digital-to-analog conversion module 312, and a first analog addition module 313; when a row of pixel units 101 is gated by the display address signal, the first number
  • the analog-to-digital conversion module 311 receives the line digital original display signal, and outputs a gamma-corrected analog original display signal to the first analog adding module 313; the second digital-to-analog conversion module 312 receives the corresponding digital display compensation signal, and outputs an analog signal.
  • the pixel matrix 100 further includes a first shift register 304 and a second shift register 305, and the first shift register 304 receives the digital original display signal of the outside world and forwards it to the first digital to analog conversion
  • the module 311, the second shift register 305 receives the digital display compensation signal from the compensator 400 and forwards the signal to the second digital to analog conversion module 312.
  • the present application provides a method for a peripheral compensation system of a pixel matrix, where the pixel matrix 100 includes N rows and M columns of pixel units 101, N rows of display address lines, and M columns of display signal lines, and pixel units. 101 and the respective display address lines and display signal lines are respectively connected, and N and M are both positive integers, and the method includes:
  • One frame time is composed of N equal line times t 1 to t N , and each row of pixel units 101 sequentially performs a display operation, wherein the nth row of pixel units 101 performs a display operation at t n : the row of pixel units 101 is displayed with an address Signal gating, receiving an analog display signal, where n is a positive integer less than or equal to N;
  • the i-th row of the pixel unit 101 performs a display operation, if the system is not in this case the peripheral compensation feedback detection state, when t i, i + k row of the pixel unit 101 performs a correction operation: this is the row of pixel units 101 Writing an analog correction signal; in the period t i+1 to t i+k-1 , the peripheral compensation system enters a feedback detection state: feeding back the feedback signal containing the aging information in the pixel unit 101 of the i+kth row to the compensation signal detection Block 303; wherein i and k are both positive integers, and i+k is less than or equal to N.
  • the present application provides a display system including the above-described peripheral compensation system and pixel matrix 100.
  • the display system using the peripheral compensation method needs to compensate each pixel unit in the display driver chip. Since the original analog display signal is gamma-corrected, it is necessary to retain the original gamma correction after compensation.
  • the prior art is The digital original display signal and the digital display compensation signal are first added by digital method and then digital-analog conversion is performed by a linear digital-to-analog conversion module, and gamma correction is realized by a digital method.
  • This type of digital gamma correction method requires a very small voltage per step compared to conventional analog methods. That is to say, the number of bits required for the digital-to-analog conversion module is relatively large, and the number of bits can still only be close to the precision of the analog-to-digital conversion.
  • the peripheral compensation system, method and display system of the present application by introducing a first analog addition module and a first digital-to-analog conversion module with gamma correction function, compensate the digital original signal while maintaining accurate gamma Correction, the structure remains simple, and the number of bits of the first digital-to-analog conversion module is also low;
  • the method of the peripheral compensation system generally requires feedback to detect the aging information of the pixel unit, and then compensate the digital original display signal.
  • the operation of the prior art feedback detection is generally performed during a blank period between frames. Because the blank period between the frame and the frame is much less than the display period, the frequency of the compensation information refresh is relatively slow.
  • the peripheral compensation system, method and display system of the present application can realize the correction operation when the display system is displayed in the middle of the frame. This can greatly increase the refresh rate of the compensation information, or maintain the same refresh rate as the prior art, so that multiple columns share a compensation signal detection module.
  • FIG. 1 is a schematic structural view of a display system in a first embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a pixel unit in a first embodiment of the present application.
  • FIG. 3 is a distribution diagram of aging degree of each pixel unit in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display signal generating module in a first embodiment of the present application.
  • FIG. 5 is a timing diagram of a peripheral compensation system in a first embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a display system in a second embodiment of the present application.
  • FIG. 7 is a schematic diagram showing four structures of a pixel unit in a second embodiment of the present application.
  • FIG. 8 is a schematic diagram showing two structures of a correction signal generating module in a second embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display system in a third embodiment of the present application.
  • FIG. 11 is a schematic diagram showing two structures of a pixel unit in a third embodiment of the present application.
  • the present embodiment is a display system including a pixel matrix 100 and a peripheral compensation system of the pixel matrix 100 (hereinafter referred to as a peripheral compensation system).
  • the pixel matrix 100 includes N rows and M columns of pixel units 101, N rows of display address lines, and M columns of display signal lines.
  • the pixel cells 101 and the respective display address lines and display signal lines are respectively connected, and N and M are positive integers.
  • Figure 1 shows only four pixel units as an example, in the position [1, 1], the first row, the first column, [N, 1], the Nth row, the first column, [1, M], the first row.
  • Column M, and [N, M] are the Nth row and the Mth column.
  • the pixel unit 101 has various circuits, one of which may be the circuit of FIG. 2, which includes a driving transistor Q1, a display switching transistor Q2, a storage capacitor C, and an organic light emitting diode OLED.
  • the display switching transistor Q2 is gated by the display address signal from the display address line to send a display signal from the display signal line to the driving transistor Q1, and the storage capacitor C simultaneously stores the analog display signal to display the switch in one frame time. After the transistor Q2 is turned off, the stable analog display signal is still supplied to the driving transistor Q1, and the driving transistor Q1 receives the analog display signal to drive the organic light emitting diode OLED to emit light corresponding to the analog display signal, where the analog display signal refers to the image containing the image.
  • the data signal of the video is gated by the display address signal from the display address line to send a display signal from the display signal line to the driving transistor Q1, and the storage capacitor C simultaneously stores the analog display signal to display the switch in one frame time. After the transistor Q2 is turned off, the stable analog display signal is still supplied to the driving transistor Q1, and the driving transistor Q1 receives the analog display signal to drive the organic light emitting diode OLED to emit light corresponding to the analog display signal, where the analog display signal refers to the
  • the above-described transistors such as the driving transistor Q1 and the display switching transistor Q2 can be fabricated by using amorphous silicon, polycrystalline silicon, an oxide semiconductor, an organic semiconductor, an NMOS/PMOS process, or a CMOS process.
  • the pixel matrix 100 peripheral compensation system includes a row scan driver 200, a compensator 400, and a column driver 300.
  • the row scan driver 200 is for transmitting a display address signal to the pixel matrix 100 through the display address line to sequentially strobe each row of pixel units 101 in one frame.
  • the compensator 400 includes a compensation information storage module 402 for storing compensation information for transmitting a digital display compensation signal to the column driver 300.
  • the compensator 400 is obtained from the compensation information storage module 402. Reading the compensation information of the corresponding row and calculating the digital display compensation signal is transmitted to the second shift register 305 in the column driver 300, and then transmitted to the display signal generating module 301, the digital display compensation signal is used to compensate the pixel unit. 101 The problem that the image video information generated due to the uneven state of the original state and aging is inaccurate.
  • the original state of the pixel unit 101 refers to the original threshold voltage of the driving transistor Q1 and the organic light emitting diode OLED, and the original luminous efficiency of the organic light emitting diode OLED.
  • the aging of the pixel unit 101 means that after the pixel unit 101 is used, the threshold voltages of the driving transistor Q1 and the organic light emitting diode OLED are shifted, and the luminous efficiency of the organic light emitting diode OLED is changed.
  • the compensation information storage module 402 stores the original state of each pixel unit 101.
  • the peripheral compensation system updates the compensation information storage module 402 according to the aging condition of each pixel unit 101 after use. Compensation information.
  • the compensation information storage module 402 in the compensator 400 may be one, or two, or may be composed of two or more memories. If the compensation information storage module 402 is a memory component, when the display system is shipped from the factory, the memory stores the original state of each pixel unit 101, and when used, it updates the compensation information in the memory according to the aging condition; if it is two One or more, the various original states and various aging conditions of the pixel unit 101 can be selectively stored separately, such as one memory stores the compensation information related to the driving transistor Q1, and the other memory stores the compensation information related to the LED OLED. Or one memory stores the original state information of the pixel unit 101, and the other memory stores the aging data and the like after the pixel unit 101 is used.
  • the memory here refers to a storage medium.
  • One of the methods for generating digital compensation information regarding the original state of each pixel unit 101 is that the test driver chip can be written to all the pixel units 101 when the display system is shipped from the factory. The same voltage is used to detect the luminance of all the pixel units 101 of the display system, and the unevenness in luminance is converted into compensation information storage module 402 stored in the compensator 400. The compensation information stored at this time characterizes the original state of each pixel unit 101 because the unevenness in luminance of each pixel unit 101 represents the unevenness of the original state of the pixel unit 101.
  • One method of extracting aging information after use of the display system is to calculate the degree of aging according to the usage of each pixel unit 101 in the peripheral compensation system, such as the time when each pixel unit 101 is illuminated and the gray scale (ie, brightness) of the display.
  • the degree of aging is calculated, and the compensation information in the compensation information storage module 402 is updated.
  • the aging-related compensation information is obtained by fitting and mathematically modeling the aging characteristic curve of the pixel unit 101; that is, the usage of the pixel unit 101 corresponds to the value of a compensation information, and the value of the compensation information corresponds to a digital display compensation signal.
  • the compensator 400 updates the compensation information in the compensation information storage module 402 according to the usage of the pixel unit 101.
  • FIG. 3 is a storage manner of the compensation information of the pixel unit 101.
  • the abscissa indicates different pixel units 101 in the figure, and there are N*M pixel units 101 in total. For the convenience of drawing, only 7 pixels are drawn in FIG. Absolute compensation information for unit 101.
  • the ordinate of FIG. 3 is the absolute digital compensation information value of each pixel unit 101.
  • the physical quantity representation of the absolute compensation information of the pixel unit 101 may be the threshold voltage of the driving transistor Q1, and/or the threshold of the organic light emitting diode OLED. The voltage, and/or the luminous efficiency of the organic light emitting diode OLED.
  • the compensation information storage module 402 stores only the difference between the absolute compensation information value of each pixel unit and the reference compensation information value.
  • the difference ⁇ V between the pixel unit 101 numbered 1 and the reference compensation information value is shown in FIG. 3.
  • the reference compensation information value may be lower than the absolute compensation information of the pixel unit 101. The lowest value.
  • the reference compensation information value is formulated according to the absolute compensation information values of all the pixel units as a whole, and when the absolute compensation information value of the overall pixel unit becomes larger, the reference compensation information value also becomes larger.
  • the column driver 300 includes a first shift register 304 and a second shift register 305, and a display signal generating module 301.
  • the first shift register 304 receives the digital original display signal one signal and one signal.
  • the second shift register 305 also receives the digital display compensation signal as a signal and a signal.
  • the first shift register 304 And the second shift register 305 receives the digital original display signal and the digital display compensation signal of the row of pixel units 101 and outputs them to the display signal generating module 301 in parallel.
  • the display signal generating module 301 receives the digital original display signals and the numbers. After the compensation signal is displayed, an analog display signal is sent to the pixel matrix 100 for providing display data containing the accurate image video information for the display signal line of the pixel unit 101.
  • the display signal generating module 301 includes a first digital-to-analog conversion module 311 having a gamma correction function, a second digital-to-analog conversion module 312, and a first analog addition module 313;
  • the first digital-to-analog conversion module 311 receives the digital original display signal, and outputs the gamma-corrected analog original display signal to the first analog addition module 313, where the first digital-to-analog conversion
  • the processing of the digital original display signal by the module 311, that is, the digital-to-analog conversion and the gamma correction is the same process, that is, the digital original display signal is not subjected to gamma correction and then digital-to-analog conversion, and the digital original display signal is not counted first.
  • the analog-to-analog conversion performs gamma correction; the second digital-to-analog conversion module 312 receives the digital display compensation signal, and outputs an analog display compensation signal to the first analog addition module 313; the first analog addition module 313 simulates the display compensation signal and undergoes gamma correction.
  • the simulated raw display signal is subjected to analog addition and the analog display signal is output to the pixel matrix 100. If the display system can directly provide the analog display compensation signal to the first adding module 313, the display system may not include the second digital-to-analog conversion module 312.
  • FIG. 5 is a waveform diagram of a display address line and a display signal line of the peripheral compensation system in the embodiment.
  • the display address line 1 is used to gate the display address line of the pixel unit 101 of the first row
  • the display address line 2 is used to gate the display address line of the pixel unit 101 of the second row
  • the address line N is displayed.
  • the display address line of the pixel unit 101 of the Nth row is gated.
  • the signal L1 on the signal line shown in FIG. 5 is an analog display signal representing that all of the pixel units 101 in the first row are compensated, that is, the signal L1 includes an analog display signal from the display signal line 1 to the display signal line M.
  • the pixel unit 101 is strobed when the display address line is at a high level.
  • the row scan driver 200 sequentially selects the row of pixel units 101 in order from the first row by displaying the address lines 1 to N. After the last row of pixel units 101, that is, the pixel row 101 of the Nth row, the frame scan driver 200 is a frame. A blank period between the frame and the frame begins to sweep the first row of pixel units 101 of the next frame.
  • the column driver 300 transmits a corresponding compensated analog display signal to the display signal line. The analog display signal on the display signal line is maintained at least until the line scan driver 200 turns off the row of pixel units 101.
  • This embodiment discloses a peripheral compensation system.
  • the column driver 300 in the embodiment also sends an analog correction signal to the pixel matrix 100, and the pixel matrix 100 sends a feedback signal for updating the compensation information stored in the compensator 400, and then
  • the compensation information calculates a digital display compensation signal, and the digital display compensation signal calculated by the updated compensation information is more accurate than the digital display compensation signal in the first embodiment.
  • the display system includes a pixel matrix 100 and a peripheral compensation system of the pixel matrix 100.
  • the pixel matrix 100 includes N rows and M columns of pixel units 101, N rows of display address lines, N rows of corrected address lines, N rows of feedback address lines, M columns of display signal lines, M columns of correction signal lines, and M
  • the stripping signal lines, the pixel unit 101 and the respective display address lines, the corrected address lines, the feedback address lines, the display signal lines, the correction signal lines, and the feedback signal lines are respectively connected, wherein N and M are positive integers.
  • the pixel unit 101 has various circuit configurations. Here are a few examples.
  • the pixel unit 101 includes a driving transistor Q1, a display switching transistor Q2, a correction switching transistor Q3, a feedback switching transistor Q4, a storage capacitor C, and an organic light emitting diode OLED.
  • the correction switching transistor Q3 is gated by the correction address signal transmitted from the correction address line to send an analog correction signal from the correction signal line to the driving transistor Q1, and the storage capacitor C simultaneously stores the analog correction signal to simulate the correction signal.
  • the stable analog correction signal is still supplied to the driving transistor Q1 before being covered by the analog display signal and after the correction switching transistor Q3 is turned off, and then the feedback signal detecting module 303 of the column driving 300 gives a voltage to the feedback signal line, which is set.
  • the feedback switching transistor Q4 is gated from the feedback address signal on the feedback address signal line, the voltage is input to the anode of the light-emitting diode OLED , turn off the LED OLED.
  • the peripheral compensation system knows the gate-to-source voltage difference of the driving transistor Q1, it is expected that the pixel unit 101 will feed back some expected current, the driving transistor Q1 is turned on, the LED OLED is turned off, and the feedback current of the driving transistor Q1 is passed.
  • the feedback switching transistor Q4 flows to the feedback signal line and is received by the compensation signal detecting module 303 of the column driver 300.
  • the compensation signal detection module 303 compares the feedback current with the expected current.
  • the feedback switching transistor Q4 will continue to be turned on until the compensation signal detection module 303 completes the feedback current detection.
  • the threshold voltage of the light emitting diode OLED of the detecting pixel unit 101 can be compensated by the correction address line and the correction signal line inputting the threshold voltage lower than the driving transistor Q1 to the driving transistor Q1, and then strobing the feedback switching transistor Q4 through the feedback address line to compensate
  • the signal detecting module 303 can apply a fixed current to the LED OLED through the feedback signal line, and then detect the aging degree of the LED OLED or the threshold voltage drift degree by detecting the voltage on the feedback signal line, and can also estimate the change of the luminous efficiency.
  • the display switching transistor Q2 is gated by the display address signal from the display address line to send an analog display signal from the display signal line to the driving transistor Q1, and the storage capacitor C simultaneously stores the analog display signal.
  • the stable analog display signal is still supplied to the driving transistor Q1 after the display switching transistor Q2 is turned off within one frame time, and the driving transistor Q1 receives the analog display signal to drive the organic light emitting diode OLED to emit light corresponding to the analog display signal.
  • the anode of the organic light emitting diode OLED of FIG. 7(b) is connected to a power source, and the cathode is connected to the first pole of the driving transistor Q1.
  • the feedback signal transmitted through the feedback signal line in FIG. 7(b) includes the driving transistor Q1 and the organic light emitting layer.
  • the signal turns transistor Q4 on and transistor Q5 turns on. 7(d) is compared with FIG. 7(b), in which the transistors Q4 and Q5 in FIG.
  • the gate of the transistor Q4 is connected to the feedback address line
  • the gate of the transistor Q5 is connected.
  • the stage is connected to an “extra feedback address line”, the signal in the feedback address line is the feedback address signal, and the signal in the additional feedback address line is the opposite signal to the feedback address signal, that is, when the feedback address line is high, additional feedback The address line is low, and when the feedback address line is low, the extra feedback address line is high.
  • one pole of the feedback switching transistor Q4 of FIG. 7(c) is not connected to the anode of the organic light emitting diode OLED, but is connected to a photosensitive element GL, and the photosensitive element GL is used for organic light emission.
  • the optical signal of the diode OLED is converted into an electrical signal, and the feedback signal transmitted through the feedback signal line in FIG. 7(c) includes aging information of both the driving transistor Q1 and the organic light emitting diode OLED.
  • the circuit structure of the pixel unit 101 can be various.
  • the pixel unit 101 can have different control lines, and is not limited to only connecting the display address lines, correcting the address lines and the feedback address lines; displaying the address lines, correcting the address lines and the feedback addresses.
  • Signal waveforms on the line can have a variety of shapes and are not limited to square waves.
  • the column driver 300 further includes a correction signal generation module 302 and a compensation signal detection module 303, and a third shift register 306 and a fourth shift register 307, as compared with the first embodiment.
  • the correction signal generation module 302 sends an analog correction signal to the pixel matrix 100 for driving the pixel unit 101 to generate a feedback signal containing the aging information.
  • the analog correction signal here may be a fixed voltage signal, or may be a signal formed by combining a fixed voltage signal and a digital correction compensation signal. According to different types of analog correction signals, the correction signal generation module 302 has different Method to realize.
  • the correction signal generation module 302 includes a module that generates a fixed voltage signal as an analog correction signal. Since the analog correction signal is a fixed signal, the pixel unit 101 may feed back different magnitudes of voltage or current signals due to the degree of aging or the original state. The voltage or current signals of different magnitudes are feedback signals, and the pixel unit 101 may be characterized. The degree of aging.
  • the analog correction signal is a signal formed by combining a fixed voltage signal and a digital correction compensation signal
  • the pixel unit 101 feeds back an expected signal (voltage or current).
  • the correction signal generation module 302. The following are two types of trials:
  • the analog correction signal generated at this time is a signal formed by combining a fixed voltage signal and a digital correction compensation signal.
  • the correction signal generation module 302 includes a third digital-to-analog conversion module 321; the third digital-to-analog conversion module 321 inputs a digital correction compensation signal and a reference voltage, respectively, and outputs an analog correction signal after processing, wherein the reference voltage is a set fixed voltage. Therefore, when the analog correction signal is a signal formed by combining a fixed voltage signal and a digital correction compensation signal, The analog correction signal is actually a signal formed by the above-mentioned fixed voltage signal being compensated by the digital correction compensation signal.
  • the analog correction signal generated at this time is a signal formed by combining a fixed voltage signal and a digital correction compensation signal.
  • the correction signal generation module 302 includes a third digital-to-analog conversion module 321 and a second analog addition module 322.
  • the third digital-to-analog conversion module 321 inputs a digital correction compensation signal, and after processing, outputs an analog correction compensation signal to the second analog addition module 322.
  • the second analog addition module 322 also inputs a fixed voltage signal, and the second analog addition module 322 adds the analog correction compensation signal and the fixed voltage signal to output an analog correction signal.
  • the input end of the compensation signal detecting module 303 is connected to the feedback signal line, the output end is connected to the input end of the fourth shift register 307, and the output end of the fourth shift register 307 is connected to the compensator 400.
  • the compensation signal detecting module 303 receives the feedback signal sent by the pixel unit 101 of the row when the pixel unit 101 is strobed by the feedback address signal, obtains the aging information from the feedback signal, and updates the compensation information storage module 402 with the aging information. Compensation information for this row of pixel units 101.
  • the compensation signal detection module 303 can be implemented by any one of an analog current comparison module, an analog voltage comparison module, or an analog to digital conversion module.
  • the compensation signal detection module 303 when the compensation signal detection module 303 is implemented by the analog current comparison module, the analog correction signal is a compensated fixed voltage during the correction operation, and the pixel unit 101 may be the circuit structure shown in FIG. 7(a).
  • the unit feeds back an expected feedback signal, and the compensation signal detection module 303 compares the received feedback signal (current) with an expected signal (reference current) to determine whether the aging degree of the pixel unit 101 (the degree of aging of the driving transistor Q1) changes. And outputting the result to the compensator 400 through the fourth shift register 307 to update the compensation information stored in the compensation information storage module 402.
  • the pixel unit 101 is another circuit structure that allows a feedback signal (current) to flow through the driving transistor Q1 and the organic light emitting diode OLED, and the feedback signal (current) simultaneously reflects the integrated aging of the driving transistor Q1 and the OLED having the OLED. degree. Case 2, when the compensation signal detection module 303 is implemented by the analog voltage comparison module, the pixel unit 101 may be the circuit structure shown in FIG. 7(a), and the signal-cut-on conduction driving transistor Q1 may be written from the correction signal line.
  • the compensation signal detecting module 303 further includes a reference current generating module (not shown), which generates a fixed current flowing through the feedback signal line into the pixel unit 101 of the feedback address signal line, so that a fixed current flows through the organic light emitting diode OLED.
  • the voltage on the feedback signal line is detected to calculate the degree of aging of the organic light emitting diode OLED.
  • Case 3 when the compensation signal detection module 303 is implemented by the analog-to-digital conversion module, the pixel unit 101 may be the circuit structure shown in FIG. 7(a), if the analog correction signal written in the pixel unit 101 is uncompensated. During the voltage correction operation, the compensation signal detection module 303 will receive the current.
  • the feedback signal of the signal or voltage signal is obtained by analog-to-digital conversion to obtain the aging information of the pixel unit 101, and then output to the compensator 400 via the fourth shift register 307 to update the compensation information stored in the compensation information storage module 402.
  • the compensation signal detection module 303 may be mixed with the current comparison module, the voltage comparison module, or the analog to digital conversion module.
  • the row scan driver 200 is further configured to, according to the first embodiment, send the corrected address signal to the pixel matrix 100 through the corrected address line according to the set timing to strobe each row of pixels in a set order in one or more frame times.
  • the row of pixel units 101 receives the corresponding analog correction signal through the correction signal line, and before the analog correction signal drives the feedback signal generated by the row of pixel units 101 to disappear.
  • the row scan driver 200 sends a feedback address signal to the pixel matrix 100 through the feedback address line to strobe the feedback signal generated by the row of pixel units 101 to the column driver 300.
  • the compensation signal detection module 303 of the column driver 300 is transmitted.
  • the feedback signal includes aging information of the row of pixel units 101.
  • the compensator 400 of the embodiment is configured to receive the detection result of the compensation signal detecting module 303, and update the stored compensation information according to the result; when a row of the pixel unit 101 is gated by the display address signal, the compensator 400 takes out the storage thereof.
  • the display signal generating module 301 of the column driver 300 receives the compensation signal and combines it with the digital original display signal to form an analog display signal; when a certain row of pixel units 101 is gated by the corrected address
  • the compensator 400 takes out the compensation information of the row of pixel units 101 stored therein and calculates a digital correction compensation signal according to the compensation information or directly transmits the stored digital correction compensation signal to the third shift register 306 without calculation.
  • the correction signal generation module 302 of the column driver 300 receives the number from the correction signal generation module 302 of the column driver 300. After the correction signal is compensated with a fixed voltage which is combined to form an analog correction signal.
  • the embodiment further discloses a method for a peripheral compensation system of a pixel matrix, comprising the following steps:
  • Each row of pixel units 101 sequentially performs a display operation, wherein the nth row of pixel units 101 performs a display operation at t n : the row of pixel units 101 is gated by the display address signal, and receives an analog display signal, where n is less than or equal to N Positive integer
  • the i-th row of the pixel unit 101 performs a display operation, if the system is not in this case the peripheral compensation feedback detection state, when t i, i + k row of the pixel unit 101 performs a correction operation: this is the row of pixel units 101 Writing an analog correction signal; in the period t i+1 to t i+k-1 , the peripheral compensation system enters a feedback detection state: feeding back the feedback signal containing the aging information in the pixel unit 101 of the i+kth row to the compensation signal detection Block 303; wherein i and k are both positive integers, and i+k is less than or equal to N.
  • the pixel unit 101 of the i+1th row to the i+k-1th row performs a display operation as usual, and is written into an analog display signal;
  • the pixel unit 101 of the i+1+kth line to the i+k-1+kth line is written with an analog correction signal, and the analog correction signal is not used to drive the pixel unit 101 to generate a feedback signal including aging information; or The pixel unit 101 of the i+1+k line to the i+k-1+kth line does not write the analog correction signal.
  • one frame time may be divided into a plurality of equal line times t 1 to t N according to the number of rows of the pixel unit 101.
  • the subscript of t is negative, it indicates that the time represented by it is in the blank period between this frame and the previous frame. For example, if the first line time of a frame is t 1 , then t -1 , t The time represented by -2 and t -3 is located in the blank period of this frame and the previous frame, and is 1, 2, and 3 line times ahead of t 1 respectively; when the subscript of t is greater than N, it indicates that it is represented at this time. The time is in the blank time between this frame and the back frame.
  • t N+1 , t N+2 , and t N+3 represent The time is in the blank period of this frame and the last frame, and is delayed by 1, 2, and 3 line times respectively than t N .
  • FIG. 9(a), (b) and (c) are timing charts of the peripheral compensation system of the present embodiment, wherein the timing chart shown in Fig. 9(a) is a timing chart of the display operation, Fig. 9(b) and The timing shown in (c) is a timing chart of the correcting operation.
  • C indicates an analog correction signal
  • C1 indicates the simulation of the pixel unit 101 of the first row.
  • Correction signal similarly, F denotes a feedback signal, and F is followed by a sequence number, which indicates a feedback signal of the pixel unit 101 of the serial number row, for example, F1 indicates a feedback signal of the pixel unit 101 of the first row;
  • the display operation portion of this embodiment is the same as the display operation portion of the embodiment 1.
  • the row scan driver 200 sequentially strobes the pixel unit 101 row by row in a frame time. Each time the pixel unit 101 of one row is gated, the display signal generating module 301 of the column driver 300 generates a compensated analog display signal to the display signal. Line to write the analog display signal to the pixel unit 101 that is gated to this row.
  • the last row of pixel units 101 completes the display operation, there will be a blank time between the frame and the frame, and then the pixel unit 101 of the first row of the next frame starts to perform the display operation.
  • the corrected address line and the feedback address line are independent; the display signal line, the correction signal line and the feedback signal line are also independent, as shown in FIG. 6.
  • the correcting operation can also be performed separately from the display operation.
  • the correction operation section shown in Fig. 9(b) describes the waveforms of the corrected address line and the correction signal line.
  • the peripheral compensation system performs a display operation on the pixel unit 101 of the i-th row, if the peripheral compensation system at this moment In the feedback detection state, the pixel unit 101 of the i+kth row does not perform any correction operation; otherwise, the peripheral compensation system performs a correction operation on the pixel unit of the i+kth row, at i+1 line to i
  • the feedback detection is performed in the time of +k-1 lines, and the peripheral compensation system is in the feedback detection state during which the i and k are positive integers, and i+k is less than or equal to N.
  • the correcting operation includes the following steps. First, the pixel unit 101 of the i+3th row is gated through the corrected address line of the row scan driver 200, and the correction signal generating module 302 of the column driver 300 issues the i+3th row of pixel units.
  • the peripheral compensation system then enters the feedback detection state, and the line scan driver 200 strobes the pixel unit 101 of the i+3th row through the feedback address line, and the pixel unit 101 of the i+3th row starts to feed back the feedback signal to the feedback signal line, and the compensation signal detection module 303 of the column driver 300 accepts and detects the feedback signal.
  • the detection result is stored in the fourth shift register 307 in parallel before the end of the feedback detection state, and then serially transmitted to the compensator 400 to update the compensation information in the compensation information storage module 402.
  • the compensation information stored in the compensation information storage module 402 may be stored in the compensation information storage module 402 after being processed by the signal, or may be processed after the compensation information is read from the compensation information storage module 402. It is forwarded to the display signal generation module 301 or the correction signal generation module 302.
  • One of the compensation signal processing is to calculate the reference compensation information value from the detection result of the entire frame, and then store the relative compensation information of each pixel unit 101 into the compensation information storage module 402.
  • One purpose of using the reference compensation information value is to prevent the relative compensation information stored in the compensation information storage module 402 from overflowing as much as possible.
  • the pixel unit 101 of the i+kth row is performing the correcting operation.
  • the analog correction signal previously written to the pixel unit 101 is overwritten by the analog display signal written to the pixel unit 101 of the i+kth row. Since the analog correction signal only has a short k-line time, it does not have a significant effect on the normal display.
  • the organic light-emitting diode OLED may not be allowed to emit light in the feedback detection state. Specifically, a voltage value lower than a threshold voltage of the organic light-emitting diode OLED is given on the feedback signal line.
  • the pixel unit 101 of the first row of the frame performs the correcting operation at time t -3 , then in the next frame, the first row is not subjected to the correcting operation, but is started from the pixel unit 101 of the second row, and is corrected at time t -2 . Operation; in the next frame, the pixel unit 101 of the 1st row and the 2nd row does not perform the correcting operation, but starts from the pixel unit 101 of the 3rd row, performs a correcting operation at time t -1 ; and then returns to the next frame. From the pixel unit 101 of the first row, a correction operation is performed at time t -3 , and so on. The pixel unit 101 of all rows performs a correction operation in the k frame.
  • the ca+b row pixel unit 101 in the N rows of pixel units in the bth frame in the a frame, the ca+b row pixel unit 101 in the N rows of pixel units:
  • the feedback operation is performed in the [[c-1)a+b] to (ca+b-1) line time, that is, t [(c-1)a+b] to t (ca+b-1) ;
  • the display operation is performed in the [ca+b] line time.
  • a is an integer greater than or equal to 1 and less than or equal to N
  • b is an integer greater than or equal to 1 and less than or equal to a
  • c is an integer greater than or equal to 0, and ca+b is less than or equal to N.
  • the correction and feedback operation for all the pixel units 101 is completed by using a frame.
  • the ca+b row of pixel units 101 in the N rows of pixel units, as described above, is in the first [( C-1)a+b-1] is performed in t line time [[c-1)a+b-1] ; in [[c-1)a+b] to (ca+b- 1)
  • the feedback operation is performed in t line time t [(c-1)a+b] ⁇ t (ca+b-1) .
  • the time when the subscript of t is not positive, the time does not fall within the frame there may be several measures, one is to add before the last row of pixel units 101 of the pixel matrix 100 or after the last row of pixel units 101 A number of rows of useless pixel units 101 increase the time of the entire frame. For example, in the above example, three rows of pixel units 101 can be added; second, the correction and feedback time that does not fall within the frame can be placed in the frame. Go with the frame.
  • t X represents the Xth line time in the frame.
  • X takes a negative value, such as -3, -2, -1 in the graph, it indicates that t X is in the gap between this frame and the upper frame. period.
  • t 1 to t 10 respectively represent the first line time to the 10th line time in one frame, and the 10 line times constitute the time of the frame; and t -3 , t -2 , t -1 indicates the blank time period between this frame and the upper frame.
  • the 13 times of t -3 , t -2 , t -1 and t 1 to t 10 are equal times. Length, and from the time before and after the time, from t -3 to t -2 , then to t -1 , then to t 1 ⁇ t 10 .
  • Correction X indicates that the pixel unit 101 of the Xth row performs a correcting operation, for example, when X takes a value of 1, that is, corrects 1, which indicates that the pixel unit 101 of the first row performs a correcting operation.
  • the display X indicates that the pixel unit 101 of the Xth row performs a display operation. For example, when X takes a value of 1, a display 1 is displayed, which indicates that the pixel unit 101 of the first row performs a display operation.
  • Feedback X indicates that the feedback signal of the pixel unit 101 of the Xth row is sent to the feedback signal line connected to each pixel unit of the row of pixel units 101, for example, when X takes a value of 1, that is, feedback 1, which is represented by The feedback signal of the pixel unit 101 of the first row is transmitted to the feedback signal line connected to each pixel unit of the row of pixel units 101.
  • the correction X is not written in the following table, and the blank indicating X and the feedback X is indicated by the fact that a row of pixel units 101 corresponding to this blank space in the chart does not perform any operation within a certain line time.
  • k is taken as 3 in the following table, and it can be seen that after three frames of k frames, all the pixel units 101 of the row have undergone a correcting operation.
  • the k+1th frame after the k frame, that is, the fourth frame, the peripheral compensation system performs the correcting operation on the pixel unit 101 of the first row at the line time of t-3 of the frame.
  • another calibration operation method of this embodiment is to connect the corrected address signal line and the feedback address signal line, that is, simultaneously cut off the gate.
  • the positive address line and the feedback address line strobe or turn off the pixel unit 101 of the same row. It can be seen that the signal waveforms of the corrected address line and the feedback address line are the same.
  • the correcting operation of the row of pixel units 101 includes the following steps. First, the pixel unit 101 of the first row is gated through the corrected address line of the row scan driver 200, and the address signal is corrected to maintain three. Line time, from t -3 to t -1 .
  • the correction signal generation module 302 of the column driver 300 issues the analog correction signal corresponding to the pixel unit 101 of the first row to the correction signal line connected thereto.
  • the peripheral compensation system also gates the pixel unit 101 of the first row through the feedback address line of the row scan driver 200, and the peripheral compensation system enters the feedback detection state, and the feedback address signal also maintains three line times, from t -3 to t - 1.
  • the pixel unit 101 of the first row starts to feed back the feedback signal to the feedback signal line, and the compensation signal detection module 303 of the driver 300 accepts and detects the feedback signal, and the detection result is stored in the fourth state before the end of the feedback detection state.
  • the shift register 307 is serially transmitted to the compensator 400 to update the compensation information in the compensation information storage module 402.
  • This embodiment discloses a peripheral compensation system.
  • the correction address signal and the display address signal can be time-multiplexed to display the address line of the line scan driver 200, and the analog correction signal and the simulation can be performed.
  • the display signal time division multiplexes the display signal lines of the column driver 300.
  • the line scan driver 200 transmits the corrected address signal or the display address signal to the display address line in a time division manner
  • the column driver 300 transmits the analog correction signal and the analog display signal to the display signal line in a time division manner.
  • FIG. 11 is two circuit configurations of the pixel unit 101 in this embodiment.
  • the pixel unit 101 includes a driving transistor Q1, a display switching transistor Q2, a feedback switching transistor Q4, a storage capacitor C, and an organic light emitting diode OLED.
  • the display switching transistor Q2 is gated by the correction address signal sent from the display address line to send the analog correction signal received from the display signal line to the driving transistor Q1, and stored in the storage capacitor C, and the driving transistor Q1 receives the analog correction signal.
  • a feedback signal is generated and sent to the feedback switching transistor Q4, before the address line is sent to the analog display signal and the feedback signal does not disappear (ie, before the analog display signal is written and the feedback signal does not disappear), the line scan driver 200 sends a feedback address signal to gate the feedback switching transistor Q4, and a voltage is input from the feedback line to the anode of the light emitting diode OLED, and the voltage is set lower than the threshold voltage of the light emitting diode OLED to ensure that the light emitting diode OLED is not turned on, The feedback current of the driving transistor Q1 will all flow to the feedback signal line, so that the received feedback signal is sent to the compensation signal detecting module 303.
  • the display switching transistor Q2 is again strobed by the display address signal sent from the display address line to receive the analog display from the display signal line.
  • the signal is sent to the driving transistor Q1, and the driving transistor Q1 receives the analog display signal to drive the organic light emitting diode OLED to emit light corresponding to the analog display signal.
  • one pole of the feedback switching transistor Q4 of FIG. 11(b) is not connected to the anode of the organic light emitting diode OLED, but is connected to a photosensitive element GL, and the photosensitive element GL is used for the organic light emitting diode.
  • the optical signal of the OLED is converted into an electrical signal, and the feedback signal transmitted through the feedback signal line in FIG. 11(b) includes aging information of both the driving transistor Q1 and the organic light emitting diode OLED.
  • the correction signal generating module 302 can time-multiplex the second digital-to-analog module 312 of the display signal generating module 301 and the first analog adding module 313.
  • the input of the third digital-to-analog conversion module 321 is a digital correction compensation signal whose reference potential is a set fixed voltage; the first relates to the first embodiment
  • the two digital-to-analog conversion module 312, the second digital-to-analog conversion module 312, and the third digital-to-analog conversion module 321 are all digital-to-analog conversion modules, and the inputs are all digital correction compensation signals, the only difference being the reference potential of the two.
  • the second digital-to-analog conversion module 312 and the third digital-to-analog conversion module 321 can be the same digital-to-analog conversion module, and the analog correction signal and the analog display signal are time-multiplexed by the digital-to-analog conversion module through a certain timing relationship.
  • the reference potential of the multiplexed digital-to-analog conversion module becomes a fixed voltage set when the analog correction signal is generated, and the reference potential of the multiplexed digital-to-analog conversion module is required when an analog display signal needs to be generated. Change back.
  • the second digital-to-analog conversion module 312 and the third digital-to-analog conversion module 321 time-multiplex the same digital-to-analog conversion module, thereby achieving the purpose of saving the device and simplifying the circuit.
  • Another implementation of the correction signal generation module 302 is that the first analog addition module 313 and the second are in addition to the second digital to analog conversion module 312 and the third digital to analog conversion module 321 which are time-multiplexed with the same digital to analog conversion module.
  • the analog addition module 322 can also be time division multiplexed.
  • the display signal generating module 301 and the correction signal generating module 302 can also time-multiplex the display signal generating module 301, that is, the display signal generating module 301 generates the analog display signal and the analog correction signal in a time-sharing manner.
  • the input of the display signal generating module 301 is a digital original display signal and a digital display compensation signal, and the digital display display signal is compensated by the digital display compensation signal to obtain an analog display signal, and the correction signal generation module 302 inputs a fixed voltage and a digital correction compensation signal.
  • the digital correction compensation signal compensates the fixed voltage to obtain an analog correction signal.
  • the digital correction compensation signal is input to the display generation module 301 instead of the digital display compensation signal. Or directly using the digital display compensation signal as a digital correction compensation signal, and simultaneously inputting the signal content of the digital original signal into a fixed voltage and inputting it to the display generation module 301, so that the display generation module 301 outputs the analog correction signal. .
  • the peripheral compensation system can also directly use the analog display signal previously written into the pixel unit 101 as an analog correction signal, so that the correction signal generation module 302 is not needed, and the pixel unit 101 does not feed back an expected feedback signal, and the compensation signal detection module 303 need
  • An analog to digital converter converts the feedback signal into a digital signal and compares it with the expected signal.
  • the expected signal is not fixed and the number of expected signals is the same as the number of analog display signals.
  • the difference from the second embodiment is that in the embodiment, the address signal and the correction address signal are displayed in a time division multiplexed display address line, and the display signal line and the correction signal line are time-multiplexed to display the signal line. Therefore, the waveform of the display address line in this embodiment is basically a waveform in which the waveform of the corrected address line is merged into the waveform of the display address line and then moved to the left by half a line time in the second embodiment.
  • the reason why the half line time is shifted is because the peripheral compensation system of this embodiment needs to complete writing the analog correction signal to the i+k line and the analog display signal to the i-th line in one line time, and can write first.
  • the analog correction signal can also be written to the analog display signal first.
  • the analog correction signal is written at the time of the first half of the line time and then the analog display signal is written in the second half of the line time.
  • the pixel unit 101 when the pixel unit is gated by the display address line, it is secondary, and it is determined what signal is written into the pixel unit 101.
  • the data signal terminal is sent to the display signal. What is the signal on the line (analog correction signal or analog display signal).
  • the address line 1 (the display address line connected to the pixel unit 101 of the first row) has two square waves, and the first square wave represents the corrected address signal for strobing the first line.
  • the pixel unit 101 writes an analog correction signal on the display signal line to the pixel unit 101.
  • the correction address signal has opened the display address line (the level of the display address line is high) after half time of the time t -4 , and the specific opening time can be adjusted according to the load size of the display address line, and the load can be large.
  • the data signal terminal sends an analog correction signal to the display signal line.
  • the second square wave is a display address line signal for strobing the pixel unit 101 and writing an analog display signal, the analog display signal overwriting the analog correction signal previously written to the pixel unit 101, and the column driver 300 is The analog display signal is sent to the display signal line through the data signal terminal before the display address line signal is turned off.
  • the peripheral compensation system may be in a feedback detection state after the line scan driver 200 transmits the current correction address signal and before the next correction address signal is issued, during which the column driver 300 may not issue any analog correction signal to the data signal line.
  • FIG. 12 (a) at time t 1, the external compensation system is completed within a time correction operation and the display operation, the correction operation is completed in the first half of the line time t 1, the display operation in the latter half of line 1 t time carry out.
  • the pixel unit 101 line scanning driver 200, the gate line 4, column driver 300 will line scan driver 200 off display address lines of the pixel unit is selected through the fourth row 101, by The data signal terminal and the display signal line complete the transmission of the analog correction signal to the pixel unit 101 of the fourth row, as shown by C4 in the figure.
  • the analog correction signal is maintained at least until the display address line time of the pixel unit 101 of the fourth row of the row scanner driver 200 is turned off, and the pixel unit is written while the display address line of the pixel unit 101 of the fourth row is turned off.
  • the analog correction signal C4 of 101 is also stored in the gate of the driving transistor Q1 of the pixel unit 101, the peripheral compensation system enters the feedback detection state, and the row scanning driver 200 turns on the feedback address line of the pixel unit 101 of the fourth row, and the pixel unit of the row is A feedback signal containing 101 aging information is sent to the feedback signal line, and the compensation signal detection module 303 of the column driver 300 receives the feedback signal.
  • the line scanning driver 200 displays the scan signal 1 to the terminal 1 transmits the address line display address signal to gate the pixel unit 101 of the first row, the column driver 300 issues to the data signal terminal of the first
  • the analog display signal L1 of the row pixel unit 101 maintains at least the line scan driver 200 off the gate display address line.
  • the line scanning driver 200 while a gate and a fourth row of pixel cells in the first row, then what signals written in the pixel unit 101 mainly depends on the cut-off gate 101 when the pixel data signal of a line unit Terminal and display signals on the signal line.
  • the feedback signal in the present application includes aging information as described above, and the aging information refers to information formed by the aging of the pixel unit 101 during the use of the original state unevenness and the use of the aging state, and the original state can be regarded as The initial aging information generated by the manufacturing process or the like when the pixel unit 101 is not used at the factory, that is, if the aging information is regarded as a function of time, the original state is the value of the aging information when the time is the factory time.

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Abstract

提供了一种像素矩阵（100）的外围补偿系统、方法和显示系统。外围补偿系统包括：行扫描驱动器(200)、补偿器(400)、列驱动器(300)，列驱动器(300)包括显示信号产生模块(301)，显示信号产生模块(301)包括具有伽马校正功能的第一数模转换模块(311)、第二数模转换模块(312)和第一模拟加法模块(313)。因此，在对数字原始信号进行了精确伽马校正的同时，结构简单，第一数模转换模块的位数低，还可以在显示系统显示的时候进行校正操作，从而可以极大限度的增加补偿信息的刷新频率。

Description

一种像素矩阵的外围补偿系统、方法和显示系统 技术领域
本发明涉及显示技术领域，尤其涉及像素矩阵的外围补偿系统、方法和显示系统。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)因具有高亮度、高发光效率、宽视角和低功耗等优点，近年来被人们广泛研究，并被迅速应用到新一代的显示系统当中。有机发光二极管的驱动方式分为无源矩阵驱动(Passive Matrix OLED，PMOLED)和有源矩阵驱动(Active Matrix OLED，AMOLED)两种。无源矩阵驱动的方式虽然成本低廉，但是存在交叉串扰现象因而不能实现高分辨率的显示，另外，无源矩阵驱动电流大，会降低有机发光二极管的使用寿命。相比之下，有源矩阵驱动的方式是在像素矩阵的每个像素单元上设置数目不同的晶体管作为电流源，从而避免了交叉串扰，实现了高分辨的显示，另外有源矩阵驱动电流又较小，功耗较低，使有机发光二极管的寿命增加。
其中一种有源矩阵驱动的像素单元是两薄膜场效应晶体管(Thin Film Transistor，TFT)结构，该像素单元包括驱动晶体管、显示开关晶体管、存储电容和有机发光二极管。显示开关晶体管响应来自显示地址线的信号，采样来自显示信号线的信号。存储电容在显示开关晶体管关断后保存所采样的显示信号线的信号电压。驱动晶体管在给定的发光期间根据存储电容所保留的输入电压来供应输出电流。有机发光二极管通过来自驱动晶体管的输出电流来发出其亮度与显示信号线的信号相称的光。根据薄膜场效应晶体管的电压电流公式，驱动电流IDS可以表示为：
IDS＝1/2μnCoxW/L(VG-VOLED-VTH)2... ...  (1)
其中，IDS为驱动晶体管的漏极流向源极的漏极电流，μn为薄膜场效应晶体管的有效迁移率，Cox为薄膜场效应晶体管单位面积的栅电容，W为薄膜场效应晶体管的有效沟道宽度，L为薄膜场效应晶体管的有效沟道长度，VG为薄膜场效应晶体管的栅极电压，VOLED是有机发光二极管上的偏置电压，VTH为薄膜场效应晶体管的阈值电压，VOLED与有机发光二极管OLED的阈值电压相关。
上述的有源矩阵驱动的像素单元的两薄膜场效应晶体管的结构电路，这种电路虽然简单，但随着时间的推移，其中的元件会老化，尤其是驱动晶体管和有机发光二极管会老化，直接后果就是驱动晶体管和有 机发光二极管的阈值电压都会产生漂移，并且像素矩阵中各处像素单元的驱动晶体管和有机发光二极管的阈值电压漂移情况也是不一样的；另外，因薄膜场效应晶体管采用多晶硅材料制成，从而会导致像素矩阵中各个像素单元的驱动晶体管的阈值电压VTH具有不均匀性的特性；以上两种情况，根据公式(1)可知，驱动电流IDS这时都会发生改变，这样就会造成像素矩阵显示的不均匀性。
针对这种驱动晶体管和有机发光二极管的阈值电压漂移和不均匀性带来的像素矩阵显示不均匀的问题，目前出现两类对阈值电压进行补偿的方法：像素单元内补偿和外围补偿。像素单元内补偿就是通过复杂的像素单元电路结构为有机发光二极管提供一个恒定的驱动电流，这种方法的电路不仅复杂，而且电路复杂又进一步会造成像素单元的开口率和良率下降；外围补偿相比来说可以采用更简单的像素单元结构，因此更适合产业化应用。
发明内容
本申请提供一种像素矩阵的外围补偿系统、方法和显示系统，实现了精确的像素单元的外围补偿。
根据本申请的第一方面，本申请提供一种像素矩阵的外围补偿系统，所述像素矩阵100包括N行M列像素单元101、N行显示地址线和M列显示信号线，像素单元101和各自的显示地址线、显示信号线分别连接，N和M均为正整数，所述外围补偿系统包括：行扫描驱动器200，用于通过显示地址线向像素矩阵100发送显示地址信号以在一帧内依次选通各行像素单元101；
补偿器400，包括储存补偿信息的补偿信息储存模块402，所述补偿器400用于向列驱动器300发送数字显示补偿信号，当某行像素单元101被显示地址信号选通时，补偿器400发出相对应的所述数字显示补偿信号以补偿像素单元101图像视频信息显示不精确的问题；
列驱动器300，包括显示信号产生模块301，用于向像素矩阵100发送模拟显示信号，所述模拟显示信号用于为像素单元101的显示信号线提供包含图像视频信息的显示数据；所述显示信号产生模块301包括具有伽马校正功能的第一数模转换模块311、第二数模转换模块312和第一模拟加法模块313；当某行像素单元101被显示地址信号选通时，第一数模转换模块311接收该行数字原始显示信号，输出经过伽马校正的模拟原始显示信号给第一模拟加法模块313；第二数模转换模块312接收所述相对应的数字显示补偿信号，输出模拟显示补偿信号给第一模拟加法模块313；第一模拟加法模块313将模拟显示补偿信号和经过伽马校正的模拟原始显示信号进行模拟加法运算后输出模拟显示信号给 像素矩阵100；还包括第一移位暂存器304和第二移位暂存器305，所述第一移位暂存器304接收外界的数字原始显示信号并转递给第一数模转换模块311，所述第二移位暂存器305接收补偿器400发出的数字显示补偿信号并转递给第二数模转换模块312。
根据本申请的第二方面，本申请提供一种像素矩阵的外围补偿系统的方法，所述像素矩阵100包括N行M列像素单元101、N行显示地址线和M列显示信号线，像素单元101和各自的显示地址线、显示信号线分别连接，N和M均为正整数，所述方法包括：
一帧时间由N个相等的行时间t1～tN组成，每行像素单元101依次进行显示操作，其中第n行像素单元101在tn时进行显示操作：此行像素单元101被显示地址信号选通，接收模拟显示信号，其中n为小于或等于N的正整数；
在ti时，第i行像素单元101进行显示操作，若此时外围补偿系统不是处于反馈检测状态，则ti时，第i+k行像素单元101进行校正操作：此行像素单元101被写入模拟校正信号；第ti+1到ti+k-1时间内，外围补偿系统进入反馈检测状态：将第i+k行像素单元101中包含老化信息的反馈信号反馈至补偿信号检测摸块303；其中i和k都为正整数，且i+k小于或等于N。
根据本申请的第三方面，本申请提供一种显示系统，包括上述的外围补偿系统以及像素矩阵100。
用外围补偿方法的显示系统需要在显示屏驱动芯片为每个像素单元做补偿，由于原有模拟显示信号是带有伽马校正的，补偿之后是需要保留本来的伽马校正，现有技术是用数字的方法将数字原始显示信号和数字显示补偿信号先相加再经线性的数模转换模块做数模转换，用数字的方法实现伽马校正。这种数字实现伽马校正的方法，相对传统模拟方法，所需要每个阶的电压非常小。也就是需要数模转换模块的位数比较多，而且再多的位数也还是只能做出接近模拟数模转换的精度。本申请的外围补偿系统、方法和显示系统，由于引入了第一模拟加法模块和具有伽马校正功能的第一数模转换模块，使得对数字原始信号进行了补偿的同时保持了精确的伽马校正，结构保持简单，同时第一数模转换模块的位数也低；
外围补偿系统的方法一般是需要反馈检测像素单元的老化信息，接着再对数字原始显示信号做补偿。现有技术反馈检测的操做一般是在帧与帧之间空白时段进行。因为帧与帧之间空白时段相对显示时段要少很多，导致补偿信息刷新的频率就比较慢。本申请的外围补偿系统、方法和显示系统，可以实现在帧中间，显示系统显示的时候进行校正操作， 这样就可以极大限度的增加补偿信息的刷新频率，或者保持跟现有技术一样的刷新频率让多列共享一个补偿信号检测模块。
附图说明
图1为本申请的第一种实施例中显示系统的一种结构示意图；
图2为本申请的第一种实施例中像素单元的一种结构示意图；
图3为本申请的一种实施例中各像素单元的老化程度分布图；
图4为本申请的第一种实施例中显示信号产生模块的一种结构示意图；
图5为本申请的第一种实施例中外围补偿系统的一种时序图；
图6为本申请的第二种实施例中显示系统的一种结构示意图；
图7为本申请的第二种实施例中像素单元的四种结构示意图；
图8为本申请的第二种实施例中校正信号产生模块的二种结构示意图；
图9(a)、(b)和(c)为本申请的第二种实施例中外围补偿系统的一种时序图；
图9(d)和(e)为本申请的第二种实施例中外围补偿系统的另一种时序图；
图10为本申请的第三种实施例中显示系统的一种结构示意图；
图11为本申请的第三种实施例中像素单元的两种结构示意图；
图12(a)和(b)为本申请的第三种实施例中外围补偿系统的一种时序图。
具体实施方式
下面通过具体实施方式结合附图对本申请作进一步详细说明。
实施例一
在一个实施例中，请参考图1，本实施例为显示系统，包括一像素矩阵100和此像素矩阵100的外围补偿系统(以下简称外围补偿系统)。
此像素矩阵100包括N行M列像素单元101、N行显示地址线和M列显示信号线，像素单元101和各自的显示地址线、显示信号线分别连接，N和M均为正整数。图1只画了4个像素单元为例子，分别在位置[1,1]即第1行第1列，[N,1]即第N行第1列，[1,M]即第1行第M列，和[N,M]即第N行第M列。
像素单元101有多种电路，其中的一种电路结构可为图2中的电路，其包括驱动晶体管Q1、显示开关晶体管Q2、存储电容C和有机发光二极管OLED。
显示开关晶体管Q2被来自显示地址线的显示地址信号选通以将来自显示信号线的显示信号发给驱动晶体管Q1，存储电容C同时会将此模拟显示信号存储，以在一帧时间内在显示开关晶体管Q2被关断后仍然将稳定的模拟显示信号供给驱动晶体管Q1，驱动晶体管Q1接收模拟显示信号来驱动有机发光二极管OLED发出与模拟显示信号相对应的光，这里模拟显示信号指的是包含图像视频的数据信号。
上述的驱动晶体管Q1、显示开关晶体管Q2等晶体管，可以采用非晶硅、多晶硅、氧化物半导体、有机半导体、NMOS/PMOS工艺或者CMOS工艺来制造。
返回参考图1，此像素矩阵100外围补偿系统包括行扫描驱动器200、补偿器400和列驱动器300。
行扫描驱动器200用于通过显示地址线向像素矩阵100发送显示地址信号以在一帧内依次选通各行像素单元101。
补偿器400包括储存补偿信息的补偿信息储存模402，用于向列驱动器300发送数字显示补偿信号，当某行像素单元101被显示地址信号选通时，补偿器400从补偿信息存储模块402中读取相对应行的补偿信息再计算数字显示补偿信号传到列驱动300里的第二移位暂存器305，之后再传给显示信号产生模块301，此数字显示补偿信号用于补偿像素单元101因原始状态不平均以及老化而产生的图像视频信息显示不精确的问题。像素单元101的原始状态是指驱动晶体管Q1和有机发光二极管OLED的原始阈值电压，以及有机发光二极管OLED的原始发光效率。像素单元101的老化是指像素单元101在使用之后，驱动晶体管Q1和有机发光二极管OLED的阈值电压发生飘移，以及有机发光二极管OLED的发光效率发生变化。当显示系统在正式使用前，补偿信息储存模块402储存的是各像素单元101的原始状态，在使用之后，外围补偿系统会根据各像素单元101使用后的老化情况更新补偿信息储存模块402里的补偿信息。补偿器400里的补偿信息储存模块402可以是一个，也可以是两个，还可以是两个以上的记忆体组成。如果补偿信息储存模块402是一个记忆体组成，那显示系统出厂时，此记忆体储存的是各像素单元101的原始状态，当使用后其会根据老化情况更新记忆体内的补偿信息；如果是两个或以上，那像素单元101各种原始状态和各种老化情况可以选择性地分开储存，如其中一个记忆体储存驱动晶体管Q1相关的补偿信息，另一个记忆体储存发光二极管OLED相关的补偿信息；又或者一个记忆体储存像素单元101的原始状态信息，另一个记忆体储存像素单元101使用后的老化数据等等。这里的记忆体指的是存储介质。
有关各像素单元101的原始状态的数字补偿信息其中一种产生方法是可以在显示系统出厂时让测试用的驱动芯片向所有像素单元101写入 相同的电压，再用光学仪器来检测显示系统所有像素单元101的发光亮度，把亮度上的不平均转换成补偿信息储存于补偿器400里的补偿信息储存模块402。这时被存储的补偿信息就表征了各像素单元101的原始状态，因为各像素单元101亮度上的不平均表征了像素单元101原始状态的不平均。
在显示系统使用后提取老化信息的一种方法是在外围补偿系统内根据每个像素单元101的使用情况计算老化程度，比如利用各像素单元101发光的时间和显示的灰阶(也就是亮度)计算老化程度，再更新补偿信息储存模块402里的补偿信息。老化相关的补偿信息是通过对像素单元101老化特性曲线进行拟合和数学建模而得到；即像素单元101的使用情况对应一个补偿信息的值，这个补偿信息的值又对应一个数字显示补偿信号，这样补偿器400通过根据像素单元101的使用情况来更新补偿信息储存模块402内的补偿信息。
请参考图3，为像素单元101的补偿信息的储存方式，图中横坐标表示不同的像素单元101，总共有N*M个像素单元101，为了便于画图，图3只画出了7个像素单元101的绝对补偿信息。图3的纵坐标为各像素单元101的绝对数字补偿信息值，需要说明的是，像素单元101的绝对补偿信息的物理量表征可以是驱动晶体管Q1的阈值电压，和/或有机发光二极管OLED的阈值电压，和/或有机发光二极管OLED的发光效率。为了节省储存空间，补偿信息储存模块402只储存各像素单元的绝对补偿信息值与参考补偿信息值之间的差值。图3中显示了图中编号为1的像素单元101和参考补偿信息值之间的差值ΔV，在一个较优的实施例中，参考补偿信息值可以是低于像素单元101的绝对补偿信息的最低值。参考补偿信息值是根据整体所有像素单元的绝对补偿信息值已拟定的，当整体像素单元的绝对补偿信息值变大是，参考补偿信息值也会跟着变大。
请返回参考图1，列驱动器300包括第一移位暂存器304和第二移位暂存器305，以及显示信号产生模块301。第一移位暂存器304一个信号一个信号地接收数字原始显示信号，相应地，第二移位暂存器305也是一个信号一个信号地接收数字显示补偿信号，第一移位暂存器304和第二移位暂存器305接收完一行像素单元101的数字原始显示信号和数字显示补偿信号之后会并行输出给显示信号产生模块301，显示信号产生模块301接收到上述数字原始显示信号和数字显示补偿信号后，再向像素矩阵100发送模拟显示信号，此模拟显示信号用于为像素单元101的显示信号线提供包含精确图像视频信息的显示数据。
请参考图4，显示信号产生模块301包括具有伽马校正功能的第一数模转换模块311、第二数模转换模块312和第一模拟加法模块313；当 某行像素单元101被显示地址信号选通时，第一数模转换模块311接收数字原始显示信号，输出经过伽马校正的模拟原始显示信号给第一模拟加法模块313，其中第一数模转换模块311对数字原始显示信号的处理，即数模转换和伽马校正为同一过程，即不是对数字原始显示信号先进行伽马校正再进行数模转换，也不是对数字原始显示信号先进行数模转换再进行伽马校正；第二数模转换模块312接收数字显示补偿信号，输出模拟显示补偿信号给第一模拟加法模块313；第一模拟加法模块313将模拟显示补偿信号和经过伽马校正的模拟原始显示信号进行模拟加法运算后输出模拟显示信号给像素矩阵100。若显示系统可以直接提供模拟显示补偿信号给第一加法模块313的话，则显示系统可以不包括第二数模转换模块312。
请参照图5，为本实施例中外围补偿系统的显示地址线和显示信号线的波形图。不妨令N＝768，M＝1024。显示地址线1是用来选通第1行像素单元101的显示地址线，显示地址线2是用来选通第2行像素单元101的显示地址线，依此类推，显示地址线N是用来选通第N行像素单元101的显示地址线。图5中显示信号线上的信号L1是代表第1行所有像素单元101被补偿后的模拟显示信号，即信号L1包含了显示信号线1到显示信号线M的模拟显示信号。在本实施例中，像素单元101是在显示地址线为高电平时选通。行扫描驱动器200通过显示地址线1～N，从第1行开始，按顺序依次选通各行像素单元101，当选通完最后一行像素单元101，即第N行像素单元101之后，会是一段帧与帧之间的空白时期，之后又开始扫下一帧的第一行像素单元101。行扫描驱动器200每选通一行像素单元101，列驱动器300就会把相应的被补偿过的模拟显示信号传输到显示信号线上。显示信号线上的模拟显示信号至少会维持到行扫描驱动器200截止选通该行像素单元101为止。
实施例二
本实施例公开了一种外围补偿系统。
为了进一步提高模拟显示信号的精确性，本实施例中列驱动器300还发出一模拟校正信号给像素矩阵100，像素矩阵100发出一反馈信号，用来更新补偿器400中存储的补偿信息，再根据补偿信息计算出一数字显示补偿信号，通过更新的补偿信息计算得到的数字显示补偿信号比实施例一中的数字显示补偿信号更为精确。
请参照图6，为本实施例中显示系统包括像素矩阵100和此像素矩阵100的外围补偿系统。
像素矩阵100包括N行M列像素单元101、N行显示地址线、N行校正地址线、N行反馈地址线、M列显示信号线、M列校正信号线和M 条反馈信号线，像素单元101和各自的显示地址线、校正地址线、反馈地址线、显示信号线、校正信号线和反馈信号线分别连接，其中N和M均为正整数。
像素单元101有多种电路结构。以下试举几例。
如图7(a)所示，像素单元101包括驱动晶体管Q1、显示开关晶体管Q2、校正开关晶体管Q3、反馈开关晶体管Q4、存储电容C和有机发光二极管OLED。
校正开关晶体管Q3被从校正地址线传送过来的校正地址信号选通以将来自校正信号线的模拟校正信号发给驱动晶体管Q1，存储电容C同时会将此模拟校正信号存储，以在模拟校正信号被模拟显示信号覆盖之前和在校正开关晶体管Q3被关断后仍然将稳定的模拟校正信号供给驱动晶体管Q1，随后列驱动300的反馈信号检测模块303会赋予反馈信号线一电压，该电压会设置低于发光二级管OLED的阈值电压，以确保发光二极管OLED没有被导通，反馈开关晶体管Q4被从反馈地址信号线上的反馈地址信号选通时，该电压会输入到发光二极管OLED的阳极，关闭发光二极管OLED。此时，由于外围补偿系统知道驱动晶体管Q1的栅源电压差，会预期该像素单元101会反馈某个预期电流，驱动晶体管Q1管导通，发光二极管OLED截至，驱动晶体管Q1的反馈电流会经反馈开关晶体管Q4流到反馈信号线，再被列驱动器300的补偿信号检测模块303接收。补偿信号检测模块303会将反馈电流和预期的电流做比较。反馈开关晶体管Q4会持续被导通直至补偿信号检测模块303完成反馈电流检测。检测像素单元101的发光二极管OLED阈值电压可以用以下方法，通过校正地址线和校正信号线输入低于驱动晶体管Q1的阈值电压截至驱动晶体管Q1，再通过反馈地址线选通反馈开关晶体管Q4，补偿信号检测模块303可以通过反馈信号线赋予发光二极管OLED一固定电流，再检测反馈信号线上的电压计算发光二极管OLED的老化程度，或阈值电压漂移程度，也可以估算发光效率的变化。反馈信号检测完毕之后，显示开关晶体管Q2被来自显示地址线的显示地址信号选通以将来自显示信号线的模拟显示信号发给驱动晶体管Q1，存储电容C同时会将此模拟显示信号存储，以在一帧时间内在显示开关晶体管Q2被关断后仍然将稳定的模拟显示信号供给驱动晶体管Q1，驱动晶体管Q1接收模拟显示信号来驱动有机发光二极管OLED发出与模拟显示信号相对应的光。
图7(b)的有机发光二极管OLED的阳极与电源相连，阴极与驱动晶体管Q1的第一极相连，图7(b)中经反馈信号线传递出来的反馈信号包括了驱动晶体管Q1和有机发光二极管OLED两者的老化信息，图中晶体管Q4为P型晶体管，晶体管Q5为N型晶体管，从而反馈地址 信号使晶体管Q4导通，晶体管Q5闭合。图7(d)与图7(b)相比，图7(d)中晶体管Q4和Q5还可以同时为N型晶体管，此时晶体管Q4的栅极接到反馈地址线，而晶体管Q5的栅级接到一根“额外反馈地址线”，反馈地址线中信号为反馈地址信号，而额外反馈地址线中的信号为与反馈地址信号相反的信号，即当反馈地址线为高时，额外反馈地址线为低，当反馈地址线为低时，额外反馈地址线为高。
与图7(a)相比，图7(c)的反馈开关晶体管Q4的一极不是连接到有机发光二极管OLED的阳极，而是连接到一感光元件GL上，感光元件GL用于将有机发光二极管OLED的光信号转变为电信号，图7(c)中经反馈信号线传递出来的反馈信号包括了驱动晶体管Q1和有机发光二极管OLED两者的老化信息。
像素单元101的电路结构可以有多种，比如像素单元101可以有不同的控制线，而不局限于只连接显示地址线，校正地址线和反馈地址线；显示地址线，校正地址线和反馈地址线上的信号波形可以有各种形状，也不局限于方波。
请返回参考图6，与实施例一相比，列驱动器300还包括校正信号产生模块302和补偿信号检测模块303，以及第三移位暂存器306和第四移位暂存器307。
校正信号产生模块302向像素矩阵100发送模拟校正信号，模拟校正信号用于驱动像素单元101产生一包含老化信息的反馈信号。这里的模拟校正信号可以为一固定电压信号，也可以为一固定电压信号与数字校正补偿信号相结合而形成的信号，根据模拟校正信号的类型不同，相应地，校正信号产生模块302有不同的实现方式。
当模拟校正信号为一固定电压信号时，校正信号产生模块302包括一产生固定电压信号作为模拟校正信号的模块。由于模拟校正信号是一固定信号，因此像素单元101会因老化程度或原始状态的不同而反馈不同大小的电压或电流信号，此不同大小的电压或电流信号即为反馈信号，可以表征像素单元101的老化程度。
当模拟校正信号为一固定电压信号与数字校正补偿信号相结合而形成的信号时，像素单元101会反馈一个预期的信号(电压或电流)。校正信号产生模块302有几种实现方式，以下试举两种：
请参考图8(a)，是校正信号产生模块302的一种实现方式，此时其产生的模拟校正信号为一固定电压信号与数字校正补偿信号相结合而形成的信号。校正信号产生模块302包括第三数模转换模块321；第三数模转换模块321分别输入数字校正补偿信号和参考电压，经处理后输出模拟校正信号，其中参考电压为一设定的固定电压。因此当模拟校正信号为一固定电压信号与数字校正补偿信号相结合而形成的信号时， 此模拟校正信号实际上也就是上述固定电压信号经过数字校正补偿信号的补偿后而形成的一个信号。
请参考图8(b)，是校正信号产生模块302的另一种实现方式，此时其产生的模拟校正信号为一固定电压信号与数字校正补偿信号相结合而形成的信号。校正信号产生模块302包括第三数模转换模块321和第二模拟加法模块322；第三数模转换模块321输入数字校正补偿信号，经处理后输出模拟校正补偿信号给第二模拟加法模块322，第二模拟加法模块322还输入一固定电压信号，第二模拟加法模块322将模拟校正补偿信号与固定电压信号进行加法运算后输出模拟校正信号。
补偿信号检测模块303的输入端与反馈信号线相连，输出端连到第四移位暂存器307的输入端，第四移位暂存器307的输出端与补偿器400相连。补偿信号检测模块303当某行像素单元101被反馈地址信号选通时，接收此行像素单元101发出的反馈信号，从反馈信号中得出老化信息，并用该老化信息更新补偿信息存储模块402存储的此行像素单元101的补偿信息。补偿信号检测模块303可以通过模拟电流比较模块、模拟电压比较模块或模数转换模块这三者中的任一者来实现。情况一，例如当补偿信号检测模块303用模拟电流比较模块来实现时，校正操作时模拟校正信号是经过补偿的固定电压，不妨令像素单元101是图7(a)所示的电路结构，像素单元会反馈一个预期的反馈信号，补偿信号检测模块303将接收到的反馈信号(电流)与一预期信号(参考电流)比较来判断像素单元101的老化程度(驱动晶体管Q1老化程度)是否发生变化，并将结果通过第四移位暂存器307输出到补偿器400以更新补偿信息存储模块402中存储的补偿信息。图7(a)的电路结构令从像素单元101反馈到补偿信号检测模块303的电流只流经像素单元101的驱动晶体管Q1，那反馈信号(电流)就只能反映驱动晶体管的老化程度；如果像素单元101是其他电路结构而该结构可以令反馈信号(电流)流经驱动晶体管Q1和有机发光二极管OLED，那么反馈信号(电流)就同时反映了驱动晶体管Q1和有极发光二极管OLED的综合老化程度。情况2，当补偿信号检测模块303用模拟电压比较模块来实现时，不妨令像素单元101是图7(a)所示的电路结构，可以先从校正信号线写入信号截止导通驱动晶体管Q1，补偿信号检测模块303还包括参考电流产生模块(无图)，其产生一固定电流通过反馈信号线流入反馈地址信号线所选通的像素单元101，让固定电流流经有机发光二极管OLED后再检测反馈信号线上的电压，来计算有机发光二极管OLED的老化程度。情况3，当补偿信号检测模块303用模数转换模块实现时，不妨令像素单元101是图7(a)所示的电路结构，如果写入像素单元101的模拟校正信号是没有经过补偿的固定电压，校正操作时，补偿信号检测模块303将接收到的为电流 信号或电压信号的反馈信号通过模数转换之后得到像素单元101的老化信息，再经第四移位暂存器307输出给补偿器400以更新补偿信息存储模块402中存储的补偿信息。补偿信号检测模块303的实现方式除了以上3种情况，也可以是按实际需要混合搭配电流比较模块、电压比较模块或模数转换模块等。
行扫描驱动器200，在实施例一的基础上，还用于按照设定的时序通过校正地址线向像素矩阵100发送校正地址信号以在一帧或多帧时间内按照设定顺序选通各行像素单元101；当某行像素单元101被校正地址信号选通时，该行像素单元101通过校正信号线接收相对应的模拟校正信号，在模拟校正信号驱动该行像素单元101产生的反馈信号消失前，行扫描驱动器200通过反馈地址线向像素矩阵100发送反馈地址信号以选通此行像素单元101将其产生的反馈信号发出给列驱动器300，具体地，发送列驱动器300的补偿信号检测模块303，其中反馈信号包含该行像素单元101的老化信息。
本实施例的补偿器400用于接收补偿信号检测模块303的检测结果，并根据该结果更新其存储的补偿信息；当某行像素单元101被显示地址信号选通时，补偿器400取出其存储的此行像素单元101的补偿信息并根据该补偿信息计算一补偿信号(数字显示补偿信号或数字校正补偿信号)或不经计算直接将储存的补偿信号经第二移位暂存器305发送给列驱动器300的显示信号产生模块301，列驱动器300的显示信号产生模块301接收此补偿信号后将其与数字原始显示信号相结合以形成模拟显示信号；当某行像素单元101被校正地址选通时，补偿器400取出其存储的此行像素单元101的补偿信息并根据该补偿信息计算一数字校正补偿信号或不经计算直接将储存的数字校正补偿信号经第三移位暂存器306发送给列驱动器300的校正信号产生模块302，列驱动器300的校正信号产生模块302接收此数字校正补偿信号后将其与固定电压相结合以形成模拟校正信号。
相应地，本实施例还公开了一种像素矩阵的外围补偿系统的方法，包括以下步骤：
每行像素单元101依次进行显示操作，其中第n行像素单元101在tn时进行显示操作：此行像素单元101被显示地址信号选通，接收模拟显示信号，其中n为小于或等于N的正整数；
在ti时，第i行像素单元101进行显示操作，若此时外围补偿系统不是处于反馈检测状态，则ti时，第i+k行像素单元101进行校正操作：此行像素单元101被写入模拟校正信号；第ti+1到ti+k-1时间内，外围补偿系统进入反馈检测状态：将第i+k行像素单元101中包含老化信息的反馈信号反馈至补偿信号检测摸块303；其中i和k都为正整数，且i+k 小于或等于N。
另外，第ti+1到ti+k-1时间内：
第i+1行到第i+k-1行的像素单元101如常进行显示操作，被写入模拟显示信号；
第i+1+k行到第i+k-1+k行的像素单元101被写入模拟校正信号，所述模拟校正信号不用于驱动像素单元101产生一包含老化信息的反馈信号；或者第i+1+k行到第i+k-1+k行的像素单元101不写入模拟校正信号。
需要说明的是，可以将一帧时间依据像素单元101的行数而划分成若干相等的行时间t1～tN。当t的下标为负数时，表明此时其代表的时间位于为此帧与前帧之间的空白时段内，比如若某帧的第1个行时间为t1，则t-1、t-2、t-3代表的时间位于此帧与前帧的空白时段内，且分别比t1超前1、2、3个行时间；当t的下标大于N时，表示此时其代表的时间位于此帧与后帧之间的空白时间，比如若某帧的第N个行时间(最后1个行时间)为tN，则tN+1、tN+2、tN+3代表的时间位于此帧与后帧的空白时段内，且分别比tN滞后1、2、3个行时间。
下面结合图9进一步说明。
图9(a)、(b)和(c)是本实施例外围补偿系统的一种时序图，其中图9(a)所示的时序图为显示操作的时序图，图9(b)和(c)所示的时序为校正操作的时序图。需要说明的是，图中C表示是模拟校正信号，C后面加上序号后，表示的是此序号行的像素单元101的模拟校正信号，比如C1表示的是第1行的像素单元101的模拟校正信号，同样，F表示的是反馈信号，F后面加上序号后，表示的是此序号行的像素单元101的反馈信号，比如F1表示的是第1行的像素单元101的反馈信号；图9(a)、(b)和(c)中不妨令N＝768，M＝1024。
如图9(a)所示，本实施例的显示操作部分是和实施例1的显示操作部分是一样的。行扫描驱动器200在一帧的时间内依次逐行选通像素单元101，每选通一行的像素单元101，列驱动器300的显示信号产生模块301就会产生一补偿过的模拟显示信号给显示信号线，以将模拟显示信号写入被选通此行的像素单元101。当最后一行像素单元101完成显示操作后，会有一段帧与帧之间的空白时间，之后又到了下一帧的第一行像素单元101开始进行显示操作。
由于本实施例的显示地址线，校正地址线和反馈地址线是各自独立的；显示信号线，校正信号线和反馈信号线也是各自独立的，如图6所示。这样的话，校正操作也是可以与显示操作独立分开进行。图9(b)所示的校正操作部分记载了校正地址线和校正信号线的波形。若外围补偿系统对第i行的像素单元101进行显示操作，如果此刻外围补偿系统 处于反馈检测状态，则第i+k行的像素单元101就不会做任何校正操作，否则的话，外围补偿系统会对第i+k行的像素单元进行校正操作，在i+1行至i+k-1行的时间里做反馈检测，外围补偿系统会在期间处于反馈检测状态，其中i、k均为正整数，且i+k小于或等于N。
图9(a)、(b)和(c)为k＝3的情况。这时校正操作包括以下步骤，首先先通过行扫描驱动器200的校正地址线选通第i+3行的像素单元101，列驱动器300的校正信号产生模块302就会发出第i+3行像素单元101相对应的模拟校正信号到与之相连的校正信号线，当行扫描驱动器200通过校正地址线截止选通第i+3行的像素单元101时，外围补偿系统随即进入反馈检测状态，行扫描驱动器200通过反馈地址线选通第i+3行的像素单元101，第i+3行的像素单元101开始反馈反馈信号到反馈信号线，列驱动器300的补偿信号检测模块303接受和检测反馈信号，检测结果会在反馈检测状态结束之前并行存入第四移位暂存器307，再一个个串行传给补偿器400更新补偿信息储存模块402中的补偿信息。存储到补偿信息储存模块402的补偿信息可以在储存之前经信号处理之后再存到补偿信息储存模块402，或者在从补偿信息储存模块402中读取补偿信息时再做信号处理，处理完之后再转递给显示信号产生模块301或校正信号产生模块302。其中一个补偿信号处理是从整个帧的检测结果里计算出参考补偿信息值，再把每个像素单元101的相对补偿信息存入补偿信息储存模块402。采用参考补偿信息值的一个目的是尽可能的让储存在补偿信息储存模块402的相对补偿信息不会溢出。
由于校正操作总是在显示操作后k行的位置，也就是第i行像素单元101在做显示操作的时候，同时第i+k行像素单元101则在做校正操作。当显示操作进行到第i+k行的时候，之前写入像素单元101的模拟校正信号就会被写入第i+k行的像素单元101的模拟显示信号覆盖。由于模拟校正信号只存在很短的k行时间，是不会对正常的显示造成明显的影响。尤其可以选择在反馈检测状态时不让有机发光二级管OLED发光，具体的做法是在反馈信号线上赋予一个电压值低于有机发光二级管OLED的阈值电压。
图9(a)、(b)和(c)所示，k＝3时，第1行像素单元101的校正操作是在第1行的模拟显示信号来之前3行的时间，也就是如图9所示在第t-3行时间，在t-2和t-1的时间做反馈检测。第t-3行时间，第t-2行时间和t-1行时间此时是位于帧与帧之间的空白时段。
如果本帧第1行像素单元101在时间t-3做校正操作，那么在下一帧，第1行就不做校正操作，而是从第2行像素单元101开始，在时间t-2做校正操作；再下一帧，第1行和第2行像素单元101都不做校正操作，而是从第3行像素单元101开始，在时间t-1做校正操作；再下一帧，又 回到从第1行像素单元101开始，在时间t-3做校正操作，依此类推。所有行的像素单元101都会在k帧里做1次校正操作。
比如：在第1帧时下列行做校正操作：
第1行，第4行，第7行，10行....
在第2帧时下列行做校正操作
第2行，第5行，第8行，第11行....
在第3帧时下列行做校正操作
第3行，第6行，第9行，第12行....
在第4帧时下列行做校正操作
第1行，第4行，第7行，第10行....
依次类推。上述归纳起来：
在a帧内所有像素101都进行一次校正操作和反馈操作，比如当a＝1时，表明在一帧内所有像素101都进行了一次校正操作和反馈操作，当a＝2时，表明在两帧内所有像素101都进行了一次校正操作和反馈操作。因此，像素101每i帧都进行了一遍校正操作和反馈操作。
在这a帧内的第b帧时，这N行像素单元中的第ca+b行像素单元101：
在第[(c-1)a+b-1]个行时间内即t[(c-1)a+b-1]进行校正操作；
在第[(c-1)a+b]到(ca+b-1)个行时间内即t[(c-1)a+b]～t(ca+b-1)进行反馈操作；
在第[ca+b]个行时间内进行显示操作。
其中a为大于等于1且小于等于N的整数，b为大于等于1且小于等于a的整数，c为大于等于0的整数且ca+b小于等于N。
用a帧完成对所有像素单元101校正、反馈操作，在这a帧内的第b帧时，这N行像素单元中的第ca+b行像素单元101，如上所述，其在第[(c-1)a+b-1]个行时间内即t[(c-1)a+b-1]进行校正操作；在第[(c-1)a+b]到(ca+b-1)个行时间内即t[(c-1)a+b]～t(ca+b-1)进行反馈操作。考虑a、b、c的实际意义，[(c-1)a+b-1]、[(c-1)a+b]和(ca+b-1)的取值可能非正——典型地，不妨令N＝100，此时可令a＝3、b＝1、c＝0，[(c-1)a+b-1]、[(c-1)a+b]和(ca+b-1)则分别为-3、-2和-1，这时候t-3、t-2、t-1虽然没有落在t1～t100的取值中，但其也是有意义的，它们分别代表的是发生在第一个行时间t1之前且与t1相距离3个、2个、1个行时间。为解决t的下标取非正数时这个时间没有落在帧内的问题，可以有几种措施，一是在像素矩阵100的第一行像素单元101之前或最后一行像素单元101之后加上若干行无用的像素单元101来使整个帧的时间增加，比如上面举的例子，就可以增加3个行像素单元101；二是可以把这部分没有落在帧内的校正、反馈时间放在帧与帧之间去。
下面再举一个例子来说明。如下表1所示，为N＝10且k＝3时的情况。图中tX表示的是帧中的第X行时间，当X取负值时，比如图表中的-3、-2、-1，表示的是tX处于此帧与上帧之间的空白时间段。总结起来，t1～t10分别表示的是一帧内的第1个行时间～第10个行时间，这10个行时间组成了此帧的时间；而t-3、t-2、t-1表示的是其处于此帧与上帧之间的空白时间段，需要说明的是，t-3、t-2、t-1及t1～t10这13个时间都是相等的时间长度，且从时间发生前后来看，依次从t-3到t-2，再到t-1，再到t1～t10。
校正X：表示的是第X行像素单元101进行校正操作，比如当X取1值时，即校正1，其表示的就是第1行像素单元101进行校正操作。
显示X：表示的是第X行像素单元101进行显示操作，比如当X取1值时，即显示1，其表示的就是第1行像素单元101进行显示操作。
反馈X：表示的是将第X行像素单元101的反馈信号发送到与此行像素单元101中各像素单元相连的反馈信号线上，比如当X取1值时，即反馈1，其表示的是将第1行像素单元101的反馈信号发送到与此行像素单元101中各像素单元相连的反馈信号线上。下表中未写有校正X，显示X和反馈X的空白的地方表示是，图表中此空白地方对应的某行像素单元101在某行时间内没有进行任何操作。
如上所述，下表中k取3，可以看到经过k帧即3帧之后，所有行的像素单元101都做了一次校正操作。
k帧之后的第k+1帧即第4帧，外围补偿系统又在此帧的t-3的行时间对第1行像素单元101进行校正操作。
Figure PCTCN2015085084-appb-000001
表1
请参照图9(d)和(e)，本实施例的另外一种校正操作方法是把校正地址信号线和反馈地址信号线连在一起，也就是同时通过截止选通校 正地址线和反馈地址线选通或截止选通同一行的像素单元101。可以看到校正地址线和反馈地址线的信号波形是一样的。
以第1行的像素单元101为例，此行像素单元101的校正操作包括以下步骤，首先先通过行扫描驱动器200的校正地址线选通第1行的像素单元101，校正地址信号维持3个行时间，从t-3到t-1。列驱动器300的校正信号产生模块302就会发出第1行像素单元101相对应的模拟校正信号到与之相连的校正信号线。同时，外围补偿系统也通过行扫描驱动器200的反馈地址线选通第1行的像素单元101，外围补偿系统进入反馈检测状态，反馈地址信号同样维持3个行时间，从t-3到t-1，在此期间，第1行的像素单元101开始反馈反馈信号到反馈信号线，驱动器300的补偿信号检测模块303接受和检测反馈信号，检测结果会在反馈检测状态结束之前并行存入第四移位暂存器307，再一个个串行传给补偿器400以便更新补偿信息储存模块402中的补偿信息。
实施例三
本实施例公开了一种外围补偿系统。
为了简化实施一和二中的显示系统和外围补偿系统的布线和减少其驱动芯片面积，可以使校正地址信号和显示地址信号分时复用行扫描驱动器200的显示地址线，模拟校正信号和模拟显示信号分时复用列驱动器300的显示信号线。
请参考图10，在本实施例中，行扫描驱动器200分时发送校正地址信号或显示地址信号到显示地址线，列驱动器300分时发送模拟校正信号和模拟显示信号到显示信号线。
请参考图11，为本实施例中像素单元101的两种电路结构。
如图11(a)所示，像素单元101包括驱动晶体管Q1、显示开关晶体管Q2、反馈开关晶体管Q4、存储电容C和有机发光二极管OLED。显示开关晶体管Q2被显示地址线送来的校正地址信号选通以将从显示信号线接收到的模拟校正信号发给驱动晶体管Q1，并储存在存储电容C，驱动晶体管Q1在接收到模拟校正信号后产生一个反馈信号发送到反馈开关晶体管Q4，在此显示地址线再送进模拟显示信号前且此反馈信号未消失前(即在模拟显示信号写入和反馈信号未消失前)，行扫描驱动器200发出反馈地址信号以选通反馈开关晶体管Q4，把一电压从反馈线上输入到发光二极管OLED的阳极，该电压会设置低于发光二级管OLED阈值电压以便确保发光二极管OLED没有导通，那驱动晶体管Q1的反馈电流就会全部流到反馈信号线，使其将接收到的反馈信号发出给补偿信号检测模块303。在另一时间段，显示开关晶体管Q2又被显示地址线送来的显示地址信号选通以将从显示信号线接收到的模拟显示 信号发给驱动晶体管Q1，驱动晶体管Q1接收模拟显示信号来驱动有机发光二极管OLED发出与模拟显示信号相对应的光。
相比图11(a)，图11(b)的反馈开关晶体管Q4的一极不是连接到有机发光二极管OLED的阳极，而是连接到一感光元件GL上，感光元件GL用于将有机发光二极管OLED的光信号转变为电信号，图11(b)中经反馈信号线传递出来的反馈信号包括了驱动晶体管Q1和有机发光二极管OLED两者的老化信息。
在本实施例中，校正信号产生模块302可以分时复用显示信号产生模块301的第二数模转模块312和第一模拟加法模块313。在校正信号产生模块302的此种实现方式中，第三数模转换模块321的输入为数字校正补偿信号，其参考电位为一设定的固定电压；对比实施例一和二中涉及到的第二数模转换模块312，第二数模转换模块312和第三数模转换模块321都是数模转换模块，且输入都是数字校正补偿信号，唯一的不同在于两者的参考电位。因此，第二数模转换模块312和第三数模转换模块321可以为同一数模转换模块，模拟校正信号和模拟显示信号通过一定的时序关系分时复用此数模转换模块，当需要产生模拟校正信号时，此复用的数模转换模块的参考电位变为上述产生模拟校正信号时设定的一固定电压，当需要产生模拟显示信号时，此复用的数模转换模块的参考电位变回来。这样第二数模转换模块312和第三数模转换模块321就分时复用了同一数模转换模块，达到了节省器件和简化电路的目的。在校正信号产生模块302的另一种实现方式是除了第二数模转换模块312和第三数模转换模块321分时复用了同一数模转换模块外，第一模拟加法模块313和第二模拟加法模块322也可以分时复用。
本实施例中，显示信号产生模块301和校正信号产生模块302还可以分时复用显示信号产生模块301，即显示信号产生模块301分时产生模拟显示信号和模拟校正信号。显示信号产生模块301输入是数字原始显示信号和数字显示补偿信号，利用数字显示补偿信号对数字原始显示信号进行补偿而得到模拟显示信号，而校正信号产生模块302输入是固定电压和数字校正补偿信号，利用数字校正补偿信号对固定电压进行补偿而得到模拟校正信号，因此，当显示信号产生模块301分时要产生模拟校正信号时，将数字校正补偿信号代替数字显示补偿信号输入到显示产生模块301中，或者直接将数字显示补偿信号当作数字校正补偿信号使用，同时将数字原始信号的信号内容变为一固定电压而输入到显示产生模块301中，这样显示产生模块301就输出了模拟校正信号。
外围补偿系统也可以直接利用之前写入像素单元101的模拟显示信号做为模拟校正信号，这样的话就不需要校正信号产生模块302，像素单元101就不是反馈一个预期的反馈信号，补偿信号检测模块303需要 有模数转换器将反馈信号转成数字信号再跟预期的信号做比较。该预期信号不是固定的，预期信号的数目是和模拟显示信号数目是一样的。
请参照图12(a)和(b)，为本实施例的外围补偿系统的一种时序图。
与实施例二不同之处在于，本实施例中显示地址信号和校正地址信号分时复用显示地址线，显示信号线和校正信号线分时复用显示信号线。所以本实施例中显示地址线的波形基本上是实施例二中把校正地址线的波形合并到显示地址线的波形里再向左移动半个行时间的波形。移半个行时间的原因是因为本实施例的外围补偿系统需要在一个行的时间内完成写入一次模拟校正信号到第i+k行和一次模拟显示信号到第i行，可先写入模拟校正信号也可先写入模拟显示信号。本实施例是先在1个行时间的前面半个行的时间写入模拟校正信号再在后半个行时间写入模拟显示信号。对于像素单元101来说，什么时候通过显示地址线选通像素单元是次要的，决定什么信号写入像素单元101的要看停止选通像素单元101时的那一刻数据信号端子发送到显示信号线上的信号是什么(模拟校正信号或模拟显示信号)。
从图12可以看到显示地址线1(与第1行像素单元101相连的显示地址线)有两个方波，第一个方波表示的是校正地址信号，用来选通第1行的像素单元101，把显示信号线上的模拟校正信号写入像素单元101。本实施例校正地址信号在时间t-4后半个行时间已经打开显示地址线(显示地址线的电平为高)，具体打开的时间根据显示地址线的负载大小可以调整，负载大可以再提前点打开，负载小可以稍微晚点打开，截止选通显示地址线(显示地址线的电平为低)的时间是在t-3的中间，在截止选通那一刻，列驱动器300会完成通过数据信号端子向显示信号线发出模拟校正信号。第二个方波是表示的是显示地址线信号，用来选通像素单元101和写入模拟显示信号，此模拟显示信号会覆盖之前写入到像素单元101的模拟校正信号，列驱动器300在显示地址线信号截止选通之前通过数据信号端子向显示信号线发出模拟显示信号。外围补偿系统会在行扫描驱动器200发送此次校正地址信号之后和发出下一个校正地址信号之前处于反馈检测状态，这期间列驱动器300可以不向数据信号线发出任何模拟校正信号。
图12(a)，在时间t1期间，外围补偿系统完成了一次校正操作和一次显示操作，校正操作在t1的前半个行时间内完成，显示操作在t1的后半个行时间内完成。在t1的前半个行时间内，行扫描驱动器200选通第4行的像素单元101，列驱动器300会在行扫描驱动器200截止选通第4行的像素单元101的显示地址线之前，通过数据信号端子和显示信号线完成向第4行像素单元101发送模拟校正信号，如图中的C4。此模拟校 正信号至少会维持至行扫描器驱动器200截止选通第4行的像素单元101的显示地址线时刻，在截止选通第4行像素单元101的显示地址线的同时，写入像素单元101的模拟校正信号C4也就储存在像素单元101的驱动晶体管Q1的栅极，外围补偿系统进入反馈检测状态，行扫描驱动器200打开第4行像素单元101的反馈地址线，将此行像素单元101的包含老化信息的反馈信号发送到反馈信号线，列驱动器300的补偿信号检测模块303接收此反馈信号。反馈检测状态维持至t3的中间时刻，直至补偿信号检测模块303完成对反馈信号的检测。在t1的后半个行时间，行扫描驱动器200通过扫描信号端子1向显示地址线1发送显示地址信号来选通第1行的像素单元101，列驱动器300向通过数据信号端子发出第1行像素单元101的模拟显示信号L1，模拟显示信号L1至少维持至行扫描驱动器200截止选通显示地址线。在t1的前半个行时间，行扫描驱动器200同时选通第4行和第1行的像素单元，这时什么信号写入像素单元101主要看截止选通某一行的像素单元101时数据信号端子和显示信号线上的信号。
需要说明的是，本申请中的反馈信号，如上所述，包含老化信息，而老化信息指的是由原始状态不平均和使用过程中像素单元101因老化而形成的信息，原始状态可看作像素单元101出厂未使用时因制造工艺等原因而产生的初始的老化信息，即若将老化信息看作关于时间的函数，原始状态就是当时间为出厂时刻时老化信息的值。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (8)

  1. 一种像素矩阵的外围补偿系统，所述像素矩阵(100)包括N行M列像素单元(101)、N行显示地址线和M列显示信号线，像素单元(101)和各自的显示地址线、显示信号线分别连接，N和M均为正整数，其特征在于，包括:
    行扫描驱动器(200)，用于通过显示地址线向像素矩阵(100)发送显示地址信号以在一帧内依次选通各行像素单元(101)；
    补偿器(400)，包括储存补偿信息的补偿信息储存模块(402)，所述补偿器(400)用于发送数字显示补偿信号，当某行像素单元(101)被显示地址信号选通时，补偿器(400)发出相对应的所述数字显示补偿信号以补偿像素单元(101)图像视频信息显示不精确的问题；
    列驱动器(300)，包括显示信号产生模块(301)，用于向像素矩阵(100)发送模拟显示信号，所述模拟显示信号用于为像素单元(101)的显示信号线提供包含图像视频信息的显示数据；所述显示信号产生模块(301)包括具有伽马校正功能的第一数模转换模块(311)、第二数模转换模块(312)和第一模拟加法模块(313)；当某行像素单元(101)被显示地址信号选通时，第一数模转换模块(311)接收该行数字原始显示信号，输出经过伽马校正的模拟原始显示信号给第一模拟加法模块(313)；第二数模转换模块(312)接收所述相对应的数字显示补偿信号，输出模拟显示补偿信号给第一模拟加法模块(313)；第一模拟加法模块(313)将模拟显示补偿信号和经过伽马校正的模拟原始显示信号进行模拟加法运算后输出模拟显示信号给像素矩阵(100)；还包括第一移位暂存器(304)和第二移位暂存器(305)，所述第一移位暂存器(304)接收外界的数字原始显示信号并转递给第一数模转换模块(311)，所述第二移位暂存器(305)接收补偿器(400)发出的数字显示补偿信号并转递给第二数模转换模块(312)。
  2. 如权利要求1所述的外围补偿系统，其特征在于：
    所述列驱动器(300)，还包括校正信号产生模块(302)，所述校正信号产生模块(302)用于产生校正信号并将此校正信号发送给像素矩阵(100)；所述校正信号为一模拟校正信号，用于驱动像素单元(101)产生一包含老化信息的反馈信号；还包含一补偿信号检测模块(303)，所述补偿信号检测模块(303)用于接收所述反馈信号，将反馈信号会与参考信号做比较得到检测结果后通过一第四移位暂存器(307)输出给补偿器(400)，或者将反馈信号经模数转换后再通过第四移位暂存器(307)输出给补偿器(400)；
    所述行扫描驱动器(200)，还用于发出校正地址信号和反馈地址信号；所述行扫描驱动器(200)按照设定的时序向像素矩阵(100)发送 校正地址信号以在一帧或多帧时间内按照设定顺序选通各行像素单元(101)，当某行像素单元(101)被校正地址信号选通时，该行像素单元(101)接收所述的模拟校正信号，在模拟校正信号被模拟显示信号覆盖之前，行扫描驱动器(200)向像素矩阵(100)发送反馈地址信号以选通此行像素单元(101)将其产生的反馈信号发出；当某行像素单元(101)被反馈地址信号选通时，该行像素单元(101)将其产生的反馈信号发送给所述补偿信号检测模块(303)；
    补偿器(400)，接收和处理补偿信号检测摸块(303)的输出，当某行像素单元(101)被显示地址信号/校正地址信号选通时，补偿器(400)取出其存储的此行像素单元(101)的补偿信息并根据该补偿信息计算一数字显示补偿信号/数字校正补偿信号发送给列驱动器(300)。
  3. 如权利要求2所述的外围补偿系统，其特征在于：
    所述校正信号产生模块(302)包括一产生固定电压信号作为模拟校正信号的模块；
    或者，所述校正信号产生模块(302)包括第三数模转换模块(321)；第三数模转换模块(321)分别输入数字校正补偿信号和参考电压，经处理后输出模拟校正信号，所述参考电压为一固定电压信号；所述列驱动器(300)还包括第三移位暂存器(306)，用于接收补偿器(400)发出的数字校正补偿信号并转递给第三数模转换模块(321)；
    或者，所述校正信号产生模块(302)包括第三数模转换模块(321)和第二模拟加法模块(322)；第三数模转换模块(321)输入数字校正补偿信号，经处理后输出模拟校正补偿信号给第二模拟加法模块(322)，第二模拟加法模块(322)还输入一固定电压信号，第二模拟加法模块(322)将模拟校正补偿信号与固定电压信号进行加法运算后输出模拟校正信号；
    或者，用补偿过的模拟显示信号当作模拟校正信号使用。
  4. 如权利要求2所述的像素矩阵外围补偿系统，其特征在于：
    所述校正地址信号和显示地址信号分时复用所述显示地址线；所述模拟校正信号和模拟显示信号分时复用所述显示信号线。
  5. 如权利要求4所述的像素矩阵外围补偿系统，其特征在于：
    所述校正信号产生模块(302)与显示信号产生模块(301)分时复用第二数模转换模块(312)来分别产生模拟校正信号和模拟显示信号；
    或者，所述校正信号产生模块(302)与显示信号产生模块(301)分时复用第二数模转换模块(312)和第一模拟加法模块(313)来分别产生模拟校正信号和模拟显示信号；
    或者，所述校正信号产生模块(302)与显示信号产生模块(301)分时复用显示信号产生模块(301)来分别产生模拟校正信号和模拟显示 信号。
  6. 一种显示系统，包括如权利要求1至5中任一项所述的外围补偿系统，以及像素矩阵(100)。
  7. 一种像素矩阵的外围补偿系统的方法，所述像素矩阵(100)包括N行M列像素单元(101)、N行显示地址线和M列显示信号线，像素单元(101)和各自的显示地址线、显示信号线分别连接，N和M均为正整数，其特征在于：
    一帧时间由N个相等的行时间t1～tN组成，每行像素单元(101)依次进行显示操作，其中第n行像素单元(101)在tn时进行显示操作：此行像素单元(101)被显示地址信号选通，接收模拟显示信号，其中n为小于或等于N的正整数；
    在ti时，第i行像素单元(101)进行显示操作，若此时外围补偿系统不是处于反馈检测状态，则ti时，第i+k行像素单元(101)进行校正操作：此行像素单元(101)被写入模拟校正信号；第ti+1到ti+k-1时间内，外围补偿系统进入反馈检测状态：将第i+k行像素单元(101)中包含老化信息的反馈信号反馈至补偿信号检测摸块(303)；其中i和k都为正整数，且i+k小于或等于N。
  8. 如权利要求7所述的方法，其特征在于：
    第ti+1到ti+k-1时间内：
    第i+1行到第i+k-1行的像素单元(101)进行显示操作，被写入模拟显示信号；
    第i+1+k行到第i+k-1+k行的像素单元(101)被写入模拟校正信号，所述模拟校正信号不用于驱动像素单元(101)产生一包含老化信息的反馈信号；或者第i+1+k行到第i+k-1+k行的像素单元(101)不写入模拟校正信号。
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