WO2017000849A1 - Lvds视频信号转换为dp视频信号的方法及系统 - Google Patents

Lvds视频信号转换为dp视频信号的方法及系统 Download PDF

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Publication number
WO2017000849A1
WO2017000849A1 PCT/CN2016/087208 CN2016087208W WO2017000849A1 WO 2017000849 A1 WO2017000849 A1 WO 2017000849A1 CN 2016087208 W CN2016087208 W CN 2016087208W WO 2017000849 A1 WO2017000849 A1 WO 2017000849A1
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WIPO (PCT)
Prior art keywords
video signal
lvds
signal
conversion
rgb
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PCT/CN2016/087208
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English (en)
French (fr)
Inventor
徐梦银
胡磊
肖家波
朱亚凡
张伟涛
Original Assignee
武汉精测电子技术股份有限公司
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Priority claimed from CN201510365974.4A external-priority patent/CN105049773A/zh
Priority claimed from CN201510777335.9A external-priority patent/CN105516632B/zh
Application filed by 武汉精测电子技术股份有限公司 filed Critical 武汉精测电子技术股份有限公司
Priority to KR1020187002656A priority Critical patent/KR102025026B1/ko
Priority to JP2017561954A priority patent/JP6574493B2/ja
Publication of WO2017000849A1 publication Critical patent/WO2017000849A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
    • H04N21/4382—Demodulation or channel decoding, e.g. QPSK demodulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/87—Regeneration of colour television signals
    • H04N9/8707—Regeneration of colour television signals using a demodulator and a remodulator, e.g. for standard conversion

Definitions

  • the invention relates to the generation of a DP video signal, in particular to a method and a system for converting an LVDS video signal into a DP video signal, and belongs to the field of display and testing of a liquid crystal module.
  • a liquid crystal display module (hereinafter referred to as a liquid crystal module) is a key component that can be normally displayed by a liquid crystal display device, and is composed of a liquid crystal panel, a backlight original, a display processing chip, and a circuit.
  • the structure of the liquid crystal module is precise, the process is complicated, and the production process is high.
  • the display interface and the internal display processing circuit of the ordinary liquid crystal module used in the television and display products use LVDS (Low-Voltage Differential Signaling) signals to work, and the existing liquid crystal module test devices also output correspondingly.
  • the LVDS video signal is used to implement the module test. Since the common liquid crystal module is put into production for a long time and the output is large, the module test device is also widely used.
  • test device of the DP liquid crystal module needs to output the same DP test signal, but the conventional liquid crystal module test device does not have this function, and the ordinary liquid crystal module continues to be produced, and the test device does not enter the replacement. The cycle will continue to be used.
  • module manufacturers also produce DP liquid crystal modules, in order to protect investment and reduce production costs, it is impossible to eliminate existing equipment and re-purchase expensive test modules for expensive DP modules. In order to produce DP liquid crystal modules in large quantities at low cost in a short period of time and to ensure their yield, large-scale reuse of existing common module test devices is still required.
  • the present invention aims to overcome the above deficiencies of the prior art and provide a method and system for converting an LVDS video signal into a DP video signal.
  • the invention can detect the quality of the LVDS video signal and the correctness of the image data, and has high reliability and error. Judgment, simple operation, high detection efficiency and low cost.
  • a technical solution adopted for achieving the object of the present invention is: a method for converting an LVDS video signal into a DP video signal, the method comprising:
  • the LVDS video signal is transmitted in any one of a single LINK, a dual LINK, and a four LINK, and converted into an RGB video signal;
  • the configuration and conversion of the DP conversion are controlled according to the DP conversion configuration command and the DP conversion startup command.
  • the present invention also provides a system for converting an LVDS video signal into a DP video signal, the system comprising:
  • An LVDS video signal conversion unit for converting an LVDS video signal into an RGB video signal
  • the DP video signal conversion unit is configured to perform configuration and conversion of the DP conversion according to the DP conversion configuration command and the DP conversion startup command.
  • the present invention also provides a method for converting an LVDS video signal into a DP video signal, the method comprising:
  • the DP conversion signal is configured and converted according to the DP conversion configuration command and the DP conversion start command to obtain a DP video signal.
  • the present invention also provides a system for converting an LVDS video signal into a DP video signal, the system comprising:
  • An LVDS video signal conversion unit for converting an LVDS video signal into an RGB video signal
  • a buffer multiplying unit for buffering and multiplying the RGB video signal
  • the DP video signal conversion unit is configured to perform DP conversion configuration and conversion on the output multiplied signal according to the DP conversion configuration command and the DP conversion start command to obtain a DP video signal.
  • the present invention can detect the DP video signals of the 1Lane, 2Lane, and 4Lane generated by the video source.
  • the present invention can be well adapted to different DP transmission characteristics, color gradation of the video signal, transmission mode, and coding. Different characteristics such as mode.
  • the present invention can detect the electrical characteristics of the DP video signal generated by the video source, and by inputting the DP electrical parameter standard, the detection result is obtained by comparison in the present invention and outputted.
  • the invention can detect the image data of the DP video signal generated by the video source, and pre-cache each frame image data and compare with the original video image to determine whether each pixel is output correctly, and each frame image can be detected. .
  • the invention can detect the highest DP video resolution, and has the advantages of high integration, reliable operation, strong anti-interference ability, simple operation, economical and practical, and can not only improve the detection reliability and efficiency of the DP liquid crystal module, but also reduce the detection reliability and efficiency of the DP liquid crystal module. Its equipment cost and production cost will further increase the popularity of related display devices.
  • the present invention can realize all of the functions by using an FPGA (Field Programmable Logic Array) chip, a DDR (Double Date Rate) memory chip, and an A/D (Analog/Digital) conversion chip; They are common chips in the market. They are not only stable in operation, easy to implement, but also inexpensive, avoiding the problems of complicated design, poor stability and high design cost caused by the use of various special chips.
  • FPGA Field Programmable Logic Array
  • DDR Double Date Rate
  • A/D Analog/Digital
  • the data transmission rate of each channel of the present invention is doubled to 5.4 Gbps, and the total bandwidth is up to 21.6 Gbps, which can greatly improve the display resolution (Max 3840x2160@60hz), color depth, refresh rate, and multi-display capability.
  • the present invention supports high-speed bidirectional data transmission, and can transfer USB2.0 or Ethernet data in a standard DP data line.
  • the present invention supports a daisy chain link, allowing the DP input display device to copy the input data and output it to other display devices through another DP.
  • FIG. 1 is a structural block diagram of an apparatus for converting an LVDS video signal into a DP video signal according to an embodiment of the present invention
  • FIG. 2 is a circuit block diagram of the LVDS video signal receiving unit and the LVDS video signal decoding unit of FIG. 1;
  • FIG. 3 is a circuit block diagram of the RGB video signal conversion unit, the DP video signal conversion unit, and the video conversion configuration unit of FIG. 1;
  • FIG. 4 is a flowchart of a method for converting an LVDS video signal into a DP video signal according to an embodiment of the present invention
  • FIG. 5 is a structural block diagram of a system for converting an LVDS video signal into a DP1.2 video signal according to an embodiment of the present invention.
  • LVDS video signal receiving unit 1-1. LVDS video signal interface, 1-2. LVDS video signal receiving terminal module, 1-3.
  • LINK LVDS clock signal demodulation module 1-4.
  • Four LINK LVDS data signal demodulation module 1-5.LVDS demodulation dynamic calibration module;
  • LVDS video signal decoding unit 2-1. LVDS video synchronization buffer module, 2-2. LINK LVDS video signal line sequence control module, 2-3. LVDS video synchronization signal decoding module, 2-4. LINK LVDS video data decoding module;
  • RGB video signal conversion unit 3-1. RGB video signal adaptive control module, 3-2. RGB video clock adaptive configuration module, 3-3RGB. Video clock generation module, 3-4. RGB video clock output adjustment Module, 3-5. Single link mode RGB video conversion module, 3-6. Dual link mode RGB video conversion module, 3-7. Four link mode RGB video conversion module, 3-8. Left and right split screen mode RGB Video conversion module, 3-9. Parity and split screen mode RGB video conversion module, 3-10.
  • Video conversion configuration unit 5-1. Manual DIP switch, 5-2. JTAG interface, 5-3.DP video conversion configuration module;
  • Cache multiplier unit 6-1. Left channel RGB video signal buffer multiplier unit, 6-2. Right channel RGB video signal buffer multiplier unit, 6-3. RGB video signal synchronization unit.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the system for converting an LVDS video signal into a DP video signal in this embodiment includes an LVDS video signal conversion unit and a DP video signal conversion unit for converting an LVDS video signal into an RGB video signal.
  • the LVDS video signal conversion unit includes an LVDS video signal receiving unit 1, an LVDS video signal decoding unit 2, and an RGB video signal conversion unit 3.
  • the working process of the system for converting the LVDS video signal into the DP video signal in the above embodiment is as shown in FIG. 4, and includes the following specific steps:
  • the LVDS video signal receiving unit 1 receives the LVDS video signal, and demodulates the received LVDS video signal to generate LVDS parallel demodulation data and an LVDS pixel clock.
  • the LVDS video signal receiving unit 1 of the present embodiment includes: an LVDS video signal interface 1-1, an LVDS video signal receiving terminal module 1-2, an LVDS clock signal demodulating module 1-3, an LVDS data signal demodulating module 1-4, and LVDS demodulation dynamic calibration module 1-5, wherein LVDS video signal receiving termination module 1-2 is connected to LVDS video signal interface 1-1, LVDS clock signal demodulation module 1-3 and LVDS data signal demodulation module 1- 4 is respectively connected to the LVDS video signal receiving terminal module 1-2, and the LVDS demodulation dynamic calibration module 1-5 is connected to the LVDS clock signal demodulating module 1-3 and the LVDS data signal demodulating module 1-4, respectively.
  • a detailed description of each module is as follows:
  • LVDS video signal interface 1-1 receives LVDS video signals, LVDS video signals include single LINK, dual LINK, four LINK LVDS video signals, single LINK LVDS video signal LINK1 transmits all video pixels; dual LINK LVDS video signals include LINK1 LINK2 two links respectively transmit parity video pixels; the four LINK LVDS video signals include four links, which are sequentially transmitted in LINK1, LINK2, LINK3, and LINK4 according to video pixel order.
  • the DP video signal of the embodiment includes a DP display module of the 1Lane type, the 2Lane type, and the 4Lane type.
  • the LVDS video signal When the DP video signal to be converted is output to the 4LANE single full screen type DP display module, the LVDS video signal is a single LINK, double LINK, four LINK in any one of the modes; when the DP video signal to be converted is output to the 8LANE split screen type, 8LANE parity screen type DP liquid crystal display module, the LVDS video signal is only transmitted in four LINK mode.
  • the LVDS video signal for each link includes the LVDS receive clock and LVDS data, and the LVDS data is transmitted by the LVDS data bus.
  • the LVDS data bus includes a number of root signal lines, each of which carries a serial coded signal.
  • the LVDS video signal interface 1-1 inputs LVDS video signals by connecting LVDS transmission line interfaces.
  • the interface includes two input connectors: industry standard horn connector and small high density commercial connector to ensure the present embodiment in industrial environments and commercial The environment can be applied.
  • a connector has an LVDS signal input
  • the interface can automatically output from the connector.
  • both connectors have signal input, the interface is output from the small high-density commercial connector by default.
  • the LVDS video signal receiving terminal module 1-2 terminates the LVDS video signal received by the LVDS video signal interface 1-1, and then transmits the LVDS receiving clock and LVDS data to the LVDS clock signal demodulating module 1-3 and LVDS, respectively.
  • the termination process includes: performing ESD (Electro Static Discharge) protection before receiving the LVDS signal to eliminate instantaneous strong discharge shock interference, and then performing common mode noise filtering to suppress transmission line noise and improve electromagnetic interference resistance.
  • ESD Electro Static Discharge
  • common mode noise filtering to suppress transmission line noise and improve electromagnetic interference resistance.
  • the termination impedance matching process is performed to eliminate the distortion caused by the signal transmission, and the additional interference of the signal is further eliminated, and the signal is equalized and de-emphasized to eliminate the signal attenuation caused by the transmission loss.
  • the signal is then buffered and the reference level decision is made to reconstruct a high quality LVDS video signal.
  • the LVDS clock signal demodulation module 1-3 demodulates the received LVDS receive clock of each LINK to generate a demodulation clock and a demodulation enable signal; the demodulation process includes: inputting the LVDS receive clock to the PLL via a high speed IO buffer (Phase Locked Loop) multiplies the frequency to the LVDS data signal frequency and performs high-speed clock conversion processing to generate LVDS demodulation clock of the same frequency as the LVDS data, LVDS pixel clock and LVDS at the same frequency as the LVDS reception clock.
  • the strobe signals are demodulated and output to a high-speed clock network, which has low delay and jitter, and strong driving capability, ensuring stable and reliable demodulation of LVDS data.
  • the clock debounce calibration signal from the LVDS demodulation dynamic calibration module 1-5 is also sent to the PLL to debounce the operation to make it uninterrupted.
  • the jitter effect and stable multiplier signal ensure that the demodulation operation can be performed without interference.
  • the LVDS data signal demodulation module 1-4 demodulates the LVDS data of the LINK into parallel data by the demodulation clock and the demodulation enable signal of each LINK, and the LVDS reception clock is simultaneously demodulated into an LVDS pixel clock.
  • the process includes: independent demodulation of each bit of data in the LVDS serial data bus.
  • Each LVDS data signal is first buffered into a low-latency, low-jitter, high-speed signal network, which is then delayed by half a data bit period so that the LVDS demodulation clock is correctly sampled at the center of each LVDS data bit.
  • the data value is periodically truncated into serialized data according to the demodulation strobe signal, and then serially converted and processed by the LVDS video source pixel clock to obtain parallel demodulated data of the LVDS signal, which is buffered by the trigger. Output to ensure signal stability and reliability.
  • Each LVDS signal line is synchronously demodulated in parallel, so that each signal line does not interfere with each other regardless of the data, resulting in demodulation. error.
  • the data debounce calibration signal from the LVDS demodulation dynamic calibration module 1-5 also performs debounce control on the operation process, so that it is not affected by the input jitter. Stable and reliable demodulated data.
  • phase delay process of the data input is always controlled by the LVDS data stream phase calibration signal of the LVDS demodulation dynamic calibration module 1-5.
  • the phase calibration signal is delayed by half a cycle in the data. Based on the delay adjustment opposite to the phase deviation, the data center is always aligned with the sample edge of the demodulation clock, ensuring that the data is correctly sampled.
  • the LVDS demodulation dynamic calibration module 1-5 separately performs dynamic calibration on the LVDS reception clock and the LVDS data serialization signals in real time in the demodulation process.
  • the S200 and LVDS video signal decoding unit 2 performs video decoding on the LVDS parallel demodulated data according to the LVDS video decoding control signal to generate LVDS video source data and an LVDS video source synchronization signal.
  • the LVDS video signal decoding unit 2 of the present embodiment includes: an LVDS video synchronization buffer module 2-1, an LVDS video signal sorting module 2-2, an LVDS video synchronization signal decoding module 2-3, and an LVDS video data decoding module 2-4, for each The detailed description of the modules is as follows:
  • the LVDS video synchronization buffer module 2-1 converts the LVDS pixel clock of the LINK1 into a LVDS video source pixel clock through the global clock path, and simultaneously writes the respective LVDS parallel demodulation data to the DC- by the input LVDS pixel clock of each LINK.
  • the LVDS video source pixel clock is read one by one to make it synchronous data, which avoids reading errors caused by inconsistent delay between signals during transmission.
  • the cache depth is as large as possible so that all LINKs have enough data to be cached to offset the maximum delay between them.
  • the LVDS video signal sorting module 2-2 exchanges the data of the LINK1 and the LINK2 in the two links when receiving the LVDS parity pixel reverse control signal, and follows the LINK1 for the four links when receiving the LVDS video signal line sequence control signal. , LINK2, LINK3, LINK4 sort order.
  • the LVDS video synchronization signal decoding module 2-3 decodes the LVDS parallel demodulated data of each LINK that is synchronously read according to the LVDS video decoding control signal received from the video conversion configuration unit 5, and decodes the LVDS video source synchronization signal; according to the LVDS
  • the VESA and JEIDA transmission coding standards in the video decoding control signal decode the LVDS video source synchronization signal and output the LVDS video source pixel clock in the sequenced LINK1.
  • the synchronization signal includes: video horizontal line synchronization signal ( Hsync), video vertical field sync signal (Vsync), video data valid signal (DE).
  • the LVDS video data decoding module 2-4 decodes the LVDS parallel demodulated data of each LINK read synchronously based on the LVDS video decoding control signal received from the video conversion configuration unit 5, and decodes the LVDS video source data signals of the respective LINKs.
  • the S300 and RGB video signal conversion unit 3 converts the LVDS video source data and the LVDS video source synchronization signal into RGB video signals according to the LVDS video conversion control signal; after the conversion is completed, the DP video conversion enable signal is transmitted to the video conversion configuration unit 5.
  • the RGB video signal conversion unit 3 of the embodiment includes: an RGB video signal adaptive control module 3-1, an RGB video clock adaptive configuration module 3-2, an RGB video clock generation module 3-3, and an RGB video clock output adjustment module 3- 4, single link mode RGB video conversion module 3-5, dual link mode RGB video conversion module 3-6, four link mode RGB video conversion module 3-7, left and right split screen mode RGB video conversion module 3-8, The parity split screen mode RGB video conversion module 3-9 and the RGB video signal output module 3-10, the detailed description of each module is as follows:
  • the RGB video signal adaptive control module 3-1 generates an RGB video clock configuration signal of any one of the matched single LINK, dual LINK, and quad LINK according to the LVDS video conversion control signal, and transmits the RGB video to the RGB video together with the LVDS video source pixel clock.
  • the clock adaptive configuration module 3-2 generates an RGB conversion module selection signal according to the LVDS video conversion control signal together with each LINK LVDS video source data signal, LVDS video source synchronization signal, and RGB video clock to the single link mode RGB video conversion module 3-5, dual link mode RGB video conversion module 3-6, four link mode RGB video conversion module 3-7, left and right split screen mode RGB video conversion module 3-8, parity split screen mode RGB video conversion module 3- 9, detecting the LVDS video synchronization signal to calculate the horizontal resolution value, the horizontal resolution value is transmitted to the single link mode RGB video conversion module 3-5;
  • the RGB video clock adaptive configuration module 3-2 generates a corresponding single LINK, dual LINK, and a local clock signal according to the RGB video clock configuration signal of any one of the generated single LINK, dual LINK, and four LINK modes.
  • the configuration parameters and configuration enable signals of any of the four LINK modes are used to dynamically reconfigure the clock generation module.
  • the RGB video clock generation module 3-3 generates an RGB video clock based on the configuration clock and the enable signal and transmits it to the RGB video signal adaptive control module 3-1 and the RGB video clock output adjustment module 3-4.
  • the PLL configuration parameters are reconfigured according to their dynamic reconfiguration timing to cause the LVDS pixel clock to be multiplied accordingly.
  • the LVDS video source pixel clock When configured in single LINK mode, the LVDS video source pixel clock is converted to its RGB video pixel clock of the same frequency (hereinafter referred to as RGB clock); when configured in dual LINK mode, the LVDS video source pixel clock is converted to double frequency RGB video pixel clock; when configured in four LINK mode, the LVDS video source pixel clock is converted to a quad-frequency RGB video pixel clock (at this time each LINK in the four LINKs transmits a quarter of a full picture image). When the RGB video signal is converted in the left-right split screen or the parity split screen mode in the four-LINK mode, the LVDS video source pixel clock is converted into its double-frequency RGB video pixel clock.
  • RGB clock RGB video pixel clock
  • the generated multiplied signal is then adjusted in phase to maintain the same phase as the LVDS pixel clock (to ensure subsequent accurate and reliable sampling of LVDS data in the sequential logic operation of the conversion process), after de-jitter processing Enter a stable, non-swinging global clock path to produce an RGB video clock.
  • the RGB video clock output adjustment module 3-4 because the RGB video source data signal and the RGB video clock are synchronized, the input RGB video clock phase is delayed by half a clock cycle as an RGB output clock signal, so that the effective edge can be in the RGB video source.
  • the center of the data thereby ensuring that the subsequent conversion operation correctly samples the RGB data through the clock, and then the signal is de-jittered and output to the RGB video signal output module 3-10 through the high-speed signal buffer component to ensure the output.
  • the clock has high stability and good signal quality.
  • LVDS video source synchronization signal and data are converted into RGB video synchronization signal and data by RGB clock; when DP liquid crystal display module is 4LANE full screen type, LVDS single LINK, double LINK, four LINK are separately performed according to LINK conversion mode control signal Mode video conversion; when the DP display module is the 8LANE split screen type, the video conversion of the left and right split screen mode and the parity split screen mode is separately performed according to the conversion control signal.
  • the single link mode RGB video conversion module 3-5 converts the single LINK LVDS video source synchronization signal and the LVDS video source data into RGB video signals and transmits them to the RGB video signal output module 3-10;
  • the dual link mode RGB video conversion module 3-6 converts the dual LINK LVDS video source synchronization signal and the LVDS video source data into RGB video signals and transmits them to the RGB video signal output module 3-10;
  • RGB video conversion module 3-7 will quad-LINK LVDS video source synchronization signal and LVDS view
  • the frequency source data is converted into an RGB video signal and transmitted to the RGB video signal output module 3-10;
  • the left and right split screen mode RGB video conversion module 3-8 converts the four LINK LVDS video source sync signal and the LVDS video source data into a left half screen RGB video signal and a right half screen RGB video signal to the RGB video signal output module 3-10.
  • the video conversion process of the left and right split screen mode is: left and right split screen mode RGB video conversion module 3-8 combines four LINK LVDS data into parallel data according to "LINK1, LINK2, LINK3, LINK4" form, according to the input LVDS synchronization
  • the signal determines that when the first complete video line starts, according to the line resolution value obtained in the foregoing, the LINK parallel data of the first and second half lines are sampled by the LVDS clock and written into the left and right half screen DC-
  • the FIFO buffer is also read by the double-frequency RGB video clock to separate the respective buffer data and separate into left half-screen RGB data, right half-screen RGB data and sync signal to form the left half-screen RGB video signal and the right half.
  • Screen RGB video signal
  • the parity/screen split mode RGB video conversion module 3-9 converts the LINK LVDS video source sync signal and the LVDS video source data into odd pixel RGB video signals and even pixel RGB video signals to the RGB video signal output module 3-10;
  • the video conversion process of the parity split screen mode is: the parity split screen mode RGB video conversion module 3-9 first detects the LINK of two odd pixels and two even pixels in the LVDS data of the four LINKs, and then the LVDS synchronization signal and the odd And even two LINK data are respectively composed of parallel data according to the double LINK mode conversion manner in the foregoing, thereby respectively generating RGB video data and RGB synchronization signals of odd pixels and even pixels, forming odd pixel RGB video signals and even pixel RGB. Video signal.
  • the RGB video signal output module 3-10 selects a corresponding RGB video signal according to the RGB conversion module selection signal to transmit to the DP video signal conversion unit 4 together with the RGB output clock.
  • the video synchronization signal is reversely operated; the phase between the effective edge of the RGB output clock and the sampling center of the RGB data is compared, and the output clock and the data are respectively subjected to delay fine adjustment processing by the signal delay component. To eliminate the phase difference between the two, ensure that the output clock valid edge is always at the sampling center of the data.
  • the DP video signal conversion unit 4 After receiving the DP video conversion start command from the video conversion configuration unit 5, the DP video signal conversion unit 4 converts the RGB video signal into a DP video signal and transmits the signal to the DP display module.
  • the DP video signal conversion unit 4 of the embodiment includes: a DP register module 4-1, a left DP video signal conversion module 4-2, a right DP video signal conversion module 4-3, and a DP liquid crystal display module connector 4 -4, a detailed description of each module is as follows:
  • the DP register module 4-1 controls the configuration and operation of the DP conversion by the left DP video signal conversion module 4-2 and the right DP video signal conversion module 4-3 according to the written DP register command.
  • These DP register commands include: DP conversion configuration command, DP conversion startup command.
  • the left DP video signal conversion module 4-2 receives the RGB video signal, performs the configuration and conversion operation of converting the RGB video signal into the left channel DP video signal, and transmits the converted left channel DP video signal to the DP liquid crystal display module.
  • the connector 4-4 completes the corresponding configuration and conversion operation when receiving the DP conversion configuration command from the DP register module 4-1, and is connected through the DP liquid crystal display module when receiving the DP display module initialization command from the DP register module 4-1.
  • the 4-4 is transmitted to the DP display module, and the conversion operation is initiated when the DP conversion start command is received from the DP register module 4-1.
  • the right DP video signal conversion module 4-3 receives the RGB video signal, performs the configuration and conversion operation of converting the RGB video signal into the right channel DP video signal, and transmits the converted right channel DP video signal to the DP liquid crystal display module connection.
  • the component 4-4 when receiving the DP conversion configuration command from the DP register module 4-1, completes the corresponding configuration and conversion operation, and passes the DP liquid crystal display module connector when receiving the DP display module initialization command from the DP register module 4-1. 4-4 is transmitted to the DP display module, and the conversion operation is initiated when the DP conversion start command is received from the DP register module 4-1.
  • the conversion module selection signal is a single, double, or four LINK mode
  • the RGB data and the synchronization signal (the entire screen signal) are copied into two outputs to the DP video signal conversion unit 4; when the left and right divided screen conversion modes are selected, the left The right half screen data and the synchronization signal respectively output the left half screen RGB video signal and the right half screen RGB video signal to the left DP video signal conversion module 4-2 and the right DP video signal conversion module 4-3; when the parity is selected In the screen conversion mode, the odd pixel parallel data, the even pixel parallel data, and the sync signal respectively output the RGB odd split screen video signal and the RGB even split screen video signal to the DP video signal conversion unit 4.
  • the DP liquid crystal display module connector 4-4 simultaneously receives the left channel DP video signal and the right channel DP video signal, and is connected to the DP display module 6, and transmits the left channel DP video signal and the right channel DP video signal to the DP display mode. group.
  • the video conversion configuration unit 5 sets the LVDS video signal decoding parameter according to the characteristics of the LVDS video signal to be received, generates an LVDS video decoding control signal, and transmits the signal to the LVDS video signal decoding unit 2; sets the LVDS video conversion parameter to generate the LVDS video conversion control. Signal, transmitted to the RGB video signal conversion unit 3; Reading the DP video conversion configuration parameter to the DP video signal conversion unit 4 to issue a DP conversion configuration command and a DP display module initialization command; after receiving the DP video conversion start signal from the RGB video signal conversion unit 3, issuing a DP video conversion start command to transmit DP video signal conversion unit 4.
  • the video conversion configuration unit 5 of this embodiment includes: a manual dial switch 5-1, a JTAG interface 5-2, and a DP video conversion configuration module 5-3. The detailed description of each module is as follows:
  • Manual DIP switch 5-1 sets LVDS video signal decoding parameters and LVDS video conversion parameters; JTAG interface 5-2 receives DP video conversion configuration parameters; DP video conversion configuration module 5-3 converts LVDS video signal decoding parameters into LVDS video decoding
  • the control signal is transmitted to the LVDS video signal decoding unit 2, the LVDS video conversion parameter is converted into an LVDS video conversion control signal, and is transmitted to the RGB video signal conversion unit 3, and the DP video conversion configuration parameter is read to issue a DP conversion to the DP video signal conversion unit 4.
  • the configuration command and the DP display module initialization command generate a DP video conversion start command to be transmitted to the DP video signal conversion unit 4 when receiving the DP video conversion enable signal from the RGB video signal conversion unit 3.
  • the LVDS video decoding and conversion configuration is manually set by the DIP switch 5-1.
  • the DP video conversion configuration module 5-3 After the power is turned on, the DP video conversion configuration module 5-3 generates the LVDS video decoding control signal and the LVDS video conversion according to the dialing state. Control signal; then read the DP video conversion configuration parameters from the JTAG interface 5-2, and write them one by one to the DP video signal conversion unit 4 in the form of register commands, first write the DP conversion configuration command, and confirm the DP video.
  • the signal conversion unit 4 writes the DP display module initialization command after the configuration starts and works normally. When each command is written, the status value of the register is read to ensure that the command execution is completed, and then the DP video conversion control is received. The signal writes the DP conversion start command to the register, causing the DP video conversion operation to begin.
  • Each function module of this embodiment can be implemented by an FPGA.
  • an ordinary MCU can also be used to implement its function.
  • two dedicated DP bridge chips can also be used. To achieve the conversion of the DP signal separately.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the buffer multiplying unit 6 is added on the basis of the first embodiment, and the LVDS video signal is converted into a DP1.2 video signal as an example for description.
  • the system for converting the LVDS video signal into the DP1.2 video signal in this embodiment includes an LVDS video signal conversion unit, a buffer multiplication unit, and a DP1.2 video signal conversion unit. among them,
  • the LVDS video signal conversion unit is configured to convert the LVDS video signal into an RGB video signal.
  • the process of converting the LVDS video signal into the RGB video signal in this embodiment may be the Chinese patent "LV104 video signal converted to 4LANE DP" with the publication number "CN104966477A”.
  • the LVDS video signal is converted into an RGB video signal as disclosed in the method and system for video signal, that is, by the LVDS video signal receiving unit 1, the LVDS video signal decoding unit 2, the RGB video signal converting unit 3, and the video conversion configuration unit 5.
  • the RGB video signal is obtained.
  • the conversion process is prior art and will not be described here.
  • the system for converting the LVDS video signal into the DP1.2 video signal of the embodiment further comprises buffering and multiplying the output RGB video signal by the output buffer multiplication unit 6, which is doubled.
  • the frequency unit 6 includes a left channel RGB video signal buffer multiplying unit 6-1, a right channel RGB video signal buffer multiplying unit 6-2, and an RGB video signal synchronizing unit 6-3.
  • the input of the left channel RGB video signal buffer multiplying unit 6-1 is connected to the RGB video signal output module 3-10, and the output is connected to the left DP1.2 video signal converting module 4-2; the right channel RGB video signal buffer multiplying unit 6-2 input and RGB video signal output module 3-10 connection output and right DP1.2 video signal conversion module 4-3; left DP1.2 video signal conversion module 4-2 and right DP1.2 video
  • the signal conversion module 4-3 is respectively connected with the DP1.2 display module connector, and the left DP1.2 video signal conversion module 4-2 and the right DP1.2 video signal conversion module 4-3 are also respectively associated with the DP1.2 register. Module 4-1 is connected.
  • the obtained RGB video signal buffer and multiplier output specifically the left channel RGB video signal buffer multiplier unit 6-1 will output the left channel RGB video signal for data buffering and data multiplication, improve left channel data and clock frequency;
  • the right channel RGB video signal buffer multiplying unit 6-2 performs data buffering and data multiplication on the output right channel RGB video signal to improve the right channel data and clock frequency;
  • the RGB video signal synchronizing unit 6-3 synchronizes the obtained left channel data and right channel data so that the two RGB data signals can be synchronously output.
  • the frequency signal is configured and converted by DP1.2 conversion to obtain a DP1.2 video signal, specifically:
  • DP1.2 register module 4-1 controls the configuration and operation of DP1.2 conversion according to the written DP1.2 register command
  • the left DP1.2 signal conversion module 4-2 receives the left channel RGB video signal after the left channel RGB video signal buffer multiplication unit 6-1 is synchronized, and converts the synchronized left channel RGB video signal into the left channel DP1.2. Video signal configuration and conversion operations;
  • the right channel DP1.2 signal conversion module 4-3 receives the right channel RGB video signal synchronized by the right channel RGB video signal buffer frequency multiplying unit 6-2, and performs conversion of the synchronized right channel RGB video signal into the right channel DP1.2. Video signal configuration and conversion operations;
  • DP1.2 display module connector 4-4 receives the left channel DP1.2 video signal and the right channel DP1.2 video signal at the same time, and is connected with the DP display module, and the left channel DP1.2 video signal and the right channel DP1 .2 The video signal is transmitted to the DP display module.
  • the present invention includes, but is not limited to, the display and test field of the liquid crystal module. Since the signal interface of the flat panel display module such as the OLED display module and the plasma display module has universal characteristics, the present invention can also be applied to the OLED. Display and test fields of flat panel display modules such as display modules and plasma display modules; in addition, since the signal interface standards of flat panel display modules are frequently updated and upgraded, the present invention includes but is not limited to the existing DP1.0/DP1. The conversion of the standard signal of the 1/DP1.2/DP1.3 interface is also compatible with the new DP interface standard signals subsequently issued by the Video Electronics Standards Association and other types of image interface standard signals having similar effects to the DP interface standard signals.

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Abstract

本发明涉及一种LVDS视频信号转换为DP视频信号的方法，该方法包括接收并解调LVDS视频信号，产生LVDS并行解调数据和LVDS像素时钟；根据LVDS视频解码控制信号，对LVDS并行解调数据进行视频解码，产生LVDS视频源数据和LVDS视频源同步信号；根据LVDS视频转换控制信号，将LVDS视频源数据和LVDS视频源同步信号转换为RGB视频信号，并对LVDS像素时钟进行相应的倍频操作，产生相应的RGB视频像素时钟；接收到DP视频转换启动命令后将RGB视频信号转换为DP视频信号。本发明能够对LVDS视频信号质量，图像数据正确性进行检测，具有可靠性高、无误判，操作简单、检测效率高、成本低的特点。

Description

LVDS视频信号转换为DP视频信号的方法及系统 技术领域
本发明涉及DP视频信号的产生，具体地指一种用于将LVDS视频信号转换为DP视频信号的方法及系统，属于液晶模组的显示和测试领域。
背景技术
液晶显示模组(Liquid Crystal Display Module，以下简称液晶模组)是液晶显示设备能正常显示的关键部件，它由液晶屏、背光原件、显示处理芯片及电路组成。液晶模组结构精密、制程复杂、生产工艺要求高，为了在生产时确保良品率，需要通过专用液晶模组测试装置产生各种测试视频信号输入到液晶模组中显示，从而严格、全面的检测其显示效果。目前，电视、显示器产品上用的普通液晶模组其显示接口和内部显示处理电路使用LVDS(Low-Voltage Differential Signaling，低压差分信号)信号来工作，而现有的液晶模组测试装置也相应输出的是LVDS视频信号以实现模组的测试，由于普通液晶模组投产时间久、产量大，因此其模组测试装置也大量使用。
然而，随着人们在液晶显示模组上不断追求更高清晰度、更逼真的显示效果及传频宽需求大幅增加，用来支援这些频宽的LVDS线路的数目大增，导致电视制造商担负更多生产成本和复杂性，因此普通液晶模组逐渐无法满足这种需要。于是市场上出现了一种具有超高分辨率和超高像素密度的新型液晶模组来满足人们的需求，这种液晶模组采用DP(DisplayPort显示接口)信号接口，具有更好传输速度，更好的传输距离，更好的EMI兼容性，以及更好的价格优势，因此带有DP接口的液晶模组已成为发展趋势。
然而DP液晶模组的测试装置需要输出同样的DP测试信号，但是现有普通液晶模组测试装置并不具备这一功能，并且普通液晶模组还继续在生产，其测试装置也未进入代换周期仍将继续使用。模组生产商虽然也生产DP液晶模组，但为了保护投资、降低生产成本，不可能淘汰现有设备、重新大量购买昂贵的DP模组专用测试装置。为了能在短时期内低成本的大批量生产DP液晶模组并保证其良品率，就仍然得大规模重复使用现有的普通模组测试装置。
因此，需要研究一种转换装置能将LVDS视频信号转换为DP视频信号，使普通液晶模组测试装置通过该转换装置能对DP模组进行测试，同时该转换装置不仅要性能可靠、集成高效、而且要价格便宜、操作简便。
发明内容
本发明目的在于克服上述现有技术的不足而提供一种LVDS视频信号转换为DP视频信号的方法及系统，本发明能够对LVDS视频信号质量，图像数据正确性进行检测，具有可靠性高、无误判，操作简单、检测效率高、成本低的特点。
实现本发明目的采用的一种技术方案是：一种LVDS视频信号转换为DP视频信号的方法，该方法包括：
将LVDS视频信号以单LINK、双LINK、四LINK中任意一种方式传输，转换为RGB视频信号；
根据DP转换配置命令和DP转换启动命令控制进行DP转换的配置和转换。
另外，本发明还提供一种LVDS视频信号转换为DP视频信号的系统，该系统包括：
LVDS视频信号转换单元，用于将LVDS视频信号转换为RGB视频信号；
DP视频信号转换单元，用于根据DP转换配置命令和DP转换启动命令控制进行DP转换的配置和转换。
另外，本发明还提供一种LVDS视频信号转换为DP视频信号的方法，该方法包括：
将LVDS视频信号转换为RGB视频信号；
对所述RGB视频信号缓冲和倍频后输出；
根据DP转换配置命令和DP转换启动命令对输出的倍频信号进行DP转换的配置和转换，得到DP视频信号。
另外，本发明还提供一种LVDS视频信号转换为DP视频信号的系统，该系统包括：
LVDS视频信号转换单元，用于将LVDS视频信号转换为RGB视频信号；
缓存倍频单元，用于对所述RGB视频信号缓冲和倍频后输出；
DP视频信号转换单元，用于根据DP转换配置命令和DP转换启动命令对输出的倍频信号进行DP转换的配置和转换，得到DP视频信号。
本发明具有以下优点：
(1)本发明能对视频源产生的1Lane、2Lane、4Lane的DP视频信号进行检测，本发明通过设置，能很好的适应于不同的DP传输特性、视频信号的色阶、传输方式、编码方式等不同特性。
(2)本发明能对视频源产生的DP视频信号的电气特性进行检测，通过输入DP电气参数标准，在本发明中经过比对得到检测结果并输出显示。
(3)本发明能对视频源产生的DP视频信号的图像数据检测，通过预先缓存每帧图像数据并和原始视频图像对比，从而判断出每个像素是否输出正确，每帧图像均可进行检测。
(4)本发明能对最高的DP视频分辨率检测，不仅集成度高，工作可靠、抗干扰能力强，而且操作简单、经济实用，不仅能提升DP液晶模组的检测可靠性和效率，降低其设备成本和生产成本，也将进一步提高相关显示设备的普及。
(5)本发明能通过用FPGA(现场可编程逻辑阵列)芯片、DDR(Double Date Rate双数据速率)存储芯片、A/D(模拟/数字)转换芯片来实现所述全部功能；上述器件均是市场常见芯片，它们不仅工作稳定、实现容易，而且价格便宜，避免了因使用各种专用芯片而导致的设计复杂、稳定性差、设计成本高等问题。
(6)本发明每个信道的数据传输率翻番到5.4Gbps，总带宽最高可达21.6Gbps，能大大提升显示分辨率(Max 3840x2160@60hz)、色深、刷新率、多显示能力。
(7)支持多流，只需一根数据线即可传输多个独立的未压缩视频和音频流。
(8)本发明支持高速双向数据传输，可在标准DP数据线内传输USB2.0或以太网数据。
(9)本发明支持菊花链链接，允许DP输入显示设备复制输入的数据，再通过另外一个DP输出到其他显示设备。
附图说明
图1为本发明实施例一LVDS视频信号转换为DP视频信号的装置结构框图；
图2为图1中LVDS视频信号接收单元和LVDS视频信号解码单元的电路方框图；
图3为图1中RGB视频信号转换单元、DP视频信号转换单元和视频转换配置单元的电路方框图；
图4为本发明实施例一LVDS视频信号转换为DP视频信号的方法流程图；
图5为本发明实施例二LVDS视频信号转换为DP1.2视频信号的系统结构框图。
图中：1.LVDS视频信号接收单元，1-1.LVDS视频信号接口，1-2.LVDS视频信号接收端接模块，1-3.四LINK的LVDS时钟信号解调模块，1-4.四LINK的LVDS数据信号解调模块，1-5.LVDS解调动态校准模块；
2.LVDS视频信号解码单元，2-1.LVDS视频同步缓冲模块，2-2.四LINK的LVDS视频信号线序控制模块，2-3.LVDS视频同步信号解码模块，2-4.四LINK的LVDS视频数据解码模块；
3.RGB视频信号转换单元，3-1.RGB视频信号自适应控制模块，3-2.RGB视频时钟自适应配置模块，3-3RGB.视频时钟产生模块，3-4.RGB视频时钟输出调整模块，3-5.单链路模式RGB视频转换模块，3-6.双链路模式RGB视频转换模块，3-7.四链路模式RGB视频转换模块，3-8.左右分屏模式RGB视频转换模块，3-9.奇偶分屏模式RGB视频转换模块，3-10.RGB视频信号输出模块；
4.DP视频信号转换单元，4-1.DP寄存器模块，4-2.左路DP视频信号转换模块，4-3.右路DP视频信号转换模块，4-4.DP显示模组连接件；
5.视频转换配置单元，5-1.手动拨码开关，5-2.JTAG接口，5-3.DP视频转换配置模块；
6.缓存倍频单元，6-1.左通道RGB视频信号缓存倍频单元，6-2.右通道RGB视频信号缓存倍频单元，6-3.RGB视频信号同步单元。
具体实施方式
下面结合附图和具体实施例对本发明作进一步的详细说明。
实施例一：
如图1～3所示，本实施例LVDS视频信号转换为DP视频信号的系统包括用于将LVDS视频信号转换为RGB视频信号的LVDS视频信号转换单元、DP视频信号转换单 元4和视频转换配置单元5。其中，LVDS视频信号转换单元包括LVDS视频信号接收单元1、LVDS视频信号解码单元2和RGB视频信号转换单元3。
上述本实施例LVDS视频信号转换为DP视频信号的系统的工作过程如图4所示，包括以下具体步骤：
S100、LVDS视频信号接收单元1接收LVDS视频信号，对接收的LVDS视频信号解调产生LVDS并行解调数据和LVDS像素时钟。本实施例LVDS视频信号接收单元1包括：LVDS视频信号接口1-1、LVDS视频信号接收端接模块1-2、LVDS时钟信号解调模块1-3、LVDS数据信号解调模块1-4和LVDS解调动态校准模块1-5，其中，LVDS视频信号接收端接模块1-2与LVDS视频信号接口1-1连接，LVDS时钟信号解调模块1-3和LVDS数据信号解调模块1-4分别与LVDS视频信号接收端接模块1-2连接，LVDS解调动态校准模块1-5分别与LVDS时钟信号解调模块1-3和LVDS数据信号解调模块1-4连接。对每个模块的详细说明如下：
LVDS视频信号接口1-1接收LVDS视频信号，LVDS视频信号包括单LINK、双LINK、四LINK的LVDS视频信号，单LINK的LVDS视频信号即LINK1传输所有视频像素；双LINK的LVDS视频信号包括LINK1、LINK2二个链路，分别传输奇偶视频像素；四LINK的LVDS视频信号包括四个链路，按照视频像素顺序的在LINK1、LINK2、LINK3、LINK4依次传输。本实施例DP视频信号包括1Lane类型、2Lane类型、4Lane类型的DP显示模组，当所要转换的DP视频信号输出给4LANE单一整屏类型的DP显示模组时，LVDS视频信号以单LINK、双LINK、四LINK中任意一种方式传输；当所要转换的DP视频信号输出给8LANE左右分屏类型、8LANE奇偶分屏类型的DP液晶显示模组时，LVDS视频信号仅以四LINK方式传输。每个链路的LVDS视频信号包括LVDS接收时钟和LVDS数据，LVDS数据由LVDS数据总线传输，LVDS数据总线包括若干根根信号线，每根信号线传送串行编码信号。LVDS视频信号接口1-1通过连接LVDS传输线接口来输入LVDS视频信号，接口包括两种输入连接件：工业标准牛角座连接件和小型高密度商业连接件，以确保本实施例在工业环境和商业环境均能适用，当某一个连接件有LVDS信号输入时，接口能自动从该连接件输出，当两个连接件都有信号输入时，接口默认从小型高密度商业连接件输出。
LVDS视频信号接收端接模块1-2对LVDS视频信号接口1-1接收的LVDS视频信号进行端接操作，然后分别将LVDS接收时钟和LVDS数据传送给LVDS时钟信号解调模块1-3和LVDS信号解调模块1-4。端接操作包括：LVDS端接电阻匹配、LVDS信号电平匹配、LVDS信号均衡与去加重、信号缓冲与重建，补偿因长距离传输所导致信号畸变、衰减，减小传输干扰，确保所接收的LVDS信号质量。端接的过程包括：在接收LVDS信号前进行ESD(Electro Static Discharge静电放电)防护处理以消除瞬间的强放电冲击干扰，再进行共模噪声滤波处理以抑制传输线噪声、提高抗电磁干扰能力。当接收信号时进行端接阻抗匹配处理以消除信号传输引起的畸变，也进一步消除信号的附加干扰，同时对信号进行均衡和去加重处理，以消除因传输损耗所导致的信号衰减。之后再对信号缓冲放大，并经过基准电平的判决来重建出高质量的LVDS视频信号。
LVDS时钟信号解调模块1-3对接收的每个LINK的LVDS接收时钟进行解调，产生解调时钟和解调使能信号；解调过程包括：将LVDS接收时钟经高速IO缓冲输入到PLL(Phase Locked Loop锁相环路)将其倍频到LVDS数据信号频率，并进行高速时钟转换处理，产生与LVDS数据同频率的LVDS解调时钟，与LVDS接收时钟同频的LVDS像素时钟和LVDS解调选通信号，并输出到高速时钟网络中，使它们具有很低的延迟和抖动、很强的驱动能力，确保能稳定可靠的对LVDS数据进行解调。在用PLL对LVDS接收时钟进行倍频操作时，来自LVDS解调动态校准模块1-5的时钟去抖动校准信号同时也送入PLL以对该操作过程进行反抖动控制，使其产生不受输入抖动影响、稳定的倍频信号，确保解调操作能不受干扰不出差错。
LVDS数据信号解调模块1-4通过每个LINK的解调时钟和解调使能信号对本LINK的LVDS数据解调成并行数据，LVDS接收时钟同时被解调为LVDS像素时钟。其过程包括：对LVDS串行数据总线中的每一位数据分别独立的解调。将每一位LVDS数据信号先缓冲到低延迟、低抖动的高速信号网络中，再将其延迟半个数据比特位周期，使得LVDS解调时钟在每个LVDS数据比特的中心能正确的采样到该数据值，并根据解调选通信号将其周期性的截断成串化数据，再用LVDS视频源像素时钟做串转并处理得到这一位LVDS信号的并行解调数据，通过触发器缓冲输出以确保信号稳定、可靠。每一位LVDS信号线均同步并行的解调，使得各信号线不管数据如何均不会相互干扰导致解调 错误。
在用LVDS解调时钟采样LVDS数据的比特值时，来自LVDS解调动态校准模块1-5的数据去抖动校准信号同时也对该操作过程进行反抖动控制，使其产生不受输入抖动影响、稳定可靠的解调数据。
在数据输入的相位延迟过程始终受到LVDS解调动态校准模块1-5的LVDS数据流相位校准信号控制，当解调时钟和LVDS数据间的相位有偏差时，相位校准信号在数据延迟半个周期基础上做出其和相位偏差相反的延迟调整，使得数据中心始终和解调时钟的采样沿保持对齐，确保正确采样到数据。
在解调选通信号进行截断串行数据的同时，也受到LVDS解调动态校准模块1-5的解调字节对齐的比特位移动校准信号控制，使之将分割的并行数据的起始位移动到下一个串行比特位上。
LVDS解调动态校准模块1-5分别对LVDS接收时钟和LVDS数据的串化信号在解调过程中分别实时地进行动态校准。
S200、LVDS视频信号解码单元2根据LVDS视频解码控制信号，对LVDS并行解调数据进行视频解码，产生LVDS视频源数据和LVDS视频源同步信号。本实施例LVDS视频信号解码单元2包括：LVDS视频同步缓冲模块2-1、LVDS视频信号排序模块2-2、LVDS视频同步信号解码模块2-3和LVDS视频数据解码模块2-4，对每个模块的详细说明如下：
LVDS视频同步缓冲模块2-1将LINK1的LVDS像素时钟通过全局时钟路径转换成LVDS视频源像素时钟，同时用所输入的各LINK的LVDS像素时钟将各自的LVDS并行解调数据分别写到DC-FIFO(First Input First Output，先入先出队列)中缓存后，用LVDS视频源像素时钟逐一读取，使之成为同步数据，避免在传输中信号间延迟不一致所导致读取错误。缓存深度尽可能大，以使所有LINK都有足够多的数据被缓存来抵消它们之间最大延迟。
LVDS视频信号排序模块2-2当接收到LVDS奇偶像素反向控制信号时将两个链路中LINK1和LINK2的数据进行交换，接收到LVDS视频信号线序控制信号时对四个链路按照LINK1、LINK2、LINK3、LINK4排列次序。
LVDS视频同步信号解码模块2-3根据从视频转换配置单元5接收的LVDS视频解码控制信号对同步读取的每个LINK的LVDS并行解调数据进行解码，解码出LVDS视频源同步信号；根据LVDS视频解码控制信号中的VESA和JEIDA传输编码标准对排序后的LINK1用LVDS视频源像素时钟以时序逻辑操作方式进行解码恢复出LVDS视频源同步信号并输出，同步信号包括：视频水平行同步信号(Hsync)、视频垂直场同步信号(Vsync)、视频数据有效信号(DE)。
LVDS视频数据解码模块2-4根据从视频转换配置单元5接收的LVDS视频解码控制信号对同步读取的每个LINK的LVDS并行解调数据进行解码，解码出各LINK的LVDS视频源数据信号。
S300、RGB视频信号转换单元3根据LVDS视频转换控制信号，将LVDS视频源数据和LVDS视频源同步信号转换为RGB视频信号；转换完成后将DP视频转换启动信号传送给视频转换配置单元5。本实施例RGB视频信号转换单元3包括：RGB视频信号自适应控制模块3-1、RGB视频时钟自适应配置模块3-2、RGB视频时钟产生模块3-3、RGB视频时钟输出调整模块3-4、单链路模式RGB视频转换模块3-5、双链路模式RGB视频转换模块3-6、四链路模式RGB视频转换模块3-7、左右分屏模式RGB视频转换模块3-8、奇偶分屏模式RGB视频转换模块3-9和RGB视频信号输出模块3-10，对每个模块的详细说明如下：
RGB视频信号自适应控制模块3-1根据LVDS视频转换控制信号产生相匹配的单LINK、双LINK、四LINK中任意一种模式的RGB视频时钟配置信号，连同LVDS视频源像素时钟传送给RGB视频时钟自适应配置模块3-2；根据LVDS视频转换控制信号产生RGB转换模块选择信号连同各LINK的LVDS视频源数据信号、LVDS视频源同步信号连同RGB视频时钟传送给单链路模式RGB视频转换模块3-5、双链路模式RGB视频转换模块3-6、四链路模式RGB视频转换模块3-7、左右分屏模式RGB视频转换模块3-8、奇偶分屏模式RGB视频转换模块3-9，检测LVDS视频同步信号计算水平分辨率值，将水平分辨率值传送给单链路模式RGB视频转换模块3-5；
RGB视频时钟自适应配置模块3-2根据所产生的单LINK、双LINK、四LINK中任意一种模式的RGB视频时钟配置信号，由本地时钟信号产生相应的单LINK、双LINK、 四LINK中任意一种模式的配置参数和配置使能信号，来对时钟产生模块进行动态重配置操作。RGB视频时钟产生模块3-3根据配置时钟和使能信号产生RGB视频时钟传送给RGB视频信号自适应控制模块3-1和RGB视频时钟输出调整模块3-4。将PLL配置参数按照其动态重配置时序对PLL进行重配置操作，使之将LVDS像素时钟进行相应的倍频操作。当配置成单LINK模式时，LVDS视频源像素时钟被转换成为其同频率的RGB视频像素时钟(以下简称RGB时钟)；当配置成双LINK模式时，LVDS视频源像素时钟被转换成为二倍频的RGB视频像素时钟；当配置成四LINK模式时，LVDS视频源像素时钟被转换成为四倍频的RGB视频像素时钟(此时四个LINK内每个LINK均传输一个完整画面的四分之一图像)。当四LINK模式中，RGB视频信号被按左右分屏或奇偶分屏模式转换时，LVDS视频源像素时钟被转换成为其二倍频的RGB视频像素时钟。所产生的倍频信号再调整其相位使之和LVDS像素时钟保持相位严格相同，(以确保后续在转换处理的时序逻辑操作中能正确、可靠的采样到LVDS数据)，再经过去抖动处理后进入稳定、无摆动的全局时钟路径，从而产生RGB视频时钟。
RGB视频时钟输出调整模块3-4，由于RGB视频源数据信号和RGB视频时钟同步，因此将输入的RGB视频时钟相位延迟半个时钟周期作为RGB输出时钟信号，使其有效沿能处于RGB视频源数据的中心，从而确保后续的转换操作通过该时钟正确采样RGB数据，之后该信号再进行去抖动处理，并通过高速信号缓冲组件将其输出给RGB视频信号输出模块3-10，以确保该输出时钟有较高的稳定性和较好的信号质量。
用RGB时钟将LVDS视频源同步信号和数据转换成RGB视频同步信号和数据；当DP液晶显示模组是4LANE整屏类型时，根据LINK转换模式控制信号单独进行LVDS单LINK、双LINK、四LINK模式的视频转换；当DP显示模组是8LANE分屏类型时根据转换控制信号单独进行左右分屏模式和奇偶分屏模式的视频转换。
单链路模式RGB视频转换模块3-5将单LINK的LVDS视频源同步信号和LVDS视频源数据转换为RGB视频信号传送给RGB视频信号输出模块3-10；
双链路模式RGB视频转换模块3-6将双LINK的LVDS视频源同步信号和LVDS视频源数据转换为RGB视频信号传送给RGB视频信号输出模块3-10；
四链路模式RGB视频转换模块3-7将四LINK的LVDS视频源同步信号和LVDS视 频源数据转换为RGB视频信号传送给RGB视频信号输出模块3-10；
左右分屏模式RGB视频转换模块3-8将四LINK的LVDS视频源同步信号和LVDS视频源数据转换为左半屏RGB视频信号、右半屏RGB视频信号传送给RGB视频信号输出模块3-10；进行左右分屏模式的视频转换过程是：左右分屏模式RGB视频转换模块3-8将四LINK的LVDS数据按照“LINK1、LINK2、LINK3、LINK4”形式组成并行数据，根据所输入的LVDS同步信号确定当第一个完整的视频行起始时，根据前述中所得出的行分辨率值，用LVDS时钟将前、后半行的LINK并行数据采样并分别写入左、右半屏DC-FIFO中缓存另一方面也被两倍频的RGB视频时钟同时读取各自的缓存数据并分离为左半屏RGB数据、右半屏RGB数据和同步信号，组成左半屏RGB视频信号和右半屏RGB视频信号；由于数据和同步信号读写操作的吞吐量相等，故转换操作能连续稳定的进行。
奇偶分屏模式RGB视频转换模块3-9将四LINK的LVDS视频源同步信号和LVDS视频源数据转换为奇像素RGB视频信号、偶像素RGB视频信号传送给RGB视频信号输出模块3-10；进行奇偶分屏模式的视频转换过程是：奇偶分屏模式RGB视频转换模块3-9在四LINK的LVDS数据中先检测出两个奇像素和两个偶像素的LINK，再将LVDS同步信号和奇、偶各两个LINK数据分别组成并行数据按照前述中的双LINK模式转换方式进行处理，从而各自产生奇像素、偶像素的RGB视频数据和RGB同步信号，组成奇像素RGB视频信号和偶像素RGB视频信号。
RGB视频信号输出模块3-10根据RGB转换模块选择信号选择相应的RGB视频信号连同RGB输出时钟传送给DP视频信号转换单元4。当产生同步模式控制时则对视频同步信号反向操作；对比RGB输出时钟的有效沿和RGB数据的采样中心之间的相位，并通过信号延时组件分别对输出时钟和数据做延时微调处理以消除两者间的相位差，确保输出时钟有效沿始终处于数据的采样中心。
S400、当从视频转换配置单元5接收到DP视频转换启动命令后DP视频信号转换单元4将RGB视频信号转换为DP视频信号传送给DP显示模组。本实施例DP视频信号转换单元4，包括：DP寄存器模块4-1、左路DP视频信号转换模块4-2、和右路DP视频信号转换模块4-3和DP液晶显示模组连接件4-4，对每个模块的详细说明如下：
DP寄存器模块4-1根据写入的DP寄存器命令控制左路DP视频信号转换模块4-2和右路DP视频信号转换模块4-3同时进行DP转换的配置和操作，这些DP寄存器命令包括：DP转换配置命令、DP转换启动命令。
左路DP视频信号转换模块4-2接收RGB视频信号，执行将RGB视频信号转换为左通道DP视频信号的配置和转换操作，将转换后的左通道的DP视频信号传送给DP液晶显示模组连接件4-4，当从DP寄存器模块4-1接收DP转换配置命令时完成相应配置、转换操作，当从DP寄存器模块4-1接收DP显示模组初始化命令时通过DP液晶显示模组连接件4-4传输给DP显示模组，当从DP寄存器模块4-1接收DP转换启动命令时启动转换操作。
右路DP视频信号转换模块4-3接收RGB视频信号，执行将RGB视频信号转换为右通道DP视频信号的配置和转换操作，将转换后的右通道DP视频信号传送给DP液晶显示模组连接件4-4，当从DP寄存器模块4-1接收DP转换配置命令时完成相应配置、转换操作，当从DP寄存器模块4-1接收DP显示模组初始化命令时通过DP液晶显示模组连接件4-4传输给DP显示模组，当从DP寄存器模块4-1接收DP转换启动命令时启动转换操作。
当转换模块选择信号是单、双、四LINK模式时，则将其RGB数据和同步信号(整屏信号)复制成两路输出给DP视频信号转换单元4；当选择左右分屏转换模式则左、右半屏数据和同步信号分别输出左半屏RGB视频信号、右半屏RGB视频信号给左路DP视频信号转换模块4-2和右路DP视频信号转换模块4-3；当选择奇偶分屏转换模式则奇像素并行数据、偶像素并行数据和同步信号分别输出RGB奇分屏视频信号和RGB偶分屏视频信号给DP视频信号转换单元4。
DP液晶显示模组连接件4-4同时接收左通道DP视频信号和右通道DP视频信号，并与DP显示模组6连接，将左通道DP视频信号和右通道DP视频信号传送给DP显示模组。
视频转换配置单元5，根据所要接收的LVDS视频信号的特性，设置LVDS视频信号解码参数，产生LVDS视频解码控制信号，传送给LVDS视频信号解码单元2；设置LVDS视频转换参数，产生LVDS视频转换控制信号，传送给RGB视频信号转换单元3； 读取DP视频转换配置参数对DP视频信号转换单元4发出DP转换配置命令、DP显示模组初始化命令；从RGB视频信号转换单元3接收到DP视频转换启动信号后发出DP视频转换启动命令传送给DP视频信号转换单元4。本实施例视频转换配置单元5包括：手动拨码开关5-1、JTAG接口5-2和DP视频转换配置模块5-3，对每个模块的详细说明如下：
手动拨码开关5-1设置LVDS视频信号解码参数和LVDS视频转换参数；JTAG接口5-2接收DP视频转换配置参数；DP视频转换配置模块5-3将LVDS视频信号解码参数转换为LVDS视频解码控制信号传送给LVDS视频信号解码单元2，将LVDS视频转换参数转换为LVDS视频转换控制信号，传送给RGB视频信号转换单元3，读取DP视频转换配置参数对DP视频信号转换单元4发出DP转换配置命令、DP显示模组初始化命令，当从RGB视频信号转换单元3接收DP视频转换启动信号后产生DP视频转换启动命令传送给DP视频信号转换单元4。
在上电前对LVDS视频解码和转换的配置先手动设置好拨码开关5-1，上电后由DP视频转换配置模块5-3根据其拨码状态产生LVDS视频解码控制信号和LVDS视频转换控制信号；之后从JTAG接口5-2读取DP视频转换配置参数，并将其以寄存器命令的方式逐一写入到DP视频信号转换单元4中，先写入DP转换配置命令，当确认DP视频信号转换单元4完成配置开始并正常工作后再写入DP显示模组初始化命令，当每写一个命令后则读取其寄存器的状态值，以确保命令执行完成，之后当收到DP视频转换控制信号则将DP转换启动命令写入寄存器，使DP视频转换操作开始进行。
本实施例的各个功能模块均可通过FPGA来实现，对于DP视频转换配置模块5-3也可用普通MCU来实现其功能，对于DP视频信号转换单元4也可通过使用两颗专用的DP桥接芯片来分别实现DP信号的转换。
实施例二：
本实施例在实施例一的基础上增加了缓存倍频单元6，以LVDS视频信号转换为DP1.2视频信号为例进行说明。
如图5、图2所示，本实施例LVDS视频信号转换为DP1.2视频信号的系统包括LVDS视频信号转换单元、缓存倍频单元和DP1.2视频信号转换单元。其中，
LVDS视频信号转换单元用于将LVDS视频信号转换为RGB视频信号，本实施例将LVDS视频信号转换为RGB视频信号的过程可为公开号为“CN104966477A”的中国专利《LVDS视频信号转换为4LANE DP视频信号的方法及系统》中所公开的将LVDS视频信号转换为RGB视频信号一样，即通过LVDS视频信号接收单元1、LVDS视频信号解码单元2、RGB视频信号转换单元3和视频转换配置单元5得到RGB视频信号，该转换过程为现有技术，此处不再赘述。
相对于公开号为“CN104966477A”的中国专利，本实施例LVDS视频信号转换为DP1.2视频信号的系统还包括用于对所得RGB视频信号缓冲和倍频后输出缓存倍频单元6，缓存倍频单元6包括左通道RGB视频信号缓存倍频单元6-1、右通道RGB视频信号缓存倍频单元6-2和RGB视频信号同步单元6-3。左通道RGB视频信号缓存倍频单元6-1的输入与RGB视频信号输出模块3-10连接，输出与左路DP1.2视频信号转换模块4-2连接；右通道RGB视频信号缓存倍频单元6-2的输入与RGB视频信号输出模块3-10连接输出与右路DP1.2视频信号转换模块4-3连接；左路DP1.2视频信号转换模块4-2和右路DP1.2视频信号转换模块4-3分别与DP1.2显示模组连接件连接，左路DP1.2视频信号转换模块4-2和右路DP1.2视频信号转换模块4-3还分别与DP1.2寄存器模块4-1连接。
通过上述系统实现LVDS视频信号转换为DP1.2视频信号的过程如下：
1、将LVDS视频信号转换为RGB视频信号，该步骤为现有技术，
此处不再赘述。
2、对所得RGB视频信号缓冲和倍频后输出，具体为左通道RGB视频信号缓存倍频单元6-1将输出的左通道RGB视频信号进行数据缓冲和数据倍频，提高左通道数据和时钟频率；
右通道RGB视频信号缓存倍频单元6-2将输出的右通道RGB视频信号进行数据缓冲和数据倍频，提高右通道数据和时钟频率；
RGB视频信号同步单元6-3将所得左通道数据和右通道数据进行同步，使2路RGB数据信号能够同步输出。
根据DP1.2转换配置命令和DP1.2转换启动命令对输出的倍
频信号进行DP1.2转换的配置和转换，得到DP1.2视频信号，具体为：
DP1.2寄存器模块4-1根据写入的DP1.2寄存器命令控制DP1.2转换的配置和操作；
左路DP1.2信号转换模块4-2接收左通道RGB视频信号缓存倍频单元6-1同步后的左通道RGB视频信号，执行将同步后的左通道RGB视频信号转换为左通道DP1.2视频信号的配置和转换操作；
右路DP1.2信号转换模块4-3接收右通道RGB视频信号缓存倍频单元6-2同步后的右通道RGB视频信号，执行将同步后的右通道RGB视频信号转换为右通道DP1.2视频信号的配置和转换操作；
DP1.2显示模组连接件4-4同时接收所得左通道DP1.2视频信号和右通道DP1.2视频信号，并与DP显示模组连接，将左通道DP1.2视频信号和右通道DP1.2视频信号传送给DP显示模组。
需要说明的是，本发明包括但不限于液晶模组的显示和测试领域，由于OLED显示模组、等离子显示模组等平板显示模组的信号接口具有通用性特点，本发明还可以应用到OLED显示模组、等离子显示模组等平板显示模组的显示和测试领域；另外，由于平板显示模组的信号接口标准频繁更新、升级，本发明包括但不限于已有的DP1.0/DP1.1/DP1.2/DP1.3接口标准信号的转换，还可以兼容视频电子标准协会后续发布的新的DP接口标准信号以及与DP接口标准信号具有类似效果的其他类型的图像接口标准信号。
本发明不局限于上述实施方式，对于本技术领域的普通技术人员来说，根据本发明的技术原理和方案或在本发明的启示下所做出的若干改进、改变、润饰、变形、替换也视为本发明专利的保护范围之内。

Claims (14)

  1. 一种LVDS视频信号转换为DP视频信号的方法，其特征在于，包括以下步骤：
    步骤1：接收LVDS视频信号并解调所接收的LVDS视频信号，产生LVDS并行解调数据和LVDS像素时钟；
    步骤2：根据LVDS视频解码控制信号和LVDS像素时钟对LVDS并行解调数据进行视频解码，产生LVDS视频源数据和LVDS视频源同步信号；
    步骤3：根据LVDS视频转换控制信号将LVDS视频源数据和LVDS视频源同步信号转换为RGB视频信号；
    步骤4：根据DP转换配置命令和DP转换启动命令对所述RGB视频信号进行DP转换配置和DP转换操作，得到DP视频信号。
  2. 根据权利要求1所述LVDS视频信号转换为DP视频信号的方法，其特征在于，步骤1包括以下步骤：
    接收LVDS视频信号，所述LVDS视频信号包括LVDS接收时钟和LVDS数据；
    对所接收的LVDS视频信号进行端接操作，将LVDS接收时钟和LVDS数据输出；
    对每个LINK的LVDS接收时钟进行解调，产生解调时钟和解调使能信号；
    通过每个LINK的解调时钟和解调使能信号将该LINK的LVDS数据解调成LVDS并行解调数据，LVDS接收时钟同时被解调为LVDS像素时钟。
  3. 根据权利要求1所述LVDS视频信号转换为DP视频信号的方法，其特征在于，步骤2包括以下步骤：
    将LVDS像素时钟通过全局时钟路径转换成LVDS视频源像素时钟；同时，用每个LINK的LVDS像素时钟分别将所述每个LINK的LVDS并行解调数据写到DC-FIFO中缓存后，并用所述LVDS视频源像素时钟逐一读取，使之成为同步数据；
    当接收到LVDS奇偶像素反向控制信号时将两个链路中LINK1和LINK2的数据进行交换，接收到LVDS视频信号线序控制信号时对四个链路按照LINK1、LINK2、LINK3、LINK4排列次序；
    根据接收的LVDS视频解码控制信号对同步读取的每个LINK的LVDS并行解调数据进行解码，解码出LVDS视频源同步信号；
    根据接收的LVDS视频解码控制信号对同步读取的每个LINK的LVDS并行解调数据进行解码，解码出各LINK的LVDS视频源数据信号。
  4. 根据权利要求3所述LVDS视频信号转换为DP视频信号的方法，其特征在于，步骤3包括以下步骤：
    根据所述LVDS视频转换控制信号产生相匹配的RGB视频时钟配置信号；
    根据所述RGB视频时钟配置信号，由本地时钟信号产生相应的配置参数和配置使能信号；
    根据所述配置时钟和配置使能信号产生RGB视频时钟，并对所述LVDS像素时钟进行相应的倍频操作，当
    配置成单LINK模式时，所述LVDS视频源像素时钟被转换成为其同频率的RGB视频像素时钟；或者，
    配置成双LINK模式时，所述LVDS视频源像素时钟被转换成为二倍频的RGB视频像素时钟；或者，
    配置成四LINK模式时，所述LVDS视频源像素时钟被转换成为四倍频的RGB视频像素时钟；
    将输入的所述RGB视频时钟相位延迟半个时钟周期作为RGB输出时钟信号；
    将单LINK的LVDS视频源同步信号和LVDS视频源数据转换为RGB视频信号输出；或者，
    将双LINK的LVDS视频源同步信号和LVDS视频源数据转换为RGB视频信号输出；或者，
    将四LINK的LVDS视频源同步信号和LVDS视频源数据转换为RGB视频信号输出；或者，
    将四LINK的LVDS视频源同步信号和LVDS视频源数据转换为左半屏RGB视频信号、右半屏RGB视频信号输出；或者，
    将四LINK的LVDS视频源同步信号和LVDS视频源数据转换为奇像素RGB视频信号、偶像素RGB视频信号传送给RGB视频信号输出；
    根据RGB转换模块选择信号选择相应的RGB视频信号连同所述RGB输出时钟输出进行DP视频信号转换。
  5. 根据权利要求1所述LVDS视频信号转换为DP视频信号的方法，其特征在于，根据写入的DP寄存器命令完成所述DP转换配置命令和所述DP转换启动命令的下发，步骤4包括以下步骤：
    接收所述左通道RGB倍频信号并根据所述DP转换配置命令和所述DP转换启动命令将所述左通道RGB倍频信号进行DP转换配置和DP转换操作，得到左通道DP视频信号；同时，
    接收所述右通道RGB倍频信号并根据所述DP转换配置命令和所述DP转换启动命令将所述右通道RGB倍频信号进行DP转换配置和DP转换操作，得到右通道DP视频信号。
  6. 一种LVDS视频信号转换为DP视频信号的系统，其特征在于，包括设置于一颗可编程逻辑器件中的LVDS视频信号转换单元和DP视频信号转换单元；其中，
    所述LVDS视频信号转换单元用于将LVDS视频信号转换为RGB视频信号；
    所述DP视频信号转换单元用于根据DP转换配置命令和DP转换启动命令对所述RGB视频信号进行DP转换配置和DP转换操作，得到DP视频信号。
  7. 根据权利要求6所述LVDS视频信号转换为DP视频信号的系统，其特征在于，所述LVDS视频信号转换单元包括：
    LVDS视频信号接收单元，用于接收LVDS视频信号，并解调所接收的LVDS视频信号，产生LVDS并行解调数据和LVDS像素时钟；
    LVDS视频信号解码单元，用于根据LVDS视频解码控制信号和LVDS像素时钟对LVDS并行解调数据进行视频解码，产生LVDS视频源数据和LVDS视频源同步信号；以及
    RGB视频信号转换单元，用于根据LVDS视频转换控制信号将LVDS视频源数据和LVDS视频源同步信号转换为RGB视频信号。
  8. 根据权利要求6或7所述LVDS视频信号转换为DP视频信号的系统，其特征在于，所述DP视频信号转换单元包括：
    DP寄存器模块，用于根据写入的DP寄存器命令完成所述DP转换配置命令和所述DP转换启动命令的下发；
    左路DP信号转换模块，用于接收所述左通道RGB倍频信号并根据所述DP转换配 置命令和所述DP转换启动命令将所述左通道RGB倍频信号进行DP转换配置和DP转换操作得到左通道DP视频信号；
    右路DP信号转换模块，用于接收所述右通道RGB倍频信号并根据所述DP转换配置命令和所述DP转换启动命令将所述右通道RGB倍频信号进行DP转换配置和DP转换操作得到右通道DP视频信号；
    DP显示模组连接件，用于同时接收左通道DP视频信号和右通道DP视频信号，并与DP显示模组连接，将左通道DP视频信号和右通道DP视频信号传送给DP显示模组。
  9. 一种LVDS视频信号转换为DP视频信号的方法，其特征在于，包括以下步骤：
    步骤S1：将LVDS视频信号转换为RGB视频信号；
    步骤S2：对所述RGB视频信号依次进行数据缓冲和数据倍频处理，得到RGB倍频信号；
    步骤S3：根据DP转换配置命令和DP转换启动命令对所述RGB倍频信号进行DP转换配置和DP转换操作，得到DP视频信号。
  10. 根据权利要求9所述LVDS视频信号转换为DP视频信号的方法，其特征在于，所述RGB视频信号包括左通道RGB视频信号和右通道RGB视频信号，步骤S2包括以下步骤：
    S21)对所述左通道RGB视频信号依次进行数据缓冲和数据倍频处理，以提高左通道数据传输速率和时钟频率；同时，对所述右通道RGB视频信号依次进行数据缓冲和数据倍频处理，以提高右通道数据传输速率和时钟频率；
    S22)对所述左通道数据和右通道数据进行同步处理，得到同步传输的左通道RGB倍频信号和右通道RGB倍频信号。
  11. 根据权利要求10所述LVDS视频信号转换为DP视频信号的方法，其特征在于，根据写入的DP寄存器命令完成所述DP转换配置命令和所述DP转换启动命令的下发，步骤S3包括以下步骤：
    接收所述左通道RGB倍频信号并根据所述DP转换配置命令和所述DP转换启动命令将所述左通道RGB倍频信号进行DP转换配置和DP转换操作，得到左通道DP视频信号；同时，
    接收所述右通道RGB倍频信号并根据所述DP转换配置命令和所述DP转换启动命 令将所述右通道RGB倍频信号进行DP转换配置和DP转换操作，得到右通道DP视频信号。
  12. 一种LVDS视频信号转换为DP视频信号的系统，其特征在于，包括设置于一颗可编程逻辑器件中的LVDS视频信号转换单元、缓存倍频单元和DP视频信号转换单元；其中，
    所述LVDS视频信号转换单元用于将LVDS视频信号转换为RGB视频信号；
    所述缓存倍频单元用于对所述RGB视频信号先后进行数据缓冲和数据倍频处理得到RGB倍频信号；
    所述DP视频信号转换单元用于根据DP转换配置命令和DP转换启动命令对所述RGB倍频信号进行DP转换配置和DP转换操作得到DP视频信号。
  13. 根据权利要求12所述LVDS视频信号转换为DP视频信号的系统，其特征在于，所述RGB视频信号包括左通道RGB视频信号和右通道RGB视频信号，所述缓存倍频单元包括：
    左通道RGB视频信号缓存倍频单元，用于对所述左通道RGB视频信号依次进行数据缓冲和数据倍频处理以提高左通道数据传输速率和时钟频率；
    右通道RGB视频信号缓存倍频单元，用于对所述右通道RGB视频信号依次进行数据缓冲和数据倍频处理以提高右通道数据传输速率和时钟频率；
    RGB视频信号同步单元，用于对所述左通道数据和右通道数据进行同步处理得到同步传输的左通道RGB倍频信号和右通道RGB倍频信号。
  14. 根据权利要求12所述LVDS视频信号转换为DP视频信号的系统，其特征在于，所述DP视频信号转换单元包括：
    DP寄存器模块，用于根据写入的DP寄存器命令完成所述DP转换配置命令和所述DP转换启动命令的下发；
    左路DP信号转换模块，用于接收所述左通道RGB倍频信号并根据所述DP转换配置命令和所述DP转换启动命令将所述左通道RGB倍频信号进行DP转换配置和DP转换操作得到左通道DP视频信号；
    右路DP信号转换模块，用于接收所述右通道RGB倍频信号并根据所述DP转换配置命令和所述DP转换启动命令将所述右通道RGB倍频信号进行DP转换配置和DP转 换操作得到右通道DP视频信号；
    DP显示模组连接件，用于同时接收左通道DP视频信号和右通道DP视频信号，并与DP显示模组连接，将左通道DP视频信号和右通道DP视频信号传送给DP显示模组。
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