WO2016201868A1 - 阵列基板及其制作方法、显示器件 - Google Patents

阵列基板及其制作方法、显示器件 Download PDF

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Publication number
WO2016201868A1
WO2016201868A1 PCT/CN2015/094249 CN2015094249W WO2016201868A1 WO 2016201868 A1 WO2016201868 A1 WO 2016201868A1 CN 2015094249 W CN2015094249 W CN 2015094249W WO 2016201868 A1 WO2016201868 A1 WO 2016201868A1
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Prior art keywords
layer
array substrate
communication line
via hole
lines
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PCT/CN2015/094249
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English (en)
French (fr)
Inventor
李全虎
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/108,186 priority Critical patent/US10121802B2/en
Publication of WO2016201868A1 publication Critical patent/WO2016201868A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • Electro-Static Discharge (ESD) phenomenon is inevitably introduced due to machine handling and process. Due to the accumulation of static electricity, the conductor portion on the array substrate will form a significant potential difference. Once an electrostatic discharge occurs, the high voltage or high current generated instantaneously may cause the performance of the semiconductor layer or the metal trace on the array substrate to be degraded or even destroyed. The performance of the array substrate is degraded or even destroyed, thereby reducing the yield of the product.
  • ESD Electro-Static Discharge
  • the protection circuit comprising a thin film transistor, using a thin film transistor to increase the output current exponentially at a large turn-on voltage, discharging an electrostatic surge current through the thin film transistor to a reference level or Large resistance to the network.
  • Relying on the protection of the protection circuit depends on the formation of the thin film transistor.
  • the formation of the thin film transistor is at least completed by the deposition of two layers of metal and the dry etching of an insulating layer. Therefore, before the fabrication of the thin film transistor is completed, The static electricity in the process has no protective ability at all. In some processes, even until the last step of the entire process, the ESD protection circuit can be completed. At this time, the protection circuit has little significance for eliminating static electricity in the process of the array substrate.
  • the present disclosure provides an array substrate, a manufacturing method thereof, and a display device for effectively performing electrostatic protection on a process of an array substrate.
  • a method for fabricating an array substrate including:
  • Forming at least one second insulating layer on the first insulating layer, and forming each of the second insulating layers comprises:
  • the manufacturing method further includes:
  • the manufacturing method as described above, optionally, before the forming the at least one second insulating layer, the manufacturing method further includes:
  • a pattern of the first conductive layer is formed, and the protective layer is formed by at least one of the first conductive layers.
  • the array substrate includes at least two types of signal lines for transmitting different signals, and the corresponding connecting lines of the at least two signal lines of the array substrate are electrically connected.
  • the method further includes: before the removing the portion of the protective layer corresponding to the region where the first via hole is located, the manufacturing method further includes:
  • the manufacturing method further includes:
  • a third insulating layer is formed at the break of the communication line.
  • the array substrate is a bottom gate type thin film transistor array substrate
  • the signal line includes a plurality of gate lines and a plurality of data lines
  • the connection lines are used for electrical connection. a first connecting line of the plurality of gate lines and a second connecting line for electrically connecting the plurality of data lines;
  • the manufacturing method specifically includes:
  • Forming a gate metal layer performing a patterning process on the gate metal layer to form a plurality of gate lines and a first connection line for electrically connecting the plurality of gate lines;
  • a source/drain metal layer on the gate insulating layer Forming a source/drain metal layer on the gate insulating layer, patterning the source/drain metal layer, forming a plurality of data lines, a second connecting line for electrically connecting the plurality of data lines, and the protecting a layer, a portion of the first communication line corresponding to the area where the first via hole is located is covered by the protection layer, and the second communication line is electrically connected to the first communication line through the third via hole;
  • the portion of the second communication line corresponding to the region where the fifth via hole is located is removed by wet etching, and the second communication line is disconnected, thereby disconnecting the electrical connection between the plurality of data lines.
  • the manufacturing method as described above, optionally, the patterning process of the source/drain metal layer is performed
  • the plurality of data lines, the second connection line for electrically connecting the plurality of data lines, and the protection layer specifically include:
  • Coating a photoresist on the source/drain metal layer exposing and developing the photoresist to form a photoresist retention region and a photoresist non-retention region, the photoresist retention region corresponding to at least the a region where the data line, the second connecting line, and the protective layer are located, where the photoresist non-reserved area corresponds to other areas;
  • the photoresist of the photoresist remaining region is peeled off to form the data line, the second connecting line, and the protective layer.
  • An array substrate is also provided in the embodiment of the present disclosure, which is produced by the manufacturing method as described above.
  • the array substrate includes a base substrate, a plurality of gate lines formed on the base substrate, and a first communication line formed on the base substrate; the first communication line and the Each of the plurality of gate lines is cross-connected; the first communication line is formed with a plurality of via holes; and the plurality of via holes are spaced apart from and alternately disposed with the plurality of gate lines.
  • first connecting line is perpendicular to the plurality of gate lines.
  • the array substrate further includes a plurality of data lines and a second communication line; the plurality of data lines are disposed to intersect with the plurality of gate lines; and the second communication line and each of the plurality of data lines One of the two is connected to each other; a plurality of via holes are formed on the second communication line; and a plurality of via holes on the second communication line are spaced apart from each other and alternately arranged.
  • the second communication line is perpendicular to the plurality of data lines.
  • the second communication line is perpendicular to the plurality of first communication lines.
  • a display device including the array substrate as described above, is also provided in an embodiment of the present disclosure.
  • connection line connecting the plurality of signal lines
  • the resistance value of the trace is increased, and the absorption capacity of the static electricity is improved, and the static electricity can be realized by only forming one layer of the connection line.
  • the protection enables electrostatic protection of the array substrate during most of the array substrate process.
  • the communication line is covered with at least two insulating layers, and the step of forming each insulating layer includes forming a via hole in the insulating layer, and corresponding positions of the via holes in the at least two insulating layers are used for disconnection
  • the connecting line avoids long-time dry etching of a plurality of insulating layers, The static electricity introduced during the formation of vias is reduced.
  • the portion of the connecting line corresponding to the area where the via hole is located is covered by the protective layer, and is used to protect the connecting line from being disconnected during the process of the array substrate, thereby functioning as an electrostatic protection.
  • the communication line is disconnected through the via holes, thereby breaking the electrical connection between the plurality of signal lines.
  • FIG. 1 is a schematic structural view showing a certain signal line of an array substrate and a connecting line thereof in the embodiment of the present disclosure
  • FIGS. 2 to 4 are schematic views 1 showing a process of fabricating an array substrate in an embodiment of the present disclosure
  • Figure 5 shows a partial cross-sectional view 1 of Figure 1 along A-A in an embodiment
  • FIG. 6 to FIG. 8 are schematic diagrams showing the manufacturing process of the array substrate in the embodiment of the present disclosure.
  • Figure 9 is a partial cross-sectional view 2 taken along line A-A of Figure 1 in another embodiment
  • FIG. 10 and FIG. 11 are schematic diagrams 3 showing a process of fabricating an array substrate in an embodiment of the present disclosure
  • FIG. 12 and FIG. 13 are schematic diagrams showing the disconnection sequence of the connection lines of the array substrate in the embodiment of the present disclosure
  • FIG. 14 and FIG. 15 are schematic diagrams showing the fabrication process of the array substrate in the embodiment of the present disclosure.
  • the present disclosure provides an array substrate and a method of fabricating the same for electrostatic protection during fabrication of an array substrate.
  • the array substrate includes a plurality of signal lines (for example, gate lines and data lines of a thin film transistor) and communication lines for transmitting the same signal.
  • the connecting line is used for electrically connecting the plurality of signal lines, reducing isolated wiring, increasing the resistance value of the wiring, and improving the absorption capacity of the electrostatic discharge, since only one layer of connecting lines is needed to implement static electricity.
  • the protection enables electrostatic protection of the array substrate during most of the array substrate process. After the fabrication of the array substrate is completed, the connection between the signal lines is disconnected to realize a normal signal transmission function.
  • the manufacturing method disconnects the signal lines by disconnecting the communication lines.
  • the communication line is covered with at least two insulating layers, and the step of forming each insulating layer includes forming via holes in the insulating layer, and the via positions in the at least two insulating layers correspond to each other After the insulating layer is fabricated, the via line is broken through the via hole, and static electricity introduced during the via formation process is greatly reduced since long-time dry etching of the plurality of insulating layers is avoided. And forming a protective layer covering a portion of the connecting line corresponding to the region where the via hole is located, for protecting the protective layer, and preventing the protective layer from being damaged in the process of the array substrate.
  • the disconnection of the connecting line is performed by a dry etching or a wet etching process.
  • the connecting line exposed through the via hole is removed by wet etching, thereby disconnecting the connecting line. .
  • the manufacturing method of the present disclosure provides a high resistance-capacitance network by making a connection line connecting the signal lines, thereby improving the absorption capacity of static electricity, and electrostatic protection can be realized by only forming one layer of communication lines, so that the process of the array substrate is large. Part of the time, the array substrate can be electrostatically protected.
  • a via hole is formed in the insulating layer, and a via hole position in all the insulating layers corresponds to disconnect the connecting line, thereby avoiding a plurality of insulating layers
  • the long-time dry etching greatly reduces the static electricity introduced during the formation of via holes.
  • the communication line is disconnected through the via holes, thereby breaking the electrical connection between the plurality of signal lines. Since the signal lines are at the same potential under the action of the connecting lines during most of the processing of the array substrate, it is difficult for the tip discharges of the different signal lines to occur, and the signal lines are shorted together to form a huge RC network, and easily absorb electrostatic discharge.
  • Etching refers to the process of selectively removing unwanted portions from a film layer by chemical or physical means.
  • the basic purpose of etching is to correctly copy the mask pattern.
  • the remaining photoresist layer or mask layer
  • the area is selectively etched away.
  • the dry etching utilizes a plasma generated in a gaseous state, and a photoresist window opened by photolithography is physically and chemically reacted with a film layer exposed to the plasma to etch away the exposed surface material on the film layer. .
  • This allows for extremely accurate feature graphics, which is an excellent dimensional control.
  • wet etching is the chemical removal of material from the surface of a film with liquid chemicals such as acids, bases, and solvents.
  • liquid chemicals such as acids, bases, and solvents.
  • wet etching has a higher selectivity ratio and higher etching efficiency.
  • wet etching is mainly used for etching thin films of metals, metal oxides, etc.
  • dry etching is mainly used for etching thin films of photoresist, silicon oxide, silicon nitride, silicon oxynitride and the like.
  • wet etching is easier to implement than dry etching, and it is easier to introduce static electricity in dry etching in a long etching process.
  • the patterning process of the film layer is: coating a photoresist on the film layer, exposing the photoresist by using a mask plate, forming a photoresist retention region and a photoresist non-reserved region after development, etching The film layer of the photoresist non-retained region is removed, and finally the photoresist of the photoresist-retained region is peeled off to complete patterning of the film layer.
  • the method for fabricating an array substrate in the embodiment of the present disclosure includes:
  • first insulating layer 101 Forming a first insulating layer 101 on the plurality of signal lines 10, and patterning the first insulating layer 101 to form a first via hole 1, as shown in FIG. 2;
  • the portion of the communication line 20 corresponding to the area where the first via hole 1 is located is covered by the protective layer 21 for protecting the connecting line 20;
  • Forming at least one second insulating layer 102 on the first insulating layer 101, the step of forming each of the second insulating layers 102 includes:
  • the manufacturing method further includes:
  • the communication line 20 is disconnected at a position corresponding to the first via hole 1, thereby disconnecting the electrical connection between the plurality of signal lines 10, as shown in FIG.
  • the signal line 10 is a gate line or a data line.
  • the protective layer 21 may be formed before the first insulating layer 101 is formed, as shown in FIG. 2; after the first insulating layer 101 is formed, the at least one second insulating layer 102 may be formed. Previously, the protective layer 21 is formed, as shown in FIG. 6, and the corresponding fabrication process is shown in FIGS. 6-8.
  • the communication line 20 corresponding to the position of the first via hole 1 is optionally removed by wet etching (hereinafter referred to as wet etching), and the communication line 20 is disconnected.
  • the above technical solution provides a high resistance-capacitance network by making a connection line connecting the signal lines, thereby improving the absorption capacity of static electricity, and electrostatic protection can be realized by only making one layer of communication lines, so that most of the process in the array substrate is performed.
  • the array substrate can be electrostatically protected during the time.
  • dry etching dry etching
  • Dry etching shown in conjunction with Figures 14 and 15 reduces the static introduced by the dry engraving process that forms the vias.
  • etching a plurality of insulating layers by a dry etching process is not easy to implement in the process, and the technical solution of the present disclosure overcomes the drawback.
  • the material of the protective layer 21 may be a conductive material, and the protective layer 21 is not damaged when the insulating layer on the protective layer 21 is dry etched to form a via.
  • the manufacturing method further includes:
  • a pattern of the first conductive layer is formed, and the protective layer 21 is formed of the first conductive layer.
  • the first conductive layer forms the protective layer 21, and the portion of the communication line 20 corresponding to the area where the first via 1 is located is covered by the protective layer 21 for protecting the connecting line 20, as shown in FIG. Show.
  • the first conductive layer 21 is formed by a newly added film layer.
  • the protective layer 21 may also be the same as the conductive pattern of the array substrate.
  • the film layer is formed.
  • the protective layer 21 is formed before the formation of the at least one second insulating layer 102.
  • the signal line 10 is a gate line
  • the first insulating layer 101 is a gate insulating layer
  • the protective layer 21 and the source electrode and the drain electrode of the thin film transistor are the same.
  • the source/drain metal film layer is formed without increasing the material and process for fabricating the protective layer 21, which simplifies the manufacturing process and reduces the production cost.
  • the material of the protective layer 21 may also be an inorganic insulating material, optionally a photoresist.
  • the specific process of forming the protective layer 21 may be: when the pattern of the connecting line 20 is formed, in the process of finally stripping the photoresist, the break corresponding to the connecting line 20 is not peeled off (the first via 1 The photoresist in the region) is formed of the remaining photoresist to form the protective layer 21. Since the photoresist can be removed by the developer only after being exposed, or peeled off by the stripping solution, the development and stripping processes are all wet etching, and therefore, the protective layer 21 formed of the photoresist is not dried by the insulating layer. The etching damage is not destroyed by the wet etching of the conductive layer, and the connection line 20 can be protected from being broken during the process of the array substrate.
  • the array substrate includes at least two signal lines for transmitting different signals, for example, the gate line 10 and the data line 30 of the thin film transistor array substrate (as shown in FIG. 12), and the connection line of the array substrate includes the first connection.
  • the line 20 and the second connecting line 40 are electrically connected by the first connecting line 20, and the data line 30 is electrically connected by the second connecting line 40, as shown in FIG.
  • the connecting lines corresponding to the at least two signal lines of the array substrate are electrically connected.
  • the first connecting line 20 and the second connecting line 40 are electrically connected to provide a larger RC network. Improve the absorption capacity of electrostatic discharge.
  • the manufacturing method further includes:
  • the electrical connection between the communication lines corresponding to the different types of signal lines is disconnected. Specifically, the electrical connection between the first communication line 20 and the second communication line 40 is disconnected, as shown in FIG.
  • the electrical connection between the connecting lines corresponding to different kinds of signal lines is first disconnected, and the same kind of signal lines are still electrically connected to absorb the electrostatic discharge.
  • the connection line is simply disconnected by wet etching, and the wet etching is not easy to introduce static electricity, which greatly reduces the electrostatic discharge phenomenon and ensures the performance of the array substrate.
  • the manufacturing method further includes:
  • a third insulating layer 103 is formed at the break of the connecting line, as shown in FIGS. 5 and 9.
  • the method for fabricating the array substrate in the embodiment of the present disclosure includes:
  • first insulating layer 101 Forming a first insulating layer 101 on the plurality of signal lines 10, and patterning the first insulating layer 101 to form a first via hole 1, as shown in FIG. 6;
  • a protective layer 21 is formed on the first insulating layer 101, and a portion of the communication line 20 corresponding to the region where the first via hole 1 is located is covered by the protective layer 21 for protecting the connecting line 20;
  • the second insulating layer 102 is patterned to form a second via 2, and the second via 2 corresponds to the position of the first via 1, as shown in FIG. 6 and FIG. 7;
  • the communication line 20 corresponding to the position of the first via hole 1 is removed by wet etching, and the communication line 20 is disconnected, thereby disconnecting the electrical connection between the plurality of signal lines 10, as shown in FIG. ;
  • a third insulating layer 103 is formed at the break of the communication line 20 as shown in FIG.
  • the conductive layer pattern of the array substrate between the two second insulating layers may be disposed to include the first pattern (eg, 22 and 23).
  • the first pattern is superposed on the protective layer 21 through the second via 2 in the second insulating layer 102 to better prevent the etching liquid in the process of fabricating the conductive layer pattern from damaging the connecting line 20.
  • the first lines and the connecting lines 20 in the region where the second via holes 2 are removed by wet etching are removed, and the connecting lines 20 can be disconnected.
  • the secondary dry etching process etches away a plurality of insulating layers, and etching a plurality of conductive layers by a wet etching process is easier to implement in the process, and long-time dry etching is more likely to introduce electrostatic discharge, wet
  • the environment in which etching is performed is not easy to introduce static electricity.
  • the fabrication process of the bottom gate thin film transistor array substrate in the embodiment of the present disclosure is as follows:
  • Step S1 providing a substrate substrate 100, such as a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate;
  • Step S2 forming a plurality of gate lines 10, a first connection line 20 for electrically connecting the plurality of gate lines 10, and a gate electrode of the thin film transistor (not shown) on the base substrate 100 completing the step S1. ;
  • a gate metal layer is formed, a photoresist is coated on the gate metal layer, and the photoresist is exposed and developed by using a mask to form a photoresist retention region and a photoresist non-reserved region.
  • the photoresist retention region corresponds to at least a plurality of gate lines 10, a first connection line 20 for electrically connecting the plurality of gate lines 10, and a region where a gate electrode of the thin film transistor is located, the photoresist non-reserved region corresponding to In other regions, the gate metal layer of the photoresist non-retained region is removed by wet etching, and finally the photoresist of the photoresist remaining region is stripped to form a plurality of gate lines 10 for electrically connecting the plurality of gate lines.
  • the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the gate metal layer may be a single layer structure or a multilayer structure,
  • the layer structure is, for example, Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, and the like.
  • Step S3 forming a gate insulating layer 101 on the base substrate 100 completing step S2, and patterning the gate insulating layer 101 to form a first via hole 1 and a third via hole 3 to expose the first via hole 1 and a first connecting line 20 in a region where the third via 3 is located, as shown in FIG. 6 and FIG. 12;
  • the gate insulating layer 101 may be SiNx, SiOx or Si(ON)x, and may have a single layer structure or a multilayer structure.
  • Step S4 forming an active layer of a thin film transistor (not shown) on the base substrate 100 completing step S3;
  • the material of the active layer may be a silicon semiconductor or a metal oxide semiconductor.
  • Step S5 forming a source/drain metal layer on the base substrate 100 completing step S4, for the source
  • the drain metal film layer is patterned to form a plurality of data lines 30, a second communication line 40 for electrically connecting the plurality of data lines 30, a protective layer 21, and source and drain electrodes of the thin film transistor, source electrode and leakage current a plurality of gate lines 10 and a plurality of data lines 30 defining a plurality of pixel regions, each of the pixel regions including the thin film transistor, the first communication line 20 corresponding to the first A portion of the region where the via 1 is located is covered by the protective layer 21, and the second via line 40 is electrically connected to the first via 20 through the third via 3 in the gate insulating layer 101;
  • the patterning process specifically includes:
  • Coating a photoresist on the source/drain metal layer exposing and developing the photoresist to form a photoresist retention region and a photoresist non-retention region, the photoresist retention region corresponding to at least the a data line 30, a second communication line 40 and a protective layer 21, and a region where the source and drain electrodes of the thin film transistor are located, and the photoresist non-reserved area corresponds to other regions;
  • the photoresist of the photoresist remaining region is peeled off to form a data line 30, a second communication line 40, and a protective layer 21, and source and drain electrodes of the thin film transistor.
  • the material of the source/drain metal layer is a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the source/drain metal layer may have a single layer structure or Multi-layer structure, multi-layer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc.
  • Step S6 forming a passivation layer 102 on the base substrate 100 completing step S5, and patterning the passivation layer 102 to form a second via hole 2, a fourth via hole (not shown), and a fifth pass.
  • the hole 4 the position of the second via hole 2 and the first via hole 1 (in combination with FIG. 6 and FIG. 7), corresponding to the disconnection position of the first communication line 20, for disconnecting between the gate lines 10 Electrical connection;
  • the fourth via is corresponding to the position of the third via 3, for disconnecting the electrical connection of the first connecting line 20 and the second connecting line 40;
  • the fifth via 4 corresponds to the first
  • the disconnected position of the two communication lines 40 is used to disconnect the electrical connection between the data lines 30, as shown in connection with FIG.
  • the first communication line 20 is disposed at one end or both ends of the gate line 10, and the first via hole 1 and the second via hole 2 are located between the adjacent gate lines 10.
  • the second communication line 40 is disposed at one or both ends of the data line 30, and the fifth via 4 is located between the adjacent data lines 30.
  • the third via hole 3 and the fourth via hole are located at one end adjacent to the first communication line 20 and the second communication line 40.
  • the passivation layer 102 may be SiNx, SiOx or Si(ON)x, and may be a single layer structure or a multilayer junction. Structure.
  • Step S7 on the base substrate 100 after the step S6 is completed, the portion of the region where the second via line 40 corresponds to the fourth via hole (corresponding to the position of the third via hole 3) is removed by wet etching, and is disconnected. Electrical connection between the first connecting line 20 and the second connecting line 40;
  • Step S8 on the base substrate 100 of the step S7, the portion of the protective layer 21 corresponding to the region where the second via 2 is located is removed by wet etching, and the first connecting line 20 corresponds to the first pass. a portion of the region where the hole 1 is located, the positions of the first via hole 1 and the second via hole 2 correspond to each other, and the first communication line 20 is disconnected, thereby breaking the electrical connection between the gate lines 20; meanwhile, the wet etching The etch is also used to remove the portion of the second communication line 40 corresponding to the area where the fifth via 4 is located, and disconnect the second communication line 40, thereby disconnecting the electrical connection between the data lines 30;
  • Step S9 forming a third insulating layer 103 on the substrate substrate 100 of the step S8 corresponding to the opening of the first connecting line 20 and the second connecting line 40;
  • the third insulating layer 103 may be SiNx, SiOx or Si(ON)x, and may have a single layer structure or a multilayer structure.
  • Step S10 forming a transparent conductive layer (the material may be indium zinc oxide or indium tin oxide) on the base substrate 100 completing step S9, and patterning the transparent conductive layer to form a pixel electrode, the pixel electrode Located in the pixel region, the sixth via (not shown) in the passivation layer 102 is electrically connected to the drain electrode of the thin film transistor.
  • a transparent conductive layer the material may be indium zinc oxide or indium tin oxide
  • the positions of the two via holes correspond to each other mean that the projections of the two via holes on the base substrate 100 at least partially overlap, for example: two The position of the via is correct.
  • the connection between the signal lines has been disconnected, and the signal test of the array substrate can be performed.
  • the measures can be taken immediately. Corrected, improved product yield.
  • An array substrate is also provided in the embodiment of the present disclosure, which is fabricated by the above method, which ensures the performance of the array substrate and improves the yield of the product.
  • a display device including the array substrate as described above, is further provided in the embodiment of the present disclosure to improve the yield and display quality of the display device.
  • the display device may be a liquid crystal display device, an organic light emitting diode display device, or other display device.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.
  • the technical solution of the present disclosure forms a communication line connecting a plurality of signal lines when the array substrate is fabricated, so as to provide a high resistance-capacitance network and improve the absorption capacity of static electricity, and electrostatic protection can be realized by only forming one layer of communication lines.
  • the array substrate can be electrostatically protected for most of the array substrate process.
  • the communication line is covered with at least two insulating layers, and the step of forming each insulating layer includes forming a via hole in the insulating layer, and corresponding positions of the via holes in the at least two insulating layers are used for disconnection
  • the connecting line avoids long-time dry etching of a plurality of insulating layers, and greatly reduces static electricity introduced during formation of via holes.
  • the portion of the connecting line corresponding to the area where the via hole is located is covered by the protective layer, and is used to protect the connecting line from being disconnected during the manufacturing process of the array substrate, thereby functioning as an electrostatic protection.
  • the communication line is disconnected through the via holes, thereby breaking the electrical connection between the plurality of signal lines.

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Abstract

本公开揭露了一种阵列基板及其制作方法、显示器件。所述阵列基板包括多条信号线及其连通所述多条信号线的连通线，以提供高的阻容网络，提高对静电的吸收能力，由于只需制作一层连通线就可以实现静电保护，在阵列基板制程的大部分时间内，都能够进行静电保护。在所述连通线上形成每个绝缘层时，在对应所述连通线的断开处形成过孔，从而避免了对多个绝缘层进行的长时间干刻，减少了形成所述过孔的干刻工艺引入的静电。并形成保护层，所述连通线对应所述过孔所在区域的部分被所述保护层覆盖，用于保护所述连通线。在完成所有绝缘层的制作后，通过所述过孔断开所述连通线，从而断开所述多条信号线之间的连接。

Description

阵列基板及其制作方法、显示器件
相关申请的交叉引用
本申请主张在2015年6月16日在中国提交的中国专利申请号No.201510334949.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板及其制作方法、显示器件。
背景技术
阵列基板的制作过程中，由于机台搬运以及制程等原因，不可避免的会引入静电放电(Electro-Static Discharge，简称ESD)现象。由于静电的累积，在阵列基板上的导体部分将形成明显的电位差异，一旦发生静电放电，瞬间产生的高电压或高电流会造成阵列基板上的半导体层或者金属走线的性能下降甚至被破坏，使得阵列基板的性能下降甚至被破坏，从而降低产品良率。
相关技术在，对阵列基板常见的静电防护方法有：
1、设计防护电路，所述防护电路包括薄膜晶体管，利用薄膜晶体管在大的开启电压下，输出电流成指数级增加的现象，将静电的冲击电流经由所述薄膜晶体管泄放到参考电平或者大的阻容网络上。
2、设计一系列尖端放电点，在尖端放电图形形成后，静电发生在尖端放电附近时，可以借由尖端放电点放电，泄放静电能量，从而保护有效走线。
以上方法的缺点有：
1、依靠防护电路保护时，依赖于薄膜晶体管的形成，一般而言，薄膜晶体管的形成至少现有完成两层金属的沉积和一道绝缘层的干刻蚀，因此，对于薄膜晶体管制作完成之前的制程中的静电，完全没有防护能力。在有些制程中，甚至直到最后整个工艺的最后一步，才能完成静电防护电路，此时的防护电路对消除阵列基板制程中的静电意义不大。
2、当设计一系列尖端放电点时，由于能量的泄放依赖金属尖端产生很大 的电场，达到击穿绝缘层的程度，静电的能力才能泄放，而静电放电的发生位置随机，能量随机，很难保证每次都能顺利产生放电。
发明内容
本公开提供一种阵列基板及其制作方法、显示器件，用以有效对阵列基板的制程中进行静电保护。
为解决上述技术问题，本公开实施例中提供一种阵列基板的制作方法，包括：
形成多条用于传输同一信号的信号线；
形成用于电性连接所述多条信号线的连通线；
在所述多条信号线上形成第一绝缘层，对所述第一绝缘层进行构图工艺，形成第一过孔；
形成保护层，所述连通线对应所述第一过孔所在区域的部分被所述保护层覆盖，用于保护所述连通线；
在所述第一绝缘层上形成至少一个第二绝缘层，形成每个所述第二绝缘层的步骤包括：
对所述第二绝缘层进行构图工艺，形成第二过孔，所述第二过孔和第一过孔的位置对应；
在完成所有第二绝缘层的制作之后，所述制作方法还包括：
去除所述保护层对应所述第一过孔所在区域的部分；
在所述第一过孔对应的位置断开所述连通线，从而断开所述多条信号线之间的电性连接。
如上所述的制作方法，可选的是，在形成所述至少一个第二绝缘层之前，所述制作方法还包括：
形成第一导电层的图案，由所述第一导电层形成所述保护层。
如上所述的制作方法，可选的是，在形成每个所述第二绝缘层之前，均形成所述第一导电层的图案，由至少一个所述第一导电层形成所述保护层。
如上所述的制作方法，可选的是，所述阵列基板包括用于传输不同信号的至少两种信号线，所述阵列基板的至少两种信号线对应的连通线电性连接。
如上所述的制作方法，可选的是，去除所述保护层对应所述第一过孔所在区域的部分之前，所述制作方法还包括：
断开不同种信号线对应的连通线之间的电性连接。
如上所述的制作方法，可选的是，在所述第一过孔对应的位置断开所述连通线之后，所述制作方法还包括：
在所述连通线的断开处形成第三绝缘层。
如上所述的制作方法，可选的是，所述阵列基板为底栅型薄膜晶体管阵列基板，所述信号线包括多条栅线和多条数据线，所述连通线包括用于电性连接所述多条栅线的第一连通线和用于电性连接所述多条数据线的第二连通线；
所述制作方法具体包括：
形成栅金属层，对所述栅金属层进行构图工艺，形成多条栅线和用于电性连接所述多条栅线的第一连通线；
在所述多条栅线上形成栅绝缘层，对所述栅绝缘层进行构图工艺，形成第一过孔和第三过孔，露出所述第一过孔和第三过孔所在区域的第一连通线；
在所述栅绝缘层上形成源漏金属层，对所述源漏金属层进行构图工艺，形成多条数据线、用于电性连接所述多条数据线的第二连通线和所述保护层，所述第一连通线对应所述第一过孔所在区域的部分被所述保护层覆盖，所述第二连通线通过所述第三过孔与所述第一连通线电性连接；
在所述源漏金属层上形成钝化层，对所述钝化层进行构图工艺，形成第二过孔、第四过孔和第五过孔，所述第二过孔和第一过孔的位置对应，所述第四过孔和第三过孔的位置对应；
采用湿法刻蚀去除所述第二连通线对应所述第四过孔所在区域的部分，从而断开所述第二连通线与所述第一连通线的电性连接；
采用湿法刻蚀去除所述保护层，以及所述第一连通线对应第一过孔所在区域的部分，断开所述第一连通线，从而断开所述多条栅线之间的电性连接；
采用湿法刻蚀去除所述第二连通线对应所述第五过孔所在区域的部分，断开所述第二连通线，从而断开所述多条数据线之间的电性连接。
如上所述的制作方法，可选的是，对所述源漏金属层进行构图工艺，形 成多条数据线、用于电性连接所述多条数据线的第二连通线和所述保护层具体包括：
在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，显影，形成光刻胶保留区域和光刻胶不保留区域，所述光刻胶保留区域至少对应所述数据线、第二连通线和保护层所在的区域，所述光刻胶不保留区域对应其他区域；
刻蚀掉光刻胶不保留区域的源漏金属层；
剥离所述光刻胶保留区域的光刻胶，形成所述数据线、第二连通线和保护层。
本公开实施例中还提供一种阵列基板，由如上所述的制作方法制得。
进一步地，所述阵列基板包括衬底基板、形成在所述衬底基板上的多条栅线，以及形成在所述衬底基板上的第一连通线；所述第一连通线与所述多条栅线的每一条均交叉连接；所述第一连通线上形成有多个过孔；所述多个过孔与所述多条栅线间隔且交替设置。
进一步地，所述第一连通线垂直于所述多条栅线。
进一步地，所述阵列基板还包括多条数据线和第二连通线；所述多条数据线与所述多条栅线交叉设置；所述第二连通线与所述多条数据线的每一条均交叉连接；所述第二连通线上形成有多个过孔；所述第二连通线上的多个过孔与所述多条数据线间隔且交替设置。
进一步地，所述第二连通线垂直于所述多条数据线。
进一步地，所述第二连通线垂直于所述多第一连通线。
本公开实施例中还提供一种显示器件，包括如上所述的阵列基板。
本公开的上述技术方案的有益效果如下：
上述技术方案中，在制作阵列基板时，形成连通多条信号线的连通线，增加了走线的阻容值，提高了对静电的吸收能力，由于只需制作一层连通线就可以实现静电保护，使得在阵列基板制程的大部分时间内，都能够对阵列基板进行静电保护。所述连通线上覆盖有至少两个绝缘层，形成每个绝缘层的步骤包括在所述绝缘层中形成过孔，且所述至少两个绝缘层中的过孔位置对应，用于断开所述连通线，避免了对多个绝缘层的长时间干法刻蚀，大大 减少了过孔形成过程中引入的静电。并形成保护层，所述连通线对应所述过孔所在区域的部分被所述保护层覆盖，用于保护所述连通线在阵列基板的制程中不会被断开，起到静电保护作用。在完成所有绝缘层的制作后，通过所述过孔断开所述连通线，从而断开所述多条信号线之间的电性连接。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1表示本公开实施例中阵列基板的某一信号线及其连通线的结构示意图；
图2-图4表示本公开实施例中阵列基板的制作过程示意图一；
图5表示一实施例中图1沿A-A的局部剖视图一；
图6-图8表示本公开实施例中阵列基板的制作过程示意图二；
图9表示另一实施例中图1沿A-A的局部剖视图二；
图10和图11表示本公开实施例中阵列基板的制作过程示意图三；
图12和图13表示本公开实施例中阵列基板的连通线的断开顺序示意图；
图14和图15表示本公开实施例中阵列基板的制作过程示意图四。
具体实施方式
本公开提供一种阵列基板及其制作方法，用于在阵列基板的制作过程中，进行静电保护。
所述阵列基板包括多条用于传输同一信号的信号线(例如：薄膜晶体管的栅线和数据线)和连通线。所述连通线用于电性连接所述多条信号线，减少孤立走线，增大走线的阻容值，提高对静电放电的吸收能力，由于只需制作一层连通线就可以实现静电保护，使得在阵列基板制程的大部分时间内，都能够对阵列基板进行静电保护。在完成阵列基板的制作后，断开信号线之间的连接，实现正常的信号传输功能。
所述制作方法通过断开所述连通线的方式来断开信号线之间的连接。所述连通线上覆盖有至少两个绝缘层，形成每个绝缘层的步骤包括在所述绝缘层中形成过孔，所述至少两个绝缘层中的所述过孔位置对应，在完成所有绝缘层的制作后，通过所述过孔来断开所述连通线，由于避免了对多个绝缘层的长时间干法刻蚀，大大减少了过孔形成过程中引入的静电。并形成保护层，覆盖所述连通线对应所述过孔所在区域的部分，用于保护所述保护层，防止所述保护层在阵列基板的制程中被破坏。
其中，所述连通线的断开采用干法刻蚀或湿法刻蚀工艺来完成，可选地，采用湿法刻蚀刻去除通过所述过孔露出的连通线，从而断开所述连通线。
本公开的制作方法通过制作连通信号线的连通线来提供高的阻容网络，提高了对静电的吸收能力，由于只需制作一层连通线就可以实现静电保护，使得在阵列基板制程的大部分时间内，都能够对阵列基板进行静电保护。在所述连通线上形成每个绝缘层时，在所述绝缘层中形成过孔，且所有绝缘层中的过孔位置对应，用于断开所述连通线，避免了对多个绝缘层的长时间干法刻蚀，大大减少了过孔形成过程中引入的静电。并形成保护层，用于保护所述连通线在阵列基板的制程中不会被破坏，起到静电保护作用。在完成所有绝缘层的制作后，通过所述过孔断开所述连通线，从而断开所述多条信号线之间的电性连接。由于在阵列基板制程的大部分时间内，信号线在连通线的作用下都处于同一电势，因此很难发生不同信号线的尖端放电，而且信号线短接在一起形成巨大的阻容网络，更容易吸收静电放电。
在对本公开实施例的技术方案进行详细说明之前，先对本公开实施例涉及到的几个工艺流程进行简单说明，以便于更好的理解本公开实施例。
在半导体制造中，需要用选定的图像、图形或物体对待处理的膜层进行遮挡，以控制刻蚀的作用区域。上述的用于遮挡的具有特定图像的物体称为掩膜版。
刻蚀，是指用化学或物理方法有选择地从膜层去除不需要的部分的过程。刻蚀的基本目的是正确的复制出掩膜图形。刻蚀过程中，保留的光刻胶层(或掩膜层)不会受到腐蚀源显著的侵蚀或刻蚀，可作为掩蔽膜，保护膜层中待保留的部分，而未被光刻胶保护的区域，则被选择性的刻蚀掉。
在半导体制造中有两种基本的刻蚀工艺：干法刻蚀和湿法刻蚀。
干法刻蚀利用气态中产生的等离子体，通过经光刻而开出的光刻胶窗口，与暴露于等离子体中的膜层行物理和化学反应，刻蚀掉膜层上暴露的表面材料。这可以获得极其精确的特征图形，也就是尺寸控制精度极佳。
湿法刻蚀就是用液体化学试剂(如酸、碱和溶剂等)以化学的方式去除膜层表面的材料。在通过湿法腐蚀获得特征图形时，也要通过经光刻开出的掩膜层窗口，腐蚀掉露出的表面材料。
相对于干法刻蚀，湿法刻蚀具有较高的选择比和较高的刻蚀效率。其中，湿法刻蚀主要用于对金属、金属氧化物等材料薄膜进行刻蚀，干法刻蚀主要用于对光刻胶、氧化硅、氮化硅、氮氧化硅等材料薄膜进行刻蚀。
湿法刻蚀比干法刻蚀在工艺上更容易实现，并且在长时间的刻蚀工艺中，干法刻蚀中更容易引人静电。
对膜层的构图工艺过程为：在所述膜层上涂覆光刻胶，利用掩膜版对光刻胶进行曝光，显影后形成光刻胶保留区域和光刻胶不保留区域，刻蚀掉光刻胶不保留区域的膜层，最后剥离所述光刻胶保留区域的光刻胶，完成对所述膜层的图形化。
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
结合图1-图4所示，本公开实施例中阵列基板的制作方法包括：
形成多条用于传输同一信号的信号线10；
形成用于电性连接所述多条信号线10的连通线20；
在所述多条信号线10上形成第一绝缘层101，对所述第一绝缘层101进行构图工艺，形成第一过孔1，如图2所示；
形成保护层21，所述连通线20对应所述第一过孔1所在区域的部分被所述保护层21覆盖，用于保护所述连通线20；
在所述第一绝缘层101上形成至少一个第二绝缘层102，形成每个所述第二绝缘层102的步骤包括：
对所述第二绝缘层102进行构图工艺，形成第二过孔2，所述第二过孔2和第一过孔1的位置对应，结合图2和图3所示；
在完成所有第二绝缘层102的制作之后，所述制作方法还包括：
去除所述保护层21对应所述第一过孔1所在区域的部分；
在所述第一过孔1对应的位置断开所述连通线20，从而断开所述多条信号线10之间的电性连接，如图4所示。
以薄膜晶体管阵列基板为例，所述信号线10为栅线或数据线。
具体可以在形成所述第一绝缘层101之前，形成所述保护层21，如图2所示；也可以在形成所述第一绝缘层101之后，在形成所述至少一个第二绝缘层102之前，形成所述保护层21，如图6所示，对应的制作过程参见图6-图8。
在实际制作工艺中，可选地采用湿法刻蚀(以下简称湿刻)去除所述第一过孔1对应位置的连通线20，断开所述连通线20。
上述技术方案，通过制作连通信号线的连通线来提供高的阻容网络，提高了对静电的吸收能力，由于只需制作一层连通线就可以实现静电保护，使得在阵列基板制程的大部分时间内，都能够对阵列基板进行静电保护。在所述连通线上形成每个绝缘层时，通过干法刻蚀(以下简称干刻)在对应所述连通线的断开处形成过孔，从而避免了对多个绝缘层进行的长时间干刻(结合图14和图15所示)，减少了形成所述过孔的干刻工艺引入的静电。而且通过一次干刻工艺刻蚀掉多个绝缘层在工艺上不易实现，本公开的技术方案克服了该缺陷。
其中，所述保护层21的材料可以为导电材料，在对保护层21上的绝缘层进行干法刻蚀形成过孔时不会破坏保护层21。则在形成所述至少一个第二绝缘层102之前，所述制作方法还包括：
形成第一导电层的图案，由所述第一导电层形成所述保护层21。
具体的，可以在形成所述第一绝缘层101之前，在所述连通线20上形成第一导电层，并对所述第一导电层进行构图工艺，形成第一导电层的图案，由所述第一导电层形成所述保护层21，所述连通线20对应所述第一过孔1所在区域的部分被所述保护层21覆盖，用于保护所述连通线20，如图2所示。所述第一导电层21通过新增的膜层来形成。
在实际应用过程中，所述保护层21也可以与阵列基板的导电图案由同一 膜层形成。则在形成所述第一绝缘层101之后，在形成所述至少一个第二绝缘层102之前，形成所述保护层21。以底栅型薄膜晶体管阵列基板为例，当所述信号线10为栅线时，所述第一绝缘层101为栅绝缘层，所述保护层21与薄膜晶体管的源电极和漏电极由同一源漏金属膜层形成，不用增加制作保护层21的材料和工艺，简化了制作工艺，降低了生产成本。
当然，所述保护层21的材料也可以为无机绝缘材料，可选地，为光刻胶。则形成保护层21的具体过程可以为：在制作所述连通线20的图案时，在最后剥离光刻胶的工艺中，不剥离对应所述连通线20的断开处(第一过孔1所在区域)的光刻胶，由所述保留的光刻胶来形成保护层21。由于光刻胶只有经过曝光后才能被显影液去除，或通过剥离液来剥离，显影和剥离工艺均为湿法刻蚀，因此，由光刻胶形成的保护层21不会被绝缘层的干法刻蚀破坏，也不会被导电层的湿法刻蚀破坏，能够在阵列基板的制程中保护连通线20不被断开。
通常地，阵列基板包括用于传输不同信号的至少两种信号线，例如：薄膜晶体管阵列基板的栅线10和数据线30(如图12所示)，则阵列基板的连通线包括第一连通线20和第二连通线40，栅线10通过第一连通线20电性连接，数据线30通过第二连通线40电性连接，如图12所示。本公开实施例中，所述阵列基板的至少两种信号线对应的连通线电性连接，具体的，第一连通线20和第二连通线40电性连接，以提供更巨大的阻容网络，提高对静电放电的吸收能力。
进一步地，在阵列基板的所有绝缘层制作完成之后，在去除所述保护层21对应所述第一过孔1所在区域的部分，以在对应所述第一过孔1的位置断开所述连通线之前，所述制作方法还包括：
断开不同种信号线对应的连通线之间的电性连接，具体的，断开第一连通线20和第二连通线40之间的电性连接，如图13所示。
即，在断开不同种信号线对应的连通线之间的电性连接后，再断开同种信号线的电性连接。
通过上述步骤，可以保证阵列基板制程的大部分时间内，所有信号线短接在一起，提供巨大的阻容网络，对静电放电具有很强的吸收能力。在完成 所有绝缘层的制作后，首先断开不同种信号线对应的连通线之间的电性连接，同种信号线仍电性连接，吸收静电放电。而在断开同种信号线的电性连接时，只需通过湿法刻蚀来断开连通线，湿法刻蚀不易引入静电，大大减少了静电放电现象，保证了阵列基板的性能。
本公开实施例中在断开同种信号线的连接之后，具体为在所述第一过孔对应的位置断开所述连通线之后，所述制作方法还包括：
在所述连通线的断开处形成第三绝缘层103，结合图5和图9所示。
以阵列基板包括一个第二绝缘层102为例，结合图1、图6-图9所示，本公开实施例中阵列基板的制作方法具体包括：
形成多条用于传输同一信号的信号线10；
形成用于电性连接所述多条信号线10的连通线20；
在所述多条信号线10上形成第一绝缘层101，对所述第一绝缘层101进行构图工艺，形成第一过孔1，如图6所示；
在第一绝缘层101上形成保护层21，所述连通线20对应所述第一过孔1所在区域的部分被所述保护层21覆盖，用于保护所述连通线20；
在所述保护层21上形成第二绝缘层102，形成所述第二绝缘层102的步骤包括：
对所述第二绝缘层102进行构图工艺，形成第二过孔2，所述第二过孔2和第一过孔1的位置对应，结合图6和图7所示；
去除所述保护层21对应所述第一过孔1所在区域的部分；
采用湿法刻蚀去除所述第一过孔1对应位置的连通线20，断开所述连通线20，从而断开所述多条信号线10之间的电性连接，如图8所示；
在所述连通线20的断开处形成第三绝缘层103，如图9所示。
当阵列基板包括至少两个第二绝缘层102时，结合图10和图11，可以设置阵列基板的位于两个第二绝缘层之间的导电层图案包括第一图案(如：22和23)，所述第一图案通过第二绝缘层102中的第二过孔2叠加在保护层21上，以更好得防止制作所述导电层图案的工艺中的刻蚀液破坏连通线20。在所有第二绝缘层102制作完成后，只需采用湿法刻蚀去除第二过孔2所在区域的所述第一图案和连通线20，就可以断开所述连通线20。相对于通过一 次干法刻蚀工艺刻蚀掉多个绝缘层，通过一次湿法刻蚀工艺刻蚀掉多个导电层在工艺上更容易实现，并且长时间的干法刻蚀更容易引入静电放电，湿法刻蚀的环境不易引入静电。
下面以底栅型薄膜晶体管阵列基板为例，来介绍本公开的具体技术方案。
结合1、图6-图9，以及图12和图13所示，本公开实施例中底栅型薄膜晶体管阵列基板的制作过程为：
步骤S1、提供一衬底基板100，如：玻璃基板、石英基板、有机树脂基板等透明基板；
步骤S2、在完成步骤S1的衬底基板100上形成多条栅线10、用于电性连接多条栅线10的第一连通线20，以及薄膜晶体管的栅电极(图中未示出)；
具体的，形成栅金属层，在所述栅金属层涂覆光刻胶，采用掩膜版对所述光刻胶进行曝光，显影，形成光刻胶保留区域和光刻胶不保留区域，所述光刻胶保留区域至少对应多条栅线10、用于电性连接多条栅线10的第一连通线20，以及薄膜晶体管的栅电极所在的区域，所述光刻胶不保留区域对应其他区域，通过湿法刻蚀去除光刻胶不保留区域的栅金属层，最后剥离所述光刻胶保留区域的光刻胶，形成多条栅线10、用于电性连接多条栅线10的第一连通线20，以及薄膜晶体管的栅电极。
其中，栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
步骤S3、在完成步骤S2的衬底基板100上形成栅绝缘层101，对栅绝缘层101进行构图工艺，形成第一过孔1和第三过孔3，露出所述第一过孔1和第三过孔3所在区域的第一连通线20，结合图6和图12所示；
栅绝缘层101可以是SiNx，SiOx或Si(ON)x，可以为单层结构或者多层结构。
步骤S4、在完成步骤S3的衬底基板100上形成薄膜晶体管的有源层(图中未示出)；
所述有源层的材料可以为硅半导体，也可以为金属氧化物半导体。
步骤S5、在完成步骤S4的衬底基板100上形成源漏金属层，对所述源 漏金属膜层进行构图工艺，形成多条数据线30、用于电性连接多条数据线30的第二连通线40、保护层21，以及薄膜晶体管的源电极和漏电极，源电极和漏电极搭接在所述有源层上，多条栅线10和多条数据线30限定多个像素区域，每个像素区域包括所述薄膜晶体管，所述第一连通线20对应所述第一过孔1所在区域的部分被所述保护层21覆盖，第二连通线40通过栅绝缘层101中的第三过孔3与第一连通线20电性连接；
所述构图工艺具体包括：
在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，显影，形成光刻胶保留区域和光刻胶不保留区域，所述光刻胶保留区域至少对应所述数据线30、第二连通线40和保护层21，以及薄膜晶体管的源电极和漏电极所在的区域，所述光刻胶不保留区域对应其他区域；
刻蚀掉光刻胶不保留区域的源漏金属层；
剥离所述光刻胶保留区域的光刻胶，形成数据线30、第二连通线40和保护层21，以及薄膜晶体管的源电极和漏电极。
所述源漏金属层的材料为Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，所述源漏金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
步骤S6、在完成步骤S5的衬底基板100上形成钝化层102，对钝化层102进行构图工艺，形成第二过孔2、第四过孔(图中未示出)和第五过孔4，所述第二过孔2和第一过孔1的位置对应(结合图6和图7所示)，对应第一连通线20的断开位置，用于断开栅线10之间的电性连接；所述第四过孔和第三过孔3的位置对应，用于断开第一连通线20和第二连通线40的电性连接；所述第五过孔4对应第二连通线40的断开位置，用于断开数据线30之间的电性连接，结合7和图12所示。
具体的，第一连通线20设置在栅线10的一端或两端，第一过孔1和第二过孔2位于相邻栅线10之间。第二连通线40设置在数据线30的一端或两端，第五过孔4位于相邻数据线30之间。第三过孔3和第四过孔位于第一连通线20和第二连通线40相邻的一端。
钝化层102可以是SiNx，SiOx或Si(ON)x，可以为单层结构或者多层结 构。
步骤S7、在完成步骤S6的衬底基板100上，采用湿法刻蚀去除第二连通线40对应所述第四过孔(与第三过孔3的位置对应)所在区域的部分，断开第一连通线20和第二连通线40的电性连接；
步骤S8、在完成步骤S7的衬底基板100上，采用湿法刻蚀去除所述保护层21对应所述第二过孔2所在区域的部分，以及所述第一连通线20对应第一过孔1所在区域的部分，第一过孔1和第二过孔2的位置对应，断开第一连通线20，从而断开栅线20之间的电性连接；同时，所述湿法刻蚀还用于去除所述第二连通线40对应所述第五过孔4所在区域的部分，断开第二连通线40，从而断开数据线30之间的电性连接；
步骤S9、在完成步骤S8的衬底基板100上对应第一连通线20和第二连通线40的断开处形成第三绝缘层103；
第三绝缘层103可以是SiNx，SiOx或Si(ON)x，可以为单层结构或者多层结构。
步骤S10、在完成步骤S9的衬底基板100上形成透明导电层(材料可以为铟锌氧化物或铟锡氧化物)，对所述透明导电层进行构图工艺，形成像素电极，所述像素电极位于像素区域，通过钝化层102中的第六过孔(图中未示出)与薄膜晶体管的漏电极电性连接。
至此完成底栅型薄膜晶体管阵列基板的制作。
其中，两个过孔的位置对应(例如：第一过孔和第二过孔的位置对应)是指：所述两个过孔在衬底基板100上的投影至少部分重叠，例如：两个过孔的位置正对。
本公开实施例中在完成阵列基板的制作工艺后，已经断开信号线之间的连接，可以对阵列基板进行信号测试，当发现有信号线短路或断路等异常情况时，能够立即采取措施进行修正，提高了产品的良率。
本公开实施例中还提供一种阵列基板，由上述方法制作而成，保证了阵列基板的性能，提高了产品的良率。
本公开实施例中还提供一种显示器件，包括如上所述的阵列基板，用以提高显示器件的良率和显示品质。
所述显示器件可以为液晶显示器件，也可以为有机发光二极管显示器件，或其他显示器件。具体的，所述显示器件可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的技术方案在制作阵列基板时，形成连通多条信号线的连通线，以提供高的阻容网络，提高对静电的吸收能力，由于只需制作一层连通线就可以实现静电保护，使得在阵列基板制程的大部分时间内，都能够对阵列基板进行静电保护。所述连通线上覆盖有至少两个绝缘层，形成每个绝缘层的步骤包括在所述绝缘层中形成过孔，且所述至少两个绝缘层中的过孔位置对应，用于断开所述连通线，避免了对多个绝缘层的长时间干法刻蚀，大大减少了过孔形成过程中引入的静电。并形成保护层所述连通线对应所述过孔所在区域的部分被所述保护层覆盖，用于保护所述连通线在阵列基板的制程中不会被断开，起到静电保护作用。在完成所有绝缘层的制作后，通过所述过孔断开所述连通线，从而断开所述多条信号线之间的电性连接。
以上所述仅是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开的保护范围。

Claims (15)

  1. 一种阵列基板的制作方法，包括：
    形成多条用于传输同一信号的信号线；
    形成用于电性连接所述多条信号线的连通线；
    在所述多条信号线上形成第一绝缘层，对所述第一绝缘层进行构图工艺，形成第一过孔；
    形成保护层，所述连通线对应所述第一过孔所在区域的部分被所述保护层覆盖，用于保护所述连通线；
    在所述第一绝缘层上形成至少一个第二绝缘层，形成每个所述第二绝缘层的步骤包括：
    对所述第二绝缘层进行构图工艺，形成第二过孔，所述第二过孔和第一过孔的位置对应；
    在完成所有第二绝缘层的制作之后，所述制作方法还包括：
    去除所述保护层对应所述第一过孔所在区域的部分；
    在所述第一过孔对应的位置断开所述连通线，从而断开所述多条信号线之间的电性连接。
  2. 根据权利要求1所述的制作方法，其中，在形成所述至少一个第二绝缘层之前，所述制作方法还包括：
    形成第一导电层的图案，由所述第一导电层形成所述保护层。
  3. 根据权利要求2所述的制作方法，其中，在形成每个所述第二绝缘层之前，均形成所述第一导电层的图案，由至少一个所述第一导电层形成所述保护层。
  4. 根据权利要求1所述的制作方法，其中，所述阵列基板包括用于传输不同信号的至少两种信号线，所述阵列基板的至少两种信号线对应的连通线电性连接。
  5. 根据权利要求4所述的制作方法，其中，去除所述保护层对应所述第一过孔所在区域的部分之前，所述制作方法还包括：
    断开不同种信号线对应的连通线之间的电性连接。
  6. 根据权利要求2-5任一项所述的制作方法，其中，在所述第一过孔对应的位置断开所述连通线之后，所述制作方法还包括：
    在所述连通线的断开处形成第三绝缘层。
  7. 根据权利要求2-5任一项所述的制作方法，其中，所述阵列基板为底栅型薄膜晶体管阵列基板，所述信号线包括多条栅线和多条数据线，所述连通线包括用于电性连接所述多条栅线的第一连通线和用于电性连接所述多条数据线的第二连通线；
    所述制作方法具体包括：
    形成栅金属层，对所述栅金属层进行构图工艺，形成多条栅线和用于电性连接所述多条栅线的第一连通线；
    在所述多条栅线上形成栅绝缘层，对所述栅绝缘层进行构图工艺，形成第一过孔和第三过孔，露出所述第一过孔和第三过孔所在区域的第一连通线；
    在所述栅绝缘层上形成源漏金属层，对所述源漏金属层进行构图工艺，形成多条数据线、用于电性连接所述多条数据线的第二连通线和所述保护层，所述第一连通线对应所述第一过孔所在区域的部分被所述保护层覆盖，所述第二连通线通过所述第三过孔与所述第一连通线电性连接；
    在所述源漏金属层上形成钝化层，对所述钝化层进行构图工艺，形成第二过孔、第四过孔和第五过孔，所述第二过孔和第一过孔的位置对应，所述第四过孔和第三过孔的位置对应；
    采用湿法刻蚀去除所述第二连通线对应所述第四过孔所在区域的部分，从而断开所述第二连通线与所述第一连通线的电性连接；
    采用湿法刻蚀去除所述保护层，以及所述第一连通线对应第一过孔所在区域的部分，断开所述第一连通线，从而断开所述多条栅线之间的电性连接；
    采用湿法刻蚀去除所述第二连通线对应所述第五过孔所在区域的部分，断开所述第二连通线，从而断开所述多条数据线之间的电性连接。
  8. 根据权利要求7所述的制作方法，其中，对所述源漏金属层进行构图工艺，形成多条数据线、用于电性连接所述多条数据线的第二连通线和所述保护层具体包括：
    在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，显影，形成 光刻胶保留区域和光刻胶不保留区域，所述光刻胶保留区域至少对应所述数据线、第二连通线和保护层所在的区域，所述光刻胶不保留区域对应其他区域；
    刻蚀掉光刻胶不保留区域的源漏金属层；
    剥离所述光刻胶保留区域的光刻胶，形成所述数据线、第二连通线和保护层。
  9. 一种阵列基板，由权利要求1-8任一项所述的制作方法制得。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板包括衬底基板、形成在所述衬底基板上的多条栅线，以及形成在所述衬底基板上的第一连通线；所述第一连通线与所述多条栅线的每一条均交叉连接；所述第一连通线上形成有多个过孔；所述多个过孔与所述多条栅线间隔且交替设置。
  11. 根据权利要求10所述的阵列基板，其中，所述第一连通线垂直于所述多条栅线。
  12. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括多条数据线和第二连通线；所述多条数据线与所述多条栅线交叉设置；所述第二连通线与所述多条数据线的每一条均交叉连接；所述第二连通线上形成有多个过孔；所述第二连通线上的多个过孔与所述多条数据线间隔且交替设置。
  13. 根据权利要求12所述的阵列基板，其中，所述第二连通线垂直于所述多条数据线。
  14. 根据权利要求12所述的阵列基板，其中，所述第二连通线垂直于所述多第一连通线。
  15. 一种显示器件，包括权利要求9至14中任一项所述的阵列基板。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104716146B (zh) * 2015-03-30 2018-06-15 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN104900589B (zh) * 2015-06-16 2017-11-10 京东方科技集团股份有限公司 阵列基板及其制作方法、显示器件
CN105742238A (zh) * 2016-03-02 2016-07-06 京东方科技集团股份有限公司 孔结构和阵列基板及其制作方法、探测装置和显示装置
CN106653746B (zh) * 2016-12-15 2019-09-06 武汉华星光电技术有限公司 一种阵列基板和显示装置
CN107611163B (zh) * 2017-09-21 2020-07-21 京东方科技集团股份有限公司 一种oled显示基板及其制作方法和显示装置
CN107490890B (zh) * 2017-09-26 2019-09-20 武汉华星光电技术有限公司 显示基板、显示面板以及显示设备
CN109407883B (zh) * 2018-09-27 2022-04-26 合肥鑫晟光电科技有限公司 一种触摸屏及其制作方法、显示装置
CN109285460B (zh) 2018-11-29 2021-02-09 上海天马微电子有限公司 阵列基板、显示面板和显示装置
KR20210094194A (ko) * 2020-01-20 2021-07-29 삼성디스플레이 주식회사 전자패널 및 이를 포함한 표시장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010028415A1 (en) * 2000-03-13 2001-10-11 Seiko Epson Corporation Semiconductor device, electro-optical device substrate, liquid crystal device substrate and manufacturing method therefor, liquid crystal device, and projection liquid crystal display device and electronic apparatus using the liquid crystal device
CN102540524A (zh) * 2010-12-30 2012-07-04 北京京东方光电科技有限公司 防止静电击穿的方法、阵列基板的制造方法和显示背板
CN103809318A (zh) * 2014-02-14 2014-05-21 京东方科技集团股份有限公司 一种阵列基板制造方法、阵列基板及显示设备
CN104900589A (zh) * 2015-06-16 2015-09-09 京东方科技集团股份有限公司 阵列基板及其制作方法、显示器件

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100527082B1 (ko) * 1999-12-22 2005-11-09 비오이 하이디스 테크놀로지 주식회사 박막 트랜지스터 액정표시장치의 제조방법
KR100839754B1 (ko) * 2007-08-14 2008-06-19 삼성에스디아이 주식회사 유기 전계 발광 표시 장치 및 이의 제조 방법
CN102289115B (zh) * 2010-06-21 2014-08-20 北京京东方光电科技有限公司 母板及tft阵列基板的制造方法
DE102011006150B4 (de) * 2011-03-25 2013-10-24 Siemens Aktiengesellschaft Magnetresonanzsystem und Verfahren zur Durchführung von Magnetresonanzmessungen in einem intra-oralen Bereich
CN202421683U (zh) * 2012-01-06 2012-09-05 京东方科技集团股份有限公司 一种tft阵列基板的中间产品、阵列基板及显示器件
US9000797B2 (en) * 2012-09-12 2015-04-07 Shenzhen China Star Optoelectronics Technology Co., Ltd. TFT-LCD array substrate having a connecting device for testing twice and test method for the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010028415A1 (en) * 2000-03-13 2001-10-11 Seiko Epson Corporation Semiconductor device, electro-optical device substrate, liquid crystal device substrate and manufacturing method therefor, liquid crystal device, and projection liquid crystal display device and electronic apparatus using the liquid crystal device
CN102540524A (zh) * 2010-12-30 2012-07-04 北京京东方光电科技有限公司 防止静电击穿的方法、阵列基板的制造方法和显示背板
CN103809318A (zh) * 2014-02-14 2014-05-21 京东方科技集团股份有限公司 一种阵列基板制造方法、阵列基板及显示设备
CN104900589A (zh) * 2015-06-16 2015-09-09 京东方科技集团股份有限公司 阵列基板及其制作方法、显示器件

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