WO2016197976A1 - Circuit de topologie d'onduleur multiniveau - Google Patents

Circuit de topologie d'onduleur multiniveau Download PDF

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Publication number
WO2016197976A1
WO2016197976A1 PCT/CN2016/085453 CN2016085453W WO2016197976A1 WO 2016197976 A1 WO2016197976 A1 WO 2016197976A1 CN 2016085453 W CN2016085453 W CN 2016085453W WO 2016197976 A1 WO2016197976 A1 WO 2016197976A1
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Prior art keywords
bidirectional switch
inverter
unit
charge
input
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PCT/CN2016/085453
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English (en)
Chinese (zh)
Inventor
汪洪亮
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汪洪亮
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Application filed by 汪洪亮 filed Critical 汪洪亮
Priority to CN201680031414.8A priority Critical patent/CN107925361B/zh
Publication of WO2016197976A1 publication Critical patent/WO2016197976A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels

Definitions

  • the present application relates to multilevel inverter topology circuits, and more particularly to single phase, three phase three level and five level inverter topology circuits.
  • Photovoltaic power generation has a good development prospect because of its abundant resources and wide distribution. For photovoltaic power generation systems, how to reduce costs and improve efficiency has become an important issue for photovoltaic power generation.
  • photovoltaic arrays are used to convert solar energy into electrical energy.
  • the PV array outputs DC power, but the grid is AC. Therefore, the grid-connected photovoltaic system requires at least one inverter to convert the direct current output from the photovoltaic array into alternating current.
  • the photovoltaic array has a Potential Induced Degradation (PID).
  • PID Potential Induced Degradation
  • Potential induced attenuation occurs when the potential and leakage current of the photovoltaic array cause ions to flow between the semiconductor material of the photovoltaic array and other materials.
  • the PID effect reduces the output performance of the photovoltaic array. Therefore, the PID effect is an undesirable feature of photovoltaic arrays.
  • the PID effect can cause up to 40% power loss.
  • the PID effect often occurs when the PV array is negative to ground potential. Maintaining the positive voltage of the PV array to ground is an effective way to suppress the PID effect.
  • the present application provides a multilevel inverter topology circuit including single-phase three-level and five-level inverter topology circuits and three-phase three-level and five-level inverter topologies. Circuitry to effectively suppress the PID effect.
  • the present invention provides a single-phase three-level inverter topology circuit, including: a floating capacitor, a charge and discharge module, and an inverter module;
  • the charge and discharge module includes at least a first inductor and a charge and discharge control unit;
  • the charge and discharge control unit includes a first end, a second end, a third end, and at least one charge and discharge control end; a connection suitable for the connection from the third end to the first end of the single-conductor charge and discharge control unit; and the charge and discharge control When the terminal is the first charge and discharge control signal, the connection between the first end and the second end of the charge and discharge control unit is turned on, and when the charge and discharge control terminal is connected to the second charge and discharge control signal, the charge and discharge control unit is turned off. a connection between one end and the second end;
  • the inverter module includes a first end, a second end, a third end, a fourth end, an AC output end, and a plurality of inverter control ends; and is adapted to be applicable to the first end, the second end, and the third end of the inverter module, Five terminals of the AC output end and the fourth end, when the inverter control terminal is connected to the first inverter control signal, only the connection between the second end and the third end of the inverter module and the AC output end and the fourth end are turned on The connection between the terminals; when the second inverter control signal is connected to the inverter control terminal, only the connection between the second end and the third end of the inverter module and the connection between the third end and the AC output end are turned on. When the third inverter control signal is connected to the inverter control end, only the connection between the first end and the second end of the inverter module and the connection between the third end and the AC output end are turned on;
  • the first inductor is connected between the second end of the charging and discharging control unit and the first end of the inverter module; one end of the floating capacitor is connected to the first end of the inverter module, and the other end of the floating capacitor is connected. a third end of the inverter module;
  • the third end of the charging and discharging control unit is connected to the second end or the third end of the inverter module
  • the fourth end of the inverter module is connected to the first end of the charging and discharging control unit or The fourth end of the inverter module is connected to the first end of the inverter module.
  • the present invention provides a single-phase five-level inverter topology circuit, including:
  • the charge and discharge module includes at least a first inductor and a charge and discharge control unit;
  • the charge and discharge control unit includes a first end, a second end, a third end, and at least one charge and discharge control end; a connection suitable for the connection from the third end to the first end of the single-conductor charge and discharge control unit; and the charge and discharge control
  • the terminal is the first charging and discharging control signal
  • the connection between the first end and the second end of the charging and discharging control unit is turned on, and when the second charging and discharging control signal is connected to the control end thereof, the charging and discharging control unit is turned off first a connection between the end and the second end;
  • the five-level inverter module includes a first inverter unit and a second inverter unit; the first inverter unit includes a first end, a second end, a third end, and a plurality of inverter control ends;
  • the different control signals provided by the inverter control terminal provide at least two working modes: for the first terminal, the second terminal, and the third terminal of the first inverter unit, only the first end of the first inverter unit is turned on a connection between the two ends; for the first terminal, the second end, and the third end of the first inverter unit, only the connection between the second end and the third end of the first inverter unit is turned on;
  • the second inverter unit includes a first input end, a second input end, a third input end, an AC output end, and a plurality of inverter control ends; and is adapted to provide at least three types of work according to different control signals provided by the inverter control end Mode: for the first input end, the second input end, the third input end, and the AC output end of the second inverter unit, only the connection between the first input end and the AC output end of the second inverter unit is turned on For the first input end, the second input end, the third input end, and the AC output end of the second inverter unit, only the connection between the second input end of the second inverter unit and the AC output end is turned on; For the first input end, the second input end, the third input end, and the AC output end of the second inverter unit, Only connecting the connection between the third input end of the second inverter unit and the AC output terminal;
  • the first inductor is connected between the second end of the charging and discharging control unit and the first end of the first inverter unit; one end of the first floating capacitor is connected to the first end of the first inverter unit, The other end of the first floating capacitor is connected to the second input end of the second inverter unit; one end of the second floating capacitor is connected to the third end of the first inverter unit and the third input end of the second inverter unit The other end of the second floating capacitor is connected to the second input end of the second inverter unit;
  • the third end of the charging/discharging control unit is connected to the second end or the third end of the first inverter unit;
  • the first input end of the second inverter unit is connected to the first end of the charge and discharge control unit or the first input end of the second inverter unit is connected to the first end of the first inverter unit.
  • the present invention provides a three-phase three-level inverter topology circuit, including: a charging and discharging module, a floating capacitor, and a three-phase inverter module;
  • the charge and discharge module includes at least a first inductor and a charge and discharge control unit;
  • the charge and discharge control unit includes a first end, a second end, a third end, and at least one charge and discharge control end; a connection suitable for the one-way connection from the third end to the first end; and the first at the charge and discharge control end
  • the charge and discharge control signal is turned on, the connection between the first end and the second end is turned on, and when the second charge and discharge control signal is connected to the charge and discharge control end, the connection between the first end and the second end is turned off;
  • the three-phase inverter module includes a first inverter unit and three second inverter units; the first inverter unit includes a first end, a second end, a third end, and a plurality of inverter control ends; Providing at least two working modes according to different control signals provided by the inverter control terminal: for the first terminal, the second terminal, and the third terminal of the first inverter unit, only the first end of the first inverter unit is turned on a connection with the second end; for the first terminal, the second end, and the third end of the first inverter unit, only the connection between the second end and the third end is turned on Connect
  • Each of the second inverter units includes a first input end, a second input end, a third input end, an AC output end, and a plurality of inverter control ends; and is adapted to provide at least three types of work according to different control signals provided by the inverter control end Mode: for the first input end, the second input end, the third input end, and the AC output end, only the connection between the first input end and the AC output end is turned on; for the first input end, the second input Four terminals of the end, the third input end and the AC output end, only the connection between the second input end and the AC output end is turned on; for the first input end, the second input end, the third input end, and the AC output end four Terminals, only connecting the connection between the third input end and the AC output end;
  • the first inductor is connected between the second end of the charge and discharge control unit and the first end of the first inverter unit; one end of the floating capacitor is connected to the first end of the first inverter unit, The other end of the floating capacitor is connected to the third end of the first inverter unit;
  • the third end of the charging/discharging control unit is connected to the second end or the third end of the first inverter unit;
  • each of the second inverter units is connected to a first end of the charge and discharge control unit or a first end connected to the first inverter unit; and a second input end is connected to a second end of the first inverter unit The third input is connected to the third end of the first inverter unit.
  • the present invention provides a three-phase three-level inverter topology circuit, comprising: three single-phase three-level inverter topology circuits according to the first aspect; three said single-phase three-electric The first end of the charging and discharging module in the flat inverter topology circuit is connected; the third ends of the charging and discharging modules in the three single-phase three-level inverter topological circuits are connected.
  • the present invention provides a three-phase five-level inverter topology circuit, including:
  • the single-phase five-level inverter topology circuit according to the third aspect; the first ends of the charging and discharging modules in the three single-phase five-level inverter topology circuits are connected; three of the single phases The third end of the charge and discharge module in the three-level inverter topology circuit is connected.
  • the normal operation can still be performed. This enables the DC power supply to always maintain a ground potential greater than or equal to zero, thus effectively suppressing the PID effect; and completely eliminating the high frequency leakage current of the inverter topology.
  • FIG. 1 is a schematic circuit diagram of a first single-phase three-level inverter topology according to an embodiment of the present invention
  • FIG. 2 is a schematic circuit diagram of a second single-phase three-level inverter topology according to an embodiment of the present invention
  • FIG. 3 is a schematic circuit diagram of a third single-phase three-level inverter topology according to an embodiment of the present invention.
  • FIG. 4 is a schematic circuit diagram of a fourth single-phase three-level inverter topology according to an embodiment of the present invention.
  • FIG. 5 is a partial block diagram of a first single-phase five-level inverter topology according to an embodiment of the present invention
  • FIG. 6 is a partial block diagram of a second single-phase five-level inverter topology according to an embodiment of the present invention.
  • FIG. 7 is a partial block diagram of a third single-phase five-level inverter topology according to an embodiment of the present invention.
  • FIG. 8 is a partial block diagram of a fourth single-phase five-level inverter topology according to an embodiment of the present invention.
  • FIG. 9 is a circuit diagram of a first type of second inverter unit M2 according to an embodiment of the present invention. schematic diagram
  • FIG. 10 is a schematic diagram of a circuit principle of a second second inverting unit M2 according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a circuit principle of a third second inverting unit M2 according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a circuit principle of a fourth second inverting unit M2 according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a circuit principle of a fifth second inverting unit M2 according to an embodiment of the present disclosure
  • FIG. 14 is a schematic circuit diagram of a first single-phase five-level inverter with a second inverting unit M2 shown in FIG. 9 according to an embodiment of the present invention
  • 15 is a partial block diagram of a first three-phase three-level inverter topology according to an embodiment of the present invention.
  • 16 is a partial block diagram of a second three-phase three-level inverter topology according to an embodiment of the present invention.
  • 17 is a partial block diagram of a third three-phase three-level inverter topology according to an embodiment of the present invention.
  • FIG. 18 is a partial block diagram of a fourth three-phase three-level inverter topology according to an embodiment of the present invention.
  • 19(a) is an equivalent block diagram of a first single-phase three-level inverter topology according to an embodiment of the present invention
  • 19(b) is a partial block diagram showing a fifth three-phase three-level inverter topology according to an embodiment of the present invention.
  • 20(a) is an equivalent block diagram of a third single-phase five-level inverter topology according to an embodiment of the present invention.
  • 20(b) is a partial block diagram showing a three-phase five-level inverter topology according to an embodiment of the present invention
  • the present invention provides a multilevel inverter topology circuit comprising single phase three level and five level inverter topology circuits and three phase three level and five level inverter topology circuits.
  • PV photovoltaic array
  • U PV denotes an output voltage of a direct current power source
  • M1 denotes a charge and discharge module
  • M2 denotes a second inverter unit
  • C s Indicates the floating capacitor
  • C s1 represents the first floating capacitor
  • C s2 represents the second floating capacitor
  • G represents the AC grid.
  • the PV can be replaced by other DC power sources, that is, the DC power source in the present invention is not limited to PV.
  • the AC grid G can be replaced with other AC loads, that is, the AC load in the present invention is not limited to the AC grid.
  • the diode is used to represent a unidirectional conduction element, but the unidirectional conduction element in the present invention is not limited to the diode, and other unidirectional conduction elements may be employed.
  • the anode of the diode refers to the anode and the cathode refers to the cathode.
  • the switching MOSFET is used to represent a controllable (on and off) semiconductor switch in the present invention, but the controllable semiconductor switch in the present invention is not limited to the MOSFET, that is, other controllable semiconductor switches can also be used. Such as IGBT.
  • An N-channel MOSFET will be described as an example. The first end of the N-channel MOSFET is the drain, the second end is the source, and the control is the gate. A drive control signal is applied to each semiconductor switch control terminal in the multilevel inverter topology circuit of the present invention. For the sake of brevity, we will not repeat them later.
  • each half of the present invention The conductor switch is connected in parallel with a diode.
  • the term "bidirectional switch" as used in the present invention refers to a semiconductor switch with an anti-parallel diode, such as an IGBT with an anti-parallel diode, or a MOSFET with a parallel diode.
  • the multilevel inverter topology circuit provided by the invention mainly comprises a charging and discharging module, at least one floating capacitor and one inverter circuit.
  • a DC power source (a photovoltaic array in this embodiment) is required to maintain a ground potential greater than or equal to zero.
  • the negative pole of the inverter DC power supply is connected to the ground of the AC grid.
  • the negative pole of the DC power supply can be connected to the ground of the AC power grid.
  • the negative pole of the DC power supply can also be connected to the ground of the AC power grid.
  • the charging and discharging module is used for charging the floating capacitor, so that the floating capacitor can provide the DC negative voltage required for the inverter circuit for a certain period of time.
  • the DC forward voltage required for the inverter circuit can be obtained from the positive pole of the DC power supply or from the positive pole of the floating capacitor.
  • the positive input of the inverter circuit has two connection modes.
  • the charge and discharge module has two freewheeling circuits. Therefore, the charge and discharge module has two connection modes (that is, the diode D f in the present invention has two connection modes).
  • an output three-level inverter circuit (referred to as a three-level inverter circuit) or an output five-level inverter circuit (referred to as a five-level inverter circuit) may be employed.
  • an embodiment of the present invention provides an inverter circuit.
  • the embodiment of the present invention provides five inverses Variable circuit.
  • FIG. 1 is a schematic diagram showing the circuit principle of a first single-phase three-level inverter topology provided by an embodiment of the present application.
  • the inverter topology circuit includes: a floating capacitor C s , a charging and discharging module M1 , and an inverter module, and the inverter module is specifically a full bridge inverter circuit.
  • the charge and discharge module M1 includes a first bidirectional switch T 11 , a first inductor L 11 , and a first diode D f .
  • the first inductor L 11 and the first diode D f are for suppressing an inrush current when charging the floating capacitor C s .
  • the full bridge inverter circuit includes a second bidirectional switch T 12 , a third bidirectional switch T 13 , a fourth bidirectional switch T 14 , and a fifth bidirectional switch T 15 .
  • the capacitor C in parallel is connected across the DC power supply PV, and the capacitor C in acts as a voltage regulator.
  • PV positive DC power source is connected to a first end of the first bidirectional switch T 11, T a second end of the first bidirectional switch 11 is connected to a first end of a first inductor L 11, a first end of the inductor L 11 is connected to a second capacitor suspension The positive pole of C s .
  • the negative pole of the first diode D f is connected to the common end of the first bidirectional switch T 11 and the first inductor L 11 (the common end here refers to the end where the first bidirectional switch T 11 and the first inductor L 11 are connected, specifically Referring to the second end of the first bidirectional switch T 11 and the first end of the first inductor L 11 ), the anode of the first diode D f is connected to the cathode of the DC power source PV.
  • the first end of the second bidirectional switch T 12 is connected to the positive terminal of the floating capacitor C s
  • the second end of the second bidirectional switch T 12 is connected to the first end of the third bidirectional switch T 13 .
  • the common ends of the second bidirectional switch T 12 and the third bidirectional switch T 13 are simultaneously connected to the negative pole of the direct current power source PV and the first end of the alternating current grid.
  • the second end of the third bidirectional switch T 13 is connected to the negative terminal of the floating capacitor C s .
  • the first end of the fourth bidirectional switch T 14 is connected to the positive pole of the floating capacitor C s
  • the second end of the fourth bidirectional switch T 14 is connected to the first end of the fifth bidirectional switch T 15
  • the second end of the fifth bidirectional switch T 15 is connected to the negative terminal of the floating capacitor C s
  • the common ends of the fourth bidirectional switch T 14 and the fifth bidirectional switch T 15 are connected to the second end of the AC grid through the second inductor L 12 . Therefore, the common ends defining the fourth bidirectional switch T 14 and the fifth bidirectional switch T 15 are the alternating current terminals.
  • the second inductor L 12 is used to filter out ripple in the output current to improve the quality of the output current.
  • the floating capacitor C s is charged by the DC power source PV, so it is assumed that the floating capacitor C s voltage is equal to the DC power supply voltage U PV .
  • the current defining the second inductance L 12 in the drawing is a forward current from left to right and a negative current from the opposite.
  • the first mode the forward current path is: N ⁇ T 13 ⁇ C s ⁇ T 14 ⁇ L 12 ⁇ G ⁇ N; the negative current path is: N ⁇ G ⁇ L 12 ⁇ T 14 ⁇ C s ⁇ T 13 ⁇ N.
  • the inverter output voltage is equal to the floating capacitor voltage U PV .
  • the DC forward voltage required by the inverter module is obtained from the positive electrode of the floating capacitor.
  • the second mode the forward current path is: N ⁇ T 13 ⁇ T 15 ⁇ L 12 ⁇ G ⁇ N; the negative current path is: N ⁇ G ⁇ L 12 ⁇ T 15 ⁇ T 13 ⁇ N.
  • the inverter output voltage is equal to zero.
  • a first mode and a second mode, suspended capacitance C s is charged or discharged.
  • the charging circuit P ⁇ T 11 ⁇ L 11 ⁇ C s ⁇ T 13 ⁇ N; discharge circuit: N ⁇ T 13 ⁇ C s ⁇ L 11 ⁇ T 11 ⁇ P.
  • the third mode the forward current path is: N ⁇ T 12 ⁇ C s ⁇ T 15 ⁇ L 12 ⁇ G ⁇ N; the negative current path is: N ⁇ G ⁇ L 12 ⁇ T 15 ⁇ C s ⁇ T 12 ⁇ N.
  • the inverter output voltage is equal to the negative floating capacitor voltage -U PV .
  • the second bidirectional switch T 12 and the first diode D f provide a freewheeling path for the inductor L 11 : L 11 ⁇ T 12 ⁇ D f ⁇ L 11 .
  • the modulation strategy of the single-phase three-level inverter topology circuit provided in this embodiment is: in the positive half cycle of the AC grid voltage, the first mode and the second mode alternately work; in the negative half cycle of the AC grid voltage, the third mode The state and the second mode alternately work.
  • the semiconductor switches in the present application can be implemented by using MOSFETs or IGBTs. Taking an N-channel MOSFET as an example, the drain is the first end, the source is the second end, and the gate is the control terminal.
  • the control terminals of each of the semiconductor switches in the single-phase three-level inverter topology circuit input corresponding driving control signals. For the sake of brevity, the description will not be repeated later.
  • the AC output can be normally operated when the AC power supply is connected to the negative pole of the DC power supply, and the DC power supply can always maintain the ground potential greater than or equal to zero. It can effectively suppress the PID effect; and can completely eliminate the high-frequency leakage current of the inverter topology circuit. Since the DC power supply side is not connected to the voltage dividing capacitor, there is no voltage balance at the midpoint of the voltage dividing capacitor. problem.
  • the first bidirectional switch T 11 and the first diode D f function together to connect the positive pole of the DC power source PV when the first bidirectional switch T 11 is turned on.
  • the left end of the first inductor L 11 is connected; and when the first bidirectional switch T 11 is turned off, the connection between the anode of the PV and the first inductor L 11 is disconnected; and the cathode of the DC power source PV and the first inductor L 11 are additionally
  • the left end is single-pass; it functions as a charging control unit.
  • other structures capable of performing the same or similar functions may be used instead of the first bidirectional switch T 11 and the first diode D f , and the corresponding technical solutions should fall within the scope of the present invention. protected range.
  • the above-mentioned inverter module functions to make the corresponding devices electrically or not connected to each other in the above three modes.
  • those skilled in the art can also design the above-mentioned inverter module as another structure to replace the second bidirectional switch T 12 , the third bidirectional switch T 13 , the fourth bidirectional switch T 14 and the fifth bidirectional switch in FIG. 1 .
  • the T 15 implements the corresponding functions, and the corresponding solutions do not affect the implementation of the present invention, and should also fall within the scope of the present invention.
  • each bidirectional switch is connected to a corresponding control end, and each control end is used to access a corresponding control signal.
  • each of the bidirectional switches may be connected to the respective control terminals one-to-one, or a plurality of bidirectional switches whose working states are always the same may be connected to the same control terminal.
  • each of the diodes may be replaced with other unidirectional conduction elements capable of achieving a single conduction.
  • unidirectional conduction elements capable of achieving a single conduction.
  • FIG. 2 is a schematic diagram showing the circuit principle of a second single-phase three-level inverter topology according to an embodiment of the present invention. Unlike the single-phase three-level inverter topology shown in FIG. 1, the first in FIG. The anode of the diode D f is connected to the cathode of the suspension capacitor C s and the freewheeling path of the inductor L 11 is: L 11 ⁇ T 12 ⁇ T 13 ⁇ D f ⁇ L 11 .
  • FIG. 3 is a schematic diagram showing the circuit principle of a third single-phase three-level inverter topology according to an embodiment of the present invention. Unlike the topology shown in FIG. 1, the first of the fourth bidirectional switch T 14 in FIG. The terminal is connected to the first end of the first bidirectional switch T 11 and the positive pole of the DC power supply PV, that is, the DC forward voltage required by the inverter module is directly obtained from the positive pole of the DC power supply.
  • FIG. 4 is a schematic diagram showing the circuit principle of a fourth single-phase three-level inverter topology according to an embodiment of the present invention. Unlike FIG. 3, the anode of the first diode D f in FIG. The negative pole of the capacitor C s has the same structure and will not be described here.
  • the second, third, and fourth single-phase three-level inverter topologies operate in the same manner as the first single-phase three-level inverter topology. Referring to the working principle analysis of the first single-phase three-level inverter topology described above, a similar working modal analysis can be performed for the second, third, and fourth single-phase three-level inverter topologies. Let me repeat.
  • FIG. 5 is a schematic diagram showing the circuit principle of a first single-phase five-level inverter topology according to an embodiment of the present invention.
  • the single-phase five-level inverter topology circuit includes: a first floating capacitor C s1 , a second floating capacitor C s2 , a charging and discharging module M1 , and a five-level inverter module.
  • the five-level inverter module includes a first inverter unit and a second inverter unit M2.
  • the first inverting unit includes a first switching circuit branch and a second switching circuit branch.
  • the first switching circuit branch includes a second bidirectional switch T 52 and the second switching circuit branch includes a third bidirectional switch T 53 .
  • the charging and discharging module M1 includes a first bidirectional switch T 11 , a first inductor L 11 , and a first diode D f .
  • the second inverter unit M2 includes a first input terminal I 1 , a second input terminal I 0 , a third input terminal I ⁇ 1 , and an AC output terminal I out .
  • the first end of the first bidirectional switch T 11 is connected to the positive end of the DC power source PV, and the second end of the first bidirectional switch T 11 is connected to the first end of the first inductor L 11 .
  • the second end of the first inductor L 11 is connected to the anode of the first floating capacitor C s1 .
  • the cathode of the first diode D f is connected to the common terminal of the first bidirectional switch T 11 and the first inductor L 11 , and the anode of the first diode D f is connected to the cathode of the DC power source PV.
  • the first inductor L 11 and the first diode D f are for suppressing an inrush current when the first floating capacitor C s1 and the second floating capacitor C s2 are charged.
  • the freewheeling path of the first inductor L 11 is: L 11 ⁇ C s1 ⁇ C s2 ⁇ T 53 ⁇ D f ⁇ L 11 .
  • the cathode of the first floating capacitor C s1 is connected to the anode of the second suspension capacitor C s2 .
  • the cathode of the second suspension capacitor C s2 is connected to the third input terminal I -1 of the second inverter unit M2.
  • the first end of the second bidirectional switch T 52 is connected to the positive terminal of the first floating capacitor C s1 , and the second end of the second bidirectional switch T 52 is connected to the first end of the third bidirectional switch T 53 .
  • the common ends of the second bidirectional switch T 52 and the third bidirectional switch T 53 are simultaneously connected to the negative pole of the direct current power source PV and the first end of the alternating current grid.
  • the second end of the third bidirectional switch T 53 is connected to the negative pole of the second floating capacitor C s2 .
  • the first input terminal I 1 of the second inverter unit M2 is connected to the anode of the first suspension capacitor C s1
  • the second input terminal I 0 of the second inverter unit M2 is connected to the first suspension capacitor C s1 and the second suspension capacitor C s2
  • the common terminal of the second inverter AC output terminal I out cell M2 connected to the second end of the AC power grid G by a second inductor L 52.
  • the second inductor L 52 is used to filter out ripple in the output current to improve current quality.
  • a switching circuit sub-branch is disposed between each input end of the second inverter unit M2 and the AC output terminal I out .
  • the second input end and the third input end are respectively a first switch circuit sub-branch, a second switch circuit sub-branch and a third switch circuit sub-branch.
  • the first suspension capacitor C s1 has a capacitive reactance equal to the second suspension capacitor C s2 .
  • the DC power supply PV is commonly charged by the first floating capacitor C s1 and the second floating capacitor C s2 , so the first floating capacitor voltage is equal to the second floating capacitor voltage, that is, equal to half of the DC power supply voltage of 0.5 U PV .
  • the first switching circuit branch operates, that is, the second bidirectional switch T 52 is turned on.
  • the first end of the AC power grid is equivalently connected to the first floating capacitor C s1 positive terminal or the first input terminal I 1 of the second inverter unit M2 .
  • the inverter output voltage is equal to zero; if the second switching circuit sub-branch operates, the inverter output voltage is equal to the negative first floating capacitor voltage, ie -0.5 U PV If the third switching circuit sub-branch operates, the inverter output voltage is equal to the sum of the negative first floating capacitor voltage and the negative second floating capacitor voltage, ie -U PV .
  • the second switching circuit branch operates, that is, the third bidirectional switch T53 is turned on.
  • the first end of the AC power grid is equivalently connected to the second floating capacitor C s2 anode or the third input terminal I -1 of the second inverter unit M2.
  • the inverter output voltage is equal to the sum of the first floating capacitor voltage and the second floating capacitor voltage, that is, U PV ;
  • the second switching circuit sub-branch operates, the inverter The output voltage of the device is equal to the second floating capacitor voltage, ie 0.5 U PV ; if the third switching circuit sub-branch is active, the inverter output voltage is equal to zero.
  • FIG. 6 is a schematic diagram showing the circuit principle of a second single-phase five-level inverter topology according to an embodiment of the present invention. Topology shown in Figure 5 except that the negative electrode and the first inductor L freewheel path anode of the first diode D f in FIG 6 is connected to a second capacitance C s2 of the suspension is 11: L 11 ⁇ C s1 ⁇ C s2 ⁇ D f ⁇ L 11 .
  • FIG. 7 is a schematic diagram showing the circuit principle of a third single-phase five-level inverter topology provided by an embodiment of the present invention. Topology shown in Figure 5 except that the first input of the second inverter in FIG. 7 means M2 simultaneously connected to the terminal I 1 of the first bidirectional switch T positive electrode terminal 11 and a first DC power source PV, other The structure is the same as that of FIG. 5. The DC forward voltage required by the inverter module is directly obtained from the positive pole of the DC power supply.
  • FIG. 8 is a schematic diagram showing the circuit principle of a fourth single-phase five-level inverter topology according to an embodiment of the present invention. The difference from the topology shown in FIG. 7 is that the anode of the first diode D f in FIG. 8 is connected to the cathode of the second suspension capacitor C s2 and the freewheeling path of the first inductor L 11 is: L 11 ⁇ C s1 ⁇ C s2 ⁇ D f ⁇ L 11 .
  • FIG. 9 is a schematic diagram showing the circuit principle of a first type of second inverter unit M2 according to an embodiment of the present invention.
  • the second inverter unit M2 includes a fourth bidirectional switch T 94 , a fifth bidirectional switch T 95 , a sixth bidirectional switch T 96 , and a seventh bidirectional switch T 97 .
  • the first end of the fourth bidirectional switch T 94 is connected to the first input end I 1 of the second inverting unit M2 , and the second end of the fourth bidirectional switch T 94 is connected to the second inverting unit M2 AC output I out .
  • the first end of the fifth bidirectional switch T 95 is connected to the second input end I 0 of the second inverting unit M2 , and the second end of the fifth bidirectional switch T 95 is connected to the second end of the sixth bidirectional switch T 96 ,
  • the first end of the six-way switch T 96 is connected to the AC output terminal I out of the second inverter unit M2.
  • the first end of the seventh bidirectional switch T 97 is connected to the AC output terminal I out of the second inverter unit M2, and the second end of the seventh bidirectional switch T 97 is connected to the third end of the second inverter unit M2 Input I-1.
  • FIG. 10 is a schematic diagram showing the circuit principle of a second second inverting unit M2 according to an embodiment of the present invention.
  • the second inverter unit M2 includes a fourth bidirectional switch T 104 , a fifth bidirectional switch T 105 , a sixth bidirectional switch T 106 , and a seventh bidirectional switch T 107 .
  • the first end of the fourth bidirectional switch T 104 is connected to the first input end I 1 of the second inverter unit M2 , and the second end of the fourth bidirectional switch T 104 is connected to the AC output end of the second inverter unit M2 . I out .
  • the second input terminal of the second T fifth bidirectional switch 105 is connected to the second terminal M2 inverter unit I 0, T fifth bidirectional switch 105 is connected to a first end of the second end 106 of the sixth bidirectional switch T.
  • the first end of the sixth bidirectional switch T 106 is connected to the AC output end I out of the second inverting unit M2.
  • the first end of the seventh bidirectional switch T 107 is connected to the second end of the sixth bidirectional switch T 106 , and the second end of the seventh bidirectional switch T 107 is connected to the third input end I -1 of the second inverting unit M2 .
  • FIG. 11 is a schematic diagram showing the circuit principle of a third second inverting unit M2 according to an embodiment of the present invention.
  • the second inverter unit M2 includes a fourth bidirectional switch T 114 , a fifth bidirectional switch T 115 , a sixth bidirectional switch T 116 , and a seventh bidirectional switch T 117 .
  • the first end of the fourth bidirectional switch T 114 is connected to the first end I 1 of the second inverting unit M2, and the second end of the fourth bidirectional switch T 114 is connected to the first end of the sixth bidirectional switch T 116 .
  • the second end of the six-way switch T 116 is connected to the AC output terminal I out of the second inverter unit M2.
  • the first end of the fifth bidirectional switch T 115 is connected to the first end of the sixth bidirectional switch T 116 , and the second end of the fifth bidirectional switch T 115 is connected to the second input end I 0 of the second inverting unit M2.
  • the first end of the seventh bidirectional switch T 117 is connected to the AC output end I out of the second inverting unit M2, and the second end of the seventh bidirectional switch T 117 is connected to the third end of the second inverting unit M2 Input I -1 .
  • FIG. 12 is a schematic diagram showing the circuit principle of a fourth second inverting unit M2 according to an embodiment of the present invention.
  • the second inverter unit M2 includes: a fourth bidirectional switch T 124 , a fifth bidirectional switch T 125 , a sixth bidirectional switch T 126 , a seventh bidirectional switch T 127 , and a second diode D 122 and a third diode D 123 .
  • the first end of the fourth bidirectional switch T 124 is connected to the first input end I 1 of the second inverting unit M2, and the second end of the fourth bidirectional switch T 124 is connected to the fifth bidirectional switch T 125 At one end, the second end of the fifth bidirectional switch T 125 is coupled to the first end of the sixth bidirectional switch T 126 .
  • T sixth bidirectional switch 126 is connected to a second terminal of the seventh end of the first bidirectional switch T 127, T seventh bidirectional switch connecting a second terminal of a third input of the second inverter unit M2 of the terminal I -1 127.
  • the common ends of the fifth bidirectional switch T 125 and the sixth bidirectional switch T 126 are connected to the AC output terminal I out of the second inverting unit M2.
  • the cathode of the second diode D 122 is connected to the common terminal of the fourth bidirectional switch T 124 and the fifth bidirectional switch T 125 , and the anode of the second diode D 122 is connected to the cathode of the third diode D 123 , the third two
  • the anode of the pole tube D 123 is connected to the common terminal of the sixth bidirectional switch T 126 and the seventh bidirectional switch T 127 .
  • the common terminal of the second diode D 122 and the anode D 123 of the third diode is connected to the second input terminal I 0 of the second inverter unit M2.
  • FIG. 13 is a schematic diagram showing the circuit principle of a fifth second inverting unit M2 according to an embodiment of the present invention.
  • the second inverter unit M2 includes: a fourth bidirectional switch T 134 , a fifth bidirectional switch T 135 , a sixth bidirectional switch T 136 , a second diode D 132 , and a third diode D 133 , fourth diode D 134 and fifth diode D 135 .
  • the first end of the fourth bidirectional switch T 134 is connected to the first input end I 1 of the second inverter unit M2 , and the second end of the fourth bidirectional switch T 134 is connected to the AC output end of the second inverter unit M2 . I out .
  • the first end of the sixth bidirectional switch T 136 is connected to the AC output end I out of the second inverter unit M2, and the second end of the sixth bidirectional switch T 136 is connected to the third input end of the second inverter unit M2. I -1 .
  • the cathode of the second diode D 132 is connected to the first end of the fifth bidirectional switch T 135 , the anode of the second diode D 132 is connected to the cathode of the third diode D 133 , and the anode of the third diode D 133 The second end of the fifth bidirectional switch T 135 is connected.
  • the common end of the second diode D 132 and the third diode D 133 is connected to the second input terminal I 0 of the second inverter unit M2; the negative terminal of the fourth diode D 134 is connected to the fifth bidirectional switch T
  • the first end of the 135 , the anode of the fourth diode D 134 is connected to the cathode of the fifth diode D 135 , and the anode of the fifth diode D 135 is connected to the second end of the fifth bidirectional switch T 135 , the fourth two
  • the common terminal of the diode D 134 and the fifth diode D 135 is connected to the AC output terminal I out of the second inverter unit M2.
  • First working mode forward current: N ⁇ T 53 ⁇ C s2 ⁇ C s1 ⁇ T 94 ⁇ L 52 ⁇ G ⁇ N; negative current: N ⁇ G ⁇ L 52 ⁇ T 94 ⁇ C s1 ⁇ C s2 ⁇ T 53 ⁇ N.
  • the inverter output voltage is equal to the sum of the first floating capacitor voltage and the second floating capacitor voltage, ie U PV .
  • Second working mode forward current: N ⁇ T 53 ⁇ C s2 ⁇ T 95 ⁇ T 96 ⁇ L 52 ⁇ G ⁇ N; negative current: N ⁇ G ⁇ L 52 ⁇ T 96 ⁇ T 95 ⁇ C s2 ⁇ T 53 ⁇ N.
  • the inverter output voltage is equal to the second floating capacitor voltage, which is 0.5U PV .
  • the third working mode forward current: N ⁇ T 53 ⁇ T 97 ⁇ L 52 ⁇ G ⁇ N; negative current: N ⁇ G ⁇ L 52 ⁇ T 97 ⁇ T 53 ⁇ N.
  • the inverter output voltage is equal to zero.
  • the inverter output voltage is equal to the sum of the negative first floating capacitor voltage and the negative second floating capacitor voltage, ie -U PV .
  • the AC output end of the second inverter unit M2 in the single-phase five-level inverter provided in this embodiment is connected to the negative pole of the DC power source through the AC power grid, thereby ensuring that the DC power source always maintains the ground potential to be greater than or equal to zero, thereby being effective.
  • the PID effect is suppressed; and the high-frequency leakage current of the inverter topology can be completely eliminated.
  • FIG. 15 is a schematic diagram showing a partial block circuit principle of a first three-phase three-level inverter topology according to an embodiment of the present invention.
  • the three-phase three-level inverter topology comprises a discharge module M1, capacitance C s and a suspension of a three-phase inverter circuit.
  • the charging and discharging module M1 includes a first bidirectional switch T 11 , a first inductor L 11 and a first diode D f .
  • the specific circuit connection and working principle are the same as those of the charging and discharging module shown in FIG. 1 . Narration.
  • the three-phase inverter circuit includes a first switching circuit branch, a second switching circuit branch, and three second inverter units M2.
  • the first switching circuit branch includes a second bidirectional switch T 152 and the second switching circuit branch includes a third bidirectional switch T 153 .
  • Each of the second inverter units M2 has a first input terminal, a second input terminal, a third input terminal, and an AC output terminal.
  • the first end of the second bidirectional switch T 152 is connected to the positive pole of the floating capacitor C s
  • the second end of the second bidirectional switch T 152 is connected to the first end of the third bidirectional switch T 153
  • the common end of the third bidirectional switch T 153 is connected to the negative pole of the DC power source PV.
  • the second end of the third bidirectional switch T 153 is connected to the negative terminal of the floating capacitor C s .
  • the first input ends of the three second inverter units M2 are connected to the first end of the second bidirectional switch T 152 ; the second input ends of the three second inverter units M2 are connected to the negative pole of the DC power supply PV; The three input terminals are connected to the negative pole of the floating capacitor C s ; the three AC output terminals of the three second inverter units M2 are respectively connected to the three phases of the AC power grid. If the ground of the AC power grid is connected to the negative pole of the DC power supply, a three-phase four-wire system is formed; conversely, if the ground of the AC power grid is not connected to the negative pole of the DC power supply, a three-phase three-wire system is formed.
  • any one of the three second inverter units M2 may adopt any one of the second inverter units shown in FIG. 9 to FIG. 13 , and details are not described herein again. Considering the ease of integration, the three second inverter units preferentially use the same second inverter unit. For example, the three second inverter units M2 all adopt the second inverter unit shown in FIG.
  • the three-phase circuit part shares the charging and discharging module, the floating capacitor and the first and second switching circuit branches, thereby simplifying the circuit structure, reducing the circuit cost, and facilitating the circuit. integrated.
  • FIG. 16 is a schematic diagram showing the principle of a partial block circuit of a second three-phase three-level inverter topology according to an embodiment of the present invention. Unlike the topology shown in FIG. 15, the three second inverters in FIG. The first input end of the unit is connected to the positive pole of the DC power supply PV, and the other parts are the same as those in FIG. 15 and will not be described again here.
  • FIG. 17 is a schematic diagram showing the principle of a partial block circuit of a third three-phase three-level inverter topology according to an embodiment of the present invention. Unlike the topology shown in FIG. 15, the first diode D in FIG. The anode of f is connected to the cathode of the suspension capacitor C s , and the other portions are the same as those of FIG. 15 and will not be described herein.
  • FIG. 18 is a schematic diagram showing a partial block circuit principle of a fourth three-phase three-level inverter topology according to an embodiment of the present invention. Unlike the topology shown in FIG. 17, three second inverters in FIG. 18 are shown. The first input end of the unit is connected to the positive pole of the DC power supply PV, and the other parts are the same as those in FIG. 17, and details are not described herein again.
  • Figure 19 (a) is a block diagram showing the equivalent circuit of the first single-phase three-level inverter topology of the embodiment of the present invention.
  • the discharge module defines a first end of the first bidirectional switch T 11 for the single-phase three-level inverter topology positive DC input terminal, while the definition of the DC power supply is connected to the negative terminal It is its negative DC input.
  • Figure 19(b) shows the single-phase three-level inverter topology shown in Figure 19(a).
  • the fifth three-phase three-level inverter topology includes three single-phase three-level inverter topologies in which three input sides are connected in parallel.
  • the two DC input terminals of each single-phase three-level inverter topology are connected in parallel at both ends of the DC power supply.
  • the positive DC input terminals of the three single-phase three-level inverter topologies are connected to the positive pole of the DC power supply, and the negative DC input terminals are connected to the negative pole of the DC power supply.
  • the three AC outputs of the three single-phase three-level inverter topologies are respectively connected to the three phases of the AC grid (A phase, B phase, C phase).
  • any of the three single-phase three-level inverter topologies may employ any of the single-phase three-level inverter topologies illustrated in Figures 1 through 4.
  • Figure 20 (a) is a block diagram showing an equivalent circuit of a single-phase five-level inverter topology in accordance with an embodiment of the present invention.
  • Fig. 20(b) is a partial block circuit schematic diagram showing a three-phase five-level inverter topology obtained by using the single-phase five-level inverter topology shown in Fig. 20(a).
  • the three-phase five-level inverter topology includes a single-phase five-level inverter topology in which three input sides are connected in parallel. Wherein, two DC input ends of each single-phase five-level inverter topology are connected in parallel to both ends of the DC power supply. Specifically, the positive DC input terminals of the three single-phase three-level inverter topologies are connected to the positive pole of the DC power supply, and the negative DC input terminals are connected to the negative pole of the DC power supply. The three AC outputs of the three single-phase three-level inverter topologies are respectively connected to the three phases of the AC grid (A phase, B phase, C phase).
  • any one of the three single-phase five-level inverter topologies may adopt any one of the single-phase five-level inverter topologies shown in FIG. 5 to FIG. 8 , and details are not described herein again.
  • the second inverting unit M2 in each single-phase five-level inverter topology may adopt any one of the second inverting units shown in FIG. 9 to FIG.
  • the three single-phase five-level inverter topologies preferentially use the same second inverter unit.
  • three single-phase five-level inverter topologies use the second inverter unit shown in FIG.
  • the AC output terminals of the inverter circuit in the single-phase three-level inverter topology and the single-phase five-level inverter topology provided by the present invention are all exchanged.
  • the grid is connected to the negative pole of the DC power supply, so that the DC power supply always maintains the ground potential greater than or equal to zero. Therefore, the PID effect can be effectively suppressed; and the high-frequency leakage current of the inverter topology can be completely eliminated.
  • the above is only a specific embodiment of the present invention, and it should be noted that those skilled in the art can make some improvements and refinements without departing from the principles of the present invention, for example, according to the present embodiment.
  • the topological circuit in the example utilizes the topology obtained by the symmetry characteristic, and these improvements and retouchings should also be regarded as the protection scope of the present invention.

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  • Power Engineering (AREA)
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Abstract

L'invention concerne un circuit de topologie d'onduleur multiniveau. Des circuits de topologie d'onduleur à trois niveaux et à cinq niveaux peuvent encore fonctionner normalement dans la condition où une extrémité de sortie en courant alternatif d'une partie d'onduleur est connectée à la cathode d'une alimentation électrique en courant continu par le biais d'un réseau en courant alternatif. Ainsi, une alimentation électrique en courant continu peut toujours maintenir un potentiel à la masse supérieur ou égal à zéro, inhibant ainsi efficacement un effet de PID; en outre, un courant de fuite à haute fréquence d'une topologie d'onduleur peut être complètement éliminé.
PCT/CN2016/085453 2015-06-12 2016-06-12 Circuit de topologie d'onduleur multiniveau WO2016197976A1 (fr)

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CN109194175A (zh) * 2018-08-27 2019-01-11 江苏大学 一种共地型无漏电流非隔离光伏并网逆变电路及控制方法
CN113037114A (zh) * 2021-02-25 2021-06-25 国网福建省电力有限公司电力科学研究院 一种三相五电平逆变电路及其工作方法
CN113783455B (zh) * 2021-09-14 2023-08-11 安徽工业大学 一种可抑制漏电流的光伏逆变器及其控制方法

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CN102088252A (zh) * 2011-02-21 2011-06-08 浙江大学 一种开关电容实现无变压器型逆变器及应用
JP2011199927A (ja) * 2010-03-17 2011-10-06 Mitsubishi Electric Corp 太陽光発電システム
CN102624267A (zh) * 2012-03-27 2012-08-01 阳光电源股份有限公司 逆变器及其在三相系统中的应用电路
CN103326606A (zh) * 2013-06-09 2013-09-25 浙江大学 一种单相五电平逆变器
WO2014192014A2 (fr) * 2013-05-02 2014-12-04 Indian Institute Of Technology Bombay Procédé et système pour un micro-inverseur photovoltaïque (pv) bidirectionnel à bas prix, raccordé au réseau

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JP2011199927A (ja) * 2010-03-17 2011-10-06 Mitsubishi Electric Corp 太陽光発電システム
CN102088252A (zh) * 2011-02-21 2011-06-08 浙江大学 一种开关电容实现无变压器型逆变器及应用
CN102624267A (zh) * 2012-03-27 2012-08-01 阳光电源股份有限公司 逆变器及其在三相系统中的应用电路
WO2014192014A2 (fr) * 2013-05-02 2014-12-04 Indian Institute Of Technology Bombay Procédé et système pour un micro-inverseur photovoltaïque (pv) bidirectionnel à bas prix, raccordé au réseau
CN103326606A (zh) * 2013-06-09 2013-09-25 浙江大学 一种单相五电平逆变器

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