WO2016197724A1 - 一种实现高压读写电源的控制装置及方法 - Google Patents

一种实现高压读写电源的控制装置及方法 Download PDF

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WO2016197724A1
WO2016197724A1 PCT/CN2016/080179 CN2016080179W WO2016197724A1 WO 2016197724 A1 WO2016197724 A1 WO 2016197724A1 CN 2016080179 W CN2016080179 W CN 2016080179W WO 2016197724 A1 WO2016197724 A1 WO 2016197724A1
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voltage
branch
read
write
power supply
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French (fr)
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崔海良
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Sanechips Technology Co Ltd
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ZTE Microelectronics Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

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  • the invention relates to a read/write control technology, in particular to a control device and a method for realizing a high voltage read/write power supply.
  • Electrically erasable memory including modules such as Erasable Programmable Read-Only Memory (EPROM) or Electrically Erasable Programmable Read-Only Memory (EEPROM) It belongs to the category of memory chips whose data is not lost after power-off. Its working status includes standby, read status and write status. The standby and read status require the power supply to be a normal power supply. For example, the 5V process requires the power supply to be 5V, while it is in the write state. Since the power supply required by the working mechanism is usually a high voltage power supply, the internal low voltage power supply of the chip cannot be directly used to provide the high voltage power required for the write operation of the erasable memory, and a separate high voltage input power supply is required to satisfy the device. Write power requirements. In this way, the internal high voltage input and the low voltage input power supply need to be respectively sent to the power bus of the erasable memory during the read and write operations, respectively, as the write operation power and the read operation power of the electrically erasable memory unit.
  • the standby and read states require a normal power supply
  • the write state requires a high voltage power supply, that is, a different power supply is required for read and write operations, and whether it can be erased.
  • Providing different power supplies when performing read or write operations on the chip of the memory is a technical problem to be solved.
  • embodiments of the present invention are directed to providing a control apparatus and method for implementing a high-voltage read/write power supply, which at least solves the above technical problems, and can provide different read or write operations on a chip of an erasable memory. power supply.
  • a control device for realizing a high-voltage read-write power supply includes:
  • Writing a branch configured to switch, according to the detected control signal, a high voltage that is output by the external multiplexing pin PIN according to the first preset condition, and is connected to the power bus in the control device according to the detected control signal Vdd_otp, as a write operation high voltage power supply outputted by the control device;
  • a read branch configured to switch an output voltage to an internal normal voltage that meets a second preset condition according to the detected control signal, and to connect to the vdd_otp as a read operation low voltage power supply output by the control device .
  • the write branch and the read branch adopt a back-to-back mode structure
  • the write branch and the read branch output the high voltage power supply or the read operation low voltage power supply in a time division manner.
  • the write branch includes: a first PMOS transistor MP1 and a second PMOS transistor MP2;
  • a switch branch of the write operation is formed by the MP1 and the MP2.
  • the write branch further includes: a first load R1, a second NMOS transistor MN2, and a fourth NMOS transistor MN4;
  • the R1 is connected to the MP1 through a first connection point A, and the A is connected to the power bus vdd_otp through the MP2;
  • the R1 is connected to the MN4 through a second connection point va, and the MN4 is connected to the MN2;
  • the write operation control provided by the R1, the MN2, and the MN4 forms a high write operation Press the power rail of the power supply.
  • the device further includes: a first NMOS transistor MN1, a third NMOS transistor MN3;
  • the MN1 is connected to the MN2;
  • a relative safe VGS voltage is formed between the A and the va such that the voltage value Vva obtained at the va is obtained at the A
  • the voltage value V A is low, and within the safe range specified by the process, the voltage value V A obtained at the A is the same as the write voltage SW;
  • the turn-on and turn-off of the MP1 and the MP2 in the write branch are controlled by the relative safe VGS voltage to control the turn-on and turn-off of the write branch.
  • the read branch includes: a third PMOS transistor MP3 and a fourth PMOS transistor MP4;
  • a switch branch of the read operation is formed by the MP3 and the MP4.
  • the read branch further includes: a second load R2, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a zeroth PMOS transistor MP0;
  • the MP4 is connected to the MP0 through a third connection point C;
  • the MP4 is connected to the R2, and the R2 is also connected to the MP0;
  • the MN 6 is connected to the MP0 through the C.
  • a method for controlling a high voltage read/write power supply includes:
  • the output voltage is switched according to the detected control signal to the high voltage corresponding to the first preset condition input by the external multiplexing pin PIN, and is connected to the power bus in the control device as a a write operation high voltage power supply outputted by the control device;
  • the output voltage is switched according to the detected control signal to an internal normal voltage that meets the second preset condition, and is connected to the power bus in the control device to serve as a read operation low voltage output by the control device. power supply.
  • the write branch and the read branch adopt a back-to-back mode structure
  • the write branch and the read branch output the high voltage power supply or the read operation low voltage power supply in a time division manner.
  • the method further includes:
  • a write power enable signal vpp_en is given in advance before the write operation is performed, and the write branch is turned on by the vpp_en.
  • the opening the write branch by using the vpp_en includes:
  • the fourth NMOS transistor MN4 is opened by the vpp_en, and the current I1 passes through the first load R1, the MN4 and the second NMOS transistor MN2 to the ground, so that a relative relationship is formed between the first connection point A and the second connection point va. Safe VGS voltage;
  • Va voltage value of the voltage value obtained at the A V A obtained is lower than Vva, and within a predetermined range of process safety, the voltage value V A of the A and obtained the same write voltage SW;
  • the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on by the relative safety VGS voltage to output the SW to the power bus vdd_otp in the control device.
  • the method further includes: turning off the read branch by using the vpp_en.
  • the closing the read branch by the vpp_en includes:
  • the MN 5 and the MN 6 are implemented using a high pressure tube.
  • the method further includes:
  • the third NMOS transistor MN3, the MN5, and the MN6 need to open the fourth PMOS transistor MP4 during the read operation;
  • Vref_okb is high, the MN5 is turned on, the third connection point C is pulled low, the MP4 of the read branch is turned on, and vpp_en is low, the third PMOS transistor MP3 is turned on, and the control device is
  • the internal power source psd_int is output to the vdd_otp, which is the read power supplied by the control device during the POR phase.
  • the method further includes:
  • the MN3 receives a current flowing through the MN1 from the reference and acts as a pull-down current, and the C is pulled low by the pull-down current to turn on the MP4 of the read branch;
  • the MP3 is still turned on when the vpp_en is low, and the switch tube branch forming a read operation by the MP3 and the MP4 outputs the psd_int to the vdd_otp, which is provided by the control device during the working phase. Read the power supply.
  • the method further includes: the MP0 is connected to the second load R2, the MP4 is connected to the R2, and the MP4 is further connected to the MP0 through the C;
  • connection method for connecting the MP0 to the R2 includes:
  • a control device for implementing a high-voltage read/write power supply includes a write branch and a read branch, and the write branch is configured to switch the output voltage according to the detected control signal during a write operation.
  • the external multiplexing pin PIN inputs a high voltage that meets the first preset condition, and is connected to the power bus vdd_otp in the control device to serve as a write operation high voltage power supply output by the control device;
  • the read branch is configured as During the read operation, the output voltage is switched according to the detected control signal to an internal normal voltage that meets the second preset condition, and is connected to the vdd_otp as a read operation low voltage power supply output by the control device.
  • the output high voltage and the low voltage are respectively realized by the write branch and the read branch, so that different power sources can be provided when a read operation or a write operation is performed on a chip of an erasable memory.
  • FIG. 1 is a schematic structural diagram of an apparatus example for applying an application scenario according to an embodiment of the present invention.
  • a control device for realizing a high-voltage read-write power supply includes:
  • Writing a branch configured to switch, according to the detected control signal, a high voltage corresponding to the first preset condition, such as 7V, input to the external multiplexing pin PIN according to the detected control signal, and connected to the control device
  • the power bus vdd_otp is used as a write operation high voltage power supply outputted by the control device;
  • the read branch is configured to switch the output voltage to an internal normal voltage according to the second preset condition according to the detected control signal during the read operation, for example 5V and connected to the vdd_otp as a read operation low voltage power supply output by the control device.
  • the write branch and the read branch adopt a back-to-back mode; the write branch and the read branch output the write time in a time-sharing manner. Operate the high voltage power supply or read the low voltage power supply.
  • the write branch includes: a first PMOS transistor MP1 and a second PMOS transistor MP2;
  • a switch branch of the write operation is formed by the MP1 and the MP2.
  • the write branch further includes: a first load R1, a second NMOS transistor MN2, and a fourth NMOS transistor MN4; the R1 is connected to the MP1 through the first connection point A, The A is connected to the power bus vdd_otp through the MP2; the R1 is connected to the MN4 through a second connection point va, the MN4 is connected to the MN2; and the R1, the MN2, the The write operation control provided by the MN4 forms a power rail for writing high voltage power.
  • the device further includes: a first NMOS transistor MN1, a third NMOS transistor MN3; the MN1 is connected to the MN2; and the write power enable signal vpp_en is applied to the MN4.
  • a safe VGS voltage is formed between the A and the va such that the voltage value Vva obtained at the va is lower than the voltage value V A obtained at the A, and is within the safety range specified by the process.
  • SW with the same write voltage V a of the voltage value a obtained; controlled by the write voltage VGS of the safe and the branch of the MP1 and MP2 are turned off to control the writing The opening and closing of the branch.
  • the read branch includes: a third PMOS transistor MP3 and a fourth PMOS transistor MP4; and a switch tube branch formed by the MP3 and the MP4 to form a read operation.
  • the read branch further includes: a second load R2, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a zeroth PMOS transistor MP0; and the MP4 passes through the third connection point C. Connected to the MP0; the MP4 is connected to the R2, and the R2 is also connected to the MP0; the MN6 is connected to the MP0 through the C.
  • a method for controlling a high voltage read/write power supply includes:
  • the output voltage is switched according to the detected control signal to the high voltage corresponding to the first preset condition input by the external multiplexing pin PIN, and is connected to the power bus in the control device as a a write operation high voltage power supply outputted by the control device;
  • the output voltage is switched according to the detected control signal during the read operation to be in accordance with the second
  • An internal normal voltage of a preset condition is connected to a power bus in the control device to serve as a read operation low voltage power source output by the control device.
  • the write branch and the read branch adopt a back-to-back mode; the write branch and the read branch output the write time in a time-sharing manner. Operate the high voltage power supply or read the low voltage power supply.
  • the method further includes:
  • a write power enable signal vpp_en is given in advance before the write operation is performed, and the write branch is turned on by the vpp_en.
  • the opening the write branch by using the vpp_en includes:
  • the fourth NMOS transistor MN4 is opened by the vpp_en, and the current I1 passes through the first load R1, the MN4 and the second NMOS transistor MN2 to the ground, so that safety is formed between the first connection point A and the second connection point va.
  • Va voltage value of the voltage value obtained at the A V A obtained is lower than Vva, and within a predetermined range of process safety, the voltage value V A of the A and obtained the same write voltage SW;
  • the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on by the relative safety VGS voltage to output the SW to the power bus vdd_otp in the control device.
  • the method further includes: turning off the read branch by using the vpp_en.
  • the closing the read branch by using the vpp_en includes:
  • the MN 5 and the MN 6 are implemented using a high pressure tube.
  • the method further includes:
  • the third NMOS transistor MN3, the MN5, and the MN6 need to open the fourth PMOS transistor MP4 during the read operation;
  • Vref_okb is high, the MN5 is turned on, the third connection point C is pulled low, the MP4 of the read branch is turned on, and vpp_en is low, the third PMOS transistor MP3 is turned on, and the control device is
  • the internal power source psd_int is output to the vdd_otp, which is the read power supplied by the control device during the POR phase.
  • the method further includes:
  • the MN3 receives a current flowing through the MN1 from the reference and acts as a pull-down current, and the C is pulled low by the pull-down current to turn on the MP4 of the read branch;
  • the MP3 is still turned on when the vpp_en is low, and the switch tube branch forming a read operation by the MP3 and the MP4 outputs the psd_int to the vdd_otp, which is provided by the control device during the working phase. Read the power supply.
  • the substrate of MP0 is connected to vdd_otp to increase the substrate bias effect of MP0, and the threshold voltage of MP0 is increased, so that MP0 is more difficult to conduct at this time, so that the circuit does not have leakage current through MP0 at this time.
  • This application scenario involves the control technology of power management in chips in the field of electrically erasable memory and similar digital-analog hybrid chips.
  • modules such as EPROM or EEPROM
  • the power supply problem of different voltage sources is required for reading and writing operations. solve.
  • the electrically erasable memory unit Since the electrically erasable memory unit is usually used as an IP core, it is integrated into the integrated circuit chip, and its power bus is connected to the outside through the chip PIN to provide read and write power of the electrically erasable memory unit.
  • This method can provide a separate power PIN in the ASIC design due to more chip PIN.
  • the read power of the electrically erasable memory unit In the digital-analog hybrid chip such as power management, in order to reduce the number of chip PINs, the read power of the electrically erasable memory unit is usually selected as The working power of the chip, its write power supply usually uses a multiplexed pin or a pin (PIN) input, which can reduce the required dedicated PAD to introduce read and write power, increase the chip a PAD, banding, packaging, etc.
  • PIN pin
  • the link will increase the cost of the chip and reduce the competitiveness of the chip.
  • the PIN is the wiring from the internal circuit of the integrated circuit (chip) and the peripheral circuit. All the pins constitute the interface function of the chip. After the PIN chip is packaged, the user sees it. The pin is the pin of the silicon chip, which is the pin that is packaged inside the chip and is not visible to the user.
  • the present application adopts the present invention.
  • the embodiment is a solution for solving the design of the high-voltage read/write power supply of the erasable memory, and the high-voltage power supply with the output voltage being the internal power supply (5v) or the external multiplexing PIN angle input can be switched according to the control signal.
  • Switch implementation 2) write power to high voltage
  • the power supply while in the current process, the withstand voltage of the high-voltage device is at the D and S terminals, and the withstand voltage of the VGS is usually the normal voltage of the process, which requires the solution to provide a relative power rail, generating a relative "ground potential”.
  • FIG. 1 is a schematic structural diagram of an apparatus for applying an application scenario according to an embodiment of the present invention. According to the foregoing three aspects, a specific implementation of the present invention includes the following content:
  • each power switch is implemented using a back-to-back switch branch.
  • MP1 and MP2 form the switching branch of the write operation
  • MP3 and MP4 form the switching branch of the read operation.
  • This two-way back-to-back switch prevents leakage between the two power supplies.
  • the read branch and the write branch are divided by the dd thick dotted line in FIG. 1, and the left part of the dd thick dotted line in the whole chip is the write branch, and the entire chip is located at the thick dotted line of dd. The right part is the read branch.
  • the power rail supply circuit of the scheme adopts the VWRITE-I*R method to obtain the relative "ground potential" of the high voltage write power source, thereby safely controlling the shutdown and opening of the high voltage write branch.
  • R1, MN2, MN4 provide control of the write operation, which produces a power rail that writes a high voltage power supply.
  • the specific production method is:
  • the write power enable signal vpp_en is given in advance before the chip performs the write operation, vpp_en turns on the MN4 tube, and the current I1 goes to the ground via R1, MN4, and MN2.
  • the voltage of the SW is 7V of the erasable memory high-voltage write voltage, so that the va point is a "relatively” lower than the A point by 5V. Potential.
  • the write voltage SW and the "relatively" absolute 5V drop differential can safely turn on the MP1 and MP2 tubes to output the write power SW to the power supply vdd_otp of the erasable memory.
  • the write power enable signal also needs to turn off the read branch.
  • the reference in the chip has been established to give the vref_ok high signal.
  • MN5 is turned off, MN6 is turned on, and MN3 mirrors the current flowing from the reference through MN1.
  • This pull-down current will be C point is pulled low to make the switching branch of the read branch MP4 turn on, the MP3 tube is still turned on because vpp_en is low, and the read switch branch composed of MP3 and MP4 outputs the internal power supply psd_int to vdd_otp, which is an erasable memory unit in the chip.
  • the working phase provides read power.
  • the substrate of MP0 is connected to vdd_otp to increase the substrate bias effect of MP0, and the threshold voltage of MP0 is increased, so that MP0 is more difficult to conduct at this time, so that the circuit does not have leakage current through MP0 at this time.
  • the application scenario of the present invention is simple in structure and small in chip area.
  • the devices used use the basic layer of PDK, which does not increase the excess mask layer and reduces the overall cost of the chip.
  • the power switching control logic adopted by the embodiment of the present invention is simple, the control mechanism is clear, and the switching of the read/write power can be controlled safely and reliably.
  • This application scenario adopts the power rail implementation method proposed by the embodiment of the invention to be simple and reliable, and can conveniently control the shutdown and open operation of the high voltage branch, so that the device works in a safe and reliable voltage range.
  • This application scenario adopts the back-to-back implementation scheme proposed by the embodiment of the present invention, so that the relative independence of the two power sources under different read and write voltages does not cause current backflow and the like.
  • the integrated modules described in the embodiments of the present invention may also be stored in a computer readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .
  • embodiments of the invention are not limited to any specific combination of hardware and software.
  • an embodiment of the present invention further provides a computer storage medium, where a calculation is stored
  • the computer program is used to execute the control method for realizing high voltage read/write power supply according to an embodiment of the present invention.
  • the write branch is configured to switch, according to the detected control signal, a high voltage corresponding to the first preset condition, which is input by the external multiplexing pin PIN, according to the detected control signal, and is connected to the
  • the power bus vdd_otp in the control device is used as a write operation high voltage power supply outputted by the control device;
  • the read branch is configured to switch the output voltage according to the detected control signal to an internal routine conforming to the second preset condition during the read operation a voltage, and connected to the vdd_otp, as a read operation low voltage power supply output by the control device.
  • the output high voltage and low voltage are respectively realized by the write branch and the read branch, so that different power sources can be provided when a read operation or a write operation is performed on a chip of an erasable memory.

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Abstract

一种实现高压读写电源的控制装置及方法，其中，所述装置包括：写支路，配置为在写操作时，根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线vdd_otp，以作为所述控制装置输出的写操作高压电源；读支路，配置为在读操作时，根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，且连通到所述vdd_otp，以作为所述控制装置输出的读操作低压电源。

Description

一种实现高压读写电源的控制装置及方法 技术领域
本发明涉及读写控制技术，尤其涉及一种实现高压读写电源的控制装置及方法。
背景技术
本申请发明人在实现本申请实施例技术方案的过程中，至少发现相关技术中存在如下技术问题：
包括可擦写可编程只读存储器(EPROM，Erasable Programmable Read-Only Memory)或电可擦除可编程只读存储器(EEPROM，Electrically Erasable Programmable Read-Only Memory)等模块在内的电可擦除存储器，属于掉电后数据不丢失的存储芯片范畴，其工作状态包括standby、读状态和写状态，其standby以及读状态要求的电源为常规电源比如5V工艺下要求电源是5V，而其在写状态由于其工作机理所要求的电源通常为高压电源，此时芯片的内部低压电源已经不能直接用来为可擦除存储器提供写操作所需要的高压电源，需要单独的高压输入电源来满足该器件的写电源需求。这样就需要将内部的高压输入和低压输入电源在读、写操作时，分别输送到可擦除存储器的电源总线，分别作为电可擦除存储器单元的写操作电源和读操作电源。
综上所述可知：standby以及读状态需要的电压为常规电源，而写状态需要的电压为高压电源，也就是说，进行读操作、写操作时需要不同的电源，能否在一个可擦除存储器的芯片上实现读操作或写操作时提供不同的电源是要解决的技术问题，然而，对于这个技术问题，相关技术并未存在有效的解决方案。
发明内容
有鉴于此，本发明实施例希望提供一种实现高压读写电源的控制装置及方法，至少解决了上述技术问题，能在一个可擦除存储器的芯片上实现在读操作或写操作时提供不同的电源。
本发明实施例的技术方案是这样实现的：
本发明实施例的一种实现高压读写电源的控制装置，所述装置包括：
写支路，配置为在写操作时，根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线vdd_otp，以作为所述控制装置输出的写操作高压电源；
读支路，配置为在读操作时，根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，且连通到所述vdd_otp，以作为所述控制装置输出的读操作低压电源。
上述方案中，所述写支路与所述读支路采用背靠背模式的结构；
所述写支路与所述读支路以分时输出方式，分时输出所述写操作高压电源或读操作低压电源。
上述方案中，所述写支路包括：第一PMOS管MP1和第二PMOS管MP2；
由所述MP1和所述MP2形成写操作的开关管支路。
上述方案中，所述写支路还包括：第一负载R1，第二NMOS管MN2、第四NMOS管MN4；
所述R1通过第一连接点A与所述MP1相连，所述A通过所述MP2与所述电源总线vdd_otp相连；
所述R1通过第二连接点va与所述MN4相连，所述MN4与所述MN2相连；
由所述R1、所述MN2、所述MN4提供的写操作控制，形成写操作高 压电源的电源轨。
上述方案中，所述装置还包括：第一NMOS管MN1、第三NMOS管MN3；
所述MN1与所述MN2相连；
在所述MN4作用有写电源使能信号vpp_en的情况下，在所述A与所述va之间形成相对的安全VGS电压，使得在所述va得到的电压值Vva比在所述A得到的电压值VA要低，且在工艺规定的安全范围内，在所述A得到的电压值VA与写电压SW相同；
通过所述相对的安全VGS电压来控制所述写支路中所述MP1和所述MP2的导通和关断，以控制写支路的开启与关断。
上述方案中，所述读支路包括：第三PMOS管MP3和第四PMOS管MP4；
由所述MP3和所述MP4形成读操作的开关管支路。
上述方案中，所述读支路还包括：第二负载R2，第五NMOS管MN5、第六NMOS管MN6、第零PMOS管MP0；
所述MP4通过第三连接点C与所述MP0相连；
所述MP4与所述R2相连，所述R2还与所述MP0相连；
所述MN6通过所述C与所述MP0相连。
本发明实施例的一种实现高压读写电源的控制方法，所述方法包括：
写支路上，在写操作时根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线以作为所述控制装置输出的写操作高压电源；
读支路上，在读操作时根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，且连通到所述控制装置中的电源总线以作为所述控制装置输出的读操作低压电源。
上述方案中，所述写支路与所述读支路采用背靠背模式的结构；
所述写支路与所述读支路以分时输出方式，分时输出所述写操作高压电源或读操作低压电源。
上述方案中，所述方法还包括：
执行所述写操作前提前给出写电源使能信号vpp_en，通过所述vpp_en开启所述写支路。
上述方案中，所述通过所述vpp_en开启所述写支路，包括：
通过所述vpp_en将第四NMOS管MN4管打开，电流I1经第一负载R1、所述MN4和第二NMOS管MN2到地，使得在第一连接点A与第二连接点va之间形成相对的安全VGS电压；
所述va得到的电压值Vva比在所述A得到的电压值VA要低，且在工艺规定的安全范围内，在所述A得到的电压值VA与写电压SW相同；
通过所述相对的安全VGS电压打开第一PMOS管MP1和第二PMOS管MP2，以将所述SW输出给所述控制装置中的电源总线vdd_otp。
上述方案中，所述方法还包括：通过所述vpp_en关断所述读支路。
上述方案中，所述通过所述vpp_en关断所述读支路，包括：
设置vpp_en为高以关掉MP3管，此时vpp_enb＝vref_okb＝0，关掉第五NMOS管MN5和第六NMOS管MN6；
采用所述相对的安全VGS电压导通第零PMOS管MP0，此时Vc＝vdd_otp＝SW，关掉所述MP0；
所述MN5和所述MN6采用高压管实现。
上述方案中，所述方法还包括：
第三NMOS管MN3、所述MN5、所述MN6在所述读操作时，需要打开第四PMOS管MP4；
检测到在POR阶段需要读寄存器时，此时基准没有建立，没有电流产 生，vref_ok＝0；
vref_okb为高电位将所述MN5打开，将第三连接点C点拉低，使读支路的所述MP4导通，同时vpp_en为低，将第三PMOS管MP3打开，将所述控制装置的内部电源psd_int输出到所述vdd_otp，为所述控制装置在POR阶段提供的读电源。
上述方案中，所述方法还包括：
检测到在工作阶段需要读寄存器，此时基准已经建立，给出vref_ok为高的信号，此时所述MN5关断，所述MN6打开；
所述MN3接收来自基准的流过MN1的电流并作为下拉电流，通过所述下拉电流将所述C拉低，使所述读支路的所述MP4导通；
所述MP3在所述vpp_en为低时仍然导通，由所述MP3和所述MP4形成读操作的开关管支路将所述psd_int输出到所述vdd_otp，为所述控制装置在工作阶段提供的读电源。
上述方案中，所述方法还包括：所述MP0与第二负载R2相连，所述MP4与所述R2相连，所述MP4还通过所述C与所述MP0相连；
针对所述MP0与所述R2相连的接法，包括：
如果内部电源psd_int为高而SW为地电位，此时MP3和MP4管打开，Vva＝VA＝vdd_otp-VT＝psd_int-VT，其中，所述VT为所述MP2的体二极管的导通压差，Vva会使MP0弱导通；
如果有电流流过所述R2和所述MP0，则经过R2的压降，MP0的导通程度进一步的缩小，直至关掉，而且MP0的衬底接vdd_otp增大MP0的衬底偏置效应，增大MP0的阈值电压使得此时MP0更难导通，使电路在此时不会出现通过MP0的漏电流。
本发明实施例的一种实现高压读写电源的控制装置包括写支路和读支路，所述写支路配置为在写操作时，根据侦测的控制信号切换输出电压为 外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线vdd_otp，以作为所述控制装置输出的写操作高压电源；读支路，配置为在读操作时，根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，且连通到所述vdd_otp，以作为所述控制装置输出的读操作低压电源。
采用本发明实施例，通过写支路和读支路分别实现输出高电压和低电压，从而能在一个可擦除存储器的芯片上实现读操作或写操作时提供不同的电源。
附图说明
图1为应用本发明实施例一应用场景的装置实例的结构示意图。
具体实施方式
下面结合附图对技术方案的实施作进一步的详细描述。
本发明实施例的一种实现高压读写电源的控制装置，所述装置包括：
写支路，配置为在写操作时，根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，比如7V，且连通到所述控制装置中的电源总线vdd_otp，以作为所述控制装置输出的写操作高压电源；读支路，配置为在读操作时，根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，比如5V且连通到所述vdd_otp，以作为所述控制装置输出的读操作低压电源。
在本发明实施例一实施方式中，所述写支路与所述读支路采用背靠背模式的结构；所述写支路与所述读支路以分时输出方式，分时输出所述写操作高压电源或读操作低压电源。
在本发明实施例一实施方式中，所述写支路包括：第一PMOS管MP1和第二PMOS管MP2；
由所述MP1和所述MP2形成写操作的开关管支路。
在本发明实施例一实施方式中，所述写支路还包括：第一负载R1，第二NMOS管MN2、第四NMOS管MN4；所述R1通过第一连接点A与所述MP1相连，所述A通过所述MP2与所述电源总线vdd_otp相连；所述R1通过第二连接点va与所述MN4相连，所述MN4与所述MN2相连；由所述R1、所述MN2、所述MN4提供的写操作控制，形成写操作高压电源的电源轨。
在本发明实施例一实施方式中，所述装置还包括：第一NMOS管MN1、第三NMOS管MN3；所述MN1与所述MN2相连；在所述MN4作用有写电源使能信号vpp_en的情况下，在所述A与所述va之间形成安全的VGS电压，使得在所述va得到的电压值Vva比在所述A得到的电压值VA要低，且在工艺规定的安全范围内，在所述A得到的电压值VA与写电压SW相同；通过所述安全的VGS电压来控制所述写支路中所述MP1和所述MP2的导通和关断，以控制写支路的开启与关断。
在本发明实施例一实施方式中，所述读支路包括：第三PMOS管MP3和第四PMOS管MP4；由所述MP3和所述MP4形成读操作的开关管支路。
在本发明实施例一实施方式中，所述读支路还包括：第二负载R2，第五NMOS管MN5、第六NMOS管MN6、第零PMOS管MP0；所述MP4通过第三连接点C与所述MP0相连；所述MP4与所述R2相连，所述R2还与所述MP0相连；所述MN6通过所述C与所述MP0相连。
本发明实施例的一种实现高压读写电源的控制方法，所述方法包括：
写支路上，在写操作时根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线以作为所述控制装置输出的写操作高压电源；
读支路上，在读操作时根据侦测的控制信号切换输出电压为符合第二 预设条件的内部常规电压，且连通到所述控制装置中的电源总线以作为所述控制装置输出的读操作低压电源。
在本发明实施例一实施方式中，所述写支路与所述读支路采用背靠背模式的结构；所述写支路与所述读支路以分时输出方式，分时输出所述写操作高压电源或读操作低压电源。
在本发明实施例一实施方式中，所述方法还包括：
执行所述写操作前提前给出写电源使能信号vpp_en，通过所述vpp_en开启所述写支路。
在本发明实施例一实施方式中，所述通过所述vpp_en开启所述写支路，包括：
通过所述vpp_en将第四NMOS管MN4管打开，电流I1经第一负载R1、所述MN4和第二NMOS管MN2到地，使得在第一连接点A与第二连接点va之间形成安全的VGS电压；
所述va得到的电压值Vva比在所述A得到的电压值VA要低，且在工艺规定的安全范围内，在所述A得到的电压值VA与写电压SW相同；
通过所述相对的安全VGS电压打开第一PMOS管MP1和第二PMOS管MP2，以将所述SW输出给所述控制装置中的电源总线vdd_otp。
在本发明实施例一实施方式中，所述方法还包括：通过所述vpp_en关断所述读支路。
在本发明实施例一实施方式中，所述通过所述vpp_en关断所述读支路，包括：
设置vpp_en为高以关掉MP3管，此时vpp_enb＝vref_okb＝0，关掉第五NMOS管MN5和第六NMOS管MN6；
采用所述相对的安全VGS电压导通第零PMOS管MP0，此时Vc＝vdd_otp＝SW，关掉所述MP0；
所述MN5和所述MN6采用高压管实现。
在本发明实施例一实施方式中，所述方法还包括：
第三NMOS管MN3、所述MN5、所述MN6在所述读操作时，需要打开第四PMOS管MP4；
检测到在POR阶段需要读寄存器时，此时基准没有建立，没有电流产生，vref_ok＝0；
vref_okb为高电位将所述MN5打开，将第三连接点C点拉低，使读支路的所述MP4导通，同时vpp_en为低，将第三PMOS管MP3打开，将所述控制装置的内部电源psd_int输出到所述vdd_otp，为所述控制装置在POR阶段提供的读电源。
在本发明实施例一实施方式中，所述方法还包括：
检测到在工作阶段需要读寄存器，此时基准已经建立，给出vref_ok为高的信号，此时所述MN5关断，所述MN6打开；
所述MN3接收来自基准的流过MN1的电流并作为下拉电流，通过所述下拉电流将所述C拉低，使所述读支路的所述MP4导通；
所述MP3在所述vpp_en为低时仍然导通，由所述MP3和所述MP4形成读操作的开关管支路将所述psd_int输出到所述vdd_otp，为所述控制装置在工作阶段提供的读电源。
在本发明实施例一实施方式中，就R2和MP0的接法而言，如果内部电源psd_int为高而SW为地电位，此时MP3和MP4管打开，Vva＝VA＝vdd_otp-VT＝psd_int-VT，这里VT是MP2的体二极管的导通压差，Vva会使MP0弱导通，如果有电流流过R2和MP0，则经过R2的压降，MP0的导通程度进一步的缩小，直至关掉。而且MP0的衬底接vdd_otp增大MP0的衬底偏置效应，增大MP0的阈值电压使得此时MP0更难导通，使电路在此时不会出现通过MP0的漏电流。
以一个现实应用场景为例对本发明实施例阐述如下：
本应用场景涉及电可擦除存储器范畴的芯片及类似的数模混合芯片中在电源管理方面的控制技术，对例如EPROM或EEPROM等模块在进行读写操作时需要采用不同电压电源的供电问题进行解决。
由于电可擦除存储器单元通常多作为IP核，集成到集成电路芯片内部，其电源总线通过芯片PIN接到外部来提供电可擦除存储器单元的读写电源。这种方法在ASIC设计中由于芯片PIN较多可以提供单独的电源PIN，而在电源管理等数模混合芯片中，为了减少芯片PIN的数量，通常将电可擦除存储器单元的读电源选择为芯片的工作电源，其写电源通常采用复用引脚或称为管脚(PIN)输入，这样可以减少所需的专用PAD来引入读写电源，增加芯片一个PAD，在芯片的banding、封装等环节会增加芯片的成本，使芯片的竞争力下降。这里需要指出的是，PIN是从集成电路(芯片)内部电路引出与外围电路的接线，所有的引脚就构成了这块芯片的接口功能，PIN芯片封装好后的管脚，是用户看到的管脚；而PAD是硅片的管脚，是封装在芯片内部的，用户看不到的管脚。
如此一来，综合考虑，为了满足电可擦除存储器单元读写电源的要求，即：需要对实现读操作或写操作时提供不同的电源，还要避免增加芯片成本，本应用场景采用本发明实施例，是用于解决可擦除存储器高压读写电源设计的方案，可以根据控制信号来切换输出电压为内部电源(5v)或是外部复用PIN角输入的高压电源。
本应用场景中，为了实现满足上述电可擦除存储器单元读写电源的要求的电源设计方案，从这几个方面进行考虑：1)可擦除存储器单元，其内部有读操作的低电压和写操作的高电压，为了实现读写电源的分时输出，电路需要采用两路开关来分时输出读电源或是写电源，而为了避免两个电源间的漏电和干扰，需要考虑每路电源开关的实现方式；2)写电源为高压 电源，而在现在的工艺下高压器件的耐压端在D和S端，而VGS的耐压通常为工艺的常规电压，这就需要方案提供相对的电源轨，产生相对的“地电位”来控制读写支路的开启与关断；3)可擦除存储器单元，其在写操作时需要高电压输出；在读操作时需要低电压输出，这就需要方案提供控制逻辑的控制机理，控制电路在读写状态分别输出不同的操作电压到可擦除存储器单元的电源总线。
图1为应用本发明实施例一应用场景的装置实例的结构示意图，结合图1所述，基于上述三个方面的考虑，本发明的具体实现方案包括如下内容：
一、为了避免两个电源间的漏电和干扰，对于读支路和写支路来说，每路电源开关的实现采用了背靠背的开关管支路。MP1和MP2形成写操作的开关管支路，而MP3和MP4形成读操作的开关管支路。这样两路背靠背实现的开关可以避免两个电源之间的漏电。这里，读支路和写支路通过图1中的d-d粗点划线来划分，整个芯片中位于d-d粗点划线以左的部分为写支路，整个芯片中位于d-d粗点划线以右的部分为读支路。
二、本方案的电源轨提供电路采用了VWRITE-I*R的方法得到高压写电源的相对“地电位”，从而安全的控制高压写支路的关断和开启。图1中，R1、MN2、MN4提供写操作的控制，其产生了写高压电源的电源轨。具体产生方法是：
当芯片执行写操作前会提前给出写电源使能信号vpp_en，vpp_en将MN4管打开，电流I1经R1、MN4和MN2到地。这样va点的电压为Vva＝VA-I1*R1，设置I1*R1＝5V，SW的电压为可擦除存储器高压写电压7V，这样va点即得到一个比A点低5V的“相对地“电位。这样，写电压SW和“相对地“的绝对5V压差可以安全的打开MP1和MP2管将写电源SW输出给可擦除存储器的电源vdd_otp。
本发明实施例一实施方式中，写电源使能信号也需要关断读支路，具体操作是vpp_en为高关掉MP3管，而此时vpp_enb＝vref_okb＝0，关掉MN5和MN6，同时Vva的“相对地“电位使得MP0管导通使得Vc＝vdd_otp＝SW关掉MP0管，因而此时的Vc为高压写电源，需要MN5和MN6采用高压管实现。
MN3、MN5、MN6在读操作是打开Mp4的。如果在芯片POR阶段需要读寄存器，由于基准没有建立，没有电流产生，vref_ok＝0，vref_okb为高电位将MN5打开将C点拉低使读支路的开关管MP4导通，同时vpp_en为低将MP3管打开将内部电源psd_int输出到vdd_otp，为可擦除存储器单元在芯片的POR阶段提供读电源。
如果在芯片工作阶段需要读寄存器，此时，芯片里面基准已经建立给出vref_ok为高的信号，此时MN5关断，MN6打开，同时MN3镜像来自基准的流过MN1的电流，此下拉电流将C点拉低使读支路的开关管MP4导通，MP3管由于vpp_en为低仍然导通，MP3和MP4组成的读开关支路将内部电源psd_int输出到vdd_otp，为可擦除存储器单元在芯片工作阶段提供读电源。
这里电阻R2和MP0的接法主要考虑如下情形，如果内部电源psd_int为高而SW为地电位，此时MP3和MP4管打开，Vva＝VA＝vdd_otp-VT＝psd_int-VT，这里VT是MP2的体二极管的导通压差，Vva会使MP0弱导通，如果有电流流过R2和MP0，则经过R2的压降，MP0的导通程度进一步的缩小，直至关掉。而且MP0的衬底接vdd_otp增大MP0的衬底偏置效应，增大MP0的阈值电压使得此时MP0更难导通，使电路在此时不会出现通过MP0的漏电流。
本应用场景采用本发明实施例，具备以下优势：
1、本应用场景采用本发明实施例所实现的电路结构简单，芯片面积小， 所用器件均采用PDK的basic层，不会增加多余的mask层减小芯片的整体成本。
2、本应用场景采用本发明实施例所采取的电源切换控制逻辑简单，控制机理清晰，可以安全可靠的控制读写电源的切换。
3、本应用场景采用本发明实施例，在POR阶段依靠MN5下拉C点可以实现此时的零功耗，可以集成到对芯片standby功耗要求苛刻的电源管理，开关充电及类似的数模混合芯片中。
4、本应用场景采用本发明实施例所提出的电源轨实现方式简单可靠，可以方便的控制高压支路的关断和开启操作，使器件工作在安全可靠的电压范围内。
5、本应用场景采用本发明实施例提出的背靠背的实现方案可以实现在不同的读、写电压下两个电源的相对独立不会出现电流倒灌等现象。
6、本应用场景采用本发明实施例，对R2和MP0的巧妙接法可以避免在psd_int为高，SW为地的情形下通过MP0的漏电。
本发明实施例所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
相应的，本发明实施例还提供一种计算机存储介质，其中存储有计算 机程序，该计算机程序用于执行本发明实施例的实现高压读写电源的控制方法。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
采用本发明实施例，将写支路配置为在写操作时，根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线vdd_otp，以作为所述控制装置输出的写操作高压电源；将读支路配置为在读操作时，根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，且连通到所述vdd_otp，以作为所述控制装置输出的读操作低压电源。通过写支路和读支路分别实现输出高电压和低电压，从而能在一个可擦除存储器的芯片上实现读操作或写操作时提供不同的电源。

Claims (16)

  1. 一种实现高压读写电源的控制装置，所述装置包括：
    写支路，配置为在写操作时，根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线vdd_otp，以作为所述控制装置输出的写操作高压电源；
    读支路，配置为在读操作时，根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，且连通到所述vdd_otp，以作为所述控制装置输出的读操作低压电源。
  2. 根据权利要求1所述的装置，其中，所述写支路与所述读支路采用背靠背模式的结构；
    所述写支路与所述读支路以分时输出方式，分时输出所述写操作高压电源或读操作低压电源。
  3. 根据权利要求2所述的装置，其中，所述写支路包括：第一PMOS管MP1和第二PMOS管MP2；
    由所述MP1和所述MP2形成写操作的开关管支路。
  4. 根据权利要求3所述的装置，其中，所述写支路还包括：第一负载R1，第二NMOS管MN2、第四NMOS管MN4；
    所述R1通过第一连接点A与所述MP1相连，所述A通过所述MP2与所述电源总线vdd_otp相连；
    所述R1通过第二连接点va与所述MN4相连，所述MN4与所述MN2相连；
    由所述R1、所述MN2、所述MN4提供的写操作控制，形成写操作高压电源的电源轨。
  5. 根据权利要求4所述的装置，其中，所述装置还包括：第一NMOS管MN1、第三NMOS管MN3；
    所述MN1与所述MN2相连；
    在所述MN4作用有写电源使能信号vpp_en的情况下，在所述A与所述va之间形成相对的安全VGS电压，使得在所述va得到的电压值Vva比在所述A得到的电压值VA要低，且在工艺规定的安全范围内，在所述A得到的电压值VA与写电压SW相同；
    通过所述相对的安全VGS电压来控制所述写支路中所述MP1和所述MP2的导通和关断，以控制写支路的开启与关断。
  6. 根据权利要求2所述的装置，其中，所述读支路包括：第三PMOS管MP3和第四PMOS管MP4；
    由所述MP3和所述MP4形成读操作的开关管支路。
  7. 根据权利要求6所述的装置，其中，所述读支路还包括：第二负载R2，第五NMOS管MN5、第六NMOS管MN6、第零PMOS管MP0；
    所述MP4通过第三连接点C与所述MP0相连；
    所述MP4与所述R2相连，所述R2还与所述MP0相连；
    所述MN6通过所述C与所述MP0相连。
  8. 一种实现高压读写电源的控制方法，所述方法包括：
    写支路上，在写操作时根据侦测的控制信号切换输出电压为外部复用管脚PIN输入的符合第一预设条件的高电压，且连通到所述控制装置中的电源总线以作为所述控制装置输出的写操作高压电源；
    读支路上，在读操作时根据侦测的控制信号切换输出电压为符合第二预设条件的内部常规电压，且连通到所述控制装置中的电源总线以作为所述控制装置输出的读操作低压电源。
  9. 根据权利要求8所述的方法，其中，所述写支路与所述读支路采用背靠背模式的结构；
    所述写支路与所述读支路以分时输出方式，分时输出所述写操作高压 电源或读操作低压电源。
  10. 根据权利要求9所述的方法，其中，所述方法还包括：
    执行所述写操作前提前给出写电源使能信号vpp_en，通过所述vpp_en开启所述写支路。
  11. 根据权利要求10所述的方法，其中，所述通过所述vpp_en开启所述写支路，包括：
    通过所述vpp_en将第四NMOS管MN4管打开，电流I1经第一负载R1、所述MN4和第二NMOS管MN2到地，使得在第一连接点A与第二连接点va之间形成相对的安全VGS电压；
    所述va得到的电压值Vva比在所述A得到的电压值VA要低，且在工艺规定的安全范围内，在所述A得到的电压值VA与写电压SW相同；
    通过所述相对的安全VGS电压打开第一PMOS管MP1和第二PMOS管MP2，以将所述SW输出给所述控制装置中的电源总线vdd_otp。
  12. 根据权利要求11所述的方法，其中，所述方法还包括：通过所述vpp_en关断所述读支路。
  13. 根据权利要求12所述的方法，其中，所述通过所述vpp_en关断所述读支路，包括：
    设置vpp_en为高以关掉MP3管，此时vpp_enb＝vref_okb＝0，关掉第五NMOS管MN5和第六NMOS管MN6；
    采用所述相对的安全VGS电压导通第零PMOS管MP0，此时Vc＝vdd_otp＝SW，关掉所述MP0；
    所述MN5和所述MN6采用高压管实现。
  14. 根据权利要求13所述的方法，其中，所述方法还包括：
    第三NMOS管MN3、所述MN5、所述MN6在所述读操作时，需要打开第四PMOS管MP4；
    检测到在POR阶段需要读寄存器时，此时基准没有建立，没有电流产生，vref_ok＝0；
    vref_okb为高电位将所述MN5打开，将第三连接点C点拉低，使读支路的所述MP4导通，同时vpp_en为低，将第三PMOS管MP3打开，将所述控制装置的内部电源psd_int输出到所述vdd_otp，为所述控制装置在POR阶段提供的读电源。
  15. 根据权利要求14所述的方法，其中，所述方法还包括：
    检测到在工作阶段需要读寄存器，此时基准已经建立，给出vref_ok为高的信号，此时所述MN5关断，所述MN6打开；
    所述MN3接收来自基准的流过MN1的电流并作为下拉电流，通过所述下拉电流将所述C拉低，使所述读支路的所述MP4导通；
    所述MP3在所述vpp_en为低时仍然导通，由所述MP3和所述MP4形成读操作的开关管支路将所述psd_int输出到所述vdd_otp，为所述控制装置在工作阶段提供的读电源。
  16. 根据权利要求15所述的方法，其中，所述方法还包括：所述MP0与第二负载R2相连，所述MP4与所述R2相连，所述MP4还通过所述C与所述MP0相连；
    针对所述MP0与所述R2相连的接法，包括：
    如果内部电源psd_int为高而SW为地电位，此时MP3和MP4管打开，Vva＝VA＝vdd_otp-VT＝psd_int-VT，其中，所述VT为所述MP2的体二极管的导通压差，Vva会使MP0弱导通；
    如果有电流流过所述R2和所述MP0，则经过R2的压降，MP0的导通程度进一步的缩小，直至关掉，而且MP0的衬底接vdd_otp增大MP0的衬底偏置效应，增大MP0的阈值电压使得此时MP0更难导通，使电路在此时不会出现通过MP0的漏电流。
PCT/CN2016/080179 2015-06-12 2016-04-25 一种实现高压读写电源的控制装置及方法 Ceased WO2016197724A1 (zh)

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