WO2016194651A1 - Amplifier, control method therefor, and electronic equipment - Google Patents

Amplifier, control method therefor, and electronic equipment Download PDF

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Publication number
WO2016194651A1
WO2016194651A1 PCT/JP2016/065021 JP2016065021W WO2016194651A1 WO 2016194651 A1 WO2016194651 A1 WO 2016194651A1 JP 2016065021 W JP2016065021 W JP 2016065021W WO 2016194651 A1 WO2016194651 A1 WO 2016194651A1
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pwm signal
output
peak value
amplifier
input
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PCT/JP2016/065021
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French (fr)
Japanese (ja)
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一樹 芥川
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2016194651A1 publication Critical patent/WO2016194651A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers

Definitions

  • the present technology relates to an amplifier, a control method thereof, and an electronic device, and more particularly, to an amplifier and a control method thereof, and an electronic device that can adjust a peak value of a PWM signal in a feedback type D amplifier.
  • a class D amplifier that outputs a PWM signal, which is a pulse width modulated signal, and amplifies power is known (for example, see Patent Document 1).
  • Class D amplifiers are classified into a feedback type and a non-feedback type. Since the feedback type corrects an error in the output signal, distortion can be easily reduced and desired output signal characteristics can be obtained.
  • Class D amplifiers are used for power amplification of audio signals.
  • the noise level depending on the operating frequency, modulation method, etc. of the preceding digital circuit can be reduced. For example, in the silent state, the noise level can be reduced. Can be reduced.
  • the present technology has been made in view of such a situation, and makes it possible to adjust a peak value of a PWM signal in a feedback class D amplifier.
  • the amplifier according to the first aspect of the present technology includes a PWM signal output unit having a variable mechanism that varies a peak value of an output PWM signal that is a PWM signal output to the outside of the device, and an input that is a PWM signal input from the outside of the device.
  • a PWM signal input unit having a variable mechanism that varies the peak value of the PWM signal, and the PWM signal input unit causes the peak value of the input PWM signal to follow the change of the peak value of the output PWM signal.
  • the control method of the amplifier according to the first aspect of the present technology includes a PWM signal output unit having a variable mechanism that varies a peak value of an output PWM signal that is a PWM signal output to the outside of the device, and a PWM signal input from outside the device.
  • the PWM signal output unit of the amplifier including a PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal, and the PWM signal input unit changes the peak value of the output PWM signal, The peak value of the input PWM signal is made to follow the change of the peak value of the output PWM signal.
  • the electronic device includes a PWM signal output unit having a variable mechanism that varies a peak value of an output PWM signal that is a PWM signal output to the outside of the device, and a PWM signal input from outside the device.
  • the peak value of the output PWM signal is changed, and the peak value of the input PWM signal is caused to follow the change of the peak value of the output PWM signal.
  • the amplifier according to the second aspect of the present technology outputs, as an output PWM signal, a PWM signal obtained by power-amplifying an input PWM signal that is a PWM signal input from outside the device, and the area of the output PWM signal is before and after noise mixing. Control to have the same area.
  • a PWM signal obtained by power amplification of an input PWM signal that is a PWM signal input from outside the apparatus is output as an output PWM signal, and the area of the output PWM signal is the same before and after noise mixing. It is controlled to be an area of.
  • the amplifier may be an independent device or an internal block constituting one device.
  • the peak value of the PWM signal can be adjusted in the feedback class D amplifier.
  • FIG. 1 is a block diagram illustrating a configuration example of a class D amplifier to which the present technology is applied.
  • the class D amplifier 1 shown in FIG. 1 includes a peak value variable input unit 11, an integrator 12, a hysteresis comparator 13, a gate driver 14, a peak value variable output unit 15, and a feedback circuit 16.
  • the PWM signal that is a pulse width modulated signal is input to the class D amplifier 1.
  • the class D amplifier 1 amplifies the power of the input PWM signal and outputs the resulting PWM signal.
  • the PWM signal input to the class D amplifier 1 is also referred to as an input PWM signal
  • the PWM signal output from the class D amplifier 1 is also referred to as an output PWM signal.
  • the peak value variable input unit 11 has a variable mechanism that changes the peak value of the input PWM signal so as to follow the change of the peak value performed by the peak value variable output unit 15.
  • the peak value represents the signal level (amplitude) of the PWM signal.
  • the peak value variable input unit 11 outputs to the integrator 12 a PWM signal in which the peak value of the input PWM signal is changed so as to follow the change of the peak value performed by the peak value variable output unit 15.
  • the integrator 12 accumulates an error between the input PWM signal and the output PWM signal. More specifically, the integrator 12 integrates the error signal of the output of the peak value variable input unit 11 and the output of the feedback circuit 16 and outputs the integration result to the hysteresis comparator 13.
  • the hysteresis comparator (comparator) 13 compares the output of the integrator 12 with a predetermined reference value, and outputs a comparison result signal representing the comparison result.
  • the gate driver 14 drives the peak value variable output unit 15 using the comparison result signal supplied from the hysteresis comparator 13.
  • the peak value variable output unit 15 is a switch circuit driven by the gate driver 14, and outputs an output PWM signal obtained by power amplification of the input PWM signal input to the class D amplifier 1.
  • the peak value variable output unit 15 has a variable mechanism that varies (adjusts) the peak value of the output PWM signal.
  • the output PWM signal output from the peak value variable output unit 15 is output to the outside of the apparatus and also supplied to the feedback circuit 16.
  • the feedback circuit 16 feeds back (negative feedback) the output signal of the peak value variable output unit 15 to the input of the integrator 12.
  • the class D amplifier 1 is configured as described above.
  • the peak value variable input unit 11 includes an inverter 31 composed of a PMOS transistor and an NMOS transistor, a power supply circuit 32 that can variably supply a positive power supply voltage to the inverter 31, and a negative power supply voltage variable to the inverter 31. And a variable resistor 34.
  • the power supply circuit 32 supplies a positive power supply voltage REF # 3 that is a predetermined voltage value within the variable range to the inverter 31, and the power supply circuit 33 is a negative power supply voltage REF # that is a predetermined voltage value within the variable range. 4 is supplied to the inverter 31.
  • output voltage variable voltage regulators Low / Dropout regulators
  • the integrator 12 is composed of an operational amplifier 35 and a capacitor 36, and the output terminal of the operational amplifier 35 is connected to its inverting input terminal via the capacitor 36 to form a negative feedback circuit.
  • the hysteresis comparator 13 compares the output of the integrator 12 with the reference voltage REF # 6 and outputs a comparison result signal representing the comparison result.
  • the gate driver 14 is composed of an even number of inverters 37.
  • the peak value variable output unit 15 includes an inverter 41 composed of a PMOS transistor and an NMOS transistor, a power supply circuit 42 that can variably supply a positive power supply voltage to the inverter 41, and a negative power supply voltage to the inverter 31.
  • the power supply circuit 43 can variably supply the power.
  • the power supply circuit 42 supplies a positive power supply voltage REF # 1 that is a predetermined voltage value within the variable range to the inverter 41
  • the power supply circuit 43 is a negative power supply voltage REF # that is a predetermined voltage value within the variable range. 2 is supplied to the inverter 41.
  • the power supply circuits 42 and 43 can also use a voltage regulator (Low Dropout regulator) whose output voltage is variable.
  • the set values of the positive side power supply voltage REF # 1 and the negative side power supply voltage REF # 2 are set, for example, from the device in which the class D amplifier 1 is incorporated (for example, the audio player 70 in FIG. 6). It is determined and controlled according to the set value.
  • the feedback circuit 16 includes a variable resistor 45, converts the output PWM signal output from the peak value variable output unit 15 into a current, and supplies the current to the inverting input terminal of the operational amplifier 35 of the integrator 12.
  • An LC filter (low-pass filter) 21 composed of a coil 51 and a capacitor 52 is disposed at the subsequent stage that is the output destination of the output PWM signal of the class D amplifier 1.
  • a load 22 such as is further connected.
  • the inverter 31 changes the peak value with respect to the input PWM signal by adjusting the power supply voltage supplied to the inverter 31 by the positive power supply circuit 32 and the negative power supply circuit 33. Outputs the inverted signal of the input PWM signal.
  • the power supply circuit 32 of the peak value variable input unit 11 adjusts the positive power supply voltage REF # 3 so as to follow the positive power supply voltage REF # 1 supplied by the power supply circuit 42 of the peak value variable output unit 15. And supplied to the inverter 31.
  • the power circuit 33 of the peak value variable input unit 11 adjusts the negative power supply voltage REF # 4 so as to follow the negative power supply voltage REF # 2 supplied by the power circuit 43 of the peak value variable output unit 15. To the inverter 31.
  • the peak value variable input unit 11 is a signal having the same peak value as the output PWM signal output from the peak value variable output unit 15, and outputs an inverted PWM signal obtained by inverting the input PWM signal.
  • FIG. 3 shows an input PWM signal input to the inverter 31 and an inverted PWM signal (an inverted signal of the input PWM signal) that is the output of the inverter 31. However, in FIG. 3, the peak values of the input PWM signal and the inverted PWM signal are not changed.
  • variable resistor 34 converts the inverted PWM signal into a current and outputs it to the inverting input terminal of the operational amplifier 35 of the integrator 12.
  • a signal obtained by converting the output PWM signal output from the peak value variable output unit 15 into a current is input from the variable resistor 45 of the feedback circuit 16 to the inverting input terminal of the operational amplifier 35 of the integrator 12.
  • the output PWM signal that is the output of the peak value variable output unit 15 and the inverted PWM signal that is the output of the inverter 31 of the peak value variable input unit 11 are the same as described above. It has been adjusted to be. Therefore, a signal corresponding to an error between the input PWM signal and the output PWM signal is input to the inverting input terminal of the operational amplifier 35.
  • the integrator 12 including the operational amplifier 35 and the capacitor 36 integrates and outputs the error between the input PWM signal and the output PWM signal input to the inverting input terminal of the operational amplifier 35.
  • the reference voltage REF # 5 input to the non-inverting input terminal of the operational amplifier 35 is a voltage that is an intermediate value between the positive power supply voltage REF # 1 and the negative power supply voltage REF # 2.
  • the hysteresis comparator 13 compares the output of the integrator 12 with the reference voltage REF # 6 and outputs the comparison result.
  • the hysteresis comparator 13 outputs a comparison result with a predetermined hysteresis width.
  • the gate driver 14 drives the inverter 41 of the peak value variable output unit 15 based on the comparison result signal supplied from the hysteresis comparator 13.
  • the positive-side power supply circuit 42 and the negative-side power supply circuit 43 of the peak value variable output unit 15 are supplied to the inverter 41 in accordance with, for example, the volume setting value of the audio player or the presence / absence of a silence state.
  • the voltage REF # 1 and the negative power supply voltage REF # 2 are changed.
  • the inverter 41 outputs a signal obtained by inverting the input from the gate driver 14. Thereby, the peak value variable output unit 15 generates an output PWM signal obtained by power amplification of the input PWM signal.
  • FIG. 3 shows an output example of the integrator 12, and the change point of the comparison result signal of the hysteresis comparator 13 is indicated by a circle ( ⁇ ) with respect to the output of the integrator 12.
  • the hysteresis comparator 13 creates a delay according to the error by changing the edge position of the comparison result signal according to the error between the input PWM signal and the output PWM signal.
  • the edge position of the comparison result signal output from the hysteresis comparator 13 changes, the pulse width of the output PWM signal changes.
  • the hysteresis comparator 13 generates an inverted PWM signal obtained by correcting the output PWM signal with the pulse width (time axis information) according to the error between the input PWM signal and the output PWM signal. Then, the inverted PWM signal after the correction is inverted and power amplified in the gate driver 14 and the peak value variable output unit 15 to be an output PWM signal.
  • the hysteresis comparator 13 has a pulse area of the input PWM signal (indicated by hatching in FIG. 4), as shown in FIG. A function of adjusting each pulse of the output PWM signal so that the corresponding pulse area of the output PWM signal becomes the same area.
  • the hysteresis comparator 13 has the same pulse area of the output PWM signal before and after the noise mixing.
  • it can also be said that it has a function of adjusting the pulse width of the output PWM signal.
  • the inflow current to the integrator 12 changes, so that the delay caused in the integrator 12, in other words, the slope of the output waveform of the integrator 12 in FIG. Changes.
  • the slope of the output waveform of the integrator 12 is determined by assuming that the output signal (voltage) of the inverter 31 of the peak value variable input unit 11 is Vin and the output signal (voltage) of the inverter 41 of the peak value variable output unit 15 is Vout.
  • C represents the capacitance value of the capacitor 36.
  • the allowable range of the delay generated in the integrator 12 is determined by the resolution of the PWM signal.
  • the delay generated in the integrator 12 exceeds the allowable range, the resistance value Rfb of the variable resistor 45 of the feedback circuit 16 and the wave
  • the resistance value Rin of the variable resistor 34 of the high-value variable input unit 11 the delay to the integrator 12 can be adjusted to be within an allowable range.
  • the resistance value Rfb of the variable resistor 45 and the resistance value Rin of the variable resistor 34 are changed according to the change of the crest value.
  • the resistance value switching stage number can be made smaller than the peak value switching stage number, for example, the resistance value switching stage can be changed in one stage with respect to the two-stage peak value change.
  • the resistance value switching stage number may be the same as the peak value switching stage number.
  • the delay caused by the integrator 12 may be adjusted not by adjusting the resistance values of the variable resistor 45 and the variable resistor 34 but by adjusting the capacitance value of the capacitor 36 of the integrator 12.
  • an LC filter 21 is disposed at the output destination of the class D amplifier 1 in order to remove high frequency components of the output PWM signal.
  • a current depending on the output PWM signal flows through the LC filter 21 and causes an error in the output waveform due to fluctuations in the power supply, the difference between the positive resistance value and the negative resistance value of the peak value variable output unit 15, and the like.
  • the distortion of the output PWM signal gets worse.
  • the resistance value Rin ( ⁇ k ⁇ ) of the variable resistor 34 can be made larger than the resistance value ( ⁇ ) of the load 22, and the peak value is variable at the output end.
  • the output unit 15 since there is no LC filter, power supply fluctuation is unlikely to occur, and the difference between the positive resistance value and the negative resistance value of the peak value variable input unit 11 appears as an offset instead of distortion. Since the output PWM signal is controlled to match the signal output from the peak value variable input section 11 having such characteristics, the class D amplifier 1 can obtain good distortion characteristics.
  • the predetermined value is supplied to the operational amplifier 35 of the integrator 12 by making the configuration of the peak value variable input unit 11 the same as that of the peak value variable output unit 15 and the feedback circuit 16.
  • the peak value variable input unit 11 is configured.
  • the peak value variable input unit 11 is changed to a current output type configuration. That is, since the peak value variable output unit 15 needs to drive the load 22, it needs to be a voltage output type output, and the output is subjected to voltage-current conversion by the variable resistor 45. However, since the output destination of the peak value variable input unit 11 does not require a voltage output type output, the peak value variable input unit 11 can be configured as a current output type.
  • the peak value variable input section 11 having the second circuit configuration includes an inverter 31, a constant current source circuit 60, and a current mirror circuit 61.
  • the constant current source circuit 60 supplies the inverter 31 and the current mirror circuit 61 with a current Iout determined by the positive power supply voltage REF # 3 output from the operational amplifier 62 and the resistance value Rin of the variable resistor 34.
  • the positive power supply voltage REF # 3 is adjusted so as to follow the positive power supply voltage REF # 1 as in the first circuit configuration.
  • the PMOS transistor of the inverter 31 When the input PWM signal is Low, the PMOS transistor of the inverter 31 is turned on, and the current Iout determined by the positive side power supply voltage REF # 3 output from the operational amplifier 62 and the resistance value Rin of the variable resistor 34 is integrated via the PMOS transistor. 12 operational amplifiers 35.
  • the current corresponding to the input PWM signal can be supplied to the operational amplifier 35 of the integrator 12 as in the first circuit configuration.
  • the power supply circuit 33 is unnecessary as compared with the first circuit configuration shown in FIG. 2, so that the power consumption of the peak value variable input unit 11 can be suppressed. it can. Therefore, the second circuit configuration is useful when the current consumption is limited.
  • the noise of the peak value variable input unit 11 is increased by using the current mirror circuit 61 as compared with the first circuit configuration. Therefore, there is a concern of deteriorating the noise characteristics of the output signal.
  • noise characteristics can be improved by inserting a resistor (source degeneration resistor) on the source side of the NMOS transistor of the current mirror circuit 61.
  • the peak value of the output PWM signal can be adjusted according to the class D amplifier 1, so that the noise component included in the input PWM signal Can be suppressed.
  • the class D amplifier 1 can adjust and output the peak value of the PWM signal to be output in accordance with the volume value set by the mounted electronic device (FIG. 6) or the like.
  • the positive-side power supply voltage REF # 1 and the negative-side power supply voltage REF # 2 of only the peak value variable output unit 15 are made variable.
  • the change in peak value is fed back to the input side, it is detected and corrected as an error between the input and output.
  • the peak value of the input PWM signal (inverted signal thereof) of the peak value variable input unit 11 is also changed by following the change of the peak value of the output PWM signal of the peak value variable output unit 15. Since the output PWM signal is controlled so as to match the signal output from the peak value variable input unit 11, an error can be suppressed and a low distortion output PWM signal can be output. Moreover, since the voltage drop which generate
  • the class D amplifier 1 can output a PWM signal with low noise, low distortion, and high output.
  • the error is suppressed by feeding back the output PWM signal to the input side and correcting the error between the input and output with the pulse width (the mechanism for reshaping the PWM signal). Can output low distortion output PWM signal.
  • the present technology is not limited to application to class D amplifiers.
  • the present technology is applicable to sound players such as an audio player that outputs sound based on an audio signal, a mobile terminal device such as a smartphone or a tablet that has a sound output function, a copier, a printer device, or an imaging device that has a sound output function.
  • the present invention can be applied to all electronic devices having an output function.
  • FIG. 6 is a block diagram illustrating a configuration example of an audio player as an electronic apparatus employing the present technology.
  • ⁇ modulation unit 76 includes an operation unit 71, a data storage unit 72, a communication unit 73, a control unit 74, a display unit 75, a delta-sigma ( ⁇ ) modulation unit 76, a PWM signal generation unit 77, a class D amplifier 78, A low-pass filter 79 and a speaker 80 are included.
  • the operation unit 71 accepts a user operation such as reproduction or stop of a predetermined music (music) stored in the data storage unit 72, and supplies an operation signal corresponding to the accepted operation to the control unit 74.
  • the data storage unit 72 is composed of, for example, a semiconductor memory, and stores data of a plurality of music pieces in a predetermined data format (for example, MP3 (MPEG (Moving Picture Experts Group) 1 Audio Layer 3)).
  • the data storage unit 72 also stores a program for the control unit 74 to control the operation of the audio player 70 as a whole.
  • the communication unit 73 is configured by, for example, a USB (Universal Serial Bus) interface or the like, and is connected to an external device under the control of the control unit 74 to transmit and receive audio data and the like.
  • the communication unit 73 may be configured with a local area network, the Internet, a network interface connected to another network, or the like, and may be connected to an external device via the network to exchange audio data.
  • the control unit 74 includes, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory), and the like, and controls the entire operation of the audio player 70.
  • the control unit 74 stores the audio data of the music instructed to be reproduced when the operation signal is supplied from the operation unit 71 to reproduce the predetermined music stored in the data storage unit 72 by the user. Obtained from the unit 72 and supplied to the delta-sigma modulation unit 76. Further, the control unit 74 controls an image displayed on the display unit 75.
  • a CPU Central Processing Unit
  • RAM Random Access Memory
  • the display unit 75 includes, for example, an LCD (Liquid Crystal Display) or an EL (Electro Luminescence) display, and is stored in the data storage unit 72 according to the control of the control unit 74 and the title and playback time of the music being played back. Displays the audio data etc.
  • LCD Liquid Crystal Display
  • EL Electro Luminescence
  • the delta-sigma modulation unit 76 performs delta-sigma modulation processing on the audio data supplied from the control unit 74, generates N-bit (N> 0) digital data that is delta-sigma modulated, and generates a PWM signal generation unit 77. Output to.
  • the PWM signal generation unit 77 converts the delta sigma modulated N-bit digital data supplied from the delta sigma modulation unit 76 into a PWM signal and outputs the PWM signal to the class D amplifier 78.
  • the class D amplifier 78 amplifies the power of the PWM signal supplied from the PWM signal generator 77 and outputs it.
  • the configuration of the class D amplifier 78 the configuration of the class D amplifier 1 of FIG. 1 is adopted.
  • the low-pass filter 79 performs a filtering process for removing high-frequency components on the PWM signal output from the class D amplifier 78, and outputs the filtered signal to the speaker 80.
  • the speaker 80 outputs sound based on the PWM signal supplied from the class D amplifier 78 via the low pass filter 79.
  • the low-pass filter 79 corresponds to the LC filter 21 in FIG. 2, and the speaker 80 corresponds to the load 22 in FIG.
  • the delta-sigma modulation unit 76, the PWM signal generation unit 77, and the class D amplifier 78 are all digital circuits, and by using the class D amplifier 78, an A / D converter that converts a digital signal into an analog signal is unnecessary. Therefore, the circuit scale can be reduced.
  • the configuration of the class D amplifier 1 of FIG. 1 described above is adopted as the class D amplifier 78, noise components included in the input PWM signal can be suppressed. At the same time, an error can be suppressed and a low distortion output PWM signal can be output to the speaker 80. Also, the maximum output power can be improved.
  • Embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.
  • the present technology can take a cloud computing configuration in which one function is shared by a plurality of devices via a network and is jointly processed.
  • this technique can also take the following structures.
  • a PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal, which is a PWM signal output to the outside of the device;
  • a PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the device, and
  • the PWM signal input unit causes the peak value of the input PWM signal to follow a change in the peak value of the output PWM signal.
  • a feedback circuit for feeding back the output PWM signal to a predetermined circuit; An integrator for accumulating an error between the output PWM signal fed back by the Fordback circuit and an output signal of the PWM signal input unit; A comparator that compares the output of the integrator with a predetermined reference value and outputs a comparison result signal representing the comparison result;
  • the amplifier according to (1) further comprising: a gate driver that drives the PWM signal output unit using the comparison result signal.
  • the comparator generates, as the comparison result signal, a signal obtained by converting error information between the output PWM signal and the output signal of the PWM signal input unit into time axis information by changing an edge position of the PWM signal.
  • the amplifier according to any one of (2) to (7).
  • the comparator generates and outputs a PWM signal obtained by correcting the output PWM signal according to an error between the output PWM signal and the output signal of the PWM signal input unit as the comparison result signal.
  • the amplifier according to any one of (8). (10) The amplifier according to (9), wherein the PWM signal obtained by correcting the output PWM signal is a signal adjusted so that a pulse area of the PWM signal is the same as that of the output signal of the PWM signal input unit.
  • a PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal that is a PWM signal that is output outside the apparatus, and a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the apparatus.
  • An amplifier having a PWM signal input unit having The PWM signal output unit changes the peak value of the output PWM signal, The method of controlling an amplifier, wherein the PWM signal input unit causes a peak value of the input PWM signal to follow a change in a peak value of the output PWM signal.
  • a PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal, which is a PWM signal output to the outside of the device;
  • a PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the device, and
  • the PWM signal input unit includes an amplifier that causes a peak value of the input PWM signal to follow a change in a peak value of the output PWM signal.

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Abstract

This technology relates to an amplifier which enables a peak value of a PWM signal to be adjusted in a feedback class-D amplifier, a control method therefor, and electronic equipment. An amplifier is provided with: a PWM signal output unit having a variable mechanism which varies the peak value of an output PWM signal that is a PWM signal to be outputted to the outside of a device; and a PWM signal input unit having a variable mechanism which varies the peak value of an input PWM signal that is a PWM signal inputted from the outside of the device. The PWM signal input unit causes the peak value of the input PWM signal to follow the change of the peak value of the output PWM signal. This technology is applicable, for example, to a class-D amplifier or the like.

Description

増幅器及びその制御方法、並びに電子機器Amplifier, control method therefor, and electronic apparatus
　本技術は、増幅器及びその制御方法、並びに電子機器に関し、特に、帰還型のD級増幅器において、PWM信号の波高値を調整することができるようにする増幅器及びその制御方法、並びに電子機器に関する。 The present technology relates to an amplifier, a control method thereof, and an electronic device, and more particularly, to an amplifier and a control method thereof, and an electronic device that can adjust a peak value of a PWM signal in a feedback type D amplifier.
　パルス幅変調された信号であるPWM信号を出力し、電力を増幅させるD級増幅器が知られている（例えば、特許文献１参照）。D級増幅器には、帰還型と無帰還型とがあり、帰還型は、出力信号の誤差を補正するため、歪を低減させやすく、所望の出力信号特性を得ることができる。D級増幅器は、オーディオ信号の電力増幅などに用いられている。 A class D amplifier that outputs a PWM signal, which is a pulse width modulated signal, and amplifies power is known (for example, see Patent Document 1). Class D amplifiers are classified into a feedback type and a non-feedback type. Since the feedback type corrects an error in the output signal, distortion can be easily reduced and desired output signal characteristics can be obtained. Class D amplifiers are used for power amplification of audio signals.
特開２０１１－６６５５９号公報JP 2011-66559 A
　ところで、出力するPWM信号の波高値を小さくすることができれば、前段のデジタル回路の動作周波数や変調方式などに依存するノイズレベルを小さくすることができるので、例えば、無音状態のときなどにおいて、ノイズを小さくすることができる。 By the way, if the peak value of the output PWM signal can be reduced, the noise level depending on the operating frequency, modulation method, etc. of the preceding digital circuit can be reduced. For example, in the silent state, the noise level can be reduced. Can be reduced.
　本技術は、このような状況に鑑みてなされたものであり、帰還型のD級増幅器において、PWM信号の波高値を調整することができるようにするものである。 The present technology has been made in view of such a situation, and makes it possible to adjust a peak value of a PWM signal in a feedback class D amplifier.
　本技術の第１の側面の増幅器は、装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部とを備え、前記PWM信号入力部は、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる。 The amplifier according to the first aspect of the present technology includes a PWM signal output unit having a variable mechanism that varies a peak value of an output PWM signal that is a PWM signal output to the outside of the device, and an input that is a PWM signal input from the outside of the device. A PWM signal input unit having a variable mechanism that varies the peak value of the PWM signal, and the PWM signal input unit causes the peak value of the input PWM signal to follow the change of the peak value of the output PWM signal.
　本技術の第１の側面の増幅器の制御方法は、装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部とを備える増幅器の、前記PWM信号出力部が、前記出力PWM信号の波高値を変更し、前記PWM信号入力部が、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる。 The control method of the amplifier according to the first aspect of the present technology includes a PWM signal output unit having a variable mechanism that varies a peak value of an output PWM signal that is a PWM signal output to the outside of the device, and a PWM signal input from outside the device. The PWM signal output unit of the amplifier including a PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal, and the PWM signal input unit changes the peak value of the output PWM signal, The peak value of the input PWM signal is made to follow the change of the peak value of the output PWM signal.
　本技術の第１の側面の電子機器は、装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部とを備え、前記PWM信号入力部は、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる増幅器を備える。 The electronic device according to the first aspect of the present technology includes a PWM signal output unit having a variable mechanism that varies a peak value of an output PWM signal that is a PWM signal output to the outside of the device, and a PWM signal input from outside the device. A PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal, and the PWM signal input unit causes the peak value of the input PWM signal to follow the change of the peak value of the output PWM signal. Is provided.
　本技術の第１の側面においては、出力PWM信号の波高値が変更され、入力PWM信号の波高値が、前記出力PWM信号の波高値の変化に追従させられる。 In the first aspect of the present technology, the peak value of the output PWM signal is changed, and the peak value of the input PWM signal is caused to follow the change of the peak value of the output PWM signal.
　本技術の第２の側面の増幅器は、装置外から入力されたPWM信号である入力PWM信号を電力増幅したPWM信号を出力PWM信号として出力し、前記出力PWM信号の面積がノイズ混入の前後で同一の面積となるように制御する。 The amplifier according to the second aspect of the present technology outputs, as an output PWM signal, a PWM signal obtained by power-amplifying an input PWM signal that is a PWM signal input from outside the device, and the area of the output PWM signal is before and after noise mixing. Control to have the same area.
　本技術の第２の側面においては、装置外から入力されたPWM信号である入力PWM信号を電力増幅したPWM信号が出力PWM信号として出力され、前記出力PWM信号の面積がノイズ混入の前後で同一の面積となるように制御される。 In the second aspect of the present technology, a PWM signal obtained by power amplification of an input PWM signal that is a PWM signal input from outside the apparatus is output as an output PWM signal, and the area of the output PWM signal is the same before and after noise mixing. It is controlled to be an area of.
　増幅器は、独立した装置であっても良いし、１つの装置を構成している内部ブロックであっても良い。 The amplifier may be an independent device or an internal block constituting one device.
　本技術の第１及び第２の側面によれば、帰還型のD級増幅器において、PWM信号の波高値を調整することができる。 According to the first and second aspects of the present technology, the peak value of the PWM signal can be adjusted in the feedback class D amplifier.
　なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。 It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
本技術を適用したD級増幅器の構成例を示すブロック図である。It is a block diagram which shows the structural example of the class D amplifier to which this technique is applied. D級増幅器の第１の回路構成例を示す図である。It is a figure which shows the 1st circuit structural example of a class-D amplifier. D級増幅器の動作について説明する図である。It is a figure explaining operation | movement of a class D amplifier. D級増幅器の動作について説明する図である。It is a figure explaining operation | movement of a class D amplifier. D級増幅器の第２の回路構成例を示す図である。It is a figure which shows the 2nd circuit structural example of a class D amplifier. 本技術を適用した電子機器としてのオーディオプレーヤの構成例を示すブロック図である。It is a block diagram which shows the structural example of the audio player as an electronic device to which this technique is applied.
　以下、本技術を実施するための形態（以下、実施の形態という）について説明する。なお、説明は以下の順序で行う。
１．D級増幅器の概略構成例
２．D級増幅器の第１の回路構成例
３．D級増幅器の第２の回路構成例
４．電子機器への適用例 Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. Schematic configuration example of class D amplifier 2. First circuit configuration example of class D amplifier Second circuit configuration example of class D amplifier Application example to electronic equipment
＜１．D級増幅器の概略構成例＞
　図１は、本技術を適用したD級増幅器の構成例を示すブロック図である。 <1. Schematic configuration example of class D amplifier>
FIG. 1 is a block diagram illustrating a configuration example of a class D amplifier to which the present technology is applied.
　図１に示されるD級増幅器１は、波高値可変入力部１１、積分器１２、ヒステリシスコンパレータ１３、ゲートドライバ１４、波高値可変出力部１５、及び、フィードバック回路１６で構成される。 The class D amplifier 1 shown in FIG. 1 includes a peak value variable input unit 11, an integrator 12, a hysteresis comparator 13, a gate driver 14, a peak value variable output unit 15, and a feedback circuit 16.
　D級増幅器１には、パルス幅変調された信号であるPWM信号が入力される。D級増幅器１は、入力されたPWM信号を電力増幅して、その結果得られたPWM信号を出力する。以下では、D級増幅器１に入力されたPWM信号を入力PWM信号、D級増幅器１から出力されるPWM信号を出力PWM信号とも称する。 The PWM signal that is a pulse width modulated signal is input to the class D amplifier 1. The class D amplifier 1 amplifies the power of the input PWM signal and outputs the resulting PWM signal. Hereinafter, the PWM signal input to the class D amplifier 1 is also referred to as an input PWM signal, and the PWM signal output from the class D amplifier 1 is also referred to as an output PWM signal.
　波高値可変入力部１１は、入力PWM信号を、波高値可変出力部１５が行う波高値の変化に追従するように波高値を変化させる可変機構を有している。ここで、波高値とは、PWM信号の信号レベル（振幅）を表す。波高値可変入力部１１は、入力PWM信号の波高値を、波高値可変出力部１５が行う波高値の変化に追従するように変化させたPWM信号を積分器１２に出力する。 The peak value variable input unit 11 has a variable mechanism that changes the peak value of the input PWM signal so as to follow the change of the peak value performed by the peak value variable output unit 15. Here, the peak value represents the signal level (amplitude) of the PWM signal. The peak value variable input unit 11 outputs to the integrator 12 a PWM signal in which the peak value of the input PWM signal is changed so as to follow the change of the peak value performed by the peak value variable output unit 15.
　積分器１２は、入力PWM信号と出力PWM信号の誤差を蓄積する。より具体的には、積分器１２は、波高値可変入力部１１の出力と、フィードバック回路１６の出力の誤差信号を積分し、積分結果をヒステリシスコンパレータ１３に出力する。 The integrator 12 accumulates an error between the input PWM signal and the output PWM signal. More specifically, the integrator 12 integrates the error signal of the output of the peak value variable input unit 11 and the output of the feedback circuit 16 and outputs the integration result to the hysteresis comparator 13.
　ヒステリシスコンパレータ（比較器）１３は、積分器１２の出力を、所定の基準値と比較し、その比較結果を表す比較結果信号を出力する。 The hysteresis comparator (comparator) 13 compares the output of the integrator 12 with a predetermined reference value, and outputs a comparison result signal representing the comparison result.
　ゲートドライバ１４は、ヒステリシスコンパレータ１３から供給される比較結果信号を用いて、波高値可変出力部１５を駆動する。 The gate driver 14 drives the peak value variable output unit 15 using the comparison result signal supplied from the hysteresis comparator 13.
　波高値可変出力部１５は、ゲートドライバ１４によって駆動されるスイッチ回路であり、D級増幅器１に入力された入力PWM信号を電力増幅した出力PWM信号を出力する。波高値可変出力部１５は、出力PWM信号の波高値を可変（調整）する可変機構を有している。 The peak value variable output unit 15 is a switch circuit driven by the gate driver 14, and outputs an output PWM signal obtained by power amplification of the input PWM signal input to the class D amplifier 1. The peak value variable output unit 15 has a variable mechanism that varies (adjusts) the peak value of the output PWM signal.
　波高値可変出力部１５から出力された出力PWM信号は、装置外へ出力されるとともに、フィードバック回路１６へも供給される。 The output PWM signal output from the peak value variable output unit 15 is output to the outside of the apparatus and also supplied to the feedback circuit 16.
　フィードバック回路１６は、波高値可変出力部１５の出力信号を積分器１２の入力へとフィードバック（負帰還）させる。 The feedback circuit 16 feeds back (negative feedback) the output signal of the peak value variable output unit 15 to the input of the integrator 12.
　D級増幅器１は、以上のように構成されている。 The class D amplifier 1 is configured as described above.
＜２．D級増幅器の第１の回路構成例＞
　図２を参照して、D級増幅器１の詳細な構成例であって、第１の回路構成例について説明する。 <2. First Circuit Configuration Example of Class D Amplifier>
With reference to FIG. 2, a detailed configuration example of the class D amplifier 1 and a first circuit configuration example will be described.
　波高値可変入力部１１は、PMOSトランジスタとNMOSトランジスタで構成されるインバータ３１、インバータ３１に正側の電源電圧を可変に供給することができる電源回路３２、インバータ３１に負側の電源電圧を可変に供給することができる電源回路３３、及び、可変抵抗３４で構成される。電源回路３２は、可変範囲内の所定の電圧値である正側電源電圧REF#3をインバータ３１に供給し、電源回路３３は、可変範囲内の所定の電圧値である負側電源電圧REF#4をインバータ３１に供給する。電源回路３２及び３３としては、出力電圧可変の電圧レギュレータ（Low Dropoutレギュレータ）を用いることができる。 The peak value variable input unit 11 includes an inverter 31 composed of a PMOS transistor and an NMOS transistor, a power supply circuit 32 that can variably supply a positive power supply voltage to the inverter 31, and a negative power supply voltage variable to the inverter 31. And a variable resistor 34. The power supply circuit 32 supplies a positive power supply voltage REF # 3 that is a predetermined voltage value within the variable range to the inverter 31, and the power supply circuit 33 is a negative power supply voltage REF # that is a predetermined voltage value within the variable range. 4 is supplied to the inverter 31. As the power supply circuits 32 and 33, output voltage variable voltage regulators (Low / Dropout regulators) can be used.
　積分器１２は、オペアンプ３５とキャパシタ３６で構成され、オペアンプ３５の出力端子は、キャパシタ３６を介して、自身の反転入力端子に接続され、負帰還回路を形成している。 The integrator 12 is composed of an operational amplifier 35 and a capacitor 36, and the output terminal of the operational amplifier 35 is connected to its inverting input terminal via the capacitor 36 to form a negative feedback circuit.
　ヒステリシスコンパレータ１３は、積分器１２の出力を基準電圧REF#6と比較し、その比較結果を表す比較結果信号を出力する。 The hysteresis comparator 13 compares the output of the integrator 12 with the reference voltage REF # 6 and outputs a comparison result signal representing the comparison result.
　ゲートドライバ１４は、偶数個のインバータ３７で構成される。 The gate driver 14 is composed of an even number of inverters 37.
　波高値可変出力部１５は、PMOSトランジスタとNMOSトランジスタで構成されるインバータ４１、インバータ４１に正側の電源電圧を可変に供給することができる電源回路４２、及び、インバータ３１に負側の電源電圧を可変に供給することができる電源回路４３で構成される。電源回路４２は、可変範囲内の所定の電圧値である正側電源電圧REF#1をインバータ４１に供給し、電源回路４３は、可変範囲内の所定の電圧値である負側電源電圧REF#2をインバータ４１に供給する。電源回路４２及び４３も、電源回路３２及び３３と同様に、出力電圧可変の電圧レギュレータ（Low Dropoutレギュレータ）を用いることができる。正側電源電圧REF#1及び負側電源電圧REF#2の設定値は、例えば、D級増幅器１が組み込まれている装置（例えば、図６のオーディオプレーヤ７０）から、無音状態の有無やボリューム設定値などに応じて決定、制御される。 The peak value variable output unit 15 includes an inverter 41 composed of a PMOS transistor and an NMOS transistor, a power supply circuit 42 that can variably supply a positive power supply voltage to the inverter 41, and a negative power supply voltage to the inverter 31. The power supply circuit 43 can variably supply the power. The power supply circuit 42 supplies a positive power supply voltage REF # 1 that is a predetermined voltage value within the variable range to the inverter 41, and the power supply circuit 43 is a negative power supply voltage REF # that is a predetermined voltage value within the variable range. 2 is supplied to the inverter 41. Similarly to the power supply circuits 32 and 33, the power supply circuits 42 and 43 can also use a voltage regulator (Low Dropout regulator) whose output voltage is variable. The set values of the positive side power supply voltage REF # 1 and the negative side power supply voltage REF # 2 are set, for example, from the device in which the class D amplifier 1 is incorporated (for example, the audio player 70 in FIG. 6). It is determined and controlled according to the set value.
　フィードバック回路１６は、可変抵抗４５で構成され、波高値可変出力部１５から出力された出力PWM信号を電流に変換して、積分器１２のオペアンプ３５の反転入力端子に供給する。 The feedback circuit 16 includes a variable resistor 45, converts the output PWM signal output from the peak value variable output unit 15 into a current, and supplies the current to the inverting input terminal of the operational amplifier 35 of the integrator 12.
　D級増幅器１の出力PWM信号の出力先となる後段には、コイル５１とキャパシタ５２で構成されるLCフィルタ（ローパスフィルタ）２１が配置されており、そのLCフィルタ２１の先には、例えばスピーカなどの負荷２２がさらに接続されている。 An LC filter (low-pass filter) 21 composed of a coil 51 and a capacitor 52 is disposed at the subsequent stage that is the output destination of the output PWM signal of the class D amplifier 1. A load 22 such as is further connected.
　図３を参照して、D級増幅器１の動作について説明する。 The operation of the class D amplifier 1 will be described with reference to FIG.
　波高値可変入力部１１では、正側の電源回路３２及び負側の電源回路３３がインバータ３１に供給する電源電圧を調整することにより、インバータ３１は、入力PWM信号に対して波高値を変更した入力PWM信号の反転信号を出力する。 In the peak value variable input unit 11, the inverter 31 changes the peak value with respect to the input PWM signal by adjusting the power supply voltage supplied to the inverter 31 by the positive power supply circuit 32 and the negative power supply circuit 33. Outputs the inverted signal of the input PWM signal.
　ここで、波高値可変入力部１１の電源回路３２は、波高値可変出力部１５の電源回路４２が供給する正側電源電圧REF#1に追従するように、正側電源電圧REF#3を調整してインバータ３１に供給する。また、波高値可変入力部１１の電源回路３３は、波高値可変出力部１５の電源回路４３が供給する負側電源電圧REF#2に追従するように、負側電源電圧REF#4を調整してインバータ３１に供給する。 Here, the power supply circuit 32 of the peak value variable input unit 11 adjusts the positive power supply voltage REF # 3 so as to follow the positive power supply voltage REF # 1 supplied by the power supply circuit 42 of the peak value variable output unit 15. And supplied to the inverter 31. The power circuit 33 of the peak value variable input unit 11 adjusts the negative power supply voltage REF # 4 so as to follow the negative power supply voltage REF # 2 supplied by the power circuit 43 of the peak value variable output unit 15. To the inverter 31.
　従って、波高値可変入力部１１は、波高値可変出力部１５が出力する出力PWM信号と同じ波高値をもつ信号であって、入力PWM信号を反転させた反転PWM信号を出力する。図３には、インバータ３１に入力される入力PWM信号と、インバータ３１の出力である反転PWM信号（入力PWM信号の反転信号）が示されている。ただし、図３では、入力PWM信号と反転PWM信号の波高値は変更されていない。 Therefore, the peak value variable input unit 11 is a signal having the same peak value as the output PWM signal output from the peak value variable output unit 15, and outputs an inverted PWM signal obtained by inverting the input PWM signal. FIG. 3 shows an input PWM signal input to the inverter 31 and an inverted PWM signal (an inverted signal of the input PWM signal) that is the output of the inverter 31. However, in FIG. 3, the peak values of the input PWM signal and the inverted PWM signal are not changed.
　反転PWM信号が可変抵抗３４に供給されると、可変抵抗３４は、その反転PWM信号を電流に変換して、積分器１２のオペアンプ３５の反転入力端子に出力する。 When the inverted PWM signal is supplied to the variable resistor 34, the variable resistor 34 converts the inverted PWM signal into a current and outputs it to the inverting input terminal of the operational amplifier 35 of the integrator 12.
　また、積分器１２のオペアンプ３５の反転入力端子には、フィードバック回路１６の可変抵抗４５から、波高値可変出力部１５の出力である出力PWM信号を電流に変換した信号も入力される。 Further, a signal obtained by converting the output PWM signal output from the peak value variable output unit 15 into a current is input from the variable resistor 45 of the feedback circuit 16 to the inverting input terminal of the operational amplifier 35 of the integrator 12.
　波高値可変出力部１５の出力である出力PWM信号と、波高値可変入力部１１のインバータ３１の出力である、入力PWM信号を反転させた反転PWM信号は、上述したように波高値が同じになるように調整されている。したがって、オペアンプ３５の反転入力端子には、入力PWM信号と出力PWM信号との誤差に相当する信号が入力されることになる。 As described above, the output PWM signal that is the output of the peak value variable output unit 15 and the inverted PWM signal that is the output of the inverter 31 of the peak value variable input unit 11 are the same as described above. It has been adjusted to be. Therefore, a signal corresponding to an error between the input PWM signal and the output PWM signal is input to the inverting input terminal of the operational amplifier 35.
　オペアンプ３５とキャパシタ３６とからなる積分器１２は、オペアンプ３５の反転入力端子に入力された、入力PWM信号と出力PWM信号との誤差を積分して出力する。オペアンプ３５の非反転入力端子に入力される基準電圧REF#5は、正側電源電圧REF#1と負側電源電圧REF#2の中間値となる電圧である。 The integrator 12 including the operational amplifier 35 and the capacitor 36 integrates and outputs the error between the input PWM signal and the output PWM signal input to the inverting input terminal of the operational amplifier 35. The reference voltage REF # 5 input to the non-inverting input terminal of the operational amplifier 35 is a voltage that is an intermediate value between the positive power supply voltage REF # 1 and the negative power supply voltage REF # 2.
　ヒステリシスコンパレータ１３は、積分器１２の出力と基準電圧REF#6とを比較し、その比較結果を出力する。ヒステリシスコンパレータ１３は、所定のヒステリシス幅をもって、比較結果を出力する。 The hysteresis comparator 13 compares the output of the integrator 12 with the reference voltage REF # 6 and outputs the comparison result. The hysteresis comparator 13 outputs a comparison result with a predetermined hysteresis width.
　ゲートドライバ１４は、ヒステリシスコンパレータ１３から供給される比較結果信号に基づいて波高値可変出力部１５のインバータ４１を駆動する。 The gate driver 14 drives the inverter 41 of the peak value variable output unit 15 based on the comparison result signal supplied from the hysteresis comparator 13.
　波高値可変出力部１５の正側の電源回路４２及び負側の電源回路４３は、例えば、オーディオプレーヤのボリュームの設定値や、無音状態の有無などに応じて、インバータ４１に供給する正側電源電圧REF#1と負側電源電圧REF#2を変化させる。また、インバータ４１は、ゲートドライバ１４からの入力を反転させた信号を出力する。これにより、波高値可変出力部１５は、入力PWM信号を電力増幅した出力PWM信号を生成する。 The positive-side power supply circuit 42 and the negative-side power supply circuit 43 of the peak value variable output unit 15 are supplied to the inverter 41 in accordance with, for example, the volume setting value of the audio player or the presence / absence of a silence state. The voltage REF # 1 and the negative power supply voltage REF # 2 are changed. The inverter 41 outputs a signal obtained by inverting the input from the gate driver 14. Thereby, the peak value variable output unit 15 generates an output PWM signal obtained by power amplification of the input PWM signal.
　図３には、積分器１２の出力例が示されており、その積分器１２の出力に対して、ヒステリシスコンパレータ１３の比較結果信号の変化点が丸（○）で示されている。 FIG. 3 shows an output example of the integrator 12, and the change point of the comparison result signal of the hysteresis comparator 13 is indicated by a circle (◯) with respect to the output of the integrator 12.
　ヒステリシスコンパレータ１３は、入力PWM信号と出力PWM信号の誤差によって比較結果信号のエッジ位置を変化させることにより、誤差に応じた遅延を作り出す。ヒステリシスコンパレータ１３が出力する比較結果信号のエッジ位置が変化すると、出力PWM信号のパルス幅が変化する。 The hysteresis comparator 13 creates a delay according to the error by changing the edge position of the comparison result signal according to the error between the input PWM signal and the output PWM signal. When the edge position of the comparison result signal output from the hysteresis comparator 13 changes, the pulse width of the output PWM signal changes.
　換言すれば、ヒステリシスコンパレータ１３は、入力PWM信号と出力PWM信号の誤差に応じて、出力PWM信号をパルス幅（時間軸情報）で補正した反転PWM信号を生成する。そして、その補正後の反転PWM信号が、ゲートドライバ１４及び波高値可変出力部１５において、反転されるとともに電力増幅され、出力PWM信号とされる。 In other words, the hysteresis comparator 13 generates an inverted PWM signal obtained by correcting the output PWM signal with the pulse width (time axis information) according to the error between the input PWM signal and the output PWM signal. Then, the inverted PWM signal after the correction is inverted and power amplified in the gate driver 14 and the peak value variable output unit 15 to be an output PWM signal.
　理解を容易にするために、入力PWM信号に対して波高値が変更されない場合で考えると、ヒステリシスコンパレータ１３は、図４に示されるように、入力PWM信号のパルス面積（図４において斜線を付した領域の面積）と、出力PWM信号の対応するパルス面積とが、同一の面積となるように、出力PWM信号の各パルスを調整する機能を備える。また例えば、ある入力PWM信号がヒステリシスコンパレータ１３に継続的に入力されている状態において、外乱ノイズが混入した場合に、ヒステリシスコンパレータ１３は、ノイズ混入の前後で、出力PWM信号のパルス面積が同一となるように、出力PWM信号のパルス幅を調整する機能を有しているとも言うことができる。 For the sake of easy understanding, considering that the peak value is not changed with respect to the input PWM signal, the hysteresis comparator 13 has a pulse area of the input PWM signal (indicated by hatching in FIG. 4), as shown in FIG. A function of adjusting each pulse of the output PWM signal so that the corresponding pulse area of the output PWM signal becomes the same area. For example, when disturbance noise is mixed in a state where a certain input PWM signal is continuously input to the hysteresis comparator 13, the hysteresis comparator 13 has the same pulse area of the output PWM signal before and after the noise mixing. Thus, it can also be said that it has a function of adjusting the pulse width of the output PWM signal.
　なお、波高値可変出力部１５が波高値を変更した場合、積分器１２への流入電流が変化するので、積分器１２で生じる遅延、換言すれば、図３における積分器１２の出力波形の傾きが変化する。積分器１２の出力波形の傾きは、波高値可変入力部１１のインバータ３１の出力信号（電圧）をVin、波高値可変出力部１５のインバータ４１の出力信号（電圧）をVoutとすると、インバータ３１の出力信号とインバータ４１の出力信号が同相である場合には、1/C｛（Vin/Rin）－（Vout/Rfb）｝で表され、逆相である場合には、1/C｛（Vin/Rin）＋（Vout/Rfb）｝で表される。ここで、Cはキャパシタ３６の容量値を表す。 When the peak value variable output unit 15 changes the peak value, the inflow current to the integrator 12 changes, so that the delay caused in the integrator 12, in other words, the slope of the output waveform of the integrator 12 in FIG. Changes. The slope of the output waveform of the integrator 12 is determined by assuming that the output signal (voltage) of the inverter 31 of the peak value variable input unit 11 is Vin and the output signal (voltage) of the inverter 41 of the peak value variable output unit 15 is Vout. Is 1 / C {(Vin / Rin) − (Vout / Rfb)} when the output signal of the inverter 41 and the output signal of the inverter 41 are in phase, and 1 / C {( Vin / Rin) + (Vout / Rfb)}. Here, C represents the capacitance value of the capacitor 36.
　積分器１２で生じる遅延の許容範囲は、PWM信号の分解能によって決定されるが、積分器１２で生じる遅延が許容範囲を超える場合には、フィードバック回路１６の可変抵抗４５の抵抗値Rfbと、波高値可変入力部１１の可変抵抗３４の抵抗値Rinとを変更することで、積分器１２への遅延が許容範囲となるように調整することができる。 The allowable range of the delay generated in the integrator 12 is determined by the resolution of the PWM signal. When the delay generated in the integrator 12 exceeds the allowable range, the resistance value Rfb of the variable resistor 45 of the feedback circuit 16 and the wave By changing the resistance value Rin of the variable resistor 34 of the high-value variable input unit 11, the delay to the integrator 12 can be adjusted to be within an allowable range.
　従って、可変抵抗４５の抵抗値Rfbと可変抵抗３４の抵抗値Rinは、波高値の変更に応じて変化させるが、積分器１２で生じる遅延が許容範囲を超えない程度に抵抗値を調整すればよいため、波高値の変化と抵抗値の変化が完全に一致する必要はない。そのため、例えば、２段階の波高値の変更に対して１段階の抵抗値の変更とするなど、抵抗値の切替え段数は、波高値の切替え段数よりも少ない段数とすることができる。勿論、抵抗値の切替え段数を、波高値の切替え段数と同じにしてもよい。 Therefore, the resistance value Rfb of the variable resistor 45 and the resistance value Rin of the variable resistor 34 are changed according to the change of the crest value. However, if the resistance value is adjusted so that the delay generated in the integrator 12 does not exceed the allowable range. For this reason, it is not necessary that the change in the crest value and the change in the resistance value coincide completely. Therefore, for example, the resistance value switching stage number can be made smaller than the peak value switching stage number, for example, the resistance value switching stage can be changed in one stage with respect to the two-stage peak value change. Of course, the resistance value switching stage number may be the same as the peak value switching stage number.
　なお、積分器１２で生じる遅延は、可変抵抗４５と可変抵抗３４の抵抗値で調整するのではなく、積分器１２のキャパシタ３６の容量値で調整する構成とすることもできる。 Note that the delay caused by the integrator 12 may be adjusted not by adjusting the resistance values of the variable resistor 45 and the variable resistor 34 but by adjusting the capacitance value of the capacitor 36 of the integrator 12.
　D級増幅器１の出力先には、図２に示したように、出力PWM信号の高周波成分を除去するため、LCフィルタ２１が配置される。LCフィルタ２１には、出力PWM信号に依存した電流が流れ、電源の変動や、波高値可変出力部１５の正側の抵抗値と負側の抵抗値の違いなどによって、出力波形の誤差を引き起こし、出力PWM信号の歪が悪化する。 As shown in FIG. 2, an LC filter 21 is disposed at the output destination of the class D amplifier 1 in order to remove high frequency components of the output PWM signal. A current depending on the output PWM signal flows through the LC filter 21 and causes an error in the output waveform due to fluctuations in the power supply, the difference between the positive resistance value and the negative resistance value of the peak value variable output unit 15, and the like. The distortion of the output PWM signal gets worse.
　一方、波高値可変入力部１１では、可変抵抗３４の抵抗値Rin（～ｋΩ）を、負荷２２の抵抗値（～Ω）よりも大きく取ることができ、また、出力端には、波高値可変出力部１５と異なりLCフィルタがないため、電源変動が発生しにくく、波高値可変入力部１１の正側の抵抗値と負側の抵抗値の違いも、歪ではなくオフセットとなって現れる。D級増幅器１は、このような特徴を有する波高値可変入力部１１から出力された信号に合わせるように出力PWM信号が制御されるため、良好な歪特性を得ることができる。 On the other hand, in the peak value variable input section 11, the resistance value Rin (˜kΩ) of the variable resistor 34 can be made larger than the resistance value (˜Ω) of the load 22, and the peak value is variable at the output end. Unlike the output unit 15, since there is no LC filter, power supply fluctuation is unlikely to occur, and the difference between the positive resistance value and the negative resistance value of the peak value variable input unit 11 appears as an offset instead of distortion. Since the output PWM signal is controlled to match the signal output from the peak value variable input section 11 having such characteristics, the class D amplifier 1 can obtain good distortion characteristics.
＜３．D級増幅器の第２の回路構成例＞
　次に、図５を参照して、D級増幅器１の詳細な構成例であって、第２の回路構成例について説明する。 <3. Second Circuit Configuration Example of Class D Amplifier>
Next, a detailed configuration example of the class D amplifier 1 and a second circuit configuration example will be described with reference to FIG.
　図５において、図２に示した第１の回路構成と対応する部分については同一の符号を付してあり、その部分の説明は省略する。 In FIG. 5, parts corresponding to those of the first circuit configuration shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.
　図５に示される第２の回路構成では、波高値可変入力部１１の構成のみが、図２に示した第１の回路構成と異なる。 In the second circuit configuration shown in FIG. 5, only the configuration of the peak value variable input unit 11 is different from the first circuit configuration shown in FIG.
　第１の回路構成では、波高値可変入力部１１の構成を、波高値可変出力部１５及びフィードバック回路１６と同じ構成にすることで、積分器１２のオペアンプ３５に所定の電流が供給されるように波高値可変入力部１１が構成されていた。 In the first circuit configuration, the predetermined value is supplied to the operational amplifier 35 of the integrator 12 by making the configuration of the peak value variable input unit 11 the same as that of the peak value variable output unit 15 and the feedback circuit 16. The peak value variable input unit 11 is configured.
　それに対して、第２の回路構成では、波高値可変入力部１１が、電流出力型の構成に変更されている。即ち、波高値可変出力部１５は、負荷２２を駆動する必要があるため、電圧出力型の出力とする必要があり、その出力を可変抵抗４５によって電圧電流変換した。しかし、波高値可変入力部１１の出力先では電圧出力型の出力が必要ではないので、波高値可変入力部１１を電流出力型の構成とすることができる。 On the other hand, in the second circuit configuration, the peak value variable input unit 11 is changed to a current output type configuration. That is, since the peak value variable output unit 15 needs to drive the load 22, it needs to be a voltage output type output, and the output is subjected to voltage-current conversion by the variable resistor 45. However, since the output destination of the peak value variable input unit 11 does not require a voltage output type output, the peak value variable input unit 11 can be configured as a current output type.
　具体的には、第２の回路構成の波高値可変入力部１１では、インバータ３１、定電流源回路６０、及び、カレントミラー回路６１で構成されている。定電流源回路６０は、インバータ３１とカレントミラー回路６１に、オペアンプ６２が出力する正側電源電圧REF#3と可変抵抗３４の抵抗値Rinで決まる電流Ioutを供給する。正側電源電圧REF#3は、第１の回路構成と同様に、正側電源電圧REF#1に追従するように調整される。 Specifically, the peak value variable input section 11 having the second circuit configuration includes an inverter 31, a constant current source circuit 60, and a current mirror circuit 61. The constant current source circuit 60 supplies the inverter 31 and the current mirror circuit 61 with a current Iout determined by the positive power supply voltage REF # 3 output from the operational amplifier 62 and the resistance value Rin of the variable resistor 34. The positive power supply voltage REF # 3 is adjusted so as to follow the positive power supply voltage REF # 1 as in the first circuit configuration.
　入力PWM信号がLoｗのとき、インバータ３１のPMOSトランジスタがオンし、オペアンプ６２が出力する正側電源電圧REF#3と可変抵抗３４の抵抗値Rinで決まる電流Ioutが、PMOSトランジスタを介して積分器１２のオペアンプ３５に供給される。 When the input PWM signal is Low, the PMOS transistor of the inverter 31 is turned on, and the current Iout determined by the positive side power supply voltage REF # 3 output from the operational amplifier 62 and the resistance value Rin of the variable resistor 34 is integrated via the PMOS transistor. 12 operational amplifiers 35.
　一方、入力PWM信号がHiのときには、インバータ３１のNMOSトランジスタがオンし、カレントミラー回路６１によりコピーされた電流Ioutが、NMOSトランジスタを介して積分器１２のオペアンプ３５から引き抜かれる。 On the other hand, when the input PWM signal is Hi, the NMOS transistor of the inverter 31 is turned on, and the current Iout copied by the current mirror circuit 61 is extracted from the operational amplifier 35 of the integrator 12 via the NMOS transistor.
　従って、第２の回路構成においても、第１の回路構成と同じように、入力PWM信号に対応する電流を積分器１２のオペアンプ３５に供給することができる。 Therefore, also in the second circuit configuration, the current corresponding to the input PWM signal can be supplied to the operational amplifier 35 of the integrator 12 as in the first circuit configuration.
　D級増幅器１を第２の回路構成とした場合、図２に示した第１の回路構成と比較すると、電源回路３３が不要となるため、波高値可変入力部１１の消費電力を抑えることができる。したがって、第２の回路構成は、消費電流に制約がある場合に有用な構成となる。 When the class D amplifier 1 has the second circuit configuration, the power supply circuit 33 is unnecessary as compared with the first circuit configuration shown in FIG. 2, so that the power consumption of the peak value variable input unit 11 can be suppressed. it can. Therefore, the second circuit configuration is useful when the current consumption is limited.
　第２の回路構成の欠点としては、第１の回路構成と比較すると、カレントミラー回路６１を使用することにより、波高値可変入力部１１のノイズが大きくなる。そのため、出力信号のノイズ特性を悪化させる懸念がある。 As a disadvantage of the second circuit configuration, the noise of the peak value variable input unit 11 is increased by using the current mirror circuit 61 as compared with the first circuit configuration. Therefore, there is a concern of deteriorating the noise characteristics of the output signal.
　そこで、カレントミラー回路６１のNMOSトランジスタのソース側に抵抗（ソース縮退抵抗）を挿入することにより、ノイズ特性を改善することができる。 Therefore, noise characteristics can be improved by inserting a resistor (source degeneration resistor) on the source side of the NMOS transistor of the current mirror circuit 61.
　第１の回路構成及び第２の回路構成のいずれを採用した場合においても、D級増幅器１によれば、出力PWM信号の波高値を調整することができるので、入力PWM信号に含まれるノイズ成分を抑圧することができる。例えば、D級増幅器１は、搭載される電子機器（図６）等で設定されるボリューム値などに応じて、出力するPWM信号の波高値を調整して出力することができる。 In either case of adopting the first circuit configuration or the second circuit configuration, the peak value of the output PWM signal can be adjusted according to the class D amplifier 1, so that the noise component included in the input PWM signal Can be suppressed. For example, the class D amplifier 1 can adjust and output the peak value of the PWM signal to be output in accordance with the volume value set by the mounted electronic device (FIG. 6) or the like.
　出力するPWM信号の波高値を調整するために、波高値可変出力部１５のみの正側電源電圧REF#1及び負側電源電圧REF#2を可変にするだけでは、波高値可変出力部１５の波高値の変化が、入力側にフィードバックされたとき、入力と出力の誤差として検出され、補正されることになる。 In order to adjust the peak value of the PWM signal to be output, the positive-side power supply voltage REF # 1 and the negative-side power supply voltage REF # 2 of only the peak value variable output unit 15 are made variable. When the change in peak value is fed back to the input side, it is detected and corrected as an error between the input and output.
　しかしながら、D級増幅器１では、波高値可変出力部１５の出力PWM信号の波高値の変化に追従させて、波高値可変入力部１１の入力PWM信号（の反転信号）の波高値も変化させる。そして、この波高値可変入力部１１から出力された信号に合わせるように出力PWM信号が制御されるため、誤差を抑圧し、低歪な出力PWM信号を出力することができる。また、フィードバックにより波高値可変出力部１５の抵抗で発生する電圧降下も補正されるため、最大出力電力を向上させることができる。 However, in the class D amplifier 1, the peak value of the input PWM signal (inverted signal thereof) of the peak value variable input unit 11 is also changed by following the change of the peak value of the output PWM signal of the peak value variable output unit 15. Since the output PWM signal is controlled so as to match the signal output from the peak value variable input unit 11, an error can be suppressed and a low distortion output PWM signal can be output. Moreover, since the voltage drop which generate | occur | produces with the resistance of the peak value variable output part 15 is correct | amended by feedback, the maximum output power can be improved.
　以上により、D級増幅器１によれば、低ノイズ、低歪、高出力なPWM信号を出力することができる。 As described above, the class D amplifier 1 can output a PWM signal with low noise, low distortion, and high output.
　また、D級増幅器１によれば、出力PWM信号を入力側にフィードバックし、入力と出力の誤差をパルス幅で補正する機構（PWM信号を再整形する機構）を有することで、誤差を抑圧し、低歪な出力PWM信号を出力することができる。 Further, according to the class D amplifier 1, the error is suppressed by feeding back the output PWM signal to the input side and correcting the error between the input and output with the pulse width (the mechanism for reshaping the PWM signal). Can output low distortion output PWM signal.
＜４．電子機器への適用例＞
　本技術は、D級増幅器への適用に限られるものではない。即ち、本技術は、例えば、オーディオ信号に基づいて音を出力するオーディオプレーヤ、音出力機能を有するスマートフォン、タブレットなどの携帯端末装置、音出力機能を有する複写機やプリンタ装置、撮像装置など、音出力機能を有する電子機器全般に対して適用可能である。 <4. Application example to electronic equipment>
The present technology is not limited to application to class D amplifiers. In other words, the present technology is applicable to sound players such as an audio player that outputs sound based on an audio signal, a mobile terminal device such as a smartphone or a tablet that has a sound output function, a copier, a printer device, or an imaging device that has a sound output function. The present invention can be applied to all electronic devices having an output function.
　図６は、本技術を採用した電子機器としての、オーディオプレーヤの構成例を示すブロック図である。 FIG. 6 is a block diagram illustrating a configuration example of an audio player as an electronic apparatus employing the present technology.
　図６のオーディオプレーヤ７０は、操作部７１、データ記憶部７２、通信部７３、制御部７４、表示部７５、デルタシグマ（△Σ）変調部７６、PWM信号生成部７７、D級増幅器７８、ローパスフィルタ７９、及び、スピーカ８０で構成される。 6 includes an operation unit 71, a data storage unit 72, a communication unit 73, a control unit 74, a display unit 75, a delta-sigma (ΔΣ) modulation unit 76, a PWM signal generation unit 77, a class D amplifier 78, A low-pass filter 79 and a speaker 80 are included.
　操作部７１は、データ記憶部７２に記憶されている所定の楽曲（音楽）の再生、停止などのユーザの操作を受け付け、受け付けた操作に対応する操作信号を制御部７４に供給する。 The operation unit 71 accepts a user operation such as reproduction or stop of a predetermined music (music) stored in the data storage unit 72, and supplies an operation signal corresponding to the accepted operation to the control unit 74.
　データ記憶部７２は、例えば、半導体メモリなどで構成され、複数の楽曲のデータを、所定のデータ形式（例えばMP3（MPEG（Moving Picture Experts Group）１ Audio Layer3））により記憶する。また、データ記憶部７２は、制御部７４がオーディオプレーヤ７０全体の動作を制御するためのプログラムなども記憶する。 The data storage unit 72 is composed of, for example, a semiconductor memory, and stores data of a plurality of music pieces in a predetermined data format (for example, MP3 (MPEG (Moving Picture Experts Group) 1 Audio Layer 3)). The data storage unit 72 also stores a program for the control unit 74 to control the operation of the audio player 70 as a whole.
　通信部７３は、例えば、USB(Universal Serial Bus)インタフェースなどで構成され、制御部７４の制御により、外部装置と接続して、オーディオデータなどを送受信する。また、通信部７３は、ローカルエリアネットワーク、インターネット、その他のネットワークに接続するネットワークインタフェースなどで構成されても良く、ネットワークを介して外部装置と接続し、オーディオデータなどをやりとりしてもよい。 The communication unit 73 is configured by, for example, a USB (Universal Serial Bus) interface or the like, and is connected to an external device under the control of the control unit 74 to transmit and receive audio data and the like. The communication unit 73 may be configured with a local area network, the Internet, a network interface connected to another network, or the like, and may be connected to an external device via the network to exchange audio data.
　制御部７４は、例えば、CPU（Central Processing Unit）、RAM（Random Access Memory）などで構成され、オーディオプレーヤ７０全体の動作を制御する。例えば、制御部７４は、データ記憶部７２に記憶されている所定の楽曲の再生がユーザによって操作された操作信号が操作部７１から供給された場合、再生指示された楽曲のオーディオデータをデータ記憶部７２から取得してデルタシグマ変調部７６に供給する。また、制御部７４は、表示部７５に表示される画像を制御する。 The control unit 74 includes, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory), and the like, and controls the entire operation of the audio player 70. For example, the control unit 74 stores the audio data of the music instructed to be reproduced when the operation signal is supplied from the operation unit 71 to reproduce the predetermined music stored in the data storage unit 72 by the user. Obtained from the unit 72 and supplied to the delta-sigma modulation unit 76. Further, the control unit 74 controls an image displayed on the display unit 75.
　表示部７５は、例えば、LCD(Liquid Crystal Display)やEL(Electro Luminescence)ディスプレイなどで構成され、制御部７４の制御に従い、再生中の楽曲のタイトルや再生時間、データ記憶部７２に記憶されているオーディオデータなどを表示する。 The display unit 75 includes, for example, an LCD (Liquid Crystal Display) or an EL (Electro Luminescence) display, and is stored in the data storage unit 72 according to the control of the control unit 74 and the title and playback time of the music being played back. Displays the audio data etc.
　デルタシグマ変調部７６は、制御部７４から供給されたオーディオデータに対してデルタシグマ変調処理を施し、デルタシグマ変調されたNビット（N＞０）のデジタルデータを生成してPWM信号生成部７７に出力する。 The delta-sigma modulation unit 76 performs delta-sigma modulation processing on the audio data supplied from the control unit 74, generates N-bit (N> 0) digital data that is delta-sigma modulated, and generates a PWM signal generation unit 77. Output to.
　PWM信号生成部７７は、デルタシグマ変調部７６から供給されるデルタシグマ変調されたNビットのデジタルデータを、PWM信号に変換してD級増幅器７８に出力する。 The PWM signal generation unit 77 converts the delta sigma modulated N-bit digital data supplied from the delta sigma modulation unit 76 into a PWM signal and outputs the PWM signal to the class D amplifier 78.
　D級増幅器７８は、PWM信号生成部７７から供給されるPWM信号を電力増幅して出力する。このD級増幅器７８の構成として、図１のD級増幅器１の構成が採用されている。 The class D amplifier 78 amplifies the power of the PWM signal supplied from the PWM signal generator 77 and outputs it. As the configuration of the class D amplifier 78, the configuration of the class D amplifier 1 of FIG. 1 is adopted.
　ローパスフィルタ７９は、D級増幅器７８が出力するPWM信号に対して、高周波成分を除去するフィルタ処理を施し、フィルタ処理後の信号をスピーカ８０に出力する。スピーカ８０は、ローパスフィルタ７９を介してD級増幅器７８から供給されるPWM信号に基づいて音を出力する。ローパスフィルタ７９は、図２のLCフィルタ２１に相当し、スピーカ８０は、図２の負荷２２に相当する。 The low-pass filter 79 performs a filtering process for removing high-frequency components on the PWM signal output from the class D amplifier 78, and outputs the filtered signal to the speaker 80. The speaker 80 outputs sound based on the PWM signal supplied from the class D amplifier 78 via the low pass filter 79. The low-pass filter 79 corresponds to the LC filter 21 in FIG. 2, and the speaker 80 corresponds to the load 22 in FIG.
　デルタシグマ変調部７６、PWM信号生成部７７、及び、D級増幅器７８はいずれもデジタル回路であり、D級増幅器７８を用いることで、デジタル信号をアナログ信号に変換するA/D変換器が不要となるので、回路規模を縮小することができる。 The delta-sigma modulation unit 76, the PWM signal generation unit 77, and the class D amplifier 78 are all digital circuits, and by using the class D amplifier 78, an A / D converter that converts a digital signal into an analog signal is unnecessary. Therefore, the circuit scale can be reduced.
　以上のように構成されるオーディオプレーヤ７０では、D級増幅器７８として、上述した図１のD級増幅器１の構成を採用しているので、入力PWM信号に含まれるノイズ成分を抑圧することができるとともに、誤差を抑圧し、低歪な出力PWM信号をスピーカ８０に出力することができる。また、最大出力電力も向上させることができる。 In the audio player 70 configured as described above, since the configuration of the class D amplifier 1 of FIG. 1 described above is adopted as the class D amplifier 78, noise components included in the input PWM signal can be suppressed. At the same time, an error can be suppressed and a low distortion output PWM signal can be output to the speaker 80. Also, the maximum output power can be improved.
　本技術の実施の形態は、上述した実施の形態に限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更が可能である。 Embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure.
　例えば、上述した複数の実施の形態の全てまたは一部を組み合わせた形態を採用することができる。 For example, it is possible to adopt a form in which all or a part of the plurality of embodiments described above are combined.
　例えば、本技術は、１つの機能をネットワークを介して複数の装置で分担、共同して処理するクラウドコンピューティングの構成をとることができる。 For example, the present technology can take a cloud computing configuration in which one function is shared by a plurality of devices via a network and is jointly processed.
　なお、本明細書に記載された効果はあくまで例示であって限定されるものではなく、本明細書に記載されたもの以外の効果があってもよい。 It should be noted that the effects described in this specification are merely examples and are not limited, and there may be effects other than those described in this specification.
　なお、本技術は以下のような構成も取ることができる。
（１）
　装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、
　装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部と
　を備え、
　前記PWM信号入力部は、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる
　増幅器。
（２）
　前記出力PWM信号を所定の回路へフィードバックさせるフィードバック回路と、
　前記フォードバック回路によりフィードバックされた前記出力PWM信号と、前記PWM信号入力部の出力信号との誤差を蓄積する積分器と、
　前記積分器の出力を所定の基準値と比較し、その比較結果を表す比較結果信号を出力する比較器と、
　前記比較結果信号を用いて前記PWM信号出力部を駆動するゲートドライバと
　をさらに備える
　前記（１）に記載の増幅器。
（３）
　前記フィードバック回路及び前記PWM信号入力部は、前記波高値の変化に応じた前記積分器での遅延量を調整する機能を有する
　前記（２）に記載の増幅器。
（４）
　前記フィードバック回路及び前記PWM信号入力部は、抵抗の抵抗値を変更することにより、前記積分器での遅延量を調整する
　前記（３）に記載の増幅器。
（５）
　前記積分器は、前記波高値の変化に応じた前記積分器での遅延量を調整する機能を有する
　前記（２）に記載の増幅器。
（６）
　前記積分器は、キャパシタの容量値を変更することにより、前記積分器での遅延量を調整する
　前記（５）に記載の増幅器。
（７）
　前記積分器での遅延量を調整する切替え段数は、前記波高値の変化の段数以下である
　前記（３）乃至（６）のいずれかに記載の増幅器。
（８）
　前記比較器は、前記比較結果信号として、前記出力PWM信号と前記PWM信号入力部の出力信号との誤差情報を、PWM信号のエッジ位置を変化させることにより時間軸情報に変換した信号を生成して出力する
　前記（２）乃至（７）のいずれかに記載の増幅器。
（９）
　前記比較器は、前記比較結果信号として、前記出力PWM信号と前記PWM信号入力部の出力信号との誤差に応じて前記出力PWM信号を補正したPWM信号を生成して出力する
　前記（２）乃至（８）のいずれかに記載の増幅器。
（１０）
　前記出力PWM信号を補正したPWM信号は、前記PWM信号入力部の出力信号と、PWM信号のパルス面積が同一となるように調整された信号である
　前記（９）に記載の増幅器。
（１１）
　装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部とを備える増幅器の、
　前記PWM信号出力部が、前記出力PWM信号の波高値を変更し、
　前記PWM信号入力部が、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる
　増幅器の制御方法。
（１２）
　装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、
　装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部と
　を備え、
　前記PWM信号入力部は、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる
　増幅器
　を備える電子機器。
（１３）
　オーディオデータを取得する取得部と、
　取得された前記オーディオデータに対応するPWM信号を生成するPWM信号生成部と、
　前記PWM信号生成部により生成された前記PWM信号が前記増幅器により電力増幅された信号に基づいて音を出力するスピーカと
　をさらに備える
　前記（１２）に記載の電子機器。
（１４）
　装置外から入力されたPWM信号である入力PWM信号を電力増幅したPWM信号を出力PWM信号として出力し、前記出力PWM信号のパルス面積がノイズ混入の前後で同一の面積となるように制御する
　増幅器。 In addition, this technique can also take the following structures.
(1)
A PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal, which is a PWM signal output to the outside of the device;
A PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the device, and
The PWM signal input unit causes the peak value of the input PWM signal to follow a change in the peak value of the output PWM signal.
(2)
A feedback circuit for feeding back the output PWM signal to a predetermined circuit;
An integrator for accumulating an error between the output PWM signal fed back by the Fordback circuit and an output signal of the PWM signal input unit;
A comparator that compares the output of the integrator with a predetermined reference value and outputs a comparison result signal representing the comparison result;
The amplifier according to (1), further comprising: a gate driver that drives the PWM signal output unit using the comparison result signal.
(3)
The amplifier according to (2), wherein the feedback circuit and the PWM signal input unit have a function of adjusting a delay amount in the integrator according to a change in the peak value.
(4)
The amplifier according to (3), wherein the feedback circuit and the PWM signal input unit adjust a delay amount in the integrator by changing a resistance value of a resistor.
(5)
The amplifier according to (2), wherein the integrator has a function of adjusting a delay amount in the integrator according to a change in the peak value.
(6)
The amplifier according to (5), wherein the integrator adjusts a delay amount in the integrator by changing a capacitance value of a capacitor.
(7)
The amplifier according to any one of (3) to (6), wherein the number of switching stages for adjusting the delay amount in the integrator is equal to or less than the number of stages of change in the peak value.
(8)
The comparator generates, as the comparison result signal, a signal obtained by converting error information between the output PWM signal and the output signal of the PWM signal input unit into time axis information by changing an edge position of the PWM signal. The amplifier according to any one of (2) to (7).
(9)
The comparator generates and outputs a PWM signal obtained by correcting the output PWM signal according to an error between the output PWM signal and the output signal of the PWM signal input unit as the comparison result signal. The amplifier according to any one of (8).
(10)
The amplifier according to (9), wherein the PWM signal obtained by correcting the output PWM signal is a signal adjusted so that a pulse area of the PWM signal is the same as that of the output signal of the PWM signal input unit.
(11)
A PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal that is a PWM signal that is output outside the apparatus, and a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the apparatus. An amplifier having a PWM signal input unit having
The PWM signal output unit changes the peak value of the output PWM signal,
The method of controlling an amplifier, wherein the PWM signal input unit causes a peak value of the input PWM signal to follow a change in a peak value of the output PWM signal.
(12)
A PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal, which is a PWM signal output to the outside of the device;
A PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the device, and
The PWM signal input unit includes an amplifier that causes a peak value of the input PWM signal to follow a change in a peak value of the output PWM signal.
(13)
An acquisition unit for acquiring audio data;
A PWM signal generator for generating a PWM signal corresponding to the acquired audio data;
The electronic device according to (12), further comprising: a speaker that outputs sound based on a signal obtained by power amplification of the PWM signal generated by the PWM signal generation unit by the amplifier.
(14)
An amplifier that outputs a PWM signal obtained by power amplification of an input PWM signal, which is a PWM signal input from outside the apparatus, as an output PWM signal, and controls the pulse area of the output PWM signal to be the same area before and after noise mixing .
　１　D級増幅器，　１１　波高値可変入力部，　１２　積分器，　１３　ヒステリシスコンパレータ（比較器），　１４　ゲートドライバ，　１５　波高値可変出力部，　１６　フィードバック回路，　２１　LCフィルタ（ローパスフィルタ），　２２　負荷，　３４　可変抵抗，　３５　オペアンプ，　３６　キャパシタ，　４５　可変抵抗，　６０　定電流源回路，　６１　カレントミラー回路，　６２　オペアンプ，　７０　オーディオプレーヤ，　７６　デルタシグマ変調部，　７７　PWM信号生成部，　７８　D級増幅器，　７９　ローパスフィルタ，　８０　スピーカ 1 class D amplifier, 11 peak value variable input section, 12 integrator, 13 hysteresis comparator (comparator), 14 gate driver, 15 peak value variable output section, 16 feedback circuit, 21 LC filter (low pass filter), 22 load, 34 variable resistors, 35 operational amplifiers, 36 capacitors, 45 variable resistors, 60 constant current source circuits, 61 current mirror circuits, 62 operational amplifiers, 70 audio players, 76 delta-sigma modulation units, 77 PWM signal generation units, 78 class D amplifiers, 79 Low-pass filter, 80 speakers

Claims (14)

  1. 　装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、
    　装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部と
    　を備え、
    　前記PWM信号入力部は、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる
    　増幅器。     A PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal, which is a PWM signal output to the outside of the device;
    A PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the device, and
    The PWM signal input unit causes the peak value of the input PWM signal to follow a change in the peak value of the output PWM signal.
  2. 　前記出力PWM信号を所定の回路へフィードバックさせるフィードバック回路と、
    　前記フォードバック回路によりフィードバックされた前記出力PWM信号と、前記PWM信号入力部の出力信号との誤差を蓄積する積分器と、
    　前記積分器の出力を所定の基準値と比較し、その比較結果を表す比較結果信号を出力する比較器と、
    　前記比較結果信号を用いて前記PWM信号出力部を駆動するゲートドライバと
    　をさらに備える
    　請求項１に記載の増幅器。     A feedback circuit for feeding back the output PWM signal to a predetermined circuit;
    An integrator for accumulating an error between the output PWM signal fed back by the Fordback circuit and an output signal of the PWM signal input unit;
    A comparator that compares the output of the integrator with a predetermined reference value and outputs a comparison result signal representing the comparison result;
    The amplifier according to claim 1, further comprising: a gate driver that drives the PWM signal output unit using the comparison result signal.
  3. 　前記フィードバック回路及び前記PWM信号入力部は、前記波高値の変化に応じた前記積分器での遅延量を調整する機能を有する
    　請求項２に記載の増幅器。     The amplifier according to claim 2, wherein the feedback circuit and the PWM signal input unit have a function of adjusting a delay amount in the integrator according to a change in the peak value.
  4. 　前記フィードバック回路及び前記PWM信号入力部は、抵抗の抵抗値を変更することにより、前記積分器での遅延量を調整する
    　請求項３に記載の増幅器。     The amplifier according to claim 3, wherein the feedback circuit and the PWM signal input unit adjust a delay amount in the integrator by changing a resistance value of a resistor.
  5. 　前記積分器は、前記波高値の変化に応じた前記積分器での遅延量を調整する機能を有する
    　請求項２に記載の増幅器。     The amplifier according to claim 2, wherein the integrator has a function of adjusting a delay amount in the integrator according to a change in the peak value.
  6. 　前記積分器は、キャパシタの容量値を変更することにより、前記積分器での遅延量を調整する
    　請求項５に記載の増幅器。     The amplifier according to claim 5, wherein the integrator adjusts a delay amount in the integrator by changing a capacitance value of a capacitor.
  7. 　前記積分器での遅延量を調整する切替え段数は、前記波高値の変化の段数以下である
    　請求項３に記載の増幅器。     The amplifier according to claim 3, wherein the number of switching stages for adjusting the delay amount in the integrator is equal to or less than the number of stages of change in the peak value.
  8. 　前記比較器は、前記比較結果信号として、前記出力PWM信号と前記PWM信号入力部の出力信号との誤差情報を、PWM信号のエッジ位置を変化させることにより時間軸情報に変換した信号を生成して出力する
    　請求項２に記載の増幅器。     The comparator generates, as the comparison result signal, a signal obtained by converting error information between the output PWM signal and the output signal of the PWM signal input unit into time axis information by changing an edge position of the PWM signal. The amplifier according to claim 2.
  9. 　前記比較器は、前記比較結果信号として、前記出力PWM信号と前記PWM信号入力部の出力信号との誤差に応じて前記出力PWM信号を補正したPWM信号を生成して出力する
    　請求項２に記載の増幅器。     The said comparator produces | generates and outputs the PWM signal which correct | amended the said output PWM signal according to the difference | error of the said output PWM signal and the output signal of the said PWM signal input part as said comparison result signal. Amplifier.
  10. 　前記出力PWM信号を補正したPWM信号は、前記PWM信号入力部の出力信号と、PWM信号のパルス面積が同一となるように調整された信号である
    　請求項９に記載の増幅器。     The amplifier according to claim 9, wherein the PWM signal obtained by correcting the output PWM signal is a signal adjusted so that a pulse area of the PWM signal is the same as that of the output signal of the PWM signal input unit.
  11. 　装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部とを備える増幅器の、
    　前記PWM信号出力部が、前記出力PWM信号の波高値を変更し、
    　前記PWM信号入力部が、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる
    　増幅器の制御方法。     A PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal that is a PWM signal that is output outside the apparatus, and a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the apparatus. An amplifier having a PWM signal input unit having
    The PWM signal output unit changes the peak value of the output PWM signal,
    The method of controlling an amplifier, wherein the PWM signal input unit causes a peak value of the input PWM signal to follow a change in a peak value of the output PWM signal.
  12. 　装置外へ出力するPWM信号である出力PWM信号の波高値を可変する可変機構を有するPWM信号出力部と、
    　装置外から入力されたPWM信号である入力PWM信号の波高値を可変する可変機構を有するPWM信号入力部と
    　を備え、
    　前記PWM信号入力部は、前記入力PWM信号の波高値を、前記出力PWM信号の波高値の変化に追従させる
    　増幅器
    　を備える電子機器。     A PWM signal output unit having a variable mechanism that varies the peak value of the output PWM signal, which is a PWM signal output to the outside of the device;
    A PWM signal input unit having a variable mechanism that varies the peak value of the input PWM signal that is a PWM signal input from outside the device, and
    The PWM signal input unit includes an amplifier that causes a peak value of the input PWM signal to follow a change in a peak value of the output PWM signal.
  13. 　オーディオデータを取得する取得部と、
    　取得された前記オーディオデータに対応するPWM信号を生成するPWM信号生成部と、
    　前記PWM信号生成部により生成された前記PWM信号が前記増幅器により電力増幅された信号に基づいて音を出力するスピーカと
    　をさらに備える
    　請求項１２に記載の電子機器。     An acquisition unit for acquiring audio data;
    A PWM signal generator for generating a PWM signal corresponding to the acquired audio data;
    The electronic device according to claim 12, further comprising: a speaker that outputs sound based on a signal obtained by power amplification of the PWM signal generated by the PWM signal generation unit by the amplifier.
  14. 　装置外から入力されたPWM信号である入力PWM信号を電力増幅したPWM信号を出力PWM信号として出力し、前記出力PWM信号のパルス面積がノイズ混入の前後で同一の面積となるように制御する
    　増幅器。     An amplifier that outputs a PWM signal obtained by power amplification of an input PWM signal that is a PWM signal input from outside the apparatus as an output PWM signal, and controls the pulse area of the output PWM signal to be the same area before and after noise mixing .
PCT/JP2016/065021 2015-06-03 2016-05-20 Amplifier, control method therefor, and electronic equipment WO2016194651A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021072551A (en) * 2019-10-31 2021-05-06 ローム株式会社 Audio circuit, and electronic device and in-vehicle audio systems using the same
CN112953581A (en) * 2021-02-23 2021-06-11 广州市慧芯电子科技有限公司 Signal integrating circuit, signal processing method and infrared signal receiving system
US11342892B2 (en) 2017-12-27 2022-05-24 Sony Semiconductor Solutions Corporation Amplifier and signal processing circuit

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Publication number Priority date Publication date Assignee Title
JPH0563457A (en) * 1991-06-18 1993-03-12 Matsushita Electric Ind Co Ltd Delta/sigma modulation amplifier
JP2000022458A (en) * 1998-07-06 2000-01-21 Sharp Corp Pulse wave amplifier
JP2011066559A (en) * 2009-09-15 2011-03-31 Yamaha Corp Class-d amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563457A (en) * 1991-06-18 1993-03-12 Matsushita Electric Ind Co Ltd Delta/sigma modulation amplifier
JP2000022458A (en) * 1998-07-06 2000-01-21 Sharp Corp Pulse wave amplifier
JP2011066559A (en) * 2009-09-15 2011-03-31 Yamaha Corp Class-d amplifier

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342892B2 (en) 2017-12-27 2022-05-24 Sony Semiconductor Solutions Corporation Amplifier and signal processing circuit
JP2021072551A (en) * 2019-10-31 2021-05-06 ローム株式会社 Audio circuit, and electronic device and in-vehicle audio systems using the same
JP7387391B2 (en) 2019-10-31 2023-11-28 ローム株式会社 Audio circuits, electronic devices using them, and in-vehicle audio systems
CN112953581A (en) * 2021-02-23 2021-06-11 广州市慧芯电子科技有限公司 Signal integrating circuit, signal processing method and infrared signal receiving system
CN112953581B (en) * 2021-02-23 2022-04-01 广州市慧芯电子科技有限公司 Signal integrating circuit, signal processing method and infrared signal receiving system

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