CN112953581B - Signal integrating circuit, signal processing method and infrared signal receiving system - Google Patents
Signal integrating circuit, signal processing method and infrared signal receiving system Download PDFInfo
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- H—ELECTRICITY
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- G08C23/04—Non-electrical signal transmission systems, e.g. optical systems using light waves, e.g. infrared
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Abstract
The invention relates to the technical field of electronic circuits, and aims to provide a signal integrating circuit, a signal processing method and an infrared signal receiving system. The signal integrating circuit comprises a first switch, a first current source, a voltage comparator, a second switch, a second current source, a third switch, a third current source, a hysteresis comparator, a fourth switch, a first capacitor and a second capacitor; the signal processing method is realized based on the signal integrating circuit; the infrared signal receiving system comprises the signal integrating circuit. The signal integrating circuit can perform integration operation on an input pulse signal, convert the integrated signal into a demodulated useful signal and perform shaping output; the other signal integrating circuit, the signal processing method and the infrared signal receiving system can effectively eliminate interference when a received pulse signal is interfered, thereby ensuring that the width of the pulse width output by the signal integrating circuit is kept unchanged.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a signal integrating circuit, a signal processing method and an infrared signal receiving system.
Background
Infrared communication technology is a wireless connection technology widely used worldwide, and uses infrared as a communication carrier to transmit data through infrared transmission in the air. The infrared signal receiving system is an important component in the infrared communication technology and is used for performing photoelectric conversion on received infrared light pulses, demodulating and decoding the infrared light pulses and then restoring original signals.
IN the prior art, as disclosed IN chinese patent publication No. CN110401425A, a block diagram of an infrared signal receiving system is shown IN fig. 1, and IN an operation process, an infrared light sensing diode 101 is externally connected to an infrared signal receiving chip 100, and is configured to receive an infrared light signal, convert the infrared light signal into a current signal, and transmit the current signal to an IN port of the infrared signal receiving chip 100. The current-voltage conversion module 102 receives a current signal input from the IN port of the infrared signal receiving chip 100, converts the current signal into a voltage signal, and outputs the voltage signal to the preamplifier 103. The preamplifier 103 receives the voltage signal output from the current-voltage conversion module 102, amplifies the voltage signal, and outputs the amplified voltage signal. The adjustable gain amplifier 104 receives the voltage signal outputted from the preamplifier 103 and also receives the gain control signal outputted from the automatic gain control module 109, which can adjust the amplification gain according to the gain control signal, and amplify and output the voltage signal outputted from the preamplifier 103 by the corresponding gain value. The band-pass filter 105 receives the output signal from the gain-adjustable amplifier 104, and outputs the output signal after performing corresponding filtering. The comparator 106 receives the output signal from the band pass filter 105, compares the signal with an internal reference voltage value, and outputs a corresponding comparison result, high level or low level. An automatic gain control module (AGC) 109 receives the signal output by the comparator 106, determines whether the signal is a desired signal or undesired interference, and correspondingly lowers or raises the gain control voltage signal at the output terminal, so that the chip loop can perform the functions of suppressing interference and amplifying the signal. The signal integration circuit 107 receives the output signal from the comparator 106, integrates the signal, converts the signal into a demodulated useful signal, and shapes and outputs the signal.
The signal integrating circuit 107 is used for controlling the shaping output according to the carrier pulse train of the input signal, and has a great effect on the use of the infrared signal receiving system, however, the specific arrangement of the signal integrating circuit is not disclosed in the prior art.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a signal integrating circuit, a signal processing method, and an infrared signal receiving system.
The technical scheme adopted by the invention is as follows:
a signal integrating circuit comprises a first switch, a first current source, a voltage comparator, a second switch, a second current source, a third switch, a third current source, a hysteresis comparator, a fourth switch, a first capacitor and a second capacitor;
a signal input end of the first switch is connected with a pulse signal, a power supply input end of the first switch is connected with a first current source, a first output end of the first switch is grounded, and a power supply input end of the first switch is grounded through a first capacitor;
the non-inverting input end of the voltage comparator is connected with the joint point of the first switch and the first capacitor, the inverting input end of the voltage comparator is connected with a reference voltage, and the output end of the voltage comparator is respectively connected with the signal input end of the second switch and the signal input end of the third switch;
the power supply input end of the second switch is connected with a second current source, the output end of the second switch is connected with the output end of a third switch, the power supply input end of the third switch is connected with a third current source, and the joint point of the output end of the second switch and the output end of the third switch is grounded through a second capacitor;
the input end of the hysteresis comparator is connected with the joint of the output end of the second switch and the output end of the third switch, the output end of the hysteresis comparator is connected with the signal input end of the fourth switch, and the power input end of the fourth switch is the signal output end of the signal integrating circuit.
Optionally, the signal integration circuit further includes a current-limiting resistor, the current-limiting resistor is connected to a power input terminal of the fourth switch, and a junction point of the power input terminal of the fourth switch (209) and the current-limiting resistor (212) is a signal output terminal of the signal integration circuit.
Optionally, the switch of the third switch is an NMOS transistor.
Optionally, the switch of the second switch is a PMOS transistor.
Further, the first current source is a constant current source.
Further, the first current source is a variable current source, and the first capacitor is a variable capacitor.
Furthermore, the combination point of the hysteresis comparator and the fourth switch is connected with the controlled end of the first current source; and the joint point of the hysteresis comparator and the fourth switch is also connected with the controlled end of the first capacitor.
A signal processing method is realized based on the signal integrating circuit, and comprises the following steps:
the first switch charges or discharges the first capacitor and then outputs the voltage of the node A; when the pulse signal is at a high level, discharging the first capacitor; when the pulse signal is at a low level, charging the first capacitor;
the voltage comparator compares the voltage of the node A with a reference voltage, judges whether the voltage of the node A is smaller than the reference voltage, outputs the voltage of the node B with low level if the voltage of the node A is smaller than the reference voltage, and outputs the voltage of the node B with high level if the voltage of the node A is not smaller than the reference voltage;
the second switch or the third switch receives the voltage of the node B, charges or discharges the second capacitor and then outputs the voltage of the node C; when the voltage of the node B is at a low level, the second capacitor is charged; when the voltage of the node B is at a high level, discharging the second capacitor;
the hysteresis comparator receives the voltage of the node C and then outputs the voltage of the node D; when the voltage of the node C gradually rises until the voltage is larger than the high level threshold value, the output voltage of the node D is changed from low level to high level; when the voltage of the node C gradually drops until the voltage of the node C is smaller than the low level threshold value, the output voltage of the node D is changed from the high level to the low level;
the fourth switch receives the D node voltage and then outputs a signal OUT that is inverted from the D node voltage.
Further, the first current source and the first capacitor are both controlled by the voltage of the node D.
An infrared signal receiving system comprising the signal integrating circuit of any one of the above.
The beneficial effects of the invention are concentrated and expressed as follows:
1) the disclosed signal integrating circuit can carry out integration operation to input pulse signal, convert the integrated signal into demodulated useful signal and carry out shaping output;
2) the embodiment discloses another signal integrating circuit, a signal processing method and an infrared signal receiving system, which can effectively eliminate interference when a received pulse signal is interfered, so that the width of the pulse width output by the signal integrating circuit is kept unchanged.
Drawings
FIG. 1 is a schematic diagram of a prior art IR signal receiving system;
FIG. 2 is a schematic circuit diagram of a signal integration circuit according to a first embodiment;
FIG. 3 is a waveform diagram of the control output of the signal integration circuit in the first embodiment;
fig. 4 is a waveform diagram of the output of the signal integrating circuit when the carrier pulse train IN is disturbed and loses a periodic signal IN the first embodiment;
fig. 5 is a waveform diagram of the output of the signal integrating circuit when the carrier pulse train IN is disturbed and a periodic signal is added IN the first embodiment;
FIG. 6 is a schematic circuit diagram of a signal integration circuit in a second embodiment;
fig. 7 is a waveform diagram of the output of the signal integrating circuit IN the second embodiment when the carrier pulse train IN is disturbed and loses a periodic signal;
fig. 8 is a waveform diagram of the signal integration circuit IN the second embodiment output when the carrier pulse train IN is disturbed and a periodic signal is added.
In the figure, 100-infrared signal receiving chip; 101-infrared light sensing diode; 102-a current-to-voltage conversion module; 103-a preamplifier; 104-a gain adjustable amplifier; 105-a band-pass filter; 106-a comparator; 107-signal integration circuit; 109-automatic gain control module; 201-a first switch; 202-a first current source; 203-a voltage comparator; 204-a second switch; 205-a second current source; 206-a third switch; 207-a third current source; 208-hysteresis comparator; 209-a fourth switch; 210-a first capacitance; 211-a second capacitance; 212-Current limiting resistor.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely illustrative of example embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention.
It should be understood that, for the term "and/or" as may appear herein, it is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, B exists alone, and A and B exist at the same time; for the term "/and" as may appear herein, which describes another associative object relationship, it means that two relationships may exist, e.g., a/and B, may mean: a exists independently, and A and B exist independently; in addition, for the character "/" that may appear herein, it generally means that the former and latter associated objects are in an "or" relationship.
It will be understood that when an element is referred to herein as being "connected," "connected," or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, if a unit is referred to herein as being "directly connected" or "directly coupled" to another unit, it is intended that no intervening units are present. In addition, other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between … …" versus "directly between … …", "adjacent" versus "directly adjacent", etc.).
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof.
It should be understood that specific details are provided in the following description to facilitate a thorough understanding of example embodiments. However, it will be understood by those of ordinary skill in the art that the example embodiments may be practiced without these specific details. For example, systems may be shown in block diagrams in order not to obscure the examples in unnecessary detail. In other instances, well-known processes, structures and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.
Example 1:
the embodiment provides a signal integrating circuit, which includes a first switch 201, a first current source 202, a voltage comparator 203, a second switch 204, a second current source 205, a third switch 206, a third current source 207, a hysteresis comparator 208, a fourth switch 209, a first capacitor 210 and a second capacitor 211;
a signal input end of the first switch 201 is an Int _ in port and is used for accessing a pulse signal, a power supply input end of the first switch 201 is connected with a first current source 202, a first output end of the first switch 201 is grounded, and a power supply input end of the first switch 201 is also grounded through a first capacitor 210;
the non-inverting input terminal of the voltage comparator 203 is connected to the junction of the first switch 201 and the first capacitor 210, the inverting input terminal of the voltage comparator 203 is connected to the reference voltage Vref, and the output terminals of the voltage comparator 203 are respectively connected to the signal input terminals of the second switch 204 and the third switch 206;
the power input end of the second switch 204 is connected to a second current source 205, the output end of the second switch 204 is connected to the output end of a third switch 206, the power input end of the third switch 206 is connected to a third current source 207, and the junction point of the output end of the second switch 204 and the output end of the third switch 206 is grounded through a second capacitor 211;
the input end of the hysteresis comparator 208 is connected with the junction of the output end of the second switch 204 and the output end of the third switch 206, the output end of the hysteresis comparator 208 is connected with the signal input end of the fourth switch 209, and the power supply input end of the fourth switch 209 is the signal output end OUT of the signal integrating circuit.
The embodiment can perform integral operation on the input pulse signal, convert the integrated signal into a demodulated useful signal and perform shaping output. Specifically, in the present embodiment, the signal integration circuit 107 may output a waveform as shown in fig. 3 according to the carrier pulse train of the input signal and control.
Specifically, after the carrier pulse train signal IN input from the IN port is processed by other modules IN the infrared chip, the signal entering the signal integration circuit 107 from the Int _ IN port of the signal integration circuit is the pulse signal Int _ IN containing the carrier, and the pulse signal Int _ IN is transmitted to the first switch 201 IN the signal integration circuit 107. Then, the first current source 202 provides a constant current to charge the first capacitor 210 at the node a, and the pulse signal Int _ in is processed through the first switch 201; when the pulse signal Int _ in is at a high level, the first capacitor 210 at the node a is rapidly discharged to a low level, and when the pulse signal Int _ in is at a low level, the first capacitor 210 at the node a is gradually charged to a voltage less than the reference voltage Vref. The voltage comparator 203 may compare the a node voltage with the reference voltage Vref, and when the a node voltage is less than the reference voltage Vref, the voltage comparator 203 outputs a B node voltage having a low level signal, and when the a node voltage is greater than the reference voltage Vref, the voltage comparator 203 outputs a B node voltage having a high level signal, and since the a node voltage is less than the reference voltage Vref during the carrier burst period, the B node voltage is a low level signal as shown in fig. 3. The second current source 205 and the third current source 207 provide constant current for charging and discharging the second capacitor 211 at the node C, when the voltage at the node B is at a low level, the switch of the third switch 206 is turned off, the switch of the second switch 204 is turned on, and the circuit charges the second capacitor 211 at the node C; when the node B voltage is high, the switch of the third switch 206 is closed, the switch of the second switch 204 is opened, and the second capacitor 211 of the node C is discharged through the circuit, so that the waveform of the node C is a ramped square wave as shown in fig. 3 during the carrier period. When the voltage of the node C gradually rises and is greater than the high level threshold value, the voltage of the node D is changed from low level to high level; when the voltage at the node C gradually decreases and is less than the low threshold, the voltage at the node D changes from high to low, so that the voltage at the node C is shaped into a square wave D by the hysteresis comparator 208. The fourth switch 209 may output a signal OUT inverted from the C node. Therefore, the signal integrating circuit can change the useful signal containing the carrier wave into a useful signal without the carrier wave, and carry out shaping and drive output.
In this embodiment, the signal integration circuit further includes a current limiting resistor 212, the current limiting resistor 212 is connected to a power input terminal of the fourth switch 209, and a junction point of the power input terminal of the fourth switch 209 and the current limiting resistor 212 is a signal output terminal of the signal integration circuit. The current limiting resistor 212 may serve to limit the current of the fourth switch 209 to prevent the fourth switch 209 from being damaged.
In this embodiment, the third switch 206 is an NMOS transistor.
In this embodiment, the switch of the second switch 204 is a PMOS transistor.
It should be understood that the switch of the second switch 204 or the switch of the third switch 206 may also be implemented by a transistor, a field effect transistor, or the like, and can perform an on-off function between the second current source 205 or the third current source 207 and the second capacitor 211.
Example 2:
on the basis of embodiment 1, the present embodiment is defined as follows, in which the first current source 202 is a constant current source, and the first capacitor 210 is cooperatively configured as a constant capacitor.
Example 3:
in the operation of example 2, the following drawbacks exist: the signal integrator circuit 107 can only make the demodulated pulse width meet the requirement when the pulse train is not interfered, and when the carrier pulse train IN is interfered, the pulse width error of the demodulated output signal is large.
Specifically, when the carrier pulse train IN is disturbed, missing one cycle or a plurality of cycles, the waveforms of the respective nodes are as shown IN fig. 4. The signal IN is a high level signal at times T1 to T3, and the pulse signal Int _ IN is a low level signal at times T1 to T3. The pulse signal Int _ in is processed by the first switch 201 in fig. 2, when the pulse signal Int _ in is at a high level, the first capacitor 210 at the a-node is rapidly discharged to a low level, and when the pulse signal Int _ in is at a low level at time T1-T3, the voltage at the a-node is charged to a voltage greater than the reference voltage Vref at time T2. The voltage comparator 203 compares the A node voltage with the reference voltage Vref, when the A node voltage is less than the reference voltage Vref, the voltage comparator 203 outputs a B node voltage with a low level signal, and when the A node voltage at T2-T3 is greater than the reference voltage Vref, the voltage comparator 203 outputs a B node voltage with a high level signal, so the B node voltage outputs a high level at T2-T3. When the node B voltage is low, the switch of the third switch 206 is turned off, the switch of the second switch 204 is turned on, and the circuit charges the second capacitor 211 of the node C; when the node B voltage is high, the switch of the third switch 206 is closed, the switch of the second switch 204 is opened, and the second capacitor 211 of the node C is discharged through the circuit. Since the node B voltage is high at time T2-T3 during the carrier burst, the second capacitor 211 of the node C starts to discharge at time T2, and after the high level of the node B is over at time T3, the second capacitor 211 of the node C is charged again, the node C voltage rises to the high level threshold of the hysteresis comparator 208 at time T5, which is later than the time T4, which originally reaches the high level threshold voltage, so that the square wave pulse width output by the hysteresis comparator 208 is smaller, and the node C voltage forms a waveform with notches at time T2-T5, as shown in the node C waveform in fig. 4. The notched C-node voltage is shaped by the hysteresis comparator 208 into a square wave D of decreasing pulse width. The square wave D outputs a signal OUT with a smaller pulse width through the fourth switch 209.
During operation of the circuit, the circuit encounters an interference signal. When the pulse train carrier signal IN increases by one or more cycles, the pulse is at a high level at times T0 to T2, and the pulse signal Int _ IN entering the signal integration circuit is at a low level at times T0 to T2. The pulse signal Int _ in is processed by the first switch 201 in fig. 2, when the pulse signal Int _ in is at a high level, the first capacitor 210 at the a-node is rapidly discharged to a low level, and when the pulse signal Int _ in is at a low level at time T0-T2, the voltage at the a-node is charged to a voltage greater than the reference voltage Vref at time T1. The voltage comparator 203 compares the a-node voltage with the reference voltage Vref, and when the a-node voltage is less than the reference voltage Vref, the voltage comparator 203 outputs a B-node voltage having a low level signal, and when the a-node voltage is greater than the reference voltage Vref, the voltage comparator 203 outputs a B-node voltage having a high level signal, so that the B-node voltage is at a high level at times T1 to T2. When the node B voltage is low, the switch of the third switch 206 is turned off, the switch of the second switch 204 is turned on, and the circuit charges the second capacitor 211 of the node C; when the node B voltage is high, the switch of the third switch 206 is closed, the switch of the second switch 204 is opened, and the second capacitor 211 of the node C is discharged through the circuit. Since the node B voltage is at a high level at time T1-T2 during the carrier burst, the node C voltage cannot be directly discharged to the lowest voltage, and will start to discharge at time T1, and after the high level at time T2 ends, the node B voltage starts to charge, and starts to discharge again at time T4, the node C voltage reaches the low level threshold of the hysteresis comparator 208 at time T6, and is delayed from the time T5 at which the node C voltage originally reaches the low level threshold voltage, which results in a larger square wave pulse width output by the hysteresis comparator 208, and the node C voltage forms a notched waveform at time T1-T4, as shown in fig. 5. The notched C-node voltage is shaped into a square wave D of increasing pulse width by the hysteresis comparator 208. The square wave D outputs a signal OUT with a large pulse width through the fourth switch 209.
To solve the technical problem in embodiment 2, this embodiment improves the following to embodiment 1 to eliminate the interference so that the width of the output pulse width of the signal integration circuit remains unchanged:
in this embodiment, the first current source 202 is a variable current source, and the first capacitor 210 is a variable capacitor.
Specifically, the junction of the hysteresis comparator 208 and the fourth switch 209 is connected to the controlled terminal of the first current source 202; the junction of the hysteresis comparator 208 and the fourth switch 209 is also connected to the controlled terminal of the first capacitor 210.
IN the operation of the present embodiment, after the pulse train carrier signal IN loses the pulse train, the waveform of each node is high at the time T1 to T2 as shown IN fig. 7, and the pulse signal Int _ IN entering the signal integration circuit is low at the time T1 to T2.
The pulse signal Int _ in is processed by the first switch 201, when the pulse signal Int _ in is at a high level, the first capacitor 210 at the node a is rapidly discharged to a low level, and when the pulse signal Int _ in is at a low level, the first capacitor 210 at the node a is charged.
When the pulse signal Int _ in is at a low level at times T1 to T2, the voltage at the node D is at a low level, the current of the variable current source in the first current source 202 decreases, the capacitance of the first capacitor 210 at the node a increases, the charging speed of the first capacitor 210 at the node a decreases, and the voltage rising slope slows down, so that the voltage at the node a cannot rise to a voltage value greater than the reference voltage Vref in a low level interval at times T1 to T2. When the voltage of the node D is at a high level, the current of the variable current source in the first switch 201 returns to its original value, the capacitance of the first capacitor 210 at the node a returns to its original value, and the voltage of the first capacitor 210 at the node a returns to its original rising slope. Therefore, the voltage at the a-node cannot rise to a voltage value larger than the reference voltage Vref in the low level interval from T1 to T2.
Therefore, the voltage at the node a is less than the reference voltage Vref throughout the burst interval, and the voltage comparator 203 outputs the signal B at a low level. When the signal B is at a low level, the switch of the second switch 204 is turned on, the switch of the third switch 206 is turned off, and the signal integration circuit charges the second capacitor 211 at the node C; when the signal B is high, the switch of the second switch 204 is open, the switch of the third switch 206 is closed, and the second capacitor 211 at the C node is discharged, so that during the carrier period, the waveform at the C node is a ramped square wave as shown in fig. 7.
The voltage at the node C is shaped into a square wave D by the hysteresis comparator 208, and then processed by the fourth switch 209 and output the signal OUT, so that the pulse width of the output OUT signal is kept constant.
When the carrier pulse train is increased by one or more cycles, the waveform of each node is high at times T0 to T3, and the pulse signal Int _ in entering the signal integration circuit is low at times T0 to T3, as shown in fig. 8.
The pulse signal Int _ in is processed by the first switch 201, and when the pulse signal Int _ in is at a high level, the first capacitor 210 at the node a is rapidly discharged to a low level, and when the pulse signal Int _ in is at a low level, the circuit charges the first capacitor 210 at the node a.
When the pulse signal Int _ in is at a low level at times T0-T3, and the voltage at the node D is at a high level, the current in the first current source 202 increases, the capacitance of the first capacitor 210 at the node a decreases, and the rising slope of the voltage at the first capacitor 210 at the node a becomes steep, so that in the low level interval at times T0-T3, the voltage at the node a rapidly rises to a voltage value greater than the reference voltage Vref at time T1, and the voltage at the node B output by the node 203 will turn to a high level at time T1, which is earlier than the time T2 before the change; at time T3, the signal is inverted to low as before the change; the transition to the high level again at time T4 is earlier than time T5 before the alteration.
The second switch 204 controls the on/off of the second current source 205 and the second capacitor 211, and the third switch 206 controls the on/off of the third current source 207 and the second capacitor 211, so as to provide a constant current for the second capacitor 211 at the node C to perform charging and discharging. When the signal B is at a low level, the switch of the third switch 206 is turned off, the switch of the second switch 204 is turned on, and the circuit charges the second capacitor 211 at the node C; when the signal B is at a high level, the switch of the third switch 206 is closed, the switch of the second switch 204 is opened, and the second capacitor 211 at the node C is discharged. The second capacitor 211 at node C will begin to discharge at time T1, earlier than time T2 before the change; stopping discharging at the time T3 and starting charging as before modification; the discharge was started again at time T4, earlier than time T5 before the alteration. And the voltage at time T6 drops to the low level threshold of the hysteretic comparator 208, causing the D node voltage output by the hysteretic comparator 208 to flip ahead of time T7 prior to the change, such that the width of the pulse width of the output D node signal is larger than it was before the change by a smaller magnitude. The final OUT signal output via the fourth switch 209 is also of a smaller magnitude than the pulse width before modification is larger.
Example 4:
the embodiment discloses a signal processing method, which is implemented based on the signal integrating circuit in embodiment 3, and the signal processing method includes the following steps:
the first switch 201 charges or discharges the first capacitor 210, and then outputs a node a voltage; when the pulse signal is at a high level, the first switch 201 is closed, and the first capacitor 210 is discharged; when the pulse signal is at a low level, the first switch 201 is turned off, and the first capacitor 210 is charged;
the voltage comparator 203 compares the voltage of the node a with a reference voltage Vref, and determines whether the voltage of the node a is smaller than the reference voltage, if so, outputs a low-level node B voltage, and if not, outputs a high-level node B voltage;
the second switch 204 or the third switch 206 receives the node B voltage, charges or discharges the second capacitor 211, and then outputs a node C voltage; when the node B voltage is at a low level, the switch of the third switch 206 is turned off, the switch of the second switch 204 is turned on, and the second capacitor 211 is charged; when the node B voltage is at a high level, the switch of the third switch 206 is turned on, the switch of the second switch 204 is turned off, and the second capacitor 211 is discharged;
the hysteresis comparator 208 receives the C node voltage and then outputs a D node voltage; when the voltage of the node C gradually rises until the voltage is larger than the high level threshold value, the output voltage of the node D is changed from low level to high level; when the voltage of the node C gradually drops until the voltage of the node C is smaller than the low level threshold value, the output voltage of the node D is changed from the high level to the low level; thus, the voltage at node C is shaped into a square wave D by the hysteresis comparator 208;
the fourth switch 209 receives the D node voltage and then outputs a signal OUT that is inverted from the D node voltage.
Specifically, in the present embodiment, the first current source 202 and the first capacitor 210 are both controlled by the voltage of the node D.
In this embodiment, since the first current source 202 and the first capacitor 210 are both controlled by the voltage of the node D, when the received pulse signal is interfered, the interference can be effectively eliminated, thereby ensuring that the width of the pulse width output by the signal integration circuit remains unchanged.
Example 5:
the present embodiment discloses an infrared signal receiving system including the signal integrating circuit described in any one of embodiments 1 to 3. When the present embodiment includes the signal integration circuit in embodiment 3, the infrared signal receiving system in this embodiment can effectively eliminate interference when the received pulse signal is interfered, thereby ensuring that the width of the pulse width output by the signal integration circuit remains unchanged and avoiding signal distortion.
The various embodiments described above are merely illustrative, and may or may not be physically separate, as they relate to elements illustrated as separate components; if reference is made to a component displayed as a unit, it may or may not be a physical unit, and may be located in one place or distributed over a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: modifications of the technical solutions described in the embodiments or equivalent replacements of some technical features may still be made. And such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Finally, it should be noted that the present invention is not limited to the above alternative embodiments, and that various other forms of products can be obtained by anyone in light of the present invention. The above detailed description should not be taken as limiting the scope of the invention, which is defined in the claims, and which the description is intended to be interpreted accordingly.
Claims (10)
1. A signal integration circuit, characterized by: the circuit comprises a first switch (201), a first current source (202), a voltage comparator (203), a second switch (204), a second current source (205), a third switch (206), a third current source (207), a hysteresis comparator (208), a fourth switch (209), a first capacitor (210) and a second capacitor (211);
a signal input end of the first switch (201) is connected with a pulse signal, a power supply input end of the first switch (201) is connected with a first current source (202), a first output end of the first switch (201) is grounded, and a power supply input end of the first switch (201) is grounded through a first capacitor (210);
the non-inverting input end of the voltage comparator (203) is connected with the junction of the first switch (201) and the first capacitor (210), the inverting input end of the voltage comparator (203) is connected with a reference voltage, and the output end of the voltage comparator (203) is respectively connected with the signal input end of the second switch (204) and the signal input end of the third switch (206);
the power supply input end of the second switch (204) is connected with a second current source (205), the output end of the second switch (204) is connected with the output end of a third switch (206), the power supply input end of the third switch (206) is connected with a third current source (207), and the joint point of the output end of the second switch (204) and the output end of the third switch (206) is grounded through a second capacitor (211);
the input end of the hysteresis comparator (208) is connected with the junction point of the output end of the second switch (204) and the output end of the third switch (206), the output end of the hysteresis comparator (208) is connected with the signal input end of the fourth switch (209), and the power supply input end of the fourth switch (209) is the signal output end of the signal integrating circuit.
2. A signal integration circuit according to claim 1, wherein: the signal integration circuit further comprises a current limiting resistor (212), the current limiting resistor (212) is connected with a power input end of a fourth switch (209), and a joint point of the power input end of the fourth switch (209) and the current limiting resistor (212) is a signal output end of the signal integration circuit.
3. A signal integration circuit according to claim 1, wherein: the switch of the third switch (206) is an NMOS tube.
4. A signal integration circuit according to claim 1, wherein: the switch of the second switch (204) is a PMOS tube.
5. A signal integration circuit according to any one of claims 1 to 4, wherein: the first current source (202) is a constant current source.
6. A signal integration circuit according to any one of claims 1 to 4, wherein: the first current source (202) is a variable current source and the first capacitor (210) is a variable capacitor.
7. A signal integration circuit according to claim 6, wherein: the joint point of the hysteresis comparator (208) and the fourth switch (209) is connected with the controlled end of the first current source (202); the joint of the hysteresis comparator (208) and the fourth switch (209) is also connected with the controlled end of the first capacitor (210).
8. A signal processing method, characterized by: the signal integration circuit implementation of claim 7, the signal processing method comprising the steps of:
the first switch (201) charges or discharges the first capacitor (210), and then outputs the voltage of the node A; when the pulse signal is at a high level, the first capacitor (210) is subjected to discharge treatment; when the pulse signal is at a low level, the first capacitor (210) is charged;
a voltage comparator (203) compares the A node voltage with a reference voltage, judges whether the A node voltage is less than the reference voltage, outputs a low-level B node voltage if the A node voltage is less than the reference voltage, and outputs a high-level B node voltage if the A node voltage is not less than the reference voltage;
the second switch (204) or the third switch (206) receives the node B voltage, charges or discharges the second capacitor (211), and then outputs a node C voltage; when the voltage of the node B is at a low level, the second capacitor (211) is charged; when the voltage of the node B is at a high level, the second capacitor (211) is discharged;
a hysteresis comparator (208) receives the node C voltage and then outputs a node D voltage; when the voltage of the node C gradually rises until the voltage is larger than the high level threshold value, the output voltage of the node D is changed from low level to high level; when the voltage of the node C gradually drops until the voltage of the node C is smaller than the low level threshold value, the output voltage of the node D is changed from the high level to the low level;
the fourth switch (209) receives the D node voltage and then outputs a signal OUT that is inverted from the D node voltage.
9. A signal processing method according to claim 8, characterized by: the first current source (202) and the first capacitor (210) are both controlled by the voltage at the node D.
10. An infrared signal receiving system, characterized by: comprising a signal integration circuit as claimed in any one of claims 1 to 7.
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| CN101093983A (en) * | 2006-06-21 | 2007-12-26 | 夏普株式会社 | Comparing circuit and infrared receiver |
| CN204833690U (en) * | 2015-06-29 | 2015-12-02 | 南京日新科技有限公司 | Be applied to invariable delay circuit of infrared receipt chip |
| CN105379120A (en) * | 2013-06-12 | 2016-03-02 | 密克罗奇普技术公司 | Capacitive proximity detection using delta-sigma conversion |
| WO2016194651A1 (en) * | 2015-06-03 | 2016-12-08 | ソニーセミコンダクタソリューションズ株式会社 | Amplifier, control method therefor, and electronic equipment |
| KR102135332B1 (en) * | 2019-05-23 | 2020-07-17 | 주식회사 알파홀딩스 | Infrared receiving device, semiconductor circuit and electronic device including the same |
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| KR100433362B1 (en) * | 2002-07-11 | 2004-06-07 | 에이디반도체(주) | Impedance comparator integrated circuits |
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| CN101093983A (en) * | 2006-06-21 | 2007-12-26 | 夏普株式会社 | Comparing circuit and infrared receiver |
| CN105379120A (en) * | 2013-06-12 | 2016-03-02 | 密克罗奇普技术公司 | Capacitive proximity detection using delta-sigma conversion |
| WO2016194651A1 (en) * | 2015-06-03 | 2016-12-08 | ソニーセミコンダクタソリューションズ株式会社 | Amplifier, control method therefor, and electronic equipment |
| CN204833690U (en) * | 2015-06-29 | 2015-12-02 | 南京日新科技有限公司 | Be applied to invariable delay circuit of infrared receipt chip |
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