KR101658076B1 - DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same - Google Patents

DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same Download PDF

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Publication number
KR101658076B1
KR101658076B1 KR1020150008929A KR20150008929A KR101658076B1 KR 101658076 B1 KR101658076 B1 KR 101658076B1 KR 1020150008929 A KR1020150008929 A KR 1020150008929A KR 20150008929 A KR20150008929 A KR 20150008929A KR 101658076 B1 KR101658076 B1 KR 101658076B1
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KR
South Korea
Prior art keywords
signal
switch
ultra
stage
dc
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KR1020150008929A
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Korean (ko)
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KR20160089233A (en
Inventor
박명철
정승환
어윤성
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실리콘알엔디(주)
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection
    • H04L25/061Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction decision circuits providing symbol by symbol detection
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0292Arrangements specific to the receiver end
    • H04L25/0296Arrangements to ensure DC-balance

Abstract

The DC compensator of the UWB impulse receiver according to the present invention includes an analog circuit for receiving a first signal and a second signal as differential signals through a first stage and a second stage, A DC comparator of an ultra-wideband impulse receiver comprising a comparator for outputting a first signal; a switch connected between said first stage and said second stage; And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal, and the switch is turned on and off according to the control signal.

Description

[0001] The present invention relates to a DC compensator of an ultra-wideband impulse receiver and an ultra-wideband impulse receiver including the same.

The present invention relates to an ultra-wideband (UWB) impulse receiver. More particularly, it relates to an analog DC correction circuit of an ultra-wideband impulse receiver and to an ultra wideband impulse receiver including the same.

In an application field of an ultra-wideband wireless communication chip or a radar sensor, in a receiver circuit using a semiconductor integrated circuit, a base-band analog (BBA) processing an envelope signal of an impulse removing a high- ) Low frequency noise, DC offset and / or DC noise of the circuit may cause problems such as lowering the sensitivity of the receiver and further saturating the circuit.

In particular, in the case of an ultra-wideband signal, the baseband signal is also difficult to configure as a signal having a high bandwidth of 500 MHz or more. At this time, DC noise and / or DC voltage may be generated due to the non-ideal characteristics of the circuit, which may degrade receiver performance.

When the frequency of the baseband signal is relatively low, a technique of removing DC noise, low frequency noise, and / or DC offset voltage through a circuit such as conventional DC offset canceling (DCOC) has been used. However, since the baseband signal has a very high frequency in the case of an ultra-wideband receiver, the DCOC circuit for this purpose is very difficult to design and the possibility of oscillation is high. In addition, current consumption of the DCOC circuit and a chip area . In addition, in the UWB receiver, since the frequency of the baseband signal is high, it is difficult to use the conventional circuit structure, which makes it difficult to configure a circuit for setting the common mode voltage to the intermediate voltage of the power supply voltage, Since the common mode voltages are different from each other in each constitution of the band circuit, separation of the bias voltage is required.

There is a technique in which a DC block capacitor is connected in series to a signal line between circuit configurations in order to eliminate a DC voltage without using a DCOC circuit and solve a problem in which common mode voltages are different from each other. However, in this case, the DC voltage may shake for a certain period of time after the envelope voltage of the impulse is generated due to the DC blocking capacitor. Such shaking of the DC voltage may be mistaken as a signal, and erroneous data recognition may occur. Therefore, it is necessary to prevent the undesired fluctuation of the DC voltage generated by the DC blocking capacitor while reducing the current consumption and the circuit area of the chip.

Korean Patent Laid-Open No. 10-2006-0113750 (published on November 11, 2006)

It is an object of the present invention to provide a DC compensator of an ultra-wideband impulse receiver that eliminates undesired DC offset and / or DC voltage shaking in a baseband analog circuit of an ultra-wideband impulse receiver receiving a high frequency impulse signal, To provide an ultra wideband impulse receiver.

It is another object of the present invention to provide a DC compensator of an ultra-wideband impulse receiver capable of solving the problem of reception sensitivity deterioration due to generation of undesired DC voltage and / or shaking caused by using a DC blocking capacitor in an ultra-wideband impulse receiver To provide an ultra wideband impulse receiver.

The DC compensator of the UWB impulse receiver according to the present invention includes an analog circuit for receiving a first signal and a second signal as differential signals through a first stage and a second stage, A DC comparator of an ultra-wideband impulse receiver comprising a comparator for outputting a first signal; a switch connected between said first stage and said second stage; And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal, and the switch is turned on and off according to the control signal.

An ultra-wideband impulse receiver according to the present invention includes: an analog circuit unit receiving a first signal and a second signal, which are differential signals, through a first stage and a second stage; A comparator that receives a signal of the analog circuit unit and outputs a data signal as an output signal; A switch connected between said first end and said second end; And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal. The turn-on and turn-off of the switch are controlled according to the control signal.

Embodiments of the disclosed technique may have effects that include the following advantages. It should be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, since the embodiments of the disclosed technology are not meant to include all such embodiments.

According to the present invention, there is provided a DC compensator of an ultra-wideband impulse receiver that eliminates unwanted DC offset and / or DC voltage fluctuation in a baseband analog circuit of an ultra-wideband impulse receiver that receives an impulse signal of a high frequency, Thereby providing an ultra wideband impulse receiver including the same.

Also, according to the present invention, there is provided a DC compensator of an ultra-wideband impulse receiver capable of solving the problem of undesired DC voltage generation and / or deterioration of reception sensitivity due to shaking phenomenon caused by using a DC blocking capacitor in an ultra-wideband impulse receiver, To provide an ultra wideband impulse receiver.

Also, according to the present invention, it is possible to provide an ultra-wideband impulse receiver capable of eliminating a shaking phenomenon of a DC voltage without using a DCOC circuit and thereby optimizing sensitivity by eliminating a shaking noise voltage signal other than an envelope signal.

1 is a structural diagram of an ultra-wideband impulse receiver according to an embodiment.
2 is a voltage signal graph illustrating the problem caused by a DC blocking capacitor in an ultra-wideband impulse receiver.
3 is a structural diagram of an ultra wideband impulse receiver including a DC compensator according to an embodiment.
FIG. 4 is a circuit diagram of a switch disposed at an input terminal of an analog circuit of an ultra-wideband impulse receiver according to an embodiment.
5 is a structural diagram of a control signal generator included in an ultra-wideband impulse receiver according to an embodiment.
6 illustrates a signal output from each circuit of the UWB impulse receiver according to the embodiment.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive.

1 is a structural diagram of an ultra-wideband impulse receiver according to an embodiment. More specifically, FIG. 1 is an overall configuration diagram of an analog baseband circuit portion of an ultra-wideband impulse receiver according to an embodiment. 1, an envelope signal obtained by removing a high frequency carrier from an envelope detector (not shown) through an envelope detector is input to the analog baseband circuit portion of the UWB impulse receiver shown in FIG. 1 .

1, an ultra-wideband impulse receiver 100 includes a variable gain amplifier 110 (VGA), an integrator 130, a D2S amplifier 140 (Differential to Single Amplifier), and a comparator 150 .

The variable gain amplifier 110 may be a wideband variable gain amplifier that amplifies the envelope signal input through the envelope detector. In FIG. 1, a plurality of variable gain amplifiers 110 may be included. The signal amplified through the variable gain amplifier 110 is input to the integrator 130 to improve the noise and widen the signal to facilitate the detection of the envelope.

At this time, the variable gain amplifier 110 and the integrator 130 may be configured in a differential structure so as to be strong against common noise. Accordingly, the first signal and the second signal, which are differential signals, can be input to the variable gain amplifier 110 and the integrator 130 through the first stage and the second stage, respectively. The differential signal output from the integrator 130 is input to the D2S amplifier 140 which changes the differential signal to a single signal so that envelope detection is possible in the comparator 150. [

The comparator 150 receives a single signal and generates a digital data signal (represented by Rx Data in FIG. 1). This data signal is the final output data of the UWB impulse receiver 100 for OOK (On-Off Keying).

In an embodiment, the analog circuitry that receives the first signal and the second signal, which are differential signals, through the first and second stages, may include at least one of a variable gain amplifier 110, an integrator 130, and a D2S amplifier 140 . Other analog circuit portions receiving the differential signal may be included according to the embodiment.

Unless a DC offset eliminating circuit (DCOC) which removes the DC offset and the shaking of the DC voltage is used in the operation of the UWB 100 as described above, the DC offset voltage is applied to the variable gain amplifier 110 ) May be excessively amplified to saturate the circuit. Accordingly, the bandwidth of circuits such as the baseband variable gain amplifier 110 or the integrator 130 must be significantly increased, and it is extremely difficult to implement the conventional baseband circuit. However, in the case of DCOC for high-frequency baseband signals, the current consumption is very large and the chip area occupies a considerable amount. In addition, the DCOC circuit may be oscillated by the high-frequency baseband signal, and circuit design is very difficult. In addition, in the case of the ultra-wideband impulse receiver 100, it is difficult to implement a common-mode voltage regulation circuit that maintains a common-mode voltage between circuits due to a large bandwidth (for example, 500 MHz or more) of an input signal which is a baseband signal.

In order to solve this problem without using the DC offset elimination circuit (DCOC), the common mode voltage between each circuit can be separated by using a DC blocking capacitor.

For example, assuming that a DC blocking capacitor is disposed between the variable gain amplifier 110 and the integrator 130, an undesired DC voltage is generated due to the DC blocking capacitor and a shaking of the DC voltage occurs, The sensitivity of the ultra wideband impulse receiver 100 can be lowered.

2 is a voltage signal graph illustrating the problem caused by a DC blocking capacitor in an ultra-wideband impulse receiver 100. FIG. Referring to FIG. 2, after the normal envelope pulse E is generated at the time T1 in the input signal Vsig, a secondary and tertiary ringing signal D are generated due to the DC offset voltage and the envelope pulse E It can be seen that the phenomenon occurs. The generation of the pulse of the secondary ringing signal D at time T2 is shown in Fig.

In order to solve the problems that may occur by using such a DC blocking capacitor, the embodiment may further include a switch 181 connected in parallel to the input and / or output of each circuit unit.

3 is a structural diagram of an ultra wideband impulse receiver including a DC compensator according to an embodiment. 3, an ultra-wideband impulse receiver 100 including a DC compensator according to an embodiment includes an input 180-1, 180-2, and 180-3 of at least one analog baseband circuitry 110,130, 180-3, respectively. Also, according to an embodiment, the switch 181 may be placed at the output of the at least one analog baseband circuitry 110,130.

4 is a switch circuit diagram 180 disposed at the input of the analog circuitry of the ultra-wideband impulse receiver 100 according to the embodiment. Figure 4 shows a switch circuit diagram 180 in which a switch 181 is placed at the input of an integrator 130 but this is merely an example and the switch 181 is connected to the input of the at least one analog circuitry 110, / RTI > and / or the output of at least one analog circuitry 110,130.

In Fig. 4, only a portion 130p of the analog circuit portion (integrator 130 in Fig. 3) is shown. The switch 181 is connected in parallel between a first terminal (d1) through which the first signal is transmitted to the integrator (130) and a second terminal (d2) through which the second signal is transmitted.

At this time, the DC blocking capacitors 171 and 172 are connected to the first end d1 and the second end d2, respectively. The DC offset voltage may be cut through the DC blocking capacitors 171 and 172 at the inputs d1 and d2 of the integrator 130, respectively. Also, VDD / 2, which is 1/2 of the power supply voltage VDD, can be set to the voltage level of the integrator 130 through the very large resistances R1, R2, R3, and R4. Thus, even if an offset occurs in the front-end circuit portion (here, the variable gain amplifier 110), the output DC voltage level of the front-end circuit portion may not affect the input terminal of the integrator 130. [

The switch 181 can be controlled to turn on and turn off according to the control signal c. The short time switch 181 is turned on immediately after the envelope pulse E is detected in the input signal so that the undesired DC voltage or the shaking of the DC voltage can be canceled by connecting the first signal and the second signal which are differential signals. That is, by turning on the switch 181 through the control signal C delayed by a predetermined time after the envelope pulse E is generated so as not to affect the envelope pulse representing the data, the second and third ringing signals D It is possible to prevent the sensitivity of the receiver from deteriorating.

At this time, the DC blocking capacitors 171 and 172 may be disposed at the input terminal of the analog circuit unit (for example, the integrator 130) and the switch 181 may be disposed at the output terminal of the analog circuit unit.

5 is a structural diagram of a control signal generator included in the ultra-wideband impulse receiver 100 according to the embodiment. In an embodiment, the control signal generator 150 'may include a comparator 150 and a delay unit 190. The comparator 150 receives a single signal from the D2S amplifier 150 and outputs a digital data signal as the output signal P0. At this time, the output signal P0 of the comparator 150 may be output as the final data signal RX Data through the buffer 155.

The delay unit 190 receives the output signal P0 of the comparator 150 and generates a control signal c delayed by a predetermined time with respect to the output signal P0. The delay unit 190 may be configured through inverter chains 191, ..., 195, 196, and 197. At this time, the inverter chain may be configured according to the time delay size required to turn on the switch 181 by delaying the input signal Vsig of FIG. 2 for a predetermined time so as not to affect the primary envelope pulse D. For example, the unit delay time of an inverter chain is determined by the impedance value seen at one buffer output. The delay time through one buffer can be determined by the resistance of the back-end buffer input seen from the output of the previous stage and the value of the capacitor connected in parallel. Therefore, the time tau in which the control signal c output from the delay unit 190 is delayed with respect to the output signal P0 is obtained by adding the delay times of the inverters 191, ..., 195, 196, and 197 The same.

At this time, the required delay time can be determined in consideration of signal delay and the like in the circuit so as not to affect the primary envelope pulse D. For example, the switch 181 does not need to be turned on exactly at T2 to remove the ringing signal D occurring at T2 time in Fig. The DC correction according to the embodiment of the present invention can be performed if the switch 181 is turned on before the T2 time point when the ringing signal D is generated after the T1 point of time when the envelope pulse E occurs. Therefore, the delay time? Of the delay unit 190 according to the embodiment of the present invention can be set so that the switch 181 is turned on between the T1 time and the T2 time.

6 illustrates a signal output from each circuit of the UWB impulse receiver according to the embodiment. 6 (a) illustrates a differential signal that is input to an ultra-wideband impulse receiver 100 as shown in FIG. 3 by removing the high-frequency carrier through an envelope detector (not shown). 6 (b) illustrates a differential signal in which the differential signal of FIG. 6 (a) is amplified through the variable gain amplifier 110. FIG. 6 (C) illustrates a differential signal in which the differential signal of FIG. 6 (b) passes through the integrator 130 to improve the noise performance and the like. 6 (d) illustrates a single signal that has passed through the D2S amplifier 140. 6 (e) illustrates the output signal P0 of the comparator 150. 6 (f) illustrates a delayed control signal (c) that has passed through the delay unit 190.

The comparator 150 according to the embodiment may be a circuit that outputs a high value when a signal equal to or higher than the reference voltage S is input. A single signal represented by a solid line including the pulse of Fig. 6 (d) may be input to the comparator 150. [ At this time, the comparator 150 can output a signal P0 including a pulse as shown in Fig. 6 (e) by outputting a high value only when a signal equal to or higher than the reference voltage S is input.

6 (f), the control signal c is delayed from the output signal P0 of the comparator 150 by the delay time?. At this time, the delay time τ is changed from the time point t1 at which the high pulse starts at the output signal P0 of the comparator 150 as shown in FIG. 6 (e) And a time t2 at which the pulse E is terminated. The switch 181 located at the input terminals 180-1, 180-2, and 180-3 of the analog circuit unit of FIG. 3 is turned on during a period in which the control signal c delayed from the output signal P0 has a high value, The secondary and tertiary ringing signals D indicated by dotted lines in Figs. 6 (b), (c) and (d) can be removed. The ringing signal D before the DC correction is performed in FIGS. 6 (b), 6 (c) and 6 (d) is indicated by the dotted line and the signal after the DC correction through the switch 181 is performed according to the embodiment of the present invention Is indicated by a solid line. As can be seen from the above, DC voltages other than the envelope signal can be removed from the signal of the UWB 100 according to the embodiment of the present invention.

In this specification, the DC compensator of ultra-wideband impulse receiver 100 may refer to including switch 181 described above. Further, in this specification, the DC compensator may be referred to as further including a delay unit 190 for delaying the output signal P0 of the comparator 150. [ Also, in this specification, the DC compensator may refer to further including a DC blocking capacitor 171, 172. In addition, the DC compensator herein may also refer to including a comparator 150.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100: Ultra-wideband impulse receiver
110: Variable gain amplifier
130: integrator
140: D2S amplifier
150: comparator
150 ': control signal generator
171, 172: DC blocking capacitors
181: Switch
190: delay section

Claims (12)

  1. An analog circuit part for receiving a first signal and a second signal which are differential signals through a first stage and a second stage, and a comparator for receiving a signal of the analog circuit part and outputting a data signal as an output signal, Compensator,
    A switch connected between said first end and said second end;
    A DC blocking capacitor coupled to the first and second ends, respectively; And
    And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal,
    Wherein the switch is turned on and off according to the control signal and the first stage and the second stage are shorted to each other when the switch is turned on,
    A DC compensator of an ultra wideband impulse receiver.
  2. delete
  3. The method according to claim 1,
    Wherein the circuitry comprises at least one of a variable gain amplifier, an integrator, and a D2S amplifier.
  4. The method according to claim 1,
    Wherein the voltage of the circuit portion is set to 1/2 of the power supply voltage (VDD).
  5. The method according to claim 1,
    Wherein the first signal and the second signal are envelope signals of an impulse with the carrier signal removed.
  6. 6. The method of claim 5,
    Wherein the switch is turned on after a predetermined time delay from a time when a pulse corresponding to the envelope is generated in the output signal.
  7. An analog circuit unit receiving the first signal and the second signal, which are differential signals, through the first and second stages;
    A comparator that receives a signal of the analog circuit unit and outputs a data signal as an output signal;
    A switch connected between said first end and said second end;
    A DC blocking capacitor coupled to the first and second ends, respectively; And
    And a delay unit receiving the output signal of the comparator and generating a control signal delayed by a predetermined time with respect to the output signal,
    Wherein the switch is turned on and off according to the control signal and the first stage and the second stage are shorted to each other when the switch is turned on,
    Ultra wideband impulse receiver.
  8. delete
  9. 8. The method of claim 7,
    Wherein the circuitry comprises at least one of a variable gain amplifier, an integrator, and a D2S amplifier.
  10. 8. The method of claim 7,
    And the voltage of the circuit portion is set to 1/2 of the power supply voltage (VDD).
  11. 8. The method of claim 7,
    Wherein the first signal and the second signal are envelope signals of an impulse with the carrier signal removed.
  12. 12. The method of claim 11,
    Wherein the switch is turned on after a predetermined time delay from a time when a pulse corresponding to the envelope is generated in the output signal.
KR1020150008929A 2015-01-19 2015-01-19 DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same KR101658076B1 (en)

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KR1020150008929A KR101658076B1 (en) 2015-01-19 2015-01-19 DC Correction Circuit of Ultra-Wideband Impulse Receiver and Ultra-Wideband Impulse Receiver including the same
PCT/KR2015/001153 WO2016117747A1 (en) 2015-01-19 2015-02-04 Dc corrector for ultra-wideband impulse receiver, and ultra-wideband impulse receiver including same

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060540A (en) 2001-08-10 2003-02-28 Pioneer Electronic Corp Receiver

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
KR910002355B1 (en) * 1988-03-24 1991-04-20 안시환 Serial data transmitting and receiving circuit between the main system and the keyphone
US6826388B1 (en) * 1999-11-15 2004-11-30 Renesas Technology Corp. Mobile communication apparatus including dividers in transmitter and receiver
JP4366401B2 (en) 2004-01-02 2009-11-18 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Method, receiver and system for receiving a transmission signal (a robust non-coherent receiver for PAM-PPM signals)
JP4332095B2 (en) * 2004-10-01 2009-09-16 パナソニック株式会社 DC offset calibration system
JP5376581B2 (en) * 2009-03-06 2013-12-25 独立行政法人情報通信研究機構 IR-UWB transceiver
KR101058703B1 (en) * 2009-08-31 2011-08-22 삼성전기주식회사 Time Division Frequency Correction and DC Offset Rejection Circuit for Continuous-Time Analog Filters

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Publication number Priority date Publication date Assignee Title
JP2003060540A (en) 2001-08-10 2003-02-28 Pioneer Electronic Corp Receiver

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