CN217307679U

CN217307679U - DC offset cancellation circuit for receiver and implementation system

Info

Publication number: CN217307679U
Application number: CN202220365624.3U
Authority: CN
Inventors: 谈熙
Original assignee: Wuxi Qilian Electronic Technology Co ltd
Current assignee: Wuxi Qilian Electronic Technology Co ltd
Priority date: 2022-02-23
Filing date: 2022-02-23
Publication date: 2022-08-26
Anticipated expiration: 2032-02-23

Abstract

The utility model relates to a direct current offset cancelling circuit and implementation system for receiver includes the amplifier circuit based on electric capacity feedback, and amplifier circuit provides biased bias network (102), amplifier circuit includes operational amplifier (101), the input of difference input signal via electric capacity back input operational amplifier (101), and the cross-over connection has feedback electric capacity between the output of operational amplifier (101) and the input, above-mentioned bias network (102) are connected to the input of operational amplifier (101) and provide the bias. The utility model relates to a direct current offset cancelling circuit and implementation system for receiver, it eliminates the direct current offset through electric capacity feedback mode.

Description

DC offset cancellation circuit for receiver and implementation system

Technical Field

The utility model relates to an intermediate frequency receiver circuit and receiver system based on variable gain amplifier circuit realizes that direct current imbalance eliminates for eliminate the direct current imbalance of receiver belongs to analog integrated circuit design field.

Background

Currently, low-if and zero-if receivers have adopted mainstream fully integrated radio frequency transceiver architecture, but the problem of DC offset (DC offset) inherent in the system is not solved well all the time, so that the if signal is distorted or even saturated due to large DC offset.

The conventional solutions today include: method 1, inter-stage capacitance alternating current coupling; method 2, medium frequency analog feedback direct current elimination; method 3, digital-assisted dc cancellation. Among them, the method 1 needs a large ac coupling capacitor in order to not lose the low frequency part of the signal, thereby resulting in a huge waste of chip area, and therefore, in order to save chip area, sometimes has to be connected to the outside of the chip through pins, increasing extra pins and peripheral BOM cost. The 2 nd method is usually based on a variable gain amplifier with resistance feedback or a low-pass filter, and a low-pass filter is connected to a feedback channel to achieve the effect of high-pass filtering. But also requires a large capacitance to achieve a low high-pass cut-off frequency, and the dc cancellation effect is limited. The 3 rd method needs to add a dc offset voltage to the signal path by means of an analog-to-digital converter (ADC), a digital baseband and a digital-to-analog converter (DAC) and injecting current to eliminate DCOC, and has a complicated structure and limited accuracy and range.

In summary, the above conventional methods are not ideal. The ideal method for eliminating the DC offset is realized by adopting a feedback amplifier of capacitive coupling, thereby not only achieving the effect of removing the DC by the capacitive AC coupling, but also providing variable gain. But has the disadvantage that the gate common mode voltage of the input transistors is difficult to determine. In addition, in the conventional structure, direct current bias is provided through a series resistor, and signals flow away from a low-resistance bias path to lose the amplification effect, so that the circuit is abnormal in function. In order to eliminate the influence of the dc bias, a series resistor needs to be increased, or a dual-gate amplifier is adopted, but the impedance of the input node is increased by similar methods, which still causes the problem that the dc bias voltage cannot be fixed. Therefore, an ideal dc offset cancellation circuit that can solve the above problems is needed.

Disclosure of Invention

An object of the utility model is to overcome above-mentioned not enough, provide a direct current is unregulated and is eliminated circuit and implementation system for receiver based on electric capacity feedback intermediate frequency amplifier, it eliminates the direct current imbalance through electric capacity feedback mode.

The purpose of the utility model is realized like this:

a direct current offset cancellation circuit for a receiver comprises an amplifying circuit based on capacitance feedback and a bias network for providing bias by the amplifying circuit; the amplifying circuit comprises an operational amplifier, wherein a differential input signal is input to the input end of the operational amplifier through a capacitor, a feedback capacitor is connected between the output end and the input end of the operational amplifier in a crossing manner, and the bias network is connected to the input end of the operational amplifier to provide bias.

Preferably, the bias network comprises a first switch tube and a second switch tube, gates of the first switch tube and the second switch tube are connected to the signal control end, sources of the first switch tube and the second switch tube are connected to the direct-current voltage end, and drains of the first switch tube and the second switch tube are connected to two input ends of the operational amplifier respectively.

Preferably, the first switch tube and the second switch tube are both NMOS tubes.

Preferably, when the signal control end inputs a high level to the gates of the first switching tube and the second switching tube, the first switching tube and the second switching tube are conducted, the direct current voltage end provides bias voltage for the input end of the operational amplifier, and the direct current offset cancellation circuit is in a bias mode standby mode; when the signal control end inputs a low level to the grids of the first switching tube and the second switching tube, the first switching tube and the second switching tube are cut off, the input end of the operational amplifier obtains direct current bias, and at the moment, the direct current offset elimination circuit enters an amplification working mode.

Preferably, the output differential dc voltage of the operational amplifier is input to the detection module, and the output terminal of the detection module is connected to the signal control terminal.

Preferably, the detection module is a detector or an analog-to-digital converter.

A receiver implementation system is based on the direct current offset cancellation circuit for performing direct current offset cancellation on received signals.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses get rid of the direct current based on electric capacity alternating current feedback coupling to the effect that the direct current imbalance was eliminated has been realized. Meanwhile, the bias network constructed based on the MOS tube can provide variable gain, so that the fixation of direct current bias voltage is realized, and the distortion of signal processing is avoided.

Drawings

Fig. 1 is a circuit block diagram of a dc offset cancellation circuit for a receiver according to the present invention.

Fig. 2 is a circuit diagram of a bias network in a dc offset cancellation circuit for a receiver according to the present invention.

Fig. 3-a is a schematic diagram of a signal of the present invention when the dc offset cancellation circuit for a receiver is in the envelope mode.

Fig. 3-b is a signal diagram of the dc offset cancellation circuit for a receiver according to the present invention in the pulse mode.

Fig. 4 is a circuit diagram of the receiver in the self-adaptive conducting operating mode with the dc offset cancellation circuit.

Wherein:

operational amplifier 101, bias network 102.

Detailed Description

The utility model relates to a direct current offset canceling circuit and implementation system for receiver includes the amplifier circuit based on electric capacity feedback and provides DC offset's biasing network 102 to the amplifier circuit of electric capacity feedback.

Referring to fig. 1, a differential input signal Vin of the operational amplifier 101 is ac-coupled to an input terminal of the operational amplifier 101 through a capacitor C11 and a capacitor C12, and a feedback capacitor C21 and a feedback capacitor C22 are connected between the input terminal and an output terminal of the operational amplifier 101.

Ideally, the closed loop gain of the amplifier circuit is:

Av=20*log(C12/C22)

therefore, by adjusting the capacitance values of the feedback capacitor C21 and the feedback capacitor C22, the closed-loop gain of the amplifier circuit can be changed, and a variable gain amplifier is realized.

However, the design difficulty of this circuit is the determination of the dc voltage at the operational amplifier input nodes Vp1 and Vp 2.

In a conventional CMOS operational amplifier, all MOS devices need to be dc biased to ensure that the devices operate normally in dc. With the conventional resistive feedback type amplifier structure (the capacitor is changed to the resistor in fig. 1), since the output and the input of the amplifier are connected through the resistor, the output and the input dc voltages are the same. The dc voltage at the input can be determined by simply providing a dc bias to the output. A common method is to determine the dc voltage at the output terminal by using a common mode negative feedback structure, and then determine the dc bias voltage of the input tube.

After the capacitor feedback structure is adopted in fig. 1, no direct current path exists between the output voltage and the input voltage, so that the direct current working point of the operational amplifier cannot be determined. If an additional bias network is adopted to provide direct-current voltage, a low-resistance path is introduced into a bias circuit, so that signal loss, gain reduction and abnormal operation of an amplifier are caused.

Referring to fig. 2, in order to ensure the normal operation of the operational amplifier 101, the present patent provides a dc voltage through the bias network 102 shown in fig. 2, wherein the NMOS transistors M1 and M2 both operate in a switching state, and the gate control voltage Vctrl switches on and off of the switch.

In operation, when the control voltage Vctrl is at a high level, the NMOS transistors M1 and M2 are turned on, and transmit the dc voltage Vcm to the input terminals Vp1 and Vp2 of the operational amplifier 101 to provide a bias voltage to the input terminal of the operational amplifier 101, and at this time, the circuit is in a bias mode (standby mode).

When the signal needs to be amplified, the control voltage Vctrl is switched to a low level, the NMOS transistors M1 and M2 are turned off, and since the charges at the input terminals Vp1 and Vp2 of the operational amplifier 101 have no low-impedance bleed-off path, a dc bias is obtained for the input terminal of the operational amplifier 101, and at this time, the circuit enters an amplification mode (operating mode).

Meanwhile, the control voltage Vctrl and the switching NMOS transistors M1 and M2 may adopt several ways according to the actual communication protocol of the radio frequency system:

referring to fig. 3-a, envelope conduction, for some communication systems, useful signal transmission takes only milliseconds or less. Therefore, the Vctrl can be used to switch off the switching tubes M1 and M2 before the useful signal comes, and switch on the switching tubes M1 and M2 after the signal transmission is completed.

Referring to fig. 3-b, the pulse-on mode requires the amplifier to be in an operating mode for a long time for a communication system with a long transmission time, and if the voltages at the input nodes Vp1 and Vp2 are changed due to charge migration, a pulsed control voltage Vctrl can intermittently generate a high level to return the input tube bias voltage to a normal state. Because the pulse time is short, the frequency is higher than that of a useful signal, and the pulse can be filtered by a low-pass filter, so that the influence on the signal-to-noise ratio can be ignored.

Referring to fig. 4, in the adaptive conduction mode, the output differential dc voltage Vout is input to the detection module for detection, and then a control voltage Vctrl is output, the detection module determines whether the input dc level of the operational amplifier 101 is shifted, and if the shift reaches a certain magnitude, the detection module outputs the control voltage Vctrl, and the control voltage Vctrl makes the switching tubes M1 and M2 conduct, so that the operating state of the operational amplifier 101 is maintained at a normal state. The detection module can adopt detectors, analog-to-digital converters and the like in various forms, and the conduction time of the output voltage is specifically determined by system requirements.

In addition: it should be noted that the above-mentioned embodiment is only a preferred embodiment of the present patent, and any modification or improvement made by those skilled in the art based on the above-mentioned conception is within the protection scope of the present patent.

Claims

1. A kind of direct current offset cancelling circuit for receiver, characterized by that: the bias circuit comprises an amplifying circuit based on capacitance feedback and a bias network (102) for providing bias by the amplifying circuit;

the amplifying circuit comprises an operational amplifier (101), wherein a differential input signal is input to an input end of the operational amplifier (101) through a capacitor, a feedback capacitor is connected between an output end and an input end of the operational amplifier (101) in a crossing manner, and the bias network (102) is connected to the input end of the operational amplifier (101) to provide bias.

2. The dc offset canceling circuit for a receiver according to claim 1, wherein: the bias network (102) comprises a first switch tube (M1) and a second switch tube (M2), gates of the first switch tube (M1) and the second switch tube (M2) are connected to the signal control end, sources of the first switch tube (M1) and the second switch tube (M2) are connected to the direct-current voltage end, and drains of the first switch tube (M1) and the second switch tube (M2) are connected to two input ends of the operational amplifier (101) respectively.

3. The dc offset canceling circuit for a receiver according to claim 2, wherein: the first switch tube (M1) and the second switch tube (M2) are both NMOS tubes.

4. The dc offset canceling circuit for a receiver according to claim 2, wherein:

when the signal control end inputs a high level to the grids of the first switch tube (M1) and the second switch tube (M2), the first switch tube (M1) and the second switch tube (M2) are conducted, the direct current voltage end provides bias voltage for the input end of the operational amplifier (101), and the direct current offset cancellation circuit is in a bias mode standby mode at the moment;

when the signal control end inputs low level to the grids of the first switch tube (M1) and the second switch tube (M2), the first switch tube (M1) and the second switch tube (M2) are cut off, the input end of the operational amplifier (101) obtains direct current bias, and at the moment, the direct current offset cancellation circuit enters an amplification working mode.

5. The dc offset cancellation circuit for a receiver according to claim 2, wherein: the output differential direct-current voltage of the operational amplifier (101) is input into the detection module, and the output end of the detection module is connected to the signal control end.

6. The circuit of claim 5, wherein: the detection module is a detector or an analog-to-digital converter.

7. A receiver implemented system, characterized by: the system is based on a receiver of any one of claims 1-6, which performs dc offset cancellation on the received signal by using a dc offset cancellation circuit.