JP5198013B2 - Method, apparatus and system for reducing the DC coupling capacitance of a switching amplifier - Google Patents

Description

  The present invention relates to an amplifier and a sound reproduction method, and more particularly to a digital amplifier and a sound reproduction method in which a reference voltage related to an analog DC component of an output node is provided to the reference node.

  A variety of amplifiers are used to amplify audio signals. Such amplifiers include class A, class B, class AB, and class D amplifiers. In general, class D amplifiers have superior power efficiency compared to class A, class B and class AB amplifiers.

  Class D amplifiers are typically used in portable devices by emphasizing the reduction in size and weight of portable devices. For example, headphones associated with various portable audio players include class D amplifiers.

  FIG. 1 is a block diagram showing a general class D amplifier 100, and FIG. 2 is a diagram showing an example of signal processing performed by each component of the class D amplifier 100 of FIG. Hereinafter, the operation of the class D amplifier 100 will be described with reference to FIGS.

  The class D amplifier 100 includes a pulse width modulation signal generator 10, a class D drive circuit 20, a low-pass filter 30, and a coupling capacitor C2. Referring to FIG. 2, the PWM signal generator 10 receives the first signal 13 or the second signal 11. The first signal 13 shown in FIG. 2A is a rectangular wave. For example, the first signal 13 can be received from an internal or external clock. Hereinafter, the second signal 11 received by the class D amplifier 100 is referred to as an audio input signal 11. For convenience of explanation, FIG. 2 shows the received audio input signal 11 as a sine wave. The PWM signal generator 10 processes the first signal 13 and the second signal 11 and outputs a PWM signal 15 to the class D drive circuit 20. The duty ratio of the PWM signal 15 shown in FIG. 2B varies according to the received audio input signal 11. The class D drive circuit 20 amplifies the PWM signal 15 and provides an amplified signal 25 as shown in FIG. 2C to the low-pass filter 30. The low pass filter 30 averages the amplified signal 25 to reduce high frequency noise and provides a filtered signal 31 to the coupling capacitor C2. The coupling capacitor C2 removes the DC voltage from the filtered signal 31 and generates an output signal 33. As shown in FIG. 1, the output signal 33 is provided to a speaker 150 connected to the class D amplifier 100, and the speaker 150 has a resistance RL. For example, the speaker 150 can be a speaker included in a headphone for a portable audio device.

  As described above, the general class D amplifier 100 includes the coupling capacitor C <b> 2 for removing the DC voltage from the filtering signal 31. The coupling capacitor C2 is used to prevent a high current from flowing into the headphones, and serves to keep the headphones in a continuous state. When the resistance RL of the speaker 150 is about 16 to 32Ω, the capacitance of the coupling capacitor C2 is typically in the range of 100 to 470 μF. However, since the size of the capacitor of 100 to 470 μF is considerably large, the general class D amplifier 100 including one or two coupling capacitors is disadvantageous for miniaturization. Therefore, an amplifier that does not require a coupling capacitor has been developed.

  FIG. 3 is a block diagram showing a conventional amplifier, which is an amplifier that does not include a coupling capacitor disclosed in Patent Document 1. In FIG.

  Referring to FIG. 3, the amplifier 200 includes a first amplifier 21 that drives the left headphone speaker, a second amplifier 22 that drives the right headphone speaker, and a DC voltage converter 40. The first amplifier 21 is connected to the headphone load RL via the connection lead 51, and the second amplifier 22 is connected to the headphone load RL via the connection lead 52. Each of the first amplifier 21, the second amplifier 22, and the DC voltage converter 40 receives the voltage VDD. The DC voltage converter 40 uses a charge pump circuit including a capacitor or inductor to store and transfer energy. The DC voltage converter 40 is used in place of the coupling capacitor and is located in series between the output of the first amplifier 21 and the left headphone speaker and between the output of the second amplifier 22 and the right headphone speaker. Can do.

  The charge pump circuit of the conventional amplifier shown in FIG. 3 generates a negative voltage −VDD with respect to ground. The negative voltage -VDD provided by the charge pump circuit supplies power to the first amplifier 21 and the second amplifier 22 and drives the amplifier between a positive voltage and a negative voltage. The negative voltage -VDD is provided to ground so that the headphone amplifier is biased to ground voltage so that the input signal can be amplified without clipping.

  As described above, the conventional headphone amplifier 200 can operate between VDD and −VDD such that the headphone speaker represented by RL is biased to 0V. That is, the lead 51 of the first amplifier 21 and the lead 52 of the second amplifier 22 can be connected to the headphone speaker RL without using a DC coupling capacitor.

Since the DC voltage converter 40 is implemented with a capacitive or inductive charge pump, that is, the charge pump circuit includes a capacitor or inductor for storing or transferring energy, an artificially negative voltage from the power supply voltage VDD. -Charging and discharging are required to generate VDD. Compared to a conventional amplifier circuit including a coupling capacitor as in the class D amplifier 100 described above, the charging and discharging operations of the DC voltage converter 40 significantly increase power consumption.
International Patent Publication No. WO2006 / 031304

  In order to solve the above problems, an object of the present invention is to provide a digital amplifier for reducing the DC component of an amplified pulse width modulation signal.

  Another object of the present invention is to provide a reference voltage generator for the digital amplifier.

  Another object of the present invention is to provide a method for reducing the DC component of an amplified pulse width modulated signal applied to an input node of a load.

  To achieve the above object, a digital amplifier according to an embodiment of the present invention includes a pulse width modulation signal generator that receives an input signal and outputs an amplified pulse width modulation signal, and the amplified pulse width modulation signal. A filter for filtering and providing a filtered pulse width modulated signal to an input node of the load, and a reference voltage corresponding to an intermediate value between a maximum voltage and a minimum voltage of the filtered pulse width modulated signal. And a reference voltage generator for reducing a DC component of the filtered pulse width modulation signal.

  A coupling capacitor may not be included between the load input node and the filter. The filtered pulse width modulated signal may be provided directly from the filter to the input node of the load. The reference voltage generator may not be a charge pump.

  The pulse width modulation signal generator may include a pulse width modulation circuit that receives the input signal and provides a pulse width modulation signal, and a drive circuit that amplifies the pulse width modulation signal.

  The reference voltage generator includes a voltage distributor that distributes a power supply voltage to provide a distribution voltage, and an analog buffer that buffers the distribution voltage and provides a reference voltage to a reference node of the load. it can. The digital amplifier may further include a comparator that compares an input node voltage of the load with a reference node voltage of the load and provides a comparison result to the reference voltage generator. The distribution voltage can be determined using the result.

  The voltage distributor includes a variable resistor that changes based on a control signal generated from information stored in a register, and can distribute the power supply voltage based on the control signal.

  The filter may include a low pass filter, and the load may include at least one speaker.

  A digital amplifier according to an embodiment of the present invention includes a pulse width modulation circuit that receives an input signal and provides a pulse width modulation signal corresponding to the input signal, and a filtered pulse width by filtering the pulse width modulation signal. A filter that provides a modulation signal directly to the input node of the load; and a reference voltage generator that provides a reference voltage directly to the reference node of the load to reduce the DC component of the filtered pulse width modulation signal. be able to.

A digital amplifier according to an embodiment of the present invention includes a pulse width modulation signal generator that receives an input signal and outputs an amplified pulse width modulation signal;
A filter for filtering the amplified pulse width modulation signal and providing the filtered pulse width modulation signal to an input node of the load; and a reference voltage having a positive value of a constant magnitude is provided to the reference node of the load. A reference voltage generator for reducing a DC component of the filtered pulse width modulation signal.

  A reference voltage generator of a digital amplifier according to an embodiment of the present invention includes a voltage divider that distributes a power supply voltage and provides a distribution voltage based on a change in an amplified pulse width modulation signal provided to an input node of a load. An analog buffer that provides a reference voltage buffered with the distribution voltage to a reference node of the load to reduce a DC component of the amplified pulse width modulated signal of the digital amplifier.

  A method for reducing the DC component of a pulse width modulation signal according to an embodiment of the present invention generates a reference voltage corresponding to an intermediate value between a maximum voltage and a minimum voltage of an amplified pulse width modulation signal applied to an input node of a load. And providing the reference voltage to a reference node of the load.

  In one embodiment, a method for reducing the DC component of the pulse width modulation signal includes: generating a pulse width modulation signal by pulse width modulating a received signal; amplifying the pulse width modulation signal; Filtering the amplified pulse width modulated signal.

  Providing the reference voltage to a reference node of the load includes receiving a power supply voltage and at least one control signal; and determining the power supply voltage based on the at least one control signal to determine the reference voltage. Distributing. Can be included.

  In one embodiment, the method may further include comparing an input node voltage of the load with a reference node voltage, and controlling generation of the reference voltage based on a comparison result.

  The step of controlling the generation of the reference voltage includes a step of distributing a signal corresponding to the comparison result into two, and a step of buffering the distributed signal to obtain the reference voltage. it can.

  The reference voltage may be set as a positive value.

A digital amplifier according to an embodiment of the present invention includes a pulse width modulation signal generator that receives an input signal and outputs an amplified pulse width modulation signal;
A filter for filtering the amplified pulse width modulation signal and providing the filtered pulse width modulation signal to an input node of a load; and a reference voltage corresponding to an average voltage of the filtered pulse width modulation signal. A reference voltage generator for providing to a reference node of a load and reducing a DC component of the filtered pulse width modulated signal.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 4 is a block diagram illustrating an amplifier circuit having a reference voltage generator according to an embodiment of the present invention.

  Referring to FIG. 4, the amplifier circuit 300 includes a pulse width modulation driving circuit 320, a low-pass filter 330, and a reference voltage generator 340. The amplifier circuit 300 provides an output signal to the output node NA and a reference signal to the reference node NB. As shown in FIG. 4, one or more speakers 390 may be connected to the output node NA and the reference node NB. Thus, the output node NA of the amplifier circuit 300 corresponds to the input node of the speaker 390 having the load RL.

  The PWM drive circuit 320 can be a class D drive circuit. The PWM drive circuit 320 modulates and amplifies the input signal by pulse width and outputs an amplified PWM signal indicating the input signal. This input signal can be an audio input signal AIJ.

  The amplified PWM signal is provided to the low pass filter 330. The low-pass filter 330 averages the amplified PWM signals to reduce high frequency components such as noise signals, and outputs a filtered signal through the output node NA.

  The reference voltage generator 340 generates a reference voltage VR from the power supply voltage VDD. For example, the reference voltage generator 340 generates a reference voltage VR having a voltage value between a high voltage (eg, maximum voltage) of the output signal and a low voltage (eg, minimum voltage) of the output signal. The output signal is a filtered signal provided to the speaker input node through output node NA. The value of the reference voltage VR generated by the reference voltage generator 340 may be a constant having a substantially constant magnitude. According to the embodiment, the reference voltage VR can be set to a predetermined value. The predetermined value may correspond to a value between the high voltage value and the low voltage value of the output signal. For example, when the high voltage value of the output signal is 5V and the low voltage value of the output signal is 0V, the predetermined value of the reference voltage VR can be set to 2.5V. An example of the configuration of the reference voltage generator 340 will be described later with reference to FIGS.

  Referring to FIG. 4, the amplifier circuit 300 is coupled to one or more speakers 390 having a resistance RL. The speaker can be a headphone speaker for a portable audio device. In particular, the output signal of the low pass filter 330 is provided to the first input node of the speaker via the output node NA (ie, the input node of the speaker 390), and the reference signal generated by the reference voltage generator 340 is the reference node NB. To the second input node of the speaker.

  As shown in FIG. 4, the amplifier circuit 300 according to an embodiment of the present invention does not include a coupling capacitor connected in series between the amplifier circuit 300 and the load RL. For example, there is no coupling capacitor between the low pass filter 330 and the speaker 390 having the load RL. That is, the filtered and amplified pulse width modulated signal is directly provided from the low-pass filter 330 to the speaker 390 having the load RL. Therefore, compared to the amplifier 100 of FIG. 1 including at least one coupling capacitor, the chip area of the amplifier circuit 300 according to an embodiment of the present invention can be reduced. The amplifier circuit 300 includes a reference voltage generator 340 instead of the charge pump. Therefore, the power consumption of the amplifier circuit 300 according to an embodiment of the present invention can be reduced as compared with the amplifier circuit 200 of FIG.

  FIG. 5 is a diagram illustrating an example of the configuration of the PWM driving circuit 320, the low-pass filter 330, and the reference voltage generator 340 included in the amplifier circuit 300 according to an embodiment of the present invention.

  Referring to FIG. 5, the PWM driving circuit 320 includes a PWM control circuit 321 and a switching amplifier 325. The PWM control circuit 321 performs pulse width modulation on the received audio input signal AI and outputs a PWM signal to the switching amplifier 325. The switching amplifier 325 illustrated in FIG. 5 includes a PMOS transistor TU and an NMOS transistor TD connected in series between the power supply voltage VDD and the ground. The source of the PMOS transistor TU is connected to the power supply voltage VDD, the first output signal of the PWM control circuit is applied to the gate of the PMOS transistor TU, and the drain of the PMOS transistor TU is the input of the low-pass filter 330 and the NMOS transistor TD. Connected to the drain. The drain of the NMOS transistor TD is connected to the input of the low-pass filter 330 and the drain of the PMOS transistor, the second output signal of the PWM control circuit is applied to the gate of the NMOS transistor TD, and the source of the NMOS transistor TD is grounded. Connected. As described above, the transistor of the switching amplifier 325 provides an amplified PWM signal by being driven by the PWM signal provided from the PWM control circuit 321.

  The low pass filter 330 shown in FIG. 5 includes an inductor and a capacitor. As described above, the low-pass filter 330 averages the amplified PWM signal to reduce high-frequency components such as a noise signal, and provides an output signal to the output node NA. Since the configuration and operation of the low-pass filter are well known to those skilled in the art, further explanation is omitted.

  FIG. 5 shows an embodiment of the reference voltage generator 340. The reference voltage generator 340 shown in FIG. 5 includes a voltage divider 341 and an analog buffer 345. The analog buffer 340 is also called a unity-gian amplifier or voltage follower. The voltage distributor 341 generates a distribution voltage VV from the power supply voltage VDD. The analog buffer 345 stabilizes the distribution voltage and provides the stabilized distribution voltage to the output node NB. Hereinafter, the stabilized distribution voltage is referred to as a reference voltage VR. The analog buffer 345 includes an operational amplifier, stabilizes the distribution voltage VV, and feeds back the distribution voltage buffered at the inverting input of the operational amplifier to provide the reference voltage VR.

  As shown in FIG. 5, the reference voltage generator 340 can be coupled to a resistor 347. The register 347 is used to control the distribution voltage provided by the voltage distributor 341.

  FIG. 6 is a diagram illustrating a voltage divider 341 included in a reference voltage generator according to an embodiment of the present invention.

  Referring to FIG. 6, the voltage distributor 341 includes a first variable resistor RU and a second variable resistor RD connected in series between the power supply voltage VDD and the ground. The first variable resistor RU and the second variable resistor RD are connected via a voltage distribution node NV of the voltage distributor 341, and the distribution voltage VV of the voltage distribution node NV is provided to the analog buffer 345. The resistance value of the first variable resistor RU is controlled based on the first control signal OSCU, and the resistance value of the second variable resistor RD is controlled based on the second control signal OSCD. Each of the first control signal OSCU and the second control signal OSCD is based on information stored in the register 347 or based on a voltage comparison result between the output node NA and the reference node NB at the initialization stage of the amplifier circuit 300. You can also. This will be described in detail later. The distribution voltage VV of the voltage distributor 341 is calculated as Equation 1.

  As described above, in one embodiment, the first control signal OSCU and the second control signal OSCD can be controlled based on information stored in the register 347. That is, the distribution voltage VV can be controlled based on the information stored in the register 347. For example, the information stored in the register 347 includes the voltage value input by the user, information related to the load RL of one or more speakers 390, the resistance values of the first and second variable resistors RU and RD, and the first value. And a table indicating a relationship between the second control signals OSCU and OSCD, a standard indicating a manufacturing process deviation of an actual component of the amplifier circuit 300, and the like.

  For example, when the power supply voltage VDD is approximately 5.0V and the first variable resistor RU and the second variable resistor RD are approximately 1 kΩ, the distribution voltage VV is approximately 2.5V according to Equation 1. However, the actual components in the voltage divider may be different due to manufacturing process deviations, etc., and therefore stored in the register 347 to control the first control signal OSCU and the second control signal OSCD. This information can be used by the voltage divider 341 to further control the distribution voltage VV. As described above, the distribution voltage VV is stabilized by the analog buffer 345, and the reference voltage VR is provided to the reference node NB.

  In one embodiment, each of the first control signal OSCU and the second control signal OSCD may be based on a voltage comparison result between the output node NA and the reference node NB at the initialization stage of the amplifier circuit 300.

  FIG. 7 shows an amplifier circuit 300 according to an embodiment of the present invention, in which the distribution voltage VV output by the voltage divider 341 is based on a voltage comparison between the output node NA of the amplifier and the reference node NA at the initialization stage. It is a figure which shows being controlled.

  The amplifier circuit 300 of FIG. 7 includes an offset detector 350 as well as the components of the amplifier circuit 300 described above in connection with FIG. The offset detector 350 detects the difference between the reference voltage provided to the speaker 380 through the reference node NB and the DC voltage provided to the speaker 390 through the output node (ie, the input node of the speaker 390) NA. The offset detector 350 illustrated in FIG. 7 includes a comparator COM. The first input of the comparator COM is connected to the output node NA of the amplifier circuit 300, and the second input of the comparator COM is connected to the reference node NB. The output of the comparator COM is provided to the voltage divider 341. The voltage distributor 341 controls the distribution voltage VV of the voltage distributor 341 based on the output of the offset detector 350.

  While the amplifier circuit 300 is not in the mute state, the output signal of the amplifier circuit 300 oscillates according to the audio input signal AI, and the comparator COM can be deactivated. However, during the mute state of the amplifier circuit 300, the comparator COM is activated and detects the difference between the reference voltage VR of the reference node NB and the DC voltage output from the output node NA of the amplifier circuit 300. The mute state of the amplifier circuit 300 can correspond to the initialization stage.

  An offset control signal corresponding to the voltage difference detected during the mute state can be used by the reference voltage generator 340 to control the reference voltage VR. The offset control signal can be used to generate the first control signal OSCU and the second control signal OSCD, and thus the resistance values of the variable resistors RU and RD included in the voltage divider 341 can be controlled. . For example, the first control signal OSCU and the second control signal OSCD generated based on the offset control signal can be used to make the reference voltage VR the same as the DC component of the output signal. The DC component of the output signal during a state other than the mute state corresponds to the value of the output signal when the amplifier circuit 300 is in the mute state. That is, the resistance value of the variable resistor can be controlled so that the difference between the DC voltage component provided from the output node NA of the amplifier circuit 300 and the reference voltage VR provided from the reference node NB becomes 0V.

  FIG. 8 is a diagram illustrating the operation of the amplifier circuit 300 according to one embodiment of the present invention. 8A and 8B, a first time period T1 indicates a period in which the amplifier circuit 300 is in a mute state, and a second time period T2 indicates that the amplifier circuit 300 is in a non-mute state and the speaker is an output signal. The section driven according to this is shown.

  Referring to FIG. 8A, the high voltage value of the output signal VA is VDD and the low voltage value of the output signal is 0. In FIG. 8A, the reference voltage VR is VDD / 2. FIG. 8B shows a voltage signal VA-VR obtained by subtracting the reference voltage applied to the reference node NB from the output signal applied to the output node NA. Accordingly, the speaker 390 having the resistance value RL is driven by an output signal having a voltage that changes between VR and VR during the second time interval T2.

  FIG. 9 is a circuit diagram showing a digital amplifier 300c coupled to the 3-terminal connector 60 according to one embodiment of the present invention. As shown in FIG. 9, a reference voltage generator 340 provides a reference voltage VR to a common reference node NC, which is used as a reference node for two or more PWM driving circuits and a low-pass filter. .

  Referring to FIG. 9, the 3-terminal connector includes a first terminal 1, a second terminal 2, and a third terminal 3. The first PWM driving circuit 320a receives the first audio input signal AIa and provides the amplified first PWM signal to the first low-pass filter 330a. The first low-pass filter 330a filters the amplified first PWM signal and provides the filtered signal to the first output node NA1 connected to the first terminal 1 of the 3-terminal connector 60. The second PWM driving circuit 320b receives the second audio input signal AIb and provides the amplified second PWM signal to the second low-pass filter 330b. The second low-pass filter 330b filters the amplified second PWM signal and provides the filtered signal to the second output node NA2 connected to the second terminal 2 of the 3-terminal connector 60. In FIG. 9, the reference voltage generator 340 provides the reference voltage to the common reference node NC connected to the third terminal 3 of the connector 6.

  The configurations of the first PWM driving circuit 320a and the second PMW driving circuit 320b are the same as or similar to the configuration of the PWM driving circuit 320 described with reference to FIG. The configurations of the first low-pass filter 330a and the second low-pass filter 330b are the same as or similar to the configurations of the low-pass filter 330 described in relation to FIG. Furthermore, the reference voltage generator 340 shown in FIG. 9 is the same as the reference voltage generator described with reference to FIG.

  However, the input signals received by the first PWM driving circuit 320a and the second PWM driving circuit 320b can be different. Since the input signals received by the first PWM driving circuit 320a and the second PWM driving circuit 320b can be different, the first PWM driving circuit 320a, the second PWM driving circuit 320b, the first low-pass filter 330a and / or At least one of the component values of the second low-pass filter 330b may be different depending on each input signal. For example, the operating critical value of the first low-pass filter 330a is different from the operating critical value of the second low-pass filter 330b due to the difference between the input signal of the first PWM driving circuit 320a and the input signal of the second PWM driving circuit 320b. Can do. In this case, the capacitance and inductance value of the first low-pass filter 330a are different from the capacitance and inductance value of the second low-pass filter 330b.

  The 3-terminal connector 60 is configured to couple with the connector plug 70. The three-terminal connector plug 70 includes a first terminal 1 a coupled to the first terminal 1 of the three-terminal connector 60, a second terminal 2 a coupled to the second terminal 2 of the three-terminal connector 60, and the three-terminal connector 60. A third terminal 3 a coupled to the third terminal 3 is included. The first terminal 1a, the second terminal 2a, the third terminal 3a, and the main body 5 are separated by the insulator 4.

  Referring to FIG. 9, various external devices can be coupled to the amplifier circuit 300c. The various external devices can be headphone speakers, stereo speakers, recording devices and the like.

  The amplifier circuit 300c of FIG. 9 does not include the offset detector 350 shown in FIG. 7, but those skilled in the art to which the present invention belongs will be able to implement the offset detector within the scope of the technical idea of the present invention. It will be understood that nine amplifier circuits 300c can be included.

  FIG. 10 is a flowchart illustrating a method for reducing the DC component of an amplified pulse width modulation signal applied to an output node of an amplifier circuit according to an embodiment of the present invention.

  Referring to FIG. 10, the method for reducing the DC component includes receiving an input signal S110, pulse width modulating the received input signal S120, and amplifying the PWM signal 130. For example, the audio input signal received by the PWM driving circuit 320 can be pulse width modulated and amplified by the PWM driving circuit 320 as described above.

  As shown in FIG. 10, the method for reducing the DC component also includes a step S140 of filtering the amplified PWM signal and a step S150 of outputting the filtered signal to an output node. For example, the low pass filter 330 can receive the amplified PWM signal from the PWM drive circuit 320, filter the amplified PWM signal, and provide the filtered signal to the output node NA.

  Referring to FIG. 10, the method for reducing the DC component includes a step S160 of distributing a power supply voltage to generate a reference voltage. For example, the reference voltage generator 340 distributes the power supply voltage and generates a reference voltage corresponding to a voltage value between a high voltage and a low voltage of the output signal. When the high voltage value of the output signal is 5V and the low voltage value of the output signal is 0V, the reference voltage is about 2.5V.

  Also, the generated reference voltage is provided to the reference node (S170). As a result, the differential voltage VA-VB is applied to the load connected between the output node and the reference node to reduce the DC voltage component of the output signal. For example, the reference voltage generator 340 provides the reference voltage to the reference node, and thus the differential voltage VA-VB is applied to one or more speakers connected between the output node NA and the reference node NB.

  Those skilled in the art to which the present invention pertains may be that steps S160 and S170 may be performed by the reference voltage generator 340, and steps S110 to S150 may be performed by the PWM driving circuit 320 and the low-pass filter 330. You will understand what you can do.

  FIG. 11 is a flowchart illustrating a method for reducing the DC component of an amplified pulse width modulation signal applied to an output node of an amplifier circuit according to another embodiment of the present invention.

  The embodiment of FIG. 11 includes the steps described in connection with the embodiment of FIG.

  Referring to FIG. 11, the method for reducing the DC component of the pulse width modulation signal compares the DC voltage component of the filtered signal provided to the output node with the voltage provided to the reference node, S161, and the comparison result. And step S162 for controlling the generation of the reference voltage based on. For example, the offset detector 350 compares the DC voltage component of the filtered signal provided to the output node NA with the voltage provided to the reference node NB. According to one embodiment, the difference between the DC voltage component of the filtered signal and the reference voltage can be zero. The comparison result of the offset detector 350 is provided to the voltage distributor 341, and the generation of the reference voltage can be controlled so that the difference between the DC voltage component of the filtered signal and the reference voltage becomes zero. For example, the comparison result of the offset detector 350 can be used to control the first control signal OSCU and the second control signal OSCD.

  The method for reducing the DC component of the digital amplifier and the pulse width modulation signal according to the embodiment of the present invention as described above can remove the coupling capacitor without providing a charge pump for generating a negative power supply voltage. it can.

  In addition, a digital amplifier adapted to a three-terminal connector according to an embodiment of the present invention can remove a coupling capacitor without providing a charge pump for generating a negative power supply voltage, and can simultaneously connect to a common reference node. Two connected audio playback devices can be driven.

  Further, the digital amplifier reference voltage generator and the DC component reducing method of the pulse width modulation signal according to the embodiment of the present invention can accurately reduce the voltage offset of the output node and the reference node.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to these embodiments, and any person who has ordinary knowledge in the technical field to which the present invention belongs can be used without departing from the spirit and spirit of the present invention. The present invention can be modified or changed.

It is a block diagram which shows a general class D amplifier. It is a figure which shows the example of the signal processing implemented by each component of the class D amplifier of FIG. It is a block diagram which shows the conventional amplifier. 1 is a block diagram illustrating an amplifier circuit including a reference voltage generator according to an embodiment of the present invention. It is a figure which shows an example of a structure of the PWM drive circuit, filter, and reference voltage generator which were included in the amplifier circuit by one Example of this invention. FIG. 3 illustrates a voltage divider that can be included in a reference voltage generator according to an embodiment of the present invention. In the amplifier circuit according to an embodiment of the present invention, the distribution voltage output by the voltage divider is controlled based on the voltage comparison between the output node of the amplifier and the reference node in the initialization stage. is there. It is a figure which shows operation | movement of the amplifier circuit by one Example of this invention. FIG. 3 is a circuit diagram illustrating a digital amplifier coupled to a 3-terminal connector according to an embodiment of the present invention. 6 is a flowchart illustrating a method for reducing a DC component of an amplified pulse width modulation signal applied to an output node of an amplifier circuit according to an embodiment of the present invention. 6 is a flowchart illustrating a method of reducing a DC component of an amplified pulse width modulation signal applied to an output node of an amplifier circuit according to another embodiment of the present invention.

Explanation of symbols

320 Class D driving circuit 321 PWM controller 325 Switching amplifier 330 Low pass filter 340 Reference voltage generator 341 Voltage distributor 345 Analog buffer 350 Offset sensor NA Output node NB Reference node NC Common reference node

Claims (5)

A pulse width modulation signal generator for receiving an input signal and outputting an amplified pulse width modulation signal;
A filter for filtering the amplified pulse width modulated signal and providing the filtered pulse width modulated signal to an input node of a load;
A reference voltage corresponding to an intermediate value between the maximum voltage and the minimum voltage of the filtered pulse width modulation signal is provided to the reference node of the load to reduce the DC component of the filtered pulse width modulation signal. A generator,
Including no coupling capacitor between the input node of the load and the filter,
The reference voltage generator is
A voltage distributor for distributing the power supply voltage and providing a distribution voltage;
An analog buffer for buffering the distributed voltage and providing the reference voltage to a reference node of the load, receiving a power supply voltage and at least one control signal, and determining the reference voltage a Lud Jitaruanpu to distribute the supply voltage based on one of the control signals,
A comparator that compares the input node voltage of the load with a reference node voltage of the load and provides a comparison result to the reference voltage generator;
The comparator is activated during the mute state of the digital amplifier and deactivated during the non-mute state,
The digital amplifier according to claim 1, wherein the voltage divider determines the distribution voltage based on a comparison result of the mute state so that a voltage of the reference node matches a DC component of an output signal.   The digital amplifier according to claim 1, wherein the filtered pulse width modulation signal is provided directly from the filter to an input node of the load.   2. The digital amplifier according to claim 1, wherein the reference voltage generator is not a charge pump. The pulse width modulation signal generator receives the input signal and provides a pulse width modulation signal; and a pulse width modulation circuit;
The digital amplifier according to claim 1, further comprising a drive circuit that amplifies the pulse width modulation signal. The voltage divider is
Comprises a variable resistance that varies based on the control signal generated from the information stored in the register, the digital amplifier according to claim 1, wherein the distributing the power supply voltage based on the control signal.

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