WO2016192153A1 - 列翻转模式的液晶显示面板及其驱动方法 - Google Patents

列翻转模式的液晶显示面板及其驱动方法 Download PDF

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Publication number
WO2016192153A1
WO2016192153A1 PCT/CN2015/082268 CN2015082268W WO2016192153A1 WO 2016192153 A1 WO2016192153 A1 WO 2016192153A1 CN 2015082268 W CN2015082268 W CN 2015082268W WO 2016192153 A1 WO2016192153 A1 WO 2016192153A1
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Prior art keywords
thin film
film transistor
column
pixels
pixel
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PCT/CN2015/082268
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English (en)
French (fr)
Inventor
左清成
谢剑星
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/777,525 priority Critical patent/US9865207B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a column flip mode liquid crystal display panel and a driving method thereof.
  • LCD Liquid Crystal Display
  • advantages such as thin body, power saving, no radiation, etc., such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or Laptop screens, etc., dominate the field of flat panel display.
  • PDA personal digital assistant
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply a driving voltage on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the liquid crystal display panel comprises a plurality of pixels arranged in an array, each pixel is electrically connected to a thin film transistor (TFT), the gate of the TFT is connected to the horizontal scanning line, and the drain is connected to the vertical.
  • TFT thin film transistor
  • the data line in the direction, the source is connected to the pixel electrode. Applying a sufficient voltage on the horizontal scanning line causes all TFTs electrically connected to the scanning line to be turned on, so that the signal voltage on the data line can be written into the pixel, and the transmittance of the liquid crystal is controlled to achieve a display effect.
  • the liquid crystal molecules have a characteristic that if a liquid crystal molecule is polarized by applying a co-directional voltage to the liquid crystal molecules for a long time, even if the voltage is canceled, the liquid crystal molecules may not be rotated by the electric field due to the destruction of the characteristics, so the liquid crystal
  • the display panel must be driven by AC. When the screen is displayed, the liquid crystal molecules are turned over at a certain frequency to prevent the liquid crystal molecules from being biased in the same direction and losing their activity.
  • the liquid crystal display panel supports a plurality of flip modes, such as a dot flip mode, a row flip mode, a column flip mode, etc., and the way to achieve flipping is mainly by constantly alternating the positive and negative polarities of the TFT source voltage (ie, the positive of the signal voltage, Negative polarity), or constantly alternating the positive and negative polarity of the common electrode to achieve the purpose of AC drive.
  • a dot flip mode ie, the positive of the signal voltage, Negative polarity
  • the common electrode ie, the positive of the signal voltage, Negative polarity
  • the voltage difference between the source voltage (ie, the signal voltage) of the positive and negative polarity of the TFT and the gate voltage is not Similarly, in the same time, the charging effect of the TFT source on the pixel will be different, which further causes the brightness and darkness of each pixel in the display screen to be different, and finally the display effect of the screen is not uniform.
  • a liquid crystal display panel of a conventional column flip mode includes a plurality of vertical data lines arranged in parallel and arranged in sequence, a plurality of horizontal scanning lines arranged in parallel and sequentially arranged, and an array arrangement.
  • a plurality of pixels, each of which is provided with a pixel driving circuit, and a plurality of pixel driving circuits in the same row of pixels are electrically connected to the scanning lines corresponding to the pixels, and the plurality of pixel driving circuits in the same column of pixels are electrically connected.
  • the pixel driving circuit includes: a driving thin film transistor T1, a gate of the driving thin film transistor T1 is electrically connected to a scan line corresponding to a row of the pixel, and a source is electrically connected to a data line corresponding to the column of the pixel, and the drain
  • the other end of the storage capacitor CST1 is electrically connected to the common electrode VCOM
  • the other end of the liquid crystal capacitor CLC1 is electrically connected to the other end of the liquid crystal capacitor CLC1. It is connected to the common electrode VCOM. Since the liquid crystal display panel shown in FIG. 1 is driven by the column flip mode, referring to FIG. 3 and FIG. 4, the polarity of the source voltage of the driving thin film transistor T1 of each adjacent two columns of pixels is opposite, between each adjacent two frames.
  • the driving process of displaying the one-frame picture of the liquid crystal display panel of the conventional column flip mode is: multiple scan lines are sequentially scanned line by line, and N and M are positive integers, when scanning When the Nth scan line is reached, the Nth scan line supplies a scan signal GATE(N) to the gate of the driving thin film transistor T1 of the Nth row of pixels, and all of the driving thin film transistors T1 of the Nth row of pixels are turned on, for the phase
  • the adjacent Mth column and the M+1th column pixel, the Mth column data line S(M) writes a positive polarity voltage to the source of the driving thin film transistor T1 of the Nth row and the Mth column pixel, and the writing time length is t
  • the M+1th column data line S(M+1) adjacent to the Mth column data line S(M) is written with a negative polarity voltage to the source of
  • An object of the present invention is to provide a column flip mode liquid crystal display panel capable of balancing the charging effects of positive and negative voltages on adjacent columns of pixels, and compensating for charging differences between positive and negative voltages on adjacent columns of pixels. Make the picture display even.
  • the object of the present invention is to provide a driving method of a liquid crystal display panel in a column flip mode, which can balance the charging effect of the positive and negative voltages on two adjacent columns of pixels, and compensate the positive and negative voltages for the adjacent two columns of pixels.
  • the difference in charging makes the picture display even.
  • the present invention provides a liquid crystal display panel of a column flip mode, comprising a plurality of vertical data lines arranged in parallel and sequentially arranged, a plurality of horizontal scanning lines arranged in parallel and sequentially arranged, and an array.
  • a plurality of pixels arranged in a matrix each of which is provided with a pixel driving circuit;
  • a plurality of pixel driving circuits in the same row of pixels are electrically connected to the scanning lines corresponding to the row of pixels; respectively, each data line is left and right
  • An odd-numbered column pixel on both sides and a plurality of pixel driving circuits in an even-numbered column of pixels are electrically connected to the data line;
  • the pixel driving circuit includes: a driving thin film transistor, a charge control thin film transistor, a storage capacitor, and a liquid crystal capacitor; wherein one of the charge control thin film transistor in the even column pixel and the charge thin film transistor in the odd column pixel is controlled by a high potential And open, the other is turned on by the low potential control;
  • the charge control thin film transistor in the even column of pixels and the gate of the charge thin film transistor in the odd column of pixels are electrically connected to the clock signal; the clock signal alternately provides high and low potentials, and controls charging control in the even column of pixels
  • the thin film transistor and the charged thin film transistor in the odd column of pixels are alternately turned on;
  • the scan line provides a scan signal with a duration of a first duration
  • the clock signal provides a second duration.
  • the high potential control of the charge control thin film transistor in the even column of pixels or the charge control thin film transistor in the odd column of pixels is turned on, while the data line provides a positive polarity voltage, so that the source voltage of the driving thin film transistor in the even column of pixels or The source voltage of the driving thin film transistor in the odd-numbered column pixel is positive polarity, and the even-numbered column pixel or the odd-numbered column pixel is charged; after that, the clock signal is further supplied with a third time duration of low potential control at the second duration
  • the charge control thin film transistor in the odd-numbered column pixel or the charge control thin film transistor in the even-numbered column pixel is turned on, and at the same time, the data line provides a negative polarity voltage, so that the source voltage of the driving thin film transistor in the odd-numbered column pixel or The source voltage of the
  • the scan line provides a scan signal with a duration of a first duration
  • the clock signal first provides a charge control thin film transistor or an odd column of pixels in a high-potential control even-numbered column with a duration of a third duration.
  • the internal charge control thin film transistor is turned on, at the same time, the data
  • the line provides a negative polarity voltage such that the source voltage of the driving thin film transistor in the even-numbered column pixel or the source voltage of the driving thin film transistor in the odd-numbered column pixel is negative polarity, and the even-numbered column pixel or the odd-numbered column pixel is charged;
  • the clock signal is further provided with a second potential duration to control the charge control thin film transistor or the charge control thin film transistor in the even column of pixels in the odd column of pixels that are not turned on in the third duration, and at the same time, the data
  • the line provides a positive polarity voltage such that the source voltage of the driving thin film transistor in the odd-numbered column pixel or the source voltage of the driving thin film transistor in the even-numbered column pixel is positive polarity, and charging the odd-numbered column pixel or the even-numbered column pixel;
  • the first duration is the sum of the second duration and the third duration.
  • the third duration is not equal to the second duration.
  • the third duration is greater than the second duration.
  • the gate of the driving thin film transistor is electrically connected to the scan line corresponding to the row of the pixel, the source is electrically connected to the drain of the charge control thin film transistor, and the drain is electrically connected to one end of the storage capacitor and one end of the liquid crystal capacitor;
  • the source of the charge control thin film transistor is electrically connected to the data line corresponding to the column of the pixel; the other end of the storage capacitor and the other end of the liquid crystal capacitor are electrically connected to the common electrode;
  • the charge control thin film transistor in the odd column pixel is a P type thin film transistor, the charge control thin film transistor in the even column pixel is an N type thin film transistor; or the charge control thin film transistor in the odd column pixel is an N type thin film
  • the transistor, the charge control thin film transistor in the even column of pixels is a P-type thin film transistor.
  • the driving thin film transistor and the charge control thin film transistor are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the invention also provides a liquid crystal display panel with a column flip mode, comprising a plurality of vertical data lines arranged in parallel and sequentially arranged, a plurality of horizontal scanning lines arranged in parallel and arranged in sequence, and an array arranged in an array.
  • a pixel each pixel is provided with a pixel driving circuit; a plurality of pixel driving circuits in the same row of pixels are electrically connected to the scanning lines corresponding to the pixels; an odd number on each of the left and right sides of each data line a plurality of pixel driving circuits in the column pixel and an even column pixel are electrically connected to the data line;
  • the pixel driving circuit includes: a driving thin film transistor, a charge control thin film transistor, a storage capacitor, and a liquid crystal capacitor; wherein one of the charge control thin film transistor in the even column pixel and the charge thin film transistor in the odd column pixel is controlled by a high potential And open, the other is turned on by the low potential control;
  • the charge control thin film transistor in the even column of pixels and the gate of the charge thin film transistor in the odd column of pixels are electrically connected to the clock signal; the clock signal alternately provides high and low potentials, and controls charging control in the even column of pixels Thin film transistor and charged thin film crystal in odd column pixels
  • the tubes are alternately opened;
  • the scan line provides a scan signal with a duration of a first duration
  • the clock signal provides a second duration.
  • the high potential control of the charge control thin film transistor in the even column of pixels or the charge control thin film transistor in the odd column of pixels is turned on, while the data line provides a positive polarity voltage, so that the source voltage of the driving thin film transistor in the even column of pixels or The source voltage of the driving thin film transistor in the odd-numbered column pixel is positive polarity, and the even-numbered column pixel or the odd-numbered column pixel is charged; after that, the clock signal is further supplied with a third time duration of low potential control at the second duration
  • the charge control thin film transistor in the odd-numbered column pixel or the charge control thin film transistor in the even-numbered column pixel is turned on, and at the same time, the data line provides a negative polarity voltage, so that the source voltage of the driving thin film transistor in the odd-numbered column pixel or The source voltage of the
  • the scan line provides a scan signal with a duration of a first duration
  • the clock signal first provides a charge control thin film transistor or an odd column of pixels in a high-potential control even-numbered column with a duration of a third duration.
  • the internal charge control thin film transistor is turned on, and at the same time, the data line provides a negative polarity voltage, so that the source voltage of the driving thin film transistor in the even-numbered column pixel or the source voltage of the driving thin film transistor in the odd-numbered column pixel is negative polarity,
  • the even-numbered column or the odd-numbered column of pixels is charged; thereafter, the clock signal is further provided with a low potential of a second duration to control a charge control thin film transistor or an even column of pixels in an odd column of pixels that are not turned on within the third duration
  • the charge control thin film transistor is turned on, and at the same time, the data line provides a positive polarity voltage, so that the source voltage of the driving thin film transistor in the odd-numbered column pixel or the source voltage of the driving thin film transistor in the even-numbered column pixel is positive polarity, An odd column pixel or an even column pixel is charged;
  • the first duration is the sum of the second duration and the third duration
  • the third duration is not equal to the second duration
  • the gate of the driving thin film transistor is electrically connected to the scan line corresponding to the row of the pixel, the source is electrically connected to the drain of the charge control thin film transistor, and the drain is electrically connected to one end of the storage capacitor and the liquid crystal capacitor.
  • the other end of the storage capacitor and the other end of the liquid crystal capacitor are electrically connected to the common electrode;
  • the charge control thin film transistor in the odd column pixel is a P type thin film transistor, the charge control thin film transistor in the even column pixel is an N type thin film transistor; or the charge control thin film transistor in the odd column pixel is an N type thin film a transistor, wherein the charge control thin film transistor in the even column of pixels is a P-type thin film transistor;
  • the driving thin film transistor and the charge control thin film transistor are both low temperature polysilicon thin A film transistor, an oxide semiconductor thin film transistor, or an amorphous silicon thin film transistor.
  • the invention also provides a driving method of a liquid crystal display panel in a column flip mode, comprising the following steps:
  • Step 1 providing a column of flip mode liquid crystal display panel
  • the column flip mode liquid crystal display panel includes a plurality of vertical data lines arranged in parallel and sequentially arranged, a plurality of horizontal scanning lines arranged in parallel and sequentially arranged, and a plurality of pixels arranged in an array, each of a pixel driving circuit is disposed in each pixel; a plurality of pixel driving circuits in the same row of pixels are electrically connected to the scanning lines corresponding to the row pixels; an odd column pixel and an even number respectively located on the left and right sides of each data line a plurality of pixel driving circuits in the column of pixels are electrically connected to the data line;
  • the pixel driving circuit includes: a driving thin film transistor, a charge control thin film transistor, a storage capacitor, and a liquid crystal capacitor; wherein one of the charge control thin film transistor in the even column pixel and the charge thin film transistor in the odd column pixel is controlled by a high potential And open, the other is turned on by the low potential control;
  • the charge control thin film transistor in the even column of pixels and the gate of the charge thin film transistor in the odd column of pixels are electrically connected to the clock signal;
  • Step 2 driving the liquid crystal display panel of the column flip mode to display one frame of the screen;
  • the Nth scan line supplies a scan signal having a duration of the first duration to the gate of the driving thin film transistor of the Nth row of pixels, and the clock signal is provided for the first time.
  • the two-time high potential control of the charge control thin film transistor in the Nth row even column of pixels or the charge control thin film transistor in the Nth row odd column pixel is turned on, at the same time, the corresponding data line provides a positive polarity voltage, so that the Nth row
  • the source voltage of the driving thin film transistor in the even-numbered column pixel or the source voltage of the driving thin film transistor in the N-th row odd-numbered column pixel is positive polarity, and the N-th row even-numbered column pixel or the N-th row odd-numbered column pixel is charged;
  • the clock signal is further provided with a low potential for a third duration to control a charge control thin film transistor in the Nth row of odd column pixels that is not turned on in the second duration or a charge control film in the N
  • Step 3 driving the liquid crystal display panel of the column flip mode to display the next frame image
  • the Nth scan line supplies a scan signal having a duration of a first duration to a gate of the driving thin film transistor of the Nth row of pixels, the clock signal being first provided for a third duration
  • the high potential control of the charge control thin film transistor in the Nth row even column of pixels or the charge control thin film transistor in the Nth row odd column pixel is turned on, at the same time, the corresponding data line provides a negative polarity voltage, so that the Nth row even column
  • the source voltage of the driving thin film transistor in the pixel or the source voltage of the driving thin film transistor in the N-th row odd-numbered column pixel is negative polarity, and the N-th row even-numbered column pixel or the N-th row odd-numbered column pixel is charged;
  • the clock signal is further provided with a second potential duration of low potential control.
  • the charge control thin film transistor in the Nth row of odd column pixels that is not turned on in the third duration or the charge control thin film transistor in the Nth row even column of pixels is turned on.
  • the corresponding data line provides a positive polarity voltage, such that the source voltage of the driving thin film transistor in the Nth row of odd-numbered columns or the source voltage of the driving thin film transistor in the N-th row of even-numbered columns is positive. Charging the Nth row of odd column pixels or the Nth row of even column pixels;
  • Step 4 step 2, and 3 alternately cycle, and the liquid crystal display panel that drives the column flip mode continuously performs screen display.
  • the third duration is not equal to the second duration.
  • the third duration is greater than the second duration.
  • the gate of the driving thin film transistor is electrically connected to the scan line corresponding to the row of the pixel, the source is electrically connected to the drain of the charge control thin film transistor, and the drain is electrically connected to one end of the storage capacitor and one end of the liquid crystal capacitor;
  • the source of the charge control thin film transistor is electrically connected to the data line corresponding to the column of the pixel; the other end of the storage capacitor and the other end of the liquid crystal capacitor are electrically connected to the common electrode;
  • the charge control thin film transistor in the odd column pixel is a P type thin film transistor, the charge control thin film transistor in the even column pixel is an N type thin film transistor; or the charge control thin film transistor in the odd column pixel is an N type thin film
  • the transistor, the charge control thin film transistor in the even column of pixels is a P-type thin film transistor.
  • the driving thin film transistor and the charge control thin film transistor are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • a column flip mode liquid crystal display panel and a driving method thereof are provided by adding a charge control thin film transistor to a pixel driving circuit, and depending on the positive and negative polarities of a voltage supplied from a data line, Adjusting the potential level and pulse width of the clock signal supplied to the gate of the charge control thin film transistor, controlling the time during which the positive and negative polarity voltages respectively charge the adjacent two columns of pixels, and balancing the positive and negative voltages to the adjacent two columns of pixels
  • the charging effect compensates for the difference in charging between the positive and negative voltages of the adjacent two columns of pixels, so that the screen display effect is uniform.
  • FIG. 1 is a circuit diagram of a liquid crystal display panel of a conventional column flip mode
  • Figure 2 is a timing diagram corresponding to the circuit shown in Figure 1;
  • FIG. 3 is a polarity diagram showing a frame of a liquid crystal display panel in a column flip mode
  • FIG. 4 is a polarity diagram of a next frame picture of one frame of the screen shown in FIG. 3;
  • FIG. 5 is a circuit diagram of a liquid crystal display panel of a column flip mode according to the present invention.
  • FIG. 6 is a timing chart showing a frame of a liquid crystal display panel in a column flip mode according to the present invention.
  • FIG. 7 is a timing chart of a next frame picture of one frame of the picture shown in FIG. 6;
  • FIG. 8 is a flow chart showing a method of driving a liquid crystal display panel in a column flip mode according to the present invention.
  • the first liquid crystal display panel of the column flip mode comprises a plurality of vertical data lines arranged in parallel and sequentially arranged, a plurality of horizontal scanning lines arranged in parallel and sequentially arranged, And a plurality of pixels arranged in an array, each of which is provided with a pixel driving circuit; a plurality of pixel driving circuits in the same row of pixels are electrically connected to the scanning lines corresponding to the pixels; respectively, each of the data lines An odd-numbered column pixel on the left and right sides and a plurality of pixel driving circuits in an even-numbered column of pixels are electrically connected to the data line.
  • the pixel driving circuit includes a driving thin film transistor T1, a charging control thin film transistor, a storage capacitor CST1, and a liquid crystal capacitor CLC1.
  • the gate of the driving thin film transistor T1 is electrically connected to the scan line corresponding to the row of the pixel, the source is electrically connected to the drain of the charge control thin film transistor, and the drain is electrically connected to one end of the storage capacitor CST1 and the liquid crystal capacitor CLC1
  • One end of the charging control thin film transistor is electrically connected to the clock signal CK, and the source is electrically connected to the data line corresponding to the column of the pixel; the other end of the storage capacitor CST1 and the other end of the liquid crystal capacitor CLC1 are Electrically connected to the common electrode VCOM.
  • Charge control thin film transistor T2 in even column pixels and charged thin film crystal in odd column pixels One of the body tubes T2' is opened by the control of the high potential, and the other is opened by the control of the low potential. Further, the charge control thin film transistor T2' in the odd-numbered column pixel is a P-type thin film transistor, and the charge control thin film transistor T2 in the even-numbered column pixel is an N-type thin film transistor; or charging control in the odd-numbered column pixel
  • the thin film transistor T2' is an N-type thin film transistor, and the charge control thin film transistor T2 in the even-numbered column pixel is a P-type thin film transistor.
  • the clock signal CK alternately supplies high and low potentials, and controls the charge control thin film transistor T2' in the even-numbered column pixel and the charge thin film transistor T2 in the odd-numbered column pixel to be alternately turned on.
  • the charge control thin film transistor T2 ′ in the odd-numbered column pixel is a P-type thin film transistor, and the charge control thin film transistor T2 in the even-numbered column pixel is an N-type thin film transistor, and the column flip mode liquid crystal display panel displays
  • the scan line provides a scan signal having a duration of a first duration t1 row by row
  • the clock signal CK first provides a high potential control even column of pixels having a duration of a second duration t2
  • the charge control thin film transistor T2 is turned on, and at the same time, the data line supplies a positive polarity voltage, so that the source voltage of the driving thin film transistor T1 in the even-numbered column pixel is positive, and the even-numbered column of pixels is charged; after that, the clock
  • the signal CK is further supplied with a low potential control of the third time length t3 to control the charge control thin film transistor T2 in the odd-numbered column pixel.
  • the data line provides a negative polarity
  • the scan line provides a scan signal having a duration of a first duration t1 row by row
  • the clock signal CK first provides a charge control thin film transistor T2 in a high-potential control even-numbered column of pixels having a duration of a third duration t3.
  • the data line provides a negative polarity voltage, so that the source voltage of the driving thin film transistor T1 in the even-numbered column pixel is negative polarity, and the even-numbered column of pixels is charged; after that, the clock signal CK is supplied for a longer period of time.
  • the low potential control of the two-time length t2 controls the charge control thin film transistor T2 in the odd-numbered column pixel, and at the same time, the data line provides a positive polarity voltage, so that the source voltage of the driving thin film transistor T1 in the odd-numbered column pixel is positive polarity, and the odd-numbered The column pixels are charged.
  • the first time length t1 is the sum of the second time length t2 and the third time length t3.
  • the third duration t3 is not equal to the second duration t2, and the third duration t3 is greater than the second duration t2, that is, the charging duration of the negative polarity voltage is not equal to the charging duration of the positive polarity voltage, and the charging of the negative polarity voltage is performed.
  • the duration of charging is longer than the positive voltage.
  • the length of the second and third durations t2 and t3 is adjusted by pulse width modulation of the clock signal CK, and the charging duration of the negative polarity voltage and the positive polarity voltage is further adjusted.
  • the driving thin film transistor T1 and the charge control thin film transistor T2 are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the charge control thin film transistor T2' in the odd column of pixels is an N type thin film transistor
  • the charge control thin film transistor T2 in the even-numbered column pixel is a P-type thin film transistor, it is necessary to charge the odd-numbered column pixels first, and then charge the even-numbered columns of pixels, and the rest is the same as the above process, and details are not described herein again.
  • the column flip mode liquid crystal display panel provided by the present invention adjusts the charge control thin film transistor T2 in the pixel driving circuit, and adjusts the positive and negative polarities of the voltage supplied by the data line to adjust the gate of the charge control thin film transistor T2.
  • the potential of the clock signal CK is high and low, and the pulse width is controlled.
  • the positive and negative voltages are respectively charged to the adjacent two columns of pixels, and the positive and negative voltages can be balanced to charge the adjacent two columns of pixels, and the positive and negative electrodes are compensated. The difference in charging caused by the polarity voltage to the adjacent two columns of pixels makes the display effect uniform.
  • the present invention further provides a driving method of a liquid crystal display panel in a column flip mode, comprising the following steps:
  • Step 1 A liquid crystal display panel providing a column flip mode.
  • the liquid crystal display panel of the column flip mode includes a plurality of vertical data lines which are parallel to each other and are sequentially arranged, a plurality of horizontal scanning lines which are parallel to each other and are sequentially arranged, and are arranged in an array.
  • a plurality of pixels each of which is provided with a pixel driving circuit; a plurality of pixel driving circuits in the same row of pixels are electrically connected to the scanning lines corresponding to the pixels; respectively, one of the left and right sides of each of the data lines
  • the odd column pixels and the plurality of pixel driving circuits in the even column pixels are electrically connected to the data lines.
  • the pixel driving circuit includes a driving thin film transistor T1, a charging control thin film transistor, a storage capacitor CST1, and a liquid crystal capacitor CLC1.
  • the gate of the driving thin film transistor T1 is electrically connected to the scan line corresponding to the row of the pixel, the source is electrically connected to the drain of the charge control thin film transistor, and the drain is electrically connected to one end of the storage capacitor CST1 and the liquid crystal capacitor CLC1
  • One end of the charging control thin film transistor is electrically connected to the clock signal CK, and the source is electrically connected to the data line corresponding to the column of the pixel; the other end of the storage capacitor CST1 and the other end of the liquid crystal capacitor CLC1 are Electrically connected to the common electrode VCOM.
  • One of the charge control thin film transistor T2 in the even-numbered column pixel and the charge thin film transistor T2' in the odd-numbered column is turned on by the high potential, and the other is turned on under the control of the low potential.
  • the charge control thin film transistor T2 in the odd-numbered column pixel is a P-type thin film transistor
  • the charge control thin film transistor T2 in the even-numbered column pixel is an N-type thin film transistor; or a charge control film in the odd-numbered column pixel
  • the transistor T2' is an N-type thin film transistor
  • the charge control thin film transistor T2 in the even-numbered column pixel is a P-type thin film transistor.
  • the driving thin film transistor T1 and the charge control thin film transistor T2 are low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • Step 2 Driving the liquid crystal display panel of the column flip mode to display one frame of the screen.
  • the charge control thin film transistor T2' in the odd-numbered column pixel is a P-type thin film transistor
  • the charge control thin film transistor T2 in the even-numbered column pixel is an N-type thin film transistor, for example, M is a positive integer.
  • the Nth scan line supplies a scan signal GATE(N) of the first duration t1 to the gate of the driving thin film transistor T1 of the Nth row of pixels, the clock signal CK
  • the charge control thin film transistor T2 in the N-th even-numbered column pixel of the second-time length t2 is opened, and at the same time, the corresponding data line S(M) provides a positive polarity voltage, so that the N-th row even-numbered column
  • the source voltage of the driving thin film transistor T1 in the pixel is positive polarity, and the N-th row of even-numbered columns of pixels is charged; after that, the clock signal CK is further supplied with a low-potential control of the N-th row of odd-numbered columns of the third time length t3
  • the charge control thin film transistor T2 is turned on, and at the same time, the corresponding data line S(M) provides a negative polarity voltage, so that the source voltage of the driving thin film transistor T1 in the odd-numbered column of the N
  • the scanning is performed line by line in the same manner until the driving of one frame is completed.
  • the third duration t3 is not equal to the second duration t2, and the third duration t3 is greater than the second duration t2, that is, the charging duration of the negative polarity voltage is not equal to the charging duration of the positive polarity voltage, and the negative polarity voltage is
  • the charging duration is longer than the charging time of the positive polarity voltage, so as to balance the charging effect of the positive and negative voltages on the adjacent two columns of pixels, and compensate the charging difference caused by the positive and negative voltages to the adjacent two columns of pixels, so that the screen display effect is uniform.
  • Step 3 Driving the liquid crystal display panel of the column flip mode to display the next frame screen.
  • the charge control thin film transistor T2 ′ in the odd-numbered column pixel is a P-type thin film transistor
  • the charge control thin film transistor T2 in the even-numbered column pixel is an N-type thin film transistor.
  • the Nth scan line supplies a scan signal GATE(N) having a duration of a first duration t1 to a gate of the driving thin film transistor T1 of the Nth row of pixels, wherein the clock signal CK is first provided for a third duration
  • the high potential control of t3 controls the charge control thin film transistor T2 in the Nth row of even columns of pixels
  • the corresponding data line S(M) provides a negative polarity voltage, so that the driving thin film transistor T1 in the Nth row of even columns of pixels
  • the source voltage is negative, charging the Nth row of even-numbered columns of pixels; after that, the clock signal CK is further supplied with a second duration t2 of low potential control of the Nth row of odd-numbered columns of pixels of the charge control thin film transistor T2
  • the corresponding data line S(M) provides a positive polarity voltage, so that the source voltage of the driving thin film transistor T1 in the odd-numbered column pixel of the Nth row is positive,
  • the scanning is sequentially performed line by line in the same manner until the driving of the next frame picture is completed.
  • the polarity of each adjacent column of pixels is opposite, and the polarity of the same pixel is opposite between each adjacent two frames, so in this step
  • the length of the high potential of the clock signal CK is set to be the third time length t3, and the low potential time is the second time length t2, so that the charging time of the negative polarity voltage is always the fourth time length t3, and the charging time of the positive polarity voltage is always The second time is t2.
  • the positive and negative voltages are controlled to charge the adjacent two columns of pixels respectively.
  • the time can balance the charging effect of the positive and negative voltages on the adjacent two columns of pixels, and compensate the difference between the positive and negative voltages for the adjacent two columns of pixels, so that the screen display effect is uniform.
  • Step 4 step 2, and 3 alternately cycle, and the liquid crystal display panel that drives the column flip mode continuously performs screen display.
  • the step 2 and Step 3 correspondingly charges the odd-numbered columns of pixels first, and then charges the even-numbered columns of pixels, and the rest of the process is the same, and details are not described herein again.
  • the above method can complete the driving of the liquid crystal display panel in the column flip mode, and does not affect the charging effect of the pixels due to the difference of positive and negative and polarity voltages, and ensures uniform display of the screen.
  • the liquid crystal display panel of the column flip mode of the present invention and the driving method thereof are provided by charging the thin film transistor in the pixel driving circuit, and adjusting and providing the charging according to the positive and negative polarities of the voltage supplied by the data line. Controlling the potential level and pulse width of the clock signal of the gate of the thin film transistor, controlling the time during which the positive and negative voltages respectively charge the adjacent two columns of pixels, and balancing the charging effect of the positive and negative voltages on the adjacent two columns of pixels. Compensating for the difference between the positive and negative voltages caused by the adjacent two columns of pixels, so that the screen display effect is uniform.

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Abstract

提供了一种列翻转模式的液晶显示面板及其驱动方法，通过在像素驱动电路中增加充电控制薄膜晶体管（T2，T2'），并依据数据线（S(m)）提供的电压的正、负极性不同，调整提供给充电控制薄膜晶体管（T2，T2'）栅极的时钟信号（CK）的电位高低及脉冲宽度，控制正、负极性电压分别对相邻两列像素进行充电的时间，能够平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。

Description

列翻转模式的液晶显示面板及其驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及一种列翻转模式的液晶显示面板及其驱动方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
液晶显示面板包括多个呈阵列式排布的像素，每个像素电性连接一个薄膜晶体管(TFT)，该TFT的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至竖直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制液晶的透光度，实现显示效果。
液晶分子具有一种特性，如果长时间给液晶分子施加同向电压，会使液晶分子极化，即使将电压取消，液晶分子亦会因为特性的破坏而无法再因电场的变化而转动，因此液晶显示面板必须是通过交流驱动，在显示画面的时候以一定的频率去翻转液晶分子，防止液晶分子固定偏向同一个方向而失去活性。目前，液晶显示面板支持多种翻转模式，比如点翻转模式、行翻转模式、列翻转模式等，实现翻转的途径主要是通过不断交替TFT源极电压的正、负极性(即信号电压的正、负极性)，或不断交替公共电极的正、负极性，以达到交流驱动的目的。而液晶显示面板在正常工作时，由于TFT正、负极性的源极电压(即信号电压)与栅极电压形成的电压差不 同，在相同的时间内，TFT源极对像素的充电效果会表现出不同，进一步造成显示画面内各个像素的亮暗不一，最终导致画面显示效果不均匀。
图1所示为一种现有的列翻转模式的液晶显示面板的电路图，图2为对应于图1所示电路的时序图。请参阅图1，现有的列翻转模式的液晶显示面板包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路，同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线，同一列像素内的多个像素驱动电路均电性连接于对应该列像素的数据线。所述像素驱动电路包括：驱动薄膜晶体管T1，所述驱动薄膜晶体管T1的栅极电性连接于对应该像素所在行的扫描线，源极电性连接于对应该像素所在列的数据线，漏极电性连接于存储电容CST1的一端及液晶电容CLC1的一端；存储电容CST1，所述存储电容CST1的另一端电性连接于公共电极VCOM；液晶电容CLC1，所述液晶电容CLC1的另一端电性连接于公共电极VCOM。由于图1所示的液晶显示面板采用列翻转模式驱动，请参阅图3、图4，每相邻两列像素的驱动薄膜晶体管T1的源极电压的极性相反，每相邻两帧之间同一像素的驱动薄膜晶体管T1的源极电压的极性相反。具体地，结合图1、图2，该现有的列翻转模式的液晶显示面板显示一帧画面的驱动过程为：多条扫描线依次逐行进行扫描，设N、M为正整数，当扫描到第N条扫描线时，第N条扫描线向该第N行像素的驱动薄膜晶体管T1的栅极提供扫描信号GATE(N)，第N行像素的所有驱动薄膜晶体管T1均开启，对于相邻的第M列、第M+1列像素，第M列数据线S(M)向第N行第M列像素的驱动薄膜晶体管T1的源极写入正极性电压，写入时间长度为t；与第M列数据线S(M)相邻的第M+1列数据线S(M+1)向第N行第M+1列像素的驱动薄膜晶体管T1的源极写入负极性电压，写入时间长度也为t；由于第N行第M列像素的驱动薄膜晶体管T1的源极电压的极性为正，而第N行第M+1列像素的驱动薄膜晶体管T1的源极电压的极性为负，且第N行第M列像素与第N行第M+1列像素的驱动薄膜晶体管T1的栅极电压相同，则第M列、第M+1列像素的驱动薄膜晶体管的源极电压与栅极电压形成的电压差不同，在第M列像素与第M+1列像素充电时间相同(均为t1)的情况下，两列像素的充电效果会表现出不同，造成第M列像素与第M+1列像素的显示亮暗不一，最终导致画面显示效果不均匀。
发明内容
本发明的目的在于提供一种列翻转模式的液晶显示面板，能够平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。
本发明的目的还在于提供一种列翻转模式的液晶显示面板的驱动方法，能够平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。
为实现上述目的，本发明提供了一种列翻转模式的液晶显示面板，包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线；
所述像素驱动电路包括：驱动薄膜晶体管、充电控制薄膜晶体管、存储电容、及液晶电容；偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的其中之一受高电位的控制而打开，另一个受低电位的控制而打开；
所述偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的栅极均电性连接于时钟信号；所述时钟信号交替提供高、低电位，控制偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管交替打开；
所述列翻转模式的液晶显示面板显示相邻两帧画面时：前一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第二时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为正极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第三时长的低电位控制在所述第二时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供负极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为负极性，对奇数列像素或偶数列像素进行充电；
后一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第三时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据 线提供负极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为负极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第二时长的低电位控制在所述第三时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为正极性，对奇数列像素或偶数列像素进行充电；
所述第一时长为第二时长与第三时长的加和。
所述第三时长不等于第二时长。
所述第三时长大于第二时长。
所述驱动薄膜晶体管的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容的一端及液晶电容的一端；所述充电控制薄膜晶体管的源极电性连接于像素所在列对应的数据线；所述存储电容的另一端及液晶电容的另一端均电性连接于公共电极；
所述奇数列像素内的充电控制薄膜晶体管为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为P型薄膜晶体管。
所述驱动薄膜晶体管、充电控制薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
本发明还提供一种列翻转模式的液晶显示面板，包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线；
所述像素驱动电路包括：驱动薄膜晶体管、充电控制薄膜晶体管、存储电容、及液晶电容；偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的其中之一受高电位的控制而打开，另一个受低电位的控制而打开；
所述偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的栅极均电性连接于时钟信号；所述时钟信号交替提供高、低电位，控制偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体 管交替打开；
所述列翻转模式的液晶显示面板显示相邻两帧画面时：前一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第二时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为正极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第三时长的低电位控制在所述第二时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供负极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为负极性，对奇数列像素或偶数列像素进行充电；
后一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第三时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供负极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为负极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第二时长的低电位控制在所述第三时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为正极性，对奇数列像素或偶数列像素进行充电；
所述第一时长为第二时长与第三时长的加和；
其中，所述第三时长不等于第二时长；
其中，所述驱动薄膜晶体管的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容的一端及液晶电容的一端；所述充电控制薄膜晶体管的源极电性连接于像素所在列对应的数据线；所述存储电容的另一端及液晶电容的另一端均电性连接于公共电极；
所述奇数列像素内的充电控制薄膜晶体管为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为P型薄膜晶体管；
其中，所述驱动薄膜晶体管、充电控制薄膜晶体管均为低温多晶硅薄 膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
本发明还提供一种列翻转模式的液晶显示面板的驱动方法，包括如下步骤：
步骤1、提供一列翻转模式的液晶显示面板；
所述列翻转模式的液晶显示面板包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线；
所述像素驱动电路包括：驱动薄膜晶体管、充电控制薄膜晶体管、存储电容、及液晶电容；偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的其中之一受高电位的控制而打开，另一个受低电位的控制而打开；
所述偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的栅极均电性连接于时钟信号；
步骤2、驱动所述列翻转模式的液晶显示面板进行一帧画面的显示；
设N、M为正整数，对于第N行像素，第N条扫描线向第N行像素的驱动薄膜晶体管的栅极提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第二时长的高电位控制第N行偶数列像素内的充电控制薄膜晶体管或第N行奇数列像素内的充电控制薄膜晶体管打开，于此同时，对应的数据线提供正极性电压，使得第N行偶数列像素内的驱动薄膜晶体管的源极电压或第N行奇数列像素内的驱动薄膜晶体管的源极电压为正极性，对第N行偶数列像素或第N行奇数列像素进行充电；之后，所述时钟信号再提供时长为第三时长的低电位控制在所述第二时长内未打开的第N行奇数列像素内的充电控制薄膜晶体管或第N行偶数列像素内的充电控制薄膜晶体管打开，于此同时，对应的数据线提供负极性电压，使得第N行奇数列像素内的驱动薄膜晶体管的源极电压或第N行偶数列像素内的驱动薄膜晶体管的源极电压为负极性，对第N行奇数列像素或第N行偶数列像素进行充电；所述第一时长为第二时长与第三时长的加和；
按同样方式依次逐行扫描，直至完成对一帧画面的驱动；
步骤3、驱动所述列翻转模式的液晶显示面板进行下一帧画面的显示；
对于第N行像素，第N条扫描线向第N行像素的驱动薄膜晶体管的栅极提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第三时长 的高电位控制第N行偶数列像素内的充电控制薄膜晶体管或第N行奇数列像素内的充电控制薄膜晶体管打开，于此同时，相应的数据线提供负极性电压，使得第N行偶数列像素内的驱动薄膜晶体管的源极电压或第N行奇数列像素内的驱动薄膜晶体管的源极电压为负极性，对第N行偶数列像素或第N行奇数列像素进行充电；之后，所述时钟信号再提供时长为第二时长的低电位控制在所述第三时长内未打开的第N行奇数列像素内的充电控制薄膜晶体管或第N行偶数列像素内的充电控制薄膜晶体管打开，于此同时，相应的数据线提供正极性电压，使得第N行奇数列像素内的驱动薄膜晶体管的源极电压或第N行偶数列像素内的驱动薄膜晶体管的源极电压为正极性，对第N行奇数列像素或第N行偶数列像素进行充电；
按同样方式依次逐行扫描，直至完成对所述下一帧画面的驱动；
步骤4、步骤2、3交替循环，驱动所述列翻转模式的液晶显示面板连续进行画面显示。
所述第三时长不等于第二时长。
所述第三时长大于第二时长。
所述驱动薄膜晶体管的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容的一端及液晶电容的一端；所述充电控制薄膜晶体管的源极电性连接于像素所在列对应的数据线；所述存储电容的另一端及液晶电容的另一端均电性连接于公共电极；
所述奇数列像素内的充电控制薄膜晶体管为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为P型薄膜晶体管。
所述驱动薄膜晶体管、充电控制薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
本发明的有益效果：本发明提供的一种列翻转模式的液晶显示面板及其驱动方法，通过在像素驱动电路中增加充电控制薄膜晶体管，并依据数据线提供的电压的正、负极性不同，调整提供给充电控制薄膜晶体管栅极的时钟信号的电位高低及脉冲宽度，控制正、负极性电压分别对相邻两列像素进行充电的时间，能够平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的列翻转模式的液晶显示面板的电路图；
图2为对应于图1所示电路的时序图；
图3为列翻转模式的液晶显示面板显示一帧画面的极性图；
图4为图3所示一帧画面的下一帧画面的极性图；
图5为本发明的列翻转模式的液晶显示面板的电路图；
图6为本发明的列翻转模式的液晶显示面板显示一帧画面的时序图；
图7为图6所示一帧画面的下一帧画面的时序图；
图8为本发明的列翻转模式的液晶显示面板的驱动方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图5至图7，本发明首先一种列翻转模式的液晶显示面板，包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线。
所述像素驱动电路包括：驱动薄膜晶体管T1、充电控制薄膜晶体管、存储电容CST1、及液晶电容CLC1。
所述驱动薄膜晶体管T1的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容CST1的一端及液晶电容CLC1的一端；所述充电控制薄膜晶体管的栅极电性连接于时钟信号CK，源极电性连接于像素所在列对应的数据线；所述存储电容CST1的另一端及液晶电容CLC1的另一端均电性连接于公共电极VCOM。
偶数列像素内的充电控制薄膜晶体管T2与奇数列像素内的充电薄膜晶 体管T2’的其中之一受高电位的控制而打开，另一个受低电位的控制而打开。进一步地，所述奇数列像素内的充电控制薄膜晶体管T2’为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管T2’为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为P型薄膜晶体管。
所述时钟信号CK交替提供高、低电位，控制偶数列像素内的充电控制薄膜晶体管T2’与奇数列像素内的充电薄膜晶体管T2交替打开。
以所述奇数列像素内的充电控制薄膜晶体管T2’为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为N型薄膜晶体管为例，所述列翻转模式的液晶显示面板显示相邻两帧画面时：前一帧画面内，所述扫描线逐行提供时长为第一时长t1的扫描信号，所述时钟信号CK先提供时长为第二时长t2的高电位控制偶数列像素内的充电控制薄膜晶体管T2打开，于此同时，数据线提供正极性电压，使得偶数列像素内的驱动薄膜晶体管T1的源极电压为正极性，对偶数列像素进行充电；之后，所述时钟信号CK再提供时长为第三时长t3的低电位控制奇数列像素内的充电控制薄膜晶体管T2打开，于此同时，数据线提供负极性电压，使得奇数列像素内的驱动薄膜晶体管T1的源极电压为负极性，对奇数列像素进行充电；
后一帧画面内，所述扫描线逐行提供时长为第一时长t1的扫描信号，所述时钟信号CK先提供时长为第三时长t3的高电位控制偶数列像素内的充电控制薄膜晶体管T2打开，于此同时，数据线提供负极性电压，使得偶数列像素内的驱动薄膜晶体管T1的源极电压为负极性，对偶数列像素进行充电；之后，所述时钟信号CK再提供时长为第二时长t2的低电位控制奇数列像素内的充电控制薄膜晶体管T2打开，于此同时，数据线提供正极性电压，使得奇数列像素内的驱动薄膜晶体管T1的源极电压为正极性，对奇数列像素进行充电。
所述第一时长t1为第二时长t2与第三时长t3的加和。
具体地，所述第三时长t3不等于第二时长t2，所述第三时长t3大于第二时长t2，即负极性电压的充电时长不等于正极性电压的充电时长，且负极性电压的充电时长大于正极性电压的充电时长。通过对所述时钟信号CK进行脉宽调制来调整所述第二、第三时长t2、t3的长短，进而调整负极性电压与正极性电压的充电时长。所述驱动薄膜晶体管T1、充电控制薄膜晶体管T2均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
当所述奇数列像素内的充电控制薄膜晶体管T2’为N型薄膜晶体管， 所述偶数列像素内的充电控制薄膜晶体管T2为P型薄膜晶体管时，需先对奇数列像素进行充电，再对偶数列像素进行充电，其余与上述过程相同，此处不再赘述。
本发明所提供的列翻转模式的液晶显示面板，通过在像素驱动电路中增加充电控制薄膜晶体管T2，并依据数据线提供的电压的正、负极性不同，调整提供给充电控制薄膜晶体管T2栅极的时钟信号CK的电位高低及脉冲宽度，控制正、负极性电压分别对相邻两列像素进行充电的时间，能够平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。
请参阅图8，本发明还提供一种列翻转模式的液晶显示面板的驱动方法，包括如下步骤：
步骤1、提供列翻转模式的一液晶显示面板。
如图5所示，所述列翻转模式的液晶显示面板包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线。
所述像素驱动电路包括：驱动薄膜晶体管T1、充电控制薄膜晶体管、存储电容CST1、及液晶电容CLC1。
所述驱动薄膜晶体管T1的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容CST1的一端及液晶电容CLC1的一端；所述充电控制薄膜晶体管的栅极电性连接于时钟信号CK，源极电性连接于像素所在列对应的数据线；所述存储电容CST1的另一端及液晶电容CLC1的另一端均电性均连接于公共电极VCOM。
偶数列像素内的充电控制薄膜晶体管T2与奇数列像素内的充电薄膜晶体管T2’的其中之一受高电位的控制而打开，另一个受低电位的控制而打开。进一步地，所述奇数列像素内的充电控制薄膜晶体管T2为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管T2’为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为P型薄膜晶体管。
具体地，所述驱动薄膜晶体管T1、充电控制薄膜晶体管T2均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
步骤2、驱动所述列翻转模式的液晶显示面板进行一帧画面的显示。
请结合图5与图6，以所述奇数列像素内的充电控制薄膜晶体管T2’为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为N型薄膜晶体管为例，设N、M为正整数，对于第N行像素，第N条扫描线向第N行像素的驱动薄膜晶体管T1的栅极提供时长为第一时长t1的扫描信号GATE(N)，所述时钟信号CK先提供时长为第二时长t2的高电位控制第N行偶数列像素内的充电控制薄膜晶体管T2打开，于此同时，对应的数据线S(M)提供正极性电压，使得第N行偶数列像素内的驱动薄膜晶体管T1的源极电压为正极性，对第N行偶数列像素进行充电；之后，所述时钟信号CK再提供时长为第三时长t3的低电位控制第N行奇数列像素内的充电控制薄膜晶体管T2打开，于此同时，对应的数据线S(M)提供负极性电压，使得第N行奇数列像素内的驱动薄膜晶体管T1的源极电压为负极性，对第N行奇数列像素进行充电；所述第一时长t1为第二时长t2与第三时长t3的加和。
按同样方式依次逐行扫描，直至完成对一帧画面的驱动。
具体地，所述第三时长t3不等于第二时长t2，且所述第三时长t3大于第二时长t2，即负极性电压的充电时长不等于正极性电压的充电时长，且负极性电压的充电时长大于正极性电压的充电时长，以平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。
步骤3、驱动所述列翻转模式的液晶显示面板进行下一帧画面的显示。
请结合图5与图7，仍以所述奇数列像素内的充电控制薄膜晶体管T2’为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为N型薄膜晶体管为例，对于第N行像素，第N条扫描线向第N行像素的驱动薄膜晶体管T1的栅极提供时长为第一时长t1的扫描信号GATE(N)，所述时钟信号CK先提供时长为第三时长t3的高电位控制第N行偶数列像素内的充电控制薄膜晶体管T2打开，于此同时，相应的数据线S(M)提供负极性电压，使得第N行偶数列像素内的驱动薄膜晶体管T1的源极电压为负极性，对第N行偶数列像素进行充电；之后，所述时钟信号CK再提供时长为第二时长t2的低电位控制第N行奇数列像素内的充电控制薄膜晶体管T2打开，于此同时，相应的数据线S(M)提供正极性电压，使得第N行奇数列像素内的驱动薄膜晶体管T1的源极电压为正极性，对第N行奇数列像素进行充电。
按同样方式依次逐行扫描，直至完成对所述下一帧画面的驱动。
进一步地，如图3、图4所示，列翻转模式的液晶显示面板中，每相邻两列像素的极性相反，每相邻两帧之间同一像素的极性相反，因此在该步骤3中需要设置时钟信号CK的高电位的时长为第三时长t3，低电位时长为第二时长t2，以保证负极性电压的充电时长始终为第四时长t3，正极性电压的充电时长始终为第二时长t2。依据数据线提供的电压的正、负极性不同，通过调整提供给充电控制薄膜晶体管T2栅极的时钟信号CK的电位高低及脉冲宽度，控制正、负极性电压分别对相邻两列像素进行充电的时间，能够平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。
步骤4、步骤2、3交替循环，驱动所述列翻转模式的液晶显示面板连续进行画面显示。
值得一提的是，当所述奇数列像素内的充电控制薄膜晶体管T2’为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管T2为P型薄膜晶体管时，所述步骤2与步骤3相应的先对奇数列像素进行充电，再对偶数列像素进行充电，其余过程相同，此处不再赘述。
上述方法能够完成对列翻转模式的液晶显示面板的驱动，且不会因正负、极性电压不同影响像素的充电效果，保证画面显示均匀。
综上所述，本发明的列翻转模式的液晶显示面板及其驱动方法，通过在像素驱动电路中增加充电控制薄膜晶体管，并依据数据线提供的电压的正、负极性不同，调整提供给充电控制薄膜晶体管栅极的时钟信号的电位高低及脉冲宽度，控制正、负极性电压分别对相邻两列像素进行充电的时间，能够平衡正、负极性电压对相邻两列像素的充电效果，补偿正、负极性电压对相邻两列像素造成的充电差异，使得画面显示效果均匀。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种列翻转模式的液晶显示面板，包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线；
    所述像素驱动电路包括：驱动薄膜晶体管、充电控制薄膜晶体管、存储电容、及液晶电容；偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的其中之一受高电位的控制而打开，另一个受低电位的控制而打开；
    所述偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的栅极均电性连接于时钟信号；所述时钟信号交替提供高、低电位，控制偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管交替打开；
    所述列翻转模式的液晶显示面板显示相邻两帧画面时：前一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第二时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为正极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第三时长的低电位控制在所述第二时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供负极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为负极性，对奇数列像素或偶数列像素进行充电；
    后一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第三时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供负极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为负极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第二时长的低电位控 制在所述第三时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为正极性，对奇数列像素或偶数列像素进行充电；
    所述第一时长为第二时长与第三时长的加和。
  2. 如权利要求1所述的列翻转模式的液晶显示面板，其中，所述第三时长不等于第二时长。
  3. 如权利要求2所述的列翻转模式的液晶显示面板，其中，所述第三时长大于第二时长。
  4. 如权利要求1所述的列翻转模式的液晶显示面板，其中，所述驱动薄膜晶体管的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容的一端及液晶电容的一端；所述充电控制薄膜晶体管的源极电性连接于像素所在列对应的数据线；所述存储电容的另一端及液晶电容的另一端均电性连接于公共电极；
    所述奇数列像素内的充电控制薄膜晶体管为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为P型薄膜晶体管。
  5. 如权利要求1所述的列翻转模式的液晶显示面板，其中，所述驱动薄膜晶体管、充电控制薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
  6. 一种列翻转模式的液晶显示面板，包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线；
    所述像素驱动电路包括：驱动薄膜晶体管、充电控制薄膜晶体管、存储电容、及液晶电容；偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的其中之一受高电位的控制而打开，另一个受低电位的控制而打开；
    所述偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的栅极均电性连接于时钟信号；所述时钟信号交替提供高、低电位，控制偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体 管交替打开；
    所述列翻转模式的液晶显示面板显示相邻两帧画面时：前一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第二时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为正极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第三时长的低电位控制在所述第二时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供负极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为负极性，对奇数列像素或偶数列像素进行充电；
    后一帧画面内，所述扫描线逐行提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第三时长的高电位控制偶数列像素内的充电控制薄膜晶体管或奇数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供负极性电压，使得偶数列像素内的驱动薄膜晶体管的源极电压或奇数列像素内的驱动薄膜晶体管的源极电压为负极性，对偶数列像素或奇数列像素进行充电；之后，所述时钟信号再提供时长为第二时长的低电位控制在所述第三时长内未打开的奇数列像素内的充电控制薄膜晶体管或偶数列像素内的充电控制薄膜晶体管打开，于此同时，数据线提供正极性电压，使得奇数列像素内的驱动薄膜晶体管的源极电压或偶数列像素内的驱动薄膜晶体管的源极电压为正极性，对奇数列像素或偶数列像素进行充电；
    所述第一时长为第二时长与第三时长的加和；
    其中，所述第三时长不等于第二时长；
    其中，所述驱动薄膜晶体管的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容的一端及液晶电容的一端；所述充电控制薄膜晶体管的源极电性连接于像素所在列对应的数据线；所述存储电容的另一端及液晶电容的另一端均电性连接于公共电极；
    所述奇数列像素内的充电控制薄膜晶体管为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为P型薄膜晶体管；
    其中，所述驱动薄膜晶体管、充电控制薄膜晶体管均为低温多晶硅薄 膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
  7. 如权利要求6所述的列翻转模式的液晶显示面板，其中，所述第三时长大于第二时长。
  8. 一种列翻转模式的液晶显示面板的驱动方法，包括如下步骤：
    步骤1、提供一列翻转模式的液晶显示面板；
    所述列翻转模式的液晶显示面板包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的多个像素，每个像素内均设置像素驱动电路；同一行像素内的多个像素驱动电路均电性连接于对应该行像素的扫描线；分别位于每条数据线左、右两侧的一奇数列像素与一偶数列像素内的多个像素驱动电路均电性连接于该条数据线；
    所述像素驱动电路包括：驱动薄膜晶体管、充电控制薄膜晶体管、存储电容、及液晶电容；偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的其中之一受高电位的控制而打开，另一个受低电位的控制而打开；
    所述偶数列像素内的充电控制薄膜晶体管与奇数列像素内的充电薄膜晶体管的栅极均电性连接于时钟信号；
    步骤2、驱动所述列翻转模式的液晶显示面板进行一帧画面的显示；
    设N、M为正整数，对于第N行像素，第N条扫描线向第N行像素的驱动薄膜晶体管的栅极提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第二时长的高电位控制第N行偶数列像素内的充电控制薄膜晶体管或第N行奇数列像素内的充电控制薄膜晶体管打开，于此同时，对应的数据线提供正极性电压，使得第N行偶数列像素内的驱动薄膜晶体管的源极电压或第N行奇数列像素内的驱动薄膜晶体管的源极电压为正极性，对第N行偶数列像素或第N行奇数列像素进行充电；之后，所述时钟信号再提供时长为第三时长的低电位控制在所述第二时长内未打开的第N行奇数列像素内的充电控制薄膜晶体管或第N行偶数列像素内的充电控制薄膜晶体管打开，于此同时，对应的数据线提供负极性电压，使得第N行奇数列像素内的驱动薄膜晶体管的源极电压或第N行偶数列像素内的驱动薄膜晶体管的源极电压为负极性，对第N行奇数列像素或第N行偶数列像素进行充电；所述第一时长为第二时长与第三时长的加和；
    按同样方式依次逐行扫描，直至完成对一帧画面的驱动；
    步骤3、驱动所述列翻转模式的液晶显示面板进行下一帧画面的显示；
    对于第N行像素，第N条扫描线向第N行像素的驱动薄膜晶体管的栅 极提供时长为第一时长的扫描信号，所述时钟信号先提供时长为第三时长的高电位控制第N行偶数列像素内的充电控制薄膜晶体管或第N行奇数列像素内的充电控制薄膜晶体管打开，于此同时，相应的数据线提供负极性电压，使得第N行偶数列像素内的驱动薄膜晶体管的源极电压或第N行奇数列像素内的驱动薄膜晶体管的源极电压为负极性，对第N行偶数列像素或第N行奇数列像素进行充电；之后，所述时钟信号再提供时长为第二时长的低电位控制在所述第三时长内未打开的第N行奇数列像素内的充电控制薄膜晶体管或第N行偶数列像素内的充电控制薄膜晶体管打开，于此同时，相应的数据线提供正极性电压，使得第N行奇数列像素内的驱动薄膜晶体管的源极电压或第N行偶数列像素内的驱动薄膜晶体管的源极电压为正极性，对第N行奇数列像素或第N行偶数列像素进行充电；
    按同样方式依次逐行扫描，直至完成对所述下一帧画面的驱动；
    步骤4、步骤2、3交替循环，驱动所述列翻转模式的液晶显示面板连续进行画面显示。
  9. 如权利要求8所述的列翻转模式的液晶显示面板的驱动方法，其中，所述第三时长不等于第二时长。
  10. 如权利要求9所述的列翻转模式的液晶显示面板的驱动方法，其中，所述第三时长大于第二时长。
  11. 如权利要求8所述的列翻转模式的液晶显示面板的驱动方法，其中，所述驱动薄膜晶体管的栅极电性连接于像素所在行对应的扫描线，源极电性连接于充电控制薄膜晶体管的漏极，漏极电性连接于存储电容的一端及液晶电容的一端；所述充电控制薄膜晶体管的源极电性连接于像素所在列对应的数据线；所述存储电容的另一端及液晶电容的另一端均电性连接于公共电极；
    所述奇数列像素内的充电控制薄膜晶体管为P型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为N型薄膜晶体管；或所述奇数列像素内的充电控制薄膜晶体管为N型薄膜晶体管，所述偶数列像素内的充电控制薄膜晶体管为P型薄膜晶体管。
  12. 如权利要求8所述的列翻转模式的液晶显示面板的驱动方法，其中，所述驱动薄膜晶体管、充电控制薄膜晶体管均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
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