WO2016188090A1 - 时钟恢复方法、装置和计算机存储介质 - Google Patents

时钟恢复方法、装置和计算机存储介质 Download PDF

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Publication number
WO2016188090A1
WO2016188090A1 PCT/CN2015/097061 CN2015097061W WO2016188090A1 WO 2016188090 A1 WO2016188090 A1 WO 2016188090A1 CN 2015097061 W CN2015097061 W CN 2015097061W WO 2016188090 A1 WO2016188090 A1 WO 2016188090A1
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Prior art keywords
data
water level
clock
buffer
recovery
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PCT/CN2015/097061
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English (en)
French (fr)
Inventor
张晓鹏
秦文平
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深圳市中兴微电子技术有限公司
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Publication of WO2016188090A1 publication Critical patent/WO2016188090A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • the present invention relates to synchronization technologies in the field of communications, and in particular, to a clock recovery method, apparatus, and computer storage medium.
  • clock recovery may be involved. If the receiving side cannot recover the clock on the transmitting side, data demodulation may be difficult, resulting in data reception errors. If the recovery clock recovered by the receiving side is not accurate enough, the error rate of data reception may be high.
  • the method for clock recovery in the prior art includes accumulating data amount of data sent by the receiving side for a period of time, reading a water level conversion of the data buffer in the period of time, and changing the water level according to the data buffer and the segment.
  • the time interval of the time, the clock frequency of the transmitting side is estimated.
  • the problem with this method is that the data is accumulated by the water level of the data buffer, and the buffer space of the data cache may be required to be large, if the data cache is cached. The space is not enough.
  • the write rate of the data cache is large, data overflow may occur during the period of time. This obviously affects the result of clock recovery. Obviously, the cache and other resources are large.
  • embodiments of the present invention are directed to a clock recovery method, apparatus, and computer storage medium to at least partially solve the problem of low clock recovery accuracy caused by data overflow in a data buffer.
  • the technical solution of the present invention is implemented as follows:
  • the first aspect of the embodiments of the present invention provides a clock recovery method, where the method includes:
  • Reading the water level of the control cache the water level of the control cache is used to characterize the write of the data cache The difference between the amount of data and the amount of data written;
  • a recovery clock is formed according to the water level of the control buffer.
  • the forming a recovery clock according to the water level of the control cache includes:
  • the loop count of the local clock is a loop count of a sampling period in which the data buffer writes data according to the local clock
  • the recovered clock is formed.
  • the comparing the water level of the control buffer with the loop count of the local clock to form a comparison result includes:
  • the output is a logic high level adjustment signal
  • the output is a logic low level adjustment signal
  • a recovery clock including:
  • the recovered clock is formed according to the adjustment signal.
  • the method further includes:
  • the average write rate and the water level of the data buffer are used to jointly form a water level of the control buffer.
  • the method further includes:
  • the smoothing result is used to form a water level of the control buffer.
  • the method further includes:
  • Adjusting the recovery clock to adjust the data level according to the water level of the control buffer The write rate of the save.
  • the method further includes:
  • the water level of the data cache characterizing an amount of data to be written in the data buffer
  • adjusting the write clock to adjust the write rate of the data cache such that the water level of the data buffer is within the second threshold range.
  • a second aspect of the embodiments of the present invention provides a clock recovery apparatus, where the apparatus includes:
  • a reading unit configured to read a water level of the control buffer; the water level of the control buffer is used to represent a difference between the amount of written data of the data buffer and the amount of written data;
  • a recovery unit configured to form a recovery clock according to a comparison result of the water level of the control buffer.
  • the recovery unit further includes:
  • a comparison module configured to compare a water level of the control buffer with a loop count of a local clock to form a comparison result;
  • a loop count of the local clock is a loop count of a sampling period in which the data buffer writes data according to a local clock;
  • a recovery module configured to form the recovery clock according to the comparison result.
  • the comparison module includes:
  • a first output submodule configured to output an adjustment signal of a logic high level when a water level of the control buffer is greater than a loop count of the local clock
  • a second output submodule configured to output an adjustment signal of a logic low level when the water level of the control buffer is less than a loop count of the local clock
  • the recovery module is configured to determine a frequency of the recovered clock according to a ratio of a logic high level to a logic low level in the adjustment signal.
  • the device further includes:
  • a statistical unit configured to count an average write rate of the data cache within a specified time period
  • the average write rate and the water level of the data buffer are used to jointly form a water level of the control buffer.
  • the recovery unit is configured to perform smoothing processing on the average write rate and the water level of the data cache to form a smoothing process result, so that the amount of write data of the data cache is evenly distributed to each time. segment;
  • the smoothing result is used to form a water level of the control buffer.
  • the recovery unit is configured to adjust a write rate of the data cache by adjusting the recovery clock according to the water level of the control cache.
  • the determining module is configured to detect a water level of the data cache when a water level change amount of the control cache is maintained within a first threshold range; and a water level of the data cache is characterized by the data cache The amount of data written; when the water level of the data buffer is outside the second threshold range, adjusting the write clock to adjust the write rate of the data cache so that the water level of the data buffer is at the Within the threshold range.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute at least one of the clock recovery methods.
  • the clock recovery method, device and computer storage medium according to the embodiments of the present invention are based on controlling the water level of the cache instead of the water level of the data cache when performing the clock recovery; thus avoiding the overflow of the data buffer.
  • the water level of the data buffer changes greatly, which leads to the problem of poor accuracy and accuracy of the recovered clock.
  • 1a is a schematic flowchart of a clock recovery method according to an embodiment of the present invention.
  • 1b is a second schematic flowchart of a clock recovery method according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing the effect of the comparison result according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of state transition of clock recovery according to an embodiment of the present invention.
  • FIG. 4a is a schematic structural diagram of a clock recovery apparatus according to an embodiment of the present invention.
  • 4b is a second schematic structural diagram of a clock recovery apparatus according to an embodiment of the present invention.
  • FIG. 5 is a third schematic flowchart of clock recovery according to an embodiment of the present invention.
  • this embodiment provides a clock recovery method, where the method includes:
  • Step S110 reading the water level of the control buffer; the water level of the control buffer is used to represent the difference between the amount of written data of the data buffer and the amount of written data;
  • Step S120 Form a recovery clock according to the water level of the control buffer.
  • the clock recovery method in this embodiment is applied to a device on the data receiving side, specifically, in a receiving device such as a receiving end of an optical signal.
  • the data cache is configured to receive data from the transmitting side and cache, and write out the cached data in the data cache.
  • the control cache is used to characterize the difference between the amount of write data of the data cache and the amount of write data.
  • the control cache may be equivalent to an up-down counter, which may be used to increment 1 when the data buffer writes one unit of data; and to decrement by 1 when the data buffer writes out one unit of data.
  • the data cache works normally, it can accurately indicate the amount of data written and written in the data cache when the data cache is working.
  • the control cache in the embodiment is in a situation in which the data cache overflows, the data overflow of the data cache is not normally written out of the data, and does not affect the water level of the control cache. For example, if the water level of the current control buffer is S1; The data buffer overflows S2 units of data. This partially overflowed data may not affect the water level of the control buffer. The water level of the control buffer remains S1 after overflowing S2 units of data.
  • the data of one unit in the embodiment can be understood as the amount of data that can be sampled by using a period, specifically, data of one bit.
  • the water level of the control buffer is used to simply know the difference between the write rate and the write rate of the data buffer over a period of time. If the write rate of the data cache is greater than the write rate of the data cache, it is obvious that the water level of the control cache becomes higher; the write rate of the data cache during the period is less than the write rate. In this way, the water level of the control buffer will become low.
  • the water level of the control cache as described above can accurately indicate the difference between the write data and the write rate of the data cache.
  • the clock recovery accuracy is greatly deviated due to the overflow of the data cache, and the clock is obviously improved. The accuracy of the recovery.
  • the buffer area corresponding to the data cache can be appropriately reduced, and the system resources such as the cache occupied by the clock recovery can be reduced.
  • the step S120 includes:
  • Step S121 Comparing the water level of the control buffer with a loop count of the local clock to form a comparison result;
  • the loop count of the local clock is a loop count of a sampling period in which the data buffer writes data according to the local clock;
  • Step S122 Form a recovery clock according to the comparison result.
  • the local clock is used for data sampling, and the data buffer performs data sampling for each local clock to form one sampling period.
  • the loop count of the local clock is counted as 1. If the loop count of the local clock is N before the data buffer is performed in the data buffer, the data cache performs the current data adoption. Thereafter, the local ten-week cycle count is M.
  • the water level of the control buffer is incremented by one when there is one unit data write in the data buffer. If the current data buffer is sampled by the local clock and sampled N times, wherein n times have sampled data, (where there is sampled data indicating that data is written to the data buffer), the local clock loop count For N, the water level of the control buffer is increased by n.
  • the number of times of sampling the data buffer is cyclically counted, that is, when the data count value reaches the maximum count value, the local clock cycle count is cleared.
  • the value of the water level of the control buffer is also limited. Usually, the upper limit is exceeded, and the water level of the control buffer is saturated. The saturation process here is that if the write rate of the data cache continues to be greater than the written data, the water level of the control buffer no longer rises and remains at the upper limit of the count. In this embodiment, it is optional to set both the upper limit of the control buffer and the maximum count value of the local loop count to the same value.
  • the loop count of the local clock and the water level of the control buffer are compared to form a comparison result; this comparison result will be applied to the recovery clock generation and generation.
  • the step S121 may include:
  • the output is a logic high level adjustment signal
  • the output is a logic low adjustment signal.
  • the logic high level and the logic low level in this embodiment are relative, wherein the logic high level and the logic low level are relative to the same reference level, and the logic high level corresponds to a high level.
  • the logic high level and the logic low level form the adjustment signal. If the maximum count value of the number of loops of the local clock is K, the length of time corresponding to the one of the adjustment signals is equal to the period of the K local clocks.
  • the step S122 may include: forming the recovery clock according to the adjustment signal.
  • the method may include: calculating a duty ratio of the adjustment signal, and forming the recovery clock according to the duty ratio.
  • the time of a logic high level in one of the adjustment signals is T1
  • the time of logic low level is T2
  • the duty ratio may be T1/(T1+T2).
  • the method of specifically generating the recovered clock in step S120 includes generating a target clock f1 using a clock source operating at a target frequency f1.
  • the recovery clock f2 is formed by adjusting the f1 according to the duty ratio.
  • the clock source here can be various types of clock generating structures, such as a voltage controlled oscillator VCXO.
  • the VCXO generates a clock for the crystal under voltage control. It is assumed that the following functional relationship is satisfied between the f2 and the f1:
  • the method further includes:
  • the average write rate and the water level of the data buffer are used to jointly form a water level of the control buffer.
  • the water level of the control buffer represents not only the difference between the amount of written data and the amount of written data, but also the average write rate.
  • the water level of the control cache can characterize the amount of data to be written by the data cache.
  • the side receives the data transmission data.
  • the receiving side performs statistics on the data written by the data receiving data within a specified time, thereby knowing the general rule of the data sent by the receiving end. This law is reflected as the average write rate for the specified time of writing data.
  • the status information of the write data described herein can be understood as the fact that the receiving end transmits substantially the same amount of data per local clock cycle of each of the receiving ends.
  • the statistical time in this embodiment is a time period determined according to the law of the data, specifically, M local clock cycles.
  • the data buffer write data amount is P every M local clock cycles. However, there may be a case in which only the previous m1 clocks have data writes in the M local clock cycles. If the smoothing process is not performed, the water level of the control buffer is caused by the previous m1. Data is written during the period and rises rapidly. In the present embodiment, the amount of write data is smoothed and the smoothed processing result is formed. The smoothing result is such that the write data is evenly distributed over various time periods.
  • the specified time may be a historical time before the current time. That is, the M local clock cycles may be M local clock cycles before the current time.
  • the clock recovery When the clock recovery is performed, if the water level of the control buffer is only used to represent the amount of write data and the amount of write data of the data cache, the clock is restored to the data source on the transmitting side according to the water level of the control buffer.
  • the clocks differ by a specified range, although clock adjustments can be made, but they are relatively slow. In the embodiment, by counting the average write rate within a specified time, the sender-side clock source clock is roughly known. If the water level of the control buffer is formed according to the water level of the data buffer and the average write rate, then According to the water level of the control buffer, the clock recovery is quickly restored to a clock range close to the source of the transmission side, thereby increasing the rate of clock capture.
  • the method further includes:
  • the smoothing result is used to form a water level of the control buffer.
  • the average write rate and the water level of the data buffer are smoothed, so that the water level of the control buffer does not cause a sudden change at a certain time point. If no smoothing is performed, the cache is directly controlled according to the mutation. The water level performs clock recovery, which causes the frequency of the recovered clock to also change at the corresponding time point. This sudden change in the recovery clock will result in data reception. Other bad issues in the process.
  • the regularity of the transmission data on the transmitting side reflects the data source clock of the transmitting side to a certain extent.
  • the recovery clock is formed by counting the status information of the written data within a specified time.
  • the approximate frequency of the clock source clock can be estimated, so that a recovery clock closer to the clock source can be quickly formed, and the subsequent adjustment only needs to be finely adjusted according to the water level of the control buffer, which obviously speeds up formation and
  • the clock source captures a clock recovery rate that is close to the clock source.
  • the smoothing process can avoid the frequency adjustment of the recovered clock according to the smoothing of the water level of the control buffer.
  • the method further includes:
  • the write rate of the data cache is formed based on the recovery clock, and usually one data is written in one recovery clock cycle.
  • the need to adjust the write rate is equivalent to adjusting the recovered clock.
  • the states of the data cache and the control cache are divided into three states: a capture state, a lock state, and a tracking state.
  • the foregoing determining the write rate of the data cache according to the water level of the control cache generally occurs when the state of the control cache is capture and trace.
  • both the control cache and the data cache can be switched between three states of a capture state, a lock state, and a tracking state.
  • the control cache can be executed from a capture state After the lock operation, the lock state is entered, and the lock state can be returned to the capture state after performing the unlock operation, and the adjustment clock needs to be reselected.
  • the data cache can be switched from the locked state to the tracking state, and enters the locked state after the unlocking operation from the tracking state, or goes through an unlocking operation or enters a capturing state.
  • both the control buffer and the data buffer are in an captured state, and in the captured state, an attempt is made to form a recovery clock identical to the data source clock on the transmitting side.
  • the change amount ⁇ of the water level of the control buffer in the specified time period is counted, and the difference between the recovered clock and the data source clock on the transmitting side is estimated according to the ⁇ prediction.
  • the Nadj is an amount of data written in the data buffer per unit time; the ⁇ n1 is an adjustment amount of the data amount written by the data buffer per unit time; and the N is a write received from the receiving side in a unit time.
  • the amount of data is the aforementioned average write rate; the th1 is the threshold for controlling the water level adjustment of the buffer.
  • the amount of change in the water level of the control buffer is between [-th1, th1]
  • the water level of the control buffer is in a safe state, and the water level of the control buffer is continuously tracked, according to the control cache.
  • the water level performs subsequent clock recovery.
  • the write rate of the data buffer the water level of the control buffer is quickly adjusted, thereby achieving the purpose of controlling the amount of change of the water level of the control buffer to be in a safe state.
  • the buffer can be controlled to enter the locked state.
  • the control cache In the capture phase, only relying on the control cache to achieve the lock condition, you can not care about the data cache state, so the cache area corresponding to the data cache can be made small, thereby reducing the use of system resources such as cache resources.
  • the recovery clock formed on the transmitting side is close to or the same as the clock source clock on the transmitting side, but the water level of the data buffer is high, and if the writing rate of the data buffer suddenly increases, This will result in a rapid overflow of the data cache, resulting in data discarding.
  • the water level of the data cache is low, the write rate of the data cache is not The adjustment of the time still maintains a high write rate, which may cause all the data in the data cache to be written out, and the suspension of data writing occurs.
  • the method further includes:
  • the amount of change may be the amount of change in the control water level per unit time; or the amount of change in the control water level within a specified length of time.
  • adjusting the write clock to adjust the write rate of the data cache such that the water level of the data buffer is within the second threshold range.
  • Steady state data buffer water level th3 ⁇ data_fifo_level ⁇ th2.
  • Th2 and th3 are set in the vicinity of the intermediate value of the amount of data that can be stored in the buffer area corresponding to the data cache, so that the data buffer is in the safest state.
  • the water level of the data buffer satisfies th3 ⁇ data_fifo_level ⁇ th2, it indicates that the data cache performs a locking operation and enters the tracking state.
  • the ⁇ n2 described in this embodiment is the step value for adjusting the write rate, that is, the step value for adjusting the recovery clock. It should be noted that the first threshold range described in this embodiment may be the aforementioned [-th1, th1].
  • the read and write rates on both sides of the control cache and the data cache are completely the same, and the drift of the data source clock is tracked depending on controlling the change of the buffer water level. If the drift of the write rate causes the water level of the data cache to exceed the lock condition of the data cache, ie, data_fifo_level>th2 or data_fifo_level ⁇ th3, it will jump to the lock state, causing the data cache to enter the lock state again after reaching the lock condition, ensuring data cache. safety.
  • the data cache and control cache are always in dynamic balance, ensuring the stability of the system for long-term operation.
  • the clock capture and formation according to the water level of the control buffer is adopted, and the data source clock of the transmitting side can be quickly captured, which can significantly improve the capture rate.
  • the buffer size of the data cache can be reduced without considering the overflow of the data cache.
  • switching between the capture state, the lock state, and the tracking state can be performed to implement continuous tracking, which effectively solves the short-term burstiness and the sudden problem caused by the drift of the clock source on the transmitting side.
  • the water level of the control buffer By adopting the water level of the control buffer, the clock recovery error caused by the sudden overflow of the data buffer is avoided, and the recovered clock has the advantages of small jitter and high precision.
  • the write rate of the data cache will affect the water level of the control cache; and the water level of the control buffer will affect the frequency of the recovered clock, thereby counteracting the write rate of the data cache, thereby achieving closed loop adjustment of the clock recovery. Thereby, long-term stable control and adjustment of the recovered clock can be realized based on the closed loop, and the stability of the recovered clock is improved.
  • the embodiment provides a clock recovery device, and the device includes:
  • the reading unit 110 is configured to read a water level of the control buffer; the water level of the control buffer is used to represent a difference between the amount of written data of the data buffer and the amount of written data;
  • the recovery unit 120 is configured to form a recovery clock according to the water level of the control buffer.
  • the clock recovery device in this embodiment is a clock recovery device applied to the receiving side or includes A clock recovery device on the receiving side.
  • the reading unit 110 may include a processor or processing chip having information reading.
  • the processor and the processing chip can implement the reading of the water level of the control buffer described above by executing the specified code.
  • the processor may be a structure such as an application processor AP, a digital signal processor DSP, a programmable array PLC, a central processing unit CPU, or a microprocessor MCU.
  • the clock recovery device directly controls the clock recovery according to the water level of the control buffer, thereby performing clock recovery control with respect to the water level of the data buffer which is prone to overflow and the like, and the generated recovery clock has accuracy and The advantage of high precision.
  • the recovery unit 120 includes:
  • the comparison module 121 is configured to compare the water level of the control buffer with a loop count of the local clock to form a comparison result; the loop count of the local clock is used to represent the amount of data read by the data cache;
  • the recovery module 122 is configured to form the recovery clock according to the comparison result.
  • the specific structure of the comparison module 121 may include various types of comparators or processors having comparison functions to form the comparison result.
  • the recovery module 122 includes a crystal oscillator or a VCXO or the like that generates a recovery clock.
  • the recovery module 122 may include a clock formation structure such as a crystal oscillator capable of forming a clock, and is connected to the comparison module 121 to form the recovery clock according to the output of the comparison module 121.
  • a clock formation structure such as a crystal oscillator capable of forming a clock
  • the comparison module 121 includes:
  • a first output submodule configured to output an adjustment signal of a logic high level when a water level of the control buffer is greater than a loop count of the local clock
  • a second output submodule configured to output an adjustment signal of a logic low level when the water level of the control buffer is less than a loop count of the local clock
  • the recovery unit 120 is configured to perform a logic high level and a logic low power according to the adjustment signal.
  • the flat ratio determines the frequency of the recovered clock.
  • the comparison module 121 in this embodiment includes a first output sub-module and a second output sub-module, and the two output modules are respectively used for a logic high level and a logic low level.
  • the adjustment signal received by the recovery module 122 from the comparison module 121 may be a logic high level and sometimes a logic low level.
  • the recovery module 122 adjusts the frequency of the clock formed by the recovery module according to the adjustment signal.
  • adjusting the recovery clock in this application refers to adjusting the frequency of the recovery clock.
  • the device further includes:
  • a statistical unit configured to count an average write rate of the data cache within a specified time; wherein the average write rate and the water level of the data cache are used to jointly form a water level of the control cache.
  • the specific structure of the statistical unit may include a counter or a processor having a counting function, etc., and the average writing rate of the written data buffer in a specified time period may be evaluated by counting the amount of data written in the specified time.
  • the frequency of the recovered clock can be quickly adjusted to achieve fast capture of the recovered clock.
  • the clock recovery device of this embodiment further includes a smoothing processing unit.
  • the smoothing processing unit is configured to perform smoothing processing on the average write rate and the water level of the data buffer to form a smoothing processing result, so that the amount of write data of the data buffer is evenly distributed to each time period;
  • the smoothing result is used to form a water level of the control buffer.
  • the structure of the smoothing processing unit may include a circuit, a processor, or a processing chip capable of forming various control signals.
  • the device in this embodiment can avoid the phenomenon that the clock frequency jumps excessively during the clock recovery process by using the smoothing processing unit.
  • the recovery unit 120 is further configured to adjust a write rate of the data cache by adjusting the recovery clock according to the water level of the control cache.
  • the adjustment module may include a clock generating device, such as a structure including various crystal oscillators or VCXO capable of forming a clock.
  • the write rate of the data buffer can be adjusted by adjusting the generated recovery clock, so that the water level of the data buffer can be lowered and the water level of the buffer can be controlled.
  • the recovery unit 120 is further configured to detect a water level of the data cache when the water level change amount of the control buffer is maintained within a first threshold range; the water level of the data cache represents the data cache The amount of data written; when the water level of the data buffer is outside the second threshold range, the write rate is adjusted such that the water level of the data buffer is within the second threshold range.
  • the recovery unit 120 adjusts the write rate of the data cache by adjusting the frequency of the recovery clock, thereby achieving the purpose of controlling the water level of the data cache to be in a safe state.
  • FIG. 5 is a flowchart of a clock recovery method according to an embodiment of the present application.
  • the clock recovery methods described in this example include:
  • the data buffer performs data sampling and data writing according to the write clock.
  • a write valid flag is also received; the write valid flag is simultaneously input into a statistical unit that performs data statistics to perform statistics on the amount of write data within a specified time.
  • the timer in the figure is used to calculate the specified time, and the statistical time may be M local clock cycles.
  • This N is the amount of data written into the data buffer per unit time determined according to the amount of write data of the statistical time , which is equivalent to the average write rate of the foregoing embodiment.
  • the statistical result is adjusted, and the N is adjusted to Nadj according to the water level of the control buffer and the water level of the data buffer.
  • the data valid identification bit is the result of the foregoing smoothing process.
  • the control buffer receives the write clock and the data valid identification bit; and adds 1 to the result of logically processing the write clock and the data identifier bit.
  • This control of the cached water level will soon determine the amount of data written to and buffered from the data cache, and will also be determined by the statistical result N.
  • the control cache will also receive the recovery clock and write out the flag bit; the result of the logic and processing after recovering the clock and writing out the flag bit indicates that the data buffer has written a data. At this point, the control cache will be decremented by one.
  • An adjustment signal is generated according to the water level of the control buffer.
  • the adjustment signal includes a logic high level and a logic low level; after the low pass filtering LPF processing, a control voltage is formed. This control voltage can be used to control the frequency of the recovered clock generated by the VCXO.
  • An embodiment of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute at least one of the foregoing clock recovery methods, for example, as shown in FIG. 1a.
  • the computer storage medium may be various types of storage media, such as optical disks, hard disks, USB flash drives, magnetic tapes, and the like, and may be non-transitory storage media.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated.
  • the components displayed as the unit may be, or may not be, physical units, that is, may be located in one place, or may be distributed to multiple network units; some or all of the units may be selected according to actual needs to implement the solution of the embodiment. purpose.
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the above integration
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing storage device includes the following steps: the foregoing storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • ROM read-only memory
  • RAM random access memory
  • magnetic disk or an optical disk.
  • optical disk A medium that can store program code.

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Abstract

本发明公开了一种时钟恢复方法及装置，所述方法包括：读取控制缓存的水位；所述控制缓存的水位用于表征数据缓存的写入数据量和写出数据量的差值；依据所述控制缓存的水位，形成恢复时钟。本发明实施例还公开了一种计算机存储介质。

Description

时钟恢复方法、装置和计算机存储介质 技术领域
本发明涉及通信领域的同步技术，尤其涉及一种时钟恢复方法、装置和计算机存储介质。
背景技术
在进行数据传输时，通常可能涉及到时钟恢复，若接收侧无法恢复出发送侧的时钟，就会导致数据解调的困难，而导致数据接收错误。若接收侧所恢复的恢复时钟不够精确，会导致数据接收的错误率高等问题。
在现有技术中时钟恢复的方法包括对接收侧发送的数据进行一段时间的数据量进行积累，读取该段时间内所述数据缓存的水位变换，依据所述数据缓存的水位变换以及该段时间的时间间隔，估算出发送侧的时钟频率，这种方式存在的问题是：以数据缓存的水位进行数据的积累，这时可能要求所述数据缓存的缓存空间较大，若数据缓存的缓存空间不够，在所述数据缓存的写入速率较大时，可能会在该段时间内出现数据溢出的现象，这样显然会影响时钟恢复的结果，显然消耗的缓存等资源较大。
发明内容
有鉴于此，本发明实施例期望提供一种时钟恢复方法、装置和计算机存储介质，以至少部分解决数据缓存内数据溢出等现象导致的时钟恢复的精度低的问题。
本发明的技术方案是这样实现的：本发明实施例第一方面提供一种时钟恢复方法，所述方法包括：
读取控制缓存的水位；所述控制缓存的水位用于表征数据缓存的写入 数据量和写出数据量的差值；
依据所述控制缓存的水位，形成恢复时钟。
基于上述方案，所述依据所述控制缓存的水位，形成恢复时钟，包括：
将所述控制缓存的水位与本地时钟的循环计数进行比较，形成比较结果；所述本地时钟的循环计数为所述数据缓存依据本地时钟写入数据的采样周期的循环计数；
依据所述比较结果，形成所述恢复时钟。
基于上述方案，所述将所述控制缓存的水位与本地时钟的循环计数进行比较，形成比较结果，包括：
当所述控制缓存的水位大于所述本地时钟的循环计数时，输出为逻辑高电平的调整信号；
当所述控制缓存的水位小于所述本地时钟的循环计数时，输出为逻辑低电平的调整信号；
所述依据所述比较结果，形成恢复时钟，包括：
依据所述调整信号，形成所述恢复时钟。
基于上述方案，所述方法还包括：
统计指定时间内所述数据缓存的平均写入速率；
其中，所述平均写入速率和所述数据缓存的水位用于共同形成所述控制缓存的水位。
基于上述方案，所述方法还包括：
对所述平均写入速率和所述数据缓存的水位进行平滑处理，形成平滑处理结果，以使所述数据缓存的写入数据量均匀分布到各个时间段；
所述平滑处理结果用于形成所述控制缓存的水位。
基于上述方案，所述方法还包括：
依据所述控制缓存的水位，通过调整所述恢复时钟以调整所述数据缓 存的写出速率。
基于上述方案，所述方法还包括：
当所述控制缓存的水位变化量保持在第一阈值范围内时，检测所述数据缓存的水位；所述数据缓存的水位表征所述数据缓存中待写出的数据量；
当所述数据缓存的水位位于第二阈值范围外时，通过调整所述恢复时钟以调整所述数据缓存的写出速率，以使所述数据缓存的水位处于所述第二阈值范围内。
本发明实施例第二方面提供一种时钟恢复装置，所述装置包括：
读取单元，配置为读取控制缓存的水位；所述控制缓存的水位用于表征数据缓存的写入数据量和写出数据量的差值；
恢复单元，配置为依据所述控制缓存的水位的比较结果，形成恢复时钟。
基于上述方案，所述恢复单元还包括：
比较模块，配置为将所述控制缓存的水位与本地时钟的循环计数进行比较，形成比较结果；所述本地时钟的循环计数为所述数据缓存依据本地时钟写入数据的采样周期的循环计数；
恢复模块，配置为依据所述比较结果，形成所述恢复时钟。
基于上述方案，所述比较模块，包括：
第一输出子模块，配置为当所述控制缓存的水位大于所述本地时钟的循环计数时，输出为逻辑高电平的调整信号；
第二输出子模块，配置为当所述控制缓存的水位小于所述本地时钟的循环计数时，输出为逻辑低电平的调整信号；
所述恢复模块，配置为依据所述调整信号中逻辑高电平与逻辑低电平的比值，确定所述恢复时钟的频率。
基于上述方案，所述装置还包括：
统计单元，配置为统计指定时间内所述数据缓存的平均写入速率；
其中，所述平均写入速率和所述数据缓存的水位用于共同形成所述控制缓存的水位。
基于上述方案，所述恢复单元，配置为对所述平均写入速率和所述数据缓存的水位进行平滑处理，形成平滑处理结果，以使所述数据缓存的写入数据量均匀分布到各个时间段；
所述平滑处理结果用于形成所述控制缓存的水位。
基于上述方案，所述恢复单元，配置为依据所述控制缓存的水位，通过调整所述恢复时钟以调整所述数据缓存的写出速率。
基于上述方案，所述确定模块，配置为当所述控制缓存的水位变化量保持在第一阈值范围内时，检测所述数据缓存的水位；所述数据缓存的水位表征所述数据缓存中待写出的数据量；当所述数据缓存的水位位于第二阈值范围外时，通过调整所述恢复时钟以调整所述数据缓存的写出速率，以使所述数据缓存的水位处于所述第二阈值范围内。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行上述时钟恢复方法的至少其中之一。
本发明实施例所述时钟恢复方法、装置和计算机存储介质，在进行所述时钟恢复时的依据的是控制缓存的水位，而非数据缓存的水位；这样就避免了所述数据缓存溢出时导致数据缓存的水位出现大变化，进而导致形成的恢复时钟准确性和精确性差的问题。同时，不用再防止数据缓存的溢出影响恢复时钟的准确性和精确性，可以适当的缩小所述数据缓存对应的缓存容量，从而能够减少缓存容量等系统资源。
附图说明
图1a为本发明实施例所述的时钟恢复方法的流程示意图之一；
图1b为本发明实施例所述的时钟恢复方法的流程示意图之二；
图2为本发明实施例所述比较结果的效果示意图；
图3为本发明实施例所述的时钟恢复的状态变换示意图；
图4a为本发明实施例所述的时钟恢复装置的结构示意图之一；
图4b为本发明实施例所述的时钟恢复装置的结构示意图之二；
图5为本发明实施例所述的时钟恢复的流程示意图之三。
具体实施方式
以下结合说明书附图及具体实施例对本发明的技术方案做进一步的详细阐述；应当理解，以下所说明的优选实施例仅用于说明和解释本发明，并不用于限定本发明。
如图1a所示，本实施例提供一种时钟恢复方法，所述方法包括：
步骤S110：读取控制缓存的水位；所述控制缓存的水位用于表征数据缓存的写入数据量和写出数据量的差值；
步骤S120：依据所述控制缓存的水位，形成恢复时钟。
本实施例所述的时钟恢复方法，为应用于数据接收侧的装置中，具体如光信号的接收端等接收设备中。
所述数据缓存用于从发送侧接收数据并缓存，同时将所述数据缓存内已缓存的数据写出。所述控制缓存用于表征所述数据缓存的写入数据量和写出数据量的差值。
所述控制缓存可相当于一个加减计数器，可用于当所述数据缓存写入一个单位数据时加1；当所述数据缓存写出一个单位的数据时减1。这样的话，若所述数据缓存正常工作，这样就能精确表明出所述数据缓存工作时，数据缓存中写入和写出的数据量。当然，本实施例中的所述控制缓存对所述数据缓存出现溢出等状况时，所述数据缓存的数据溢出不是数据正常写出，不影响所述控制缓存的水位。例如，若当前控制缓存的水位为S1；若 数据缓存溢出S2个单位的数据，这一部分溢出的数据可不影响所述控制缓存的水位，所述控制缓存的水位在溢出S2个单位的数据后，保持S1。
本实施例中所述1个单位的数据可理解为一个采用周期能够采样到的数据量，具体如1个比特的数据。
本实施例中利用控制缓存的水位简单的知道了数据缓存在一段时间内的写入速率和写出速率之间的差值。若所述数据缓存的写入速率大于所述数据缓存的写出速率，显然这样的所述控制缓存的水位会变高；所述数据缓存在该段时间内的写入速率小于写出速率，这样所述控制缓存的水位会变低。显然这样所述控制缓存的水位能够精确的表明所述数据缓存的写入数据和写出速率之间的差异。通过读取控制缓存的水位来确定所述数据缓存的写入速率和写出速率之间的关系，显然不会因为数据缓存的溢出导致时钟恢复精确度出现较大偏差的问题，显然提高了时钟恢复的精度。且用于不用特意的防止所述数据缓存的溢出，可以适当的减少所述数据缓存对应的缓冲区域，从而能够减少时钟恢复中占用的缓存等系统资源。
具体如何依据所述控制缓存的水位来控制时钟恢复，有很多种方式，以下提供一种可选方式。
如图1b所示，所述步骤S120包括：
步骤S121：将所述控制缓存的水位与本地时钟的循环计数进行比较，形成比较结果；所述本地时钟的循环计数为所述数据缓存依据本地时钟写入数据的采样周期的循环计数；
步骤S122：依据所述比较结果，形成恢复时钟。
所述数据缓存进行数据缓存时，是采用本地时钟进行数据采样的，所述数据缓存每一个本地时钟进行一次数据采样形成一个所述采样周期。所述本地时钟的循环计数就计1。如在所述数据缓存在进行本次数据采样之前，所述本地时钟的循环计数为N，则所述数据缓存执行了本次数据采用 之后，所述本地十周的循环计数为M。所述控制缓存的水位则是在所述数据缓存有一个单位数据写入时，计数加1。若当前数据缓存采用本地时钟进行采样，采样了N次，其中n次有采样到数据，(这里的有采样到数据表示有数据写入到所述数据缓存)，则所述本地时钟的循环计数为N，所述控制缓存的水位加n。
在本实施例中对所述数据缓存的采样次数是进行循环计数的，即当所述数据计数值达到最大计数值，则所述本地时钟循环计数清零。在本实施例中所述控制缓存的水位的取值也是有上限的，通常超过所述上限，所述控制缓存的水位做饱和处理。此处的所述饱和处理为：若数据缓存的写入速率继续大于所写出数据，所述控制缓存的水位不再上升维持在计数上限。在本实施例中可选的为将所述控制缓存的上限和所述本地循环计数的最大计数值都设置为同样的取值。
在本实施例中将比较所述本地时钟的循环计数与所述控制缓存的水位，形成比较结果；这个比较结果将作用于恢复时钟的形成和产生。
所述步骤S121可包括：
当所述控制缓存的水位大于所述本地时钟的循环计数时，输出为逻辑高电平的调整信号；
当所述控制缓存的水位小于所述本地时钟的循环计数时，输出为逻辑低电平的调整信号。
本实施例所述逻辑高电平和所述逻辑低电平是相对而言的，这里逻辑高电平和所述逻辑低电平相对于同一参考电平时，所述逻辑高电平对应的电平高于所述逻辑低电平的对应的电平。所述逻辑高电平和所述逻辑低电平形成所述调整信号。若所述本地时钟的循环次数的最大计数值为K个，则所述一个所述调整信号对应的时间长度等于K个所述本地时钟的周期。
所述步骤S122可包括：依据所述调整信号，形成所述恢复时钟。此处， 具体可包括：计算所述调整信号的占空比，依据所述占空比来形成所述恢复时钟。
如图2所示，一个所述调整信号中为逻辑高电平的时间为T1，为逻辑低电平的时间为T2；则所述占空比可为T1/(T1+T2)。
在步骤S120中具体产生所述恢复时钟的方法，包括采用工作在目标频率f1的时钟源产生目标时钟f1。依据所述占空比调整所述f1，形成所述恢复时钟f2。此处的时钟源可为各种类型的产生时钟的结构，如压控振荡器VCXO等结构。所述VCXO在电压控制下晶振产生时钟。假设所述f2和所述f1之间满足如下函数关系：
f2＝f1+2{T1/(T1+T2)-0.5}*X
这样的话，当所述占空比为1时，所述f2＝f1+X*f1；所述X可为时钟调整范围，所述X的取值范围一般可为任意指定值，具体如，所述X的取值为100PPM。若所述占空比为0时，所述f2＝f1-X*f1。若所述占空比为0.5时，所述f2＝f1。显然这样的话，所述控制缓存的水位将决定所述恢复时钟的调整。所述恢复时钟的精度等于2X*f1/K。
作为本实施例的进一步改进，所述方法还包括：
统计指定时间内所述数据缓存的平均写入速率；
其中，所述平均写入速率和所述数据缓存的水位用于共同形成所述控制缓存的水位。此时，所述控制缓存的水位表征的不仅包括写入数据量和写出数据量的差值，还包括所述平均写入速率。
所述控制缓存的水位能够表征所述数据缓存待写出的数据量。
侧接收数据发送数据是存在一定的规律，在本实施例中所述接收侧将对指定时间内所述数据接收数据的写入数据进行统计，从而知道所述接收端发送数据的大致规律。这个规律就体现为所述写入数据的指定时间内的平均写入速率。这里所述写入数据的状况信息可理解为接收端大致每M个所述接收端的本地时钟周期发送数据量大致相同。
本实施例中的所述统计时间即为根据所述数据的规律确定的时间段，具体如M个本地时钟周期。
假设如每隔M个本地时钟周期内，所述数据缓存写入数据量为P。但是可能存在这样的情况，在所述M个本地时钟周期内，仅有前面的m1个时钟有数据写入，若不经过所述平滑处理的话，则会导致所述控制缓存的水位因前m1个周期内有数据写入，而迅速上升。在本实施例中将会对所述写入数据量做平滑处理，并形成的平滑处理结果。所述平滑处理结果是使得写入数据平均分配在各个时间段。所述指定时间可以为当前时间之前的历史时间。即所述M个本地时钟周期可为当前时刻以前的M个本地时钟周期。
在进行时钟恢复时，若所述控制缓存的水位仅用于表征所述数据缓存的写入数据量和写出数据量，则依据所述控制缓存的水位进行时钟恢复到与发送侧的数据源时钟相差到指定范围内，虽然能够进行时钟调整，但是相对缓慢。在本实施例中通过统计指定时间内的平均写入速率，就大概知道发送侧时钟源时钟，若所述控制缓存的水位是根据所述数据缓存的水位和平均写入速率共同形成的，那么根据控制缓存的水位进行时钟恢复，就快速恢复到与发送侧时钟源相近的时钟范围内，从而提高时钟捕获的速率。
作为本实施例进一步改进，所述方法还包括：
对所述平均写入速率和所述数据缓存的水位进行平滑处理，形成平滑处理结果，以使所述数据缓存的写入数据量均匀分布到各个时间段；
所述平滑处理结果用于形成所述控制缓存的水位。
在本实施例中将对平均写入速率和数据缓存的水位进行平滑处理，这样的话不会导致控制缓存的水位在某个时间点发送突变，若不进行平滑处理，直接依据突变的控制缓存的水位进行时钟恢复，这回导致恢复时钟的频率在对应的时间点也会发生变化。恢复时钟的这种突变会导致数据接收 过程中的其他不良问题。
例如，100个本地时钟周期内的前50个时钟有数据写入，则进行平滑处理之后会使得写入数据在每隔一个本地时钟周期有数据写入。这样的话，第1、3、5、7、9、……99个本地时钟周期有数据写入，而非是前50个本地时钟。由于发送侧的发送数据的规律性，这种规律性从一定程度上体现了发送侧的数据源时钟，本实施例中通过统计指定时间内的写入数据的状况信息，在形成所述恢复时钟时，就能预估出时钟源时钟的大致频率，从而能够快速的形成一个较为接近所述时钟源的恢复时钟，后续仅需通过依据控制缓存的水位进行细微的调整即可，显然加快形成与所述时钟源时钟相近的精确的恢复时钟的时钟捕获速率。且由于平滑处理可以避免根据控制缓存的水位平滑的进行所述恢复时钟的频率调整。
所述方法还包括：
依据所述控制缓存的水位，通过调整所述恢复时钟以调整所述数据缓存的写出速率。
当所述控制缓存的水位很高时或基于所述数据缓存当前的写入速率和写出速率，导致所述控制缓存的水位逐步增高到一定的阈值时，这时就需要调整所述数据缓存的写出速率，从而降低所述控制缓存的水位。
当然所述数据缓存的写出速率是基于恢复时钟形成的，通常一个恢复时钟周期写出一个数据。这里需要调整所述写出速率相当于调整所述恢复时钟。
所述数据缓存和控制缓存的状态均分为三个状态包括：捕获状态、锁定状态以及跟踪状态。前述的依据所述控制缓存的水位，调整所述数据缓存的写出速率，通常发生在所述控制缓存的状态为捕获及跟踪时。
如图3所示，所述控制缓存和数据缓存都可以在捕获状态、锁定状态以及跟踪状态三个状态之间进行切换。所述控制缓存可以从捕获状态执行 锁定操作后，进入锁定状态，还可以从锁定状态通过执行解锁操作后返回到捕获状态，需要重选调整时钟。所述数据缓存可以从锁定状态切换到跟踪状态，并从跟踪状态通过解锁操作后进入锁定状态，或经过解锁操作或进入捕获状态。
通常当接收侧装置刚启动时，所述控制缓存和所述数据缓存都处于捕获状态，在捕获状态将试图形成与发送侧的数据源时钟相同的恢复时钟。
在捕获状态时，统计指定时间内所述控制缓存的水位的变化量δ，根据所δ预估恢复时钟与发送侧数据源时钟的差别。
如果δ>th1，写出速率Nadj＝N+Δn1，如果δ<-th1，Nadj＝N-Δn1。所述Nadj为单位时间上所述数据缓存的写出数据量；所述Δn1为单位时间上所述数据缓存写出数据量的调整量；所述N为单位时间内从接收侧接收的写入数据量，即为前述的平均写入速率；所述th1为控制缓存的水位调整的阈值。显然在本示例中，所述控制缓存的水位的变化量处于[-th1，th1]之间时，所述控制缓存的水位处于安全状态下，持续跟踪所述控制缓存的水位，依据控制缓存的水位进行后续的时钟恢复。这样的话，通过使数据缓存的写出速率的变换，从而快速的调整所述控制缓存的水位，从而达到控制所述控制缓存的水位的变换量处于安全状态的目的。
当然，如果-th1<δ<th1，说明接收侧装置形成恢复时钟与发送侧数据源时钟接近，则可以控制缓存都可以进入锁定状态。在捕获阶段，只依赖于控制缓存来达到锁定条件，可以不关心数据缓存状态，因此数据缓存对应的缓存区域可以做得很小，从而减少缓存资源等系统资源的使用。
若所述控制缓存处于锁定状态后，相当于发送侧形成的恢复时钟与发送侧时钟源时钟很接近或相同，但是所述数据缓存的水位很高，若突然数据缓存的写入速率增大，就会导致数据缓存的迅速溢出，从而导致数据丢弃的现象；同时若所述数据缓存的水位很低，数据缓存的写出速率没有及 时的调整，依然保持较高的写出速率，可能就会导致数据缓存内的数据全部被写出，出现数据写出的中止等问题。为了解决这些问题，在本实施例中还对上述方法做了以下改进。
所述方法还包括：
当所述控制缓存的水位变化量保持在第一阈值范围内时，检测所述数据缓存的水位；所述数据缓存的水位表征所述数据缓存中待写出的数据量；这里的控制的水位的变化量，可为单位时间内所述控制水位的变化量；或指定时长内的所述控制水位的变化量。
当所述数据缓存的水位位于第二阈值范围外时，通过调整所述恢复时钟以调整所述数据缓存的写出速率，以使所述数据缓存的水位处于所述第二阈值范围内。
具体如，数据缓存的水位data_fifo_level大于th2，Nadj＝N+Δn2，如果data_fifo_level<th3，Nadj＝N-Δn2，使得控制缓存水位变化，调整VCXO恢复时钟的频点，最终使控制缓存与数据缓存达到平稳状态，数据缓存水位th3<data_fifo_level<th2。th2和th3设置在数据缓存对应的缓存区域可存储数据量的中间值附近，以便使得数据缓存处于最安全状态。当数据缓存的水位满足th3<data_fifo_level<th2使，表明数据缓存执行锁定操作，进入跟踪状态。
本实施例所述的Δn2即为所述调整所述写出速率的步长值，也即为调整所述恢复时钟的步长值。值得注意的是，本实施例中所述的第一阈值范围可为前述的[-th1，th1]。
依据所述恢复时钟加快所述数据缓存的写出速率，并使所述数据缓存内的水位降低，腾出更多的剩余缓存空间。这样的话所述控制缓存的水位也会迅速降低。依据所述恢复时钟减小所述数据缓存的写出速率，保持所述数据缓存内的水位处于一定的高度，避免数据缓存内没有数据写出导致 的写出中止的现象。
当所述数据缓存进入跟踪状态之后，控制缓存和数据缓存两侧读写速率完全一致，依赖于控制缓存水位变化情况跟踪数据源时钟的漂移。如果写入速率的漂移导致数据缓存的水位超过数据缓存的锁定条件，即data_fifo_level>th2或data_fifo_level<th3，会跳转到锁定状态，使数据缓存再次在达到锁定条件进入锁定状态，保证数据缓存的安全性。数据缓存和控制缓存始终处于动态平衡状态，保证了系统长期运行的稳定性。
综合上述本实施例所述时钟恢复方法，采用根据控制缓存的水位来进行时钟的捕获和形成，能够快速的捕获发送侧数据源时钟，能够显著的提高捕获速率。其次，由于是基于控制缓存的水位来进行时钟捕获的，在不考虑所述数据缓存的溢出的状况下，能够减小所述数据缓存的缓冲大小。
在本实施例中所述时钟恢复方法中，可以在捕获状态、锁定状态和跟踪状态之间进行切换，实现连续跟踪，有效解决短期突发性和发送侧时钟源漂移导致的突发问题。采用控制缓存的水位，避免了数据缓存突然溢出导致的时钟恢复误差大等显现，从而形成的恢复时钟，具有抖动小及精确度高的优点。数据缓存的写出速率将影响所述控制缓存的水位；而所述控制缓存的水位将影响恢复时钟的频率，从而反作用于所述数据缓存的写出速率，从而实现了时钟恢复的闭环调整，从而能够基于这种闭环实现所述恢复时钟的长期稳定的控制和调整，提高了恢复时钟的稳定性。
设备实施例：
如图4a所示，本实施例提供一种时钟恢复装置，所述装置包括：
读取单元110，配置为读取控制缓存的水位；所述控制缓存的水位用于表征数据缓存的写入数据量和写出数据量的差值；
恢复单元120，配置为依据所述控制缓存的水位，形成恢复时钟。
本实施例中所述时钟恢复装置为应用在接收侧的时钟恢复装置或包括 在所述接收侧的时钟恢复装置。
所述读取单元110可包括具有信息读取的处理器或处理芯片。所述处理器和处理芯片可通过执行指定代码来实现上述控制缓存的水位的读取。所述处理器可为应用处理器AP、数字信号处理器DSP、可编程阵列PLC、中央处理器CPU或微处理器MCU等结构。
在本实施例中所述时钟恢复装置直接依据控制缓存的水位来控制时钟恢复，从而相对于依据容易出现溢出等现象的数据缓存的水位来进行时钟恢复的控制，形成的恢复时钟具有准确性和精确性高的优点。
如图4b所述，所述恢复单元120包括：
比较模块121，配置为将所述控制缓存的水位与本地时钟的循环计数进行比较，形成比较结果；所述本地时钟的循环计数用于表征所述数据缓存读取的数据量；
恢复模块122，配置为依据所述比较结果，形成所述恢复时钟。
所述比较模块121的具体结构可包括各种类型的比较器或具有比较功能的处理器，来形成所述比较结果。
所述恢复模块122包括产生恢复时钟的晶振或VCXO等结构。
所述恢复模块122可包括能够形成时钟的晶振等时钟形成结构，将与所述比较模块121连接，依据所述比较模块121的输出来形成所述恢复时钟。
所述比较模块121，包括：
第一输出子模块，配置为当所述控制缓存的水位大于所述本地时钟的循环计数时，输出为逻辑高电平的调整信号；
第二输出子模块，配置为当所述控制缓存的水位小于所述本地时钟的循环计数时，输出为逻辑低电平的调整信号；
所述恢复单元120，配置为依据所述调整信号中逻辑高电平与逻辑低电 平的比值，确定所述恢复时钟的频率。
本实施例中所述比较模块121包括第一输出子模块和第二输出子模块，这两个输出模块分别用于逻辑高电平和逻辑低电平。这样的话，所述恢复模块122从比较模块121收到的调整信号，可能时而为逻辑高电平，时而为逻辑低电平。所述恢复模块122根据所述调整信号，调整其形成的时钟的频率。
值得注意的是，在本申请中调整恢复时钟，均指的是调整恢复时钟的频率。
此外，所述装置还包括：
统计单元，配置为统计指定时间内所述数据缓存的平均写入速率；其中，所述平均写入速率和所述数据缓存的水位用于共同形成所述控制缓存的水位。
所述统计单元具体结构可包括计数器或具有计数功能的处理器等结构，可以通过对指定时间内写入数据量的统计，从而评估出指定时间内写入数据缓存的平均写入速率。
本实施例中通过在时钟恢复装置增加统计单元，可以实现快速的调整所述恢复时钟的频率，实现恢复时钟的快速捕获。
本实施例所述的时钟恢复装置还包括平滑处理单元。
所述平滑处理单元，配置为对所述平均写入速率和所述数据缓存的水位进行平滑处理，形成平滑处理结果，以使所述数据缓存的写入数据量均匀分布到各个时间段；
所述平滑处理结果用于形成所述控制缓存的水位。所述平滑处理单元的结构可包括能够形成各种控制信号的电路、处理器或处理芯片等结构。
本实施例所述的装置通过平滑处理单元，能够避免时钟恢复过程中恢复时钟频率跳变过大的现象。
所述恢复单元120，还配置为依据所述控制缓存的水位，通过调整所述恢复时钟以调整所述数据缓存的写出速率。
所述调整模块可包括时钟产生装置，具体如包括各种能够形成时钟的晶振或VCXO等结构。通过调整产生的恢复时钟能够调整所述数据缓存的写出速率，从而能够下调所述数据缓存的水位及控制缓存的水位。
此外，所述恢复单元120，还配置为当所述控制缓存的水位变化量保持在第一阈值范围内时，检测所述数据缓存的水位；所述数据缓存的水位表征所述数据缓存中待写出的数据量；当所述数据缓存的水位位于第二阈值范围外时，调整所述写出速率，以使所述数据缓存的水位处于所述第二阈值范围内。
在本实施例中所述恢复单元120通过调整恢复时钟的频率从而调整所述数据缓存的写出速率，从而达到控制所述数据缓存的水位处于安全状态的目的。
以下结合上述任意实施例所述的方案，提供一个具体示例。
图5所示的利用本申请实施例中所述时钟恢复方法的流程图。
本示例所述的时钟恢复方法包括:
数据缓存按照写入时钟进行数据采样接收数据进行数据写入。当接收一个数据时，还会接收到写入有效标志；所述写入有效标志同时输入到进行数据统计的统计单元中进行指定时间内的写入数据量的统计。图中的定时器用于计算所述指定时间，所述统计时间可以为M个本地时钟周期。
数据统计后形成统计结果N。这个N为依据统计时间诶的写入数据量确定的单位时间内写入所述数据缓存的数据量，即相当于前述实施例的平均写入速率。
统计结果调整，依据控制缓存的水位和数据缓存的水位进行所述N调整为Nadj。
对所述Nadj做平滑处理，输出数据有效标位。所述数据有效标识位即为前述平滑处理结果。
控制缓存接收写入时钟及所述数据有效标识位；对所述写入时钟和所述数据标识位进行逻辑与处理后的结果进行加1操作。这样控制缓存的水位不久决定与数据缓存的写入数据量和写出数据量，还将决定于统计结果N。同时控制缓存还将接收恢复时钟和写出标记位；恢复时钟和写出标记位进行逻辑与处理之后得到的结果表明数据缓存写出了一个数据。此时，所述控制缓存将做减1处理。
依据控制缓存的水位生成调整信号。所述调整信号包括逻辑高电平和逻辑低电平；经过低通滤波LPF处理后，形成一个控制电压。该控制电压能够用于控制VCXO产生的恢复时钟的频率。
本发明实施例提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述时钟恢复方法的至少其中之一，例如，可执行如图1a、图1b及图5所示的方法。所述计算机存储介质可为各种类型的存储介质，例如光盘、硬盘、U盘、磁带等各种类型的存储介质，可选为非瞬间存储介质。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的， 作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个处理模块中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，凡按照本发明原理所作的修改，都应当理解为落入本发明的保护范围。

Claims (15)

  1. 一种时钟恢复方法，所述方法包括：
    读取控制缓存的水位；所述控制缓存的水位用于表征数据缓存的写入数据量和写出数据量的差值；
    依据所述控制缓存的水位，形成恢复时钟。
  2. 根据权利要求1所述的方法，其中，
    所述依据所述控制缓存的水位，形成恢复时钟，包括：
    将所述控制缓存的水位与本地时钟的循环计数进行比较，形成比较结果；所述本地时钟的循环计数为所述数据缓存依据本地时钟写入数据的采样周期的循环计数；
    依据所述比较结果，形成所述恢复时钟。
  3. 根据权利要求2所述的方法，其中，
    所述将所述控制缓存的水位与本地时钟的循环计数进行比较，形成比较结果，包括：
    当所述控制缓存的水位大于所述本地时钟的循环计数时，输出为逻辑高电平的调整信号；
    当所述控制缓存的水位小于所述本地时钟的循环计数时，输出为逻辑低电平的调整信号；
    所述依据所述比较结果，形成恢复时钟，包括：
    依据所述调整信号，形成所述恢复时钟。
  4. 根据权利要求1至3任一项所述的方法，其中，
    所述方法还包括：
    统计指定时间内所述数据缓存的平均写入速率；
    其中，所述平均写入速率和所述数据缓存的水位用于共同形成所述控 制缓存的水位。
  5. 根据权利要求4所述的方法，其中，
    所述方法还包括：
    对所述平均写入速率和所述数据缓存的水位进行平滑处理，形成平滑处理结果，以使所述数据缓存的写入数据量均匀分布到各个时间段；
    所述平滑处理结果用于形成所述控制缓存的水位。
  6. 根据权利要求5所述的方法，其中，
    所述方法还包括：
    依据所述控制缓存的水位，通过调整所述恢复时钟以调整所述数据缓存的写出速率。
  7. 根据权利要求6所述的方法，其中，
    所述方法还包括：
    当所述控制缓存的水位变化量保持在第一阈值范围内时，检测所述数据缓存的水位；所述数据缓存的水位表征所述数据缓存中待写出的数据量；
    当所述数据缓存的水位位于第二阈值范围外时，通过调整所述恢复时钟以调整所述数据缓存的写出速率，以使所述数据缓存的水位处于所述第二阈值范围内。
  8. 一种时钟恢复装置，所述装置包括：
    读取单元，配置为读取控制缓存的水位；所述控制缓存的水位用于表征数据缓存的写入数据量和写出数据量的差值；
    恢复单元，配置为依据所述控制缓存的水位的比较结果，形成恢复时钟。
  9. 根据权利要求8所述的装置，其中，
    所述恢复单元还包括：
    比较模块，配置为将所述控制缓存的水位与本地时钟的循环计数进行 比较，形成比较结果；所述本地时钟的循环计数为所述数据缓存依据本地时钟写入数据的采样周期的循环计数；
    恢复模块，配置为依据所述比较结果，形成所述恢复时钟。
  10. 根据权利要求9所述的装置，其中，
    所述比较模块，包括：
    第一输出子模块，配置为当所述控制缓存的水位大于所述本地时钟的循环计数时，输出为逻辑高电平的调整信号；
    第二输出子模块，配置为当所述控制缓存的水位小于所述本地时钟的循环计数时，输出为逻辑低电平的调整信号；
    所述恢复模块，配置为依据所述调整信号中逻辑高电平与逻辑低电平的比值，确定所述恢复时钟的频率。
  11. 根据权利要求8至10任一项所述的装置，其中，
    所述装置还包括：
    统计单元，配置为统计指定时间内所述数据缓存的平均写入速率；
    其中，所述平均写入速率和所述数据缓存的水位用于共同形成所述控制缓存的水位。
  12. 根据权利要求11所述的装置，其中，
    所述恢复单元，配置为对所述平均写入速率和所述数据缓存的水位进行平滑处理，形成平滑处理结果，以使所述数据缓存的写入数据量均匀分布到各个时间段；
    所述平滑处理结果用于形成所述控制缓存的水位。
  13. 根据权利要求12所述的装置，其中，
    所述恢复单元，配置为依据所述控制缓存的水位，通过调整所述恢复时钟以调整所述数据缓存的写出速率。
  14. 根据权利要求13所述的装置，其中，
    所述确定模块，配置为当所述控制缓存的水位变化量保持在第一阈值范围内时，检测所述数据缓存的水位；所述数据缓存的水位表征所述数据缓存中待写出的数据量；当所述数据缓存的水位位于第二阈值范围外时，通过调整所述恢复时钟以调整所述数据缓存的写出速率，以使所述数据缓存的水位处于所述第二阈值范围内。
  15. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至7所述的方法的至少其中之一。
PCT/CN2015/097061 2015-05-28 2015-12-10 时钟恢复方法、装置和计算机存储介质 WO2016188090A1 (zh)

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