WO2016169155A1 - 显示面板及具有该显示面板的显示器 - Google Patents

显示面板及具有该显示面板的显示器 Download PDF

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WO2016169155A1
WO2016169155A1 PCT/CN2015/086663 CN2015086663W WO2016169155A1 WO 2016169155 A1 WO2016169155 A1 WO 2016169155A1 CN 2015086663 W CN2015086663 W CN 2015086663W WO 2016169155 A1 WO2016169155 A1 WO 2016169155A1
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thin film
film transistor
pixel units
pixel
same
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PCT/CN2015/086663
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English (en)
French (fr)
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衣志光
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深圳市华星光电技术有限公司
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Priority to US14/888,172 priority Critical patent/US20170148406A1/en
Publication of WO2016169155A1 publication Critical patent/WO2016169155A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/64—Normally black display, i.e. the off state being black
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a display panel and a display having the same.
  • a display panel comprising: a plurality of pixel units, the pixel unit comprising at least a thin film transistor, wherein a width value of a channel in the thin film transistor is W, a channel in the thin film transistor The length value is L; a plurality of scan lines and a plurality of data lines, the scan lines and the data lines are arranged to intersect to define a position of the pixel unit; and a source driver for connecting the data lines And providing a data signal to each of the data lines; a gate driver for connecting the scan lines and providing a scan signal to the scan lines; wherein adjusting a channel width value W and a channel length in the thin film transistor The ratio of the value L is W/L so that the pixel cells connected to the same scanning line are simultaneously charged.
  • the W/L of the thin film transistor of the previous pixel unit is smaller than the W/L of the thin film transistor of the latter pixel unit.
  • the pixel units connected to the same scan line are divided into a plurality of groups, and the thin film transistors of the latter group of pixel units are sequentially arranged away from the gate driver.
  • the W/L is larger than the W/L of the thin film transistor of the previous group of pixel units, and the W/L of the thin film transistors of the same group of pixel units is the same.
  • an absolute value of a difference between a W/L of a thin film transistor of the previous pixel unit and a W/L of a thin film transistor of the subsequent pixel unit is W/L of a thin film transistor of the subsequent pixel unit.
  • the ratio is proportional to the ratio of the absolute value of the difference between the charging time of the previous pixel unit and the charging time of the latter pixel unit to the charging time of the previous pixel unit.
  • an absolute value of a difference between a W/L of a thin film transistor of the previous group of pixel units and a W/L of a thin film transistor of the latter group of pixel units is different from a thin film transistor of the latter group of pixel units
  • the ratio of /L is proportional to the ratio of the absolute value of the difference between the charging time of the previous set of pixel units and the charging time of the latter group of pixel units to the charging time of the previous set of pixel units.
  • the W/L of the thin film transistors of the pixel cells connected to the same data line are the same.
  • a display comprising the above display panel.
  • the invention completes charging at the same time by the pixel unit connected to the same scanning line, thereby avoiding the phenomenon of display whitening of the pixel unit adjacent to the gate driver side.
  • FIG. 1 shows an architectural diagram of a display panel in accordance with an embodiment of the present invention
  • FIG. 2 shows a schematic diagram of the length and width of a channel of a thin film transistor in accordance with an embodiment of the present invention.
  • LCD liquid crystal display
  • OLED organic light emitting display
  • FIG. 1 shows an architectural diagram of a display panel in accordance with an embodiment of the present invention.
  • 2 shows a schematic diagram of the length and width of a channel of a thin film transistor in accordance with an embodiment of the present invention.
  • display panel at least comprises: a timing controller (not shown), a source driver 2, a gate driver 3, a plurality of data lines S 1 to S n, a plurality of scan lines G 1 to G m and a plurality of pixel units P 11 , ... P 1n , ... P mn .
  • the display panel 1 may further include other suitable types of devices such as a voltage converter (not shown).
  • the timing controller provides timing control signals for the source driver 2 and the gate driver 3 to control the operations of the source driver 2 and the gate driver 3.
  • the source driver 2 is connected to the plurality of data lines S 1 to S n , and supplies data signals to the plurality of data lines S 1 to S n according to a timing control signal provided by the timing controller to drive the plurality of data lines S 1 to S n .
  • n is an integer.
  • the gate driver 3 is connected to the plurality of scan lines G 1 to G m , and supplies scan signals to the plurality of scan lines G 1 to G m according to timing control signals provided by the timing controller to drive the plurality of scan lines G 1 to G m .
  • m is an integer.
  • a plurality of data lines S1 to Sn and the plurality of scanning lines G 1 to G m are arranged perpendicularly intersect each other to form m ⁇ n array.
  • the number of pixel units is m ⁇ n.
  • Each of the pixel units P ij may be disposed at a node between the i-th scan line and the j-th data line (1 ⁇ i ⁇ m, 1 ⁇ j ⁇ n).
  • the pixel unit P ij includes a thin film transistor (TFT), a liquid crystal capacitor, and a storage capacitor.
  • the gate of the TFT is connected to the ith scan line, and the source of the TFT is connected to the jth data line.
  • One end of the liquid crystal capacitor and the storage capacitor are connected to the drain of the TFT, and the other end of the liquid crystal capacitor and the storage capacitor are connected to the ground.
  • the W/L of the thin film transistor of the previous pixel unit is smaller than the thinness of the latter pixel unit in the order of gradually moving away from the gate driver 3.
  • the W/L of the film transistor can realize charging at the same time for all pixel units (ie, the same row of pixel units) connected to the same scanning line, wherein, as shown in FIG. 2, W represents the width of the channel in the thin film transistor, L Indicates the length of the channel in the thin film transistor.
  • the thin film transistor further includes a gate electrode 41, a source electrode 42, and a drain electrode 43.
  • the W/L of the thin film transistor of the previous pixel cell P 1j is smaller than the latter pixel cell P 1 (j+1 ) in the order of gradually moving away from the gate driver 3 . ) a thin film transistor W / L, so that the first row of the pixel unit P 11, whil P 1n simultaneously charging is completed (1 ⁇ j ⁇ n).
  • the absolute value of the difference between the W/L of the thin film transistor of the previous pixel unit and the W/L of the thin film transistor of the latter pixel unit is in the order of gradually moving away from the gate driver 3
  • the ratio of the W/L of the thin film transistor of the pixel unit is proportional to the ratio of the absolute value of the difference between the charging time of the previous pixel unit and the charging time of the latter pixel unit to the charging time of the previous pixel unit.
  • the W/L of the thin film transistors of each of the pixel cells in each column is the same.
  • the first column of the pixel unit P 11, ?? P m1 the first column of the pixel unit P 11, whil thin film transistor of each pixel unit P m1 P i1 of W / L of the same.
  • each row of pixel units is divided into groups according to the order of gradually moving away from the gate driver 3, and the W/L of the thin film transistors of the latter group of pixel units is larger than the previous one.
  • the W/L of the thin film transistor of the group of pixel units, and the W/L of the thin film transistors of the same group of pixel units are the same, so that all the pixel units connected to the same scanning line (ie, the same row of pixel units) can be charged at the same time.
  • W represents the width of the channel in the thin film transistor
  • L represents the length of the channel in the thin film transistor.
  • the thin film transistor further includes a gate electrode 41, a source electrode 42, and a drain electrode 43.
  • the first row of pixel cells P 11 , . . . , P 1n are divided into n/q groups in the order of gradually moving away from the gate driver 3 (q can be divided by n) ), the W/L of the thin film transistor of the latter group of pixel units P 1(n-q+1) , . . . , P 1n is larger than the previous group of pixel units P 1(n-2q+2) , . . .
  • P 1(n -q+1) W/L of the thin film transistor and the same group of pixel units (for example, the latter group of pixel units P 1 (n-q+1) , ... P 1n or the previous group of pixel units P 1 (n The W/L of the thin film transistors of -2q+2) , ...P 1(n-q+1) ) are all the same, so that the first row of pixel cells P 11 , ... P 1n are simultaneously charged (1 ⁇ j ⁇ n).
  • the absolute value of the difference between the W/L of the thin film transistor of the previous group of pixel units and the thin film transistor of the latter group of pixel units is the same as that of the latter group of pixel units.
  • the ratio of the W/L of the thin film transistor is proportional to the ratio of the absolute value of the difference between the charging time of the previous group of pixel units and the charging time of the latter group of pixel units to the charging time of the previous group of pixel units.
  • /(W/L) n/q is proportional to the (n/q)-1 group of pixel units P 1(n-2q+2 ), «
  • P 1 (n-q+1) The ratio of the charging time T (n/q)-1
  • /(W/L) n/q b ⁇
  • the W/L of the thin film transistors of each of the pixel cells in each column is the same.
  • the first column of the pixel unit P 11, ?? P m1 the first column of the pixel unit P 11, whil thin film transistor of each pixel unit P m1 P i1 of W / L of the same.
  • the pixel unit connected to the same scanning line is simultaneously charged, thereby preventing the pixel unit on the side adjacent to the gate driver from appearing white.

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Abstract

一种显示面板（1）及具有该显示面板（1）的显示器，包括：多个像素单元，所述像素单元至少包括薄膜晶体管，薄膜晶体管中沟道的宽度值为W，薄膜晶体管中沟道的长度值为L；多条扫描线和多条数据线，所述扫描线和所述数据线交叉布置，以用于限定所述像素单元的位置；源极驱动器（2），用于连接所述数据线且向每条所述数据线提供数据信号；栅极驱动器（3），用于连接所述扫描线且向所述扫描线提供扫描信号；调制所述薄膜晶体管中沟道宽度值W与沟道长度值L的比值，以使与同一条扫描线相连的像素单元同时完成充电。通过使与同一条扫描线相连的像素单元同时完成充电，从而避免邻近栅极驱动器一侧的像素单元出现显示偏白现象。

Description

显示面板及具有该显示面板的显示器 技术领域
本发明属于显示技术领域，具体地讲，涉及一种显示面板及具有该显示面板的显示器。
背景技术
现有的常暗式(Normal Black)液晶显示器(LCD)中，存在阻容延迟效应(RC delay)，因此在给每行像素单元进行充电时，将每行像素单元中的每个像素单元充满的时间(即每个像素单元的充电时间)不相同。
由于邻近栅极驱动器(Gate IC)一侧的阻容延迟效应较小，而远离栅极驱动器一侧的阻容延迟效应较大，因此针对每行像素单元，在远离栅极驱动器一侧的像素单元还未充满电时，邻近栅极驱动器一侧的像素单元已经完成充电。这样，为了给远离栅极驱动器一侧的像素单元充满电，势必会对邻近栅极驱动器一侧的像素单元形成过充电。此外，还可能出现远离栅极驱动器一侧的像素单元因为阻容延迟效应而无法充到指定电位，使该行像素单元的两端形成电位差，从而导致邻近栅极驱动器一侧出现显示偏白现象。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种避免邻近栅极驱动器一侧出现显示偏白现象的显示面板及显示器。
根据本发明的一方面，提供了一种显示面板，包括：多个像素单元，所述像素单元至少包括薄膜晶体管，所述薄膜晶体管中沟道的宽度值为W，所述薄膜晶体管中沟道的长度值为L；多条扫描线和多条数据线，所述扫描线和所述数据线交叉布置，以用于限定所述像素单元的位置；源极驱动器，用于连接所述数据线且向每条所述数据线提供数据信号；栅极驱动器，用于连接所述扫描线且向所述扫描线提供扫描信号；其中，调整所述薄膜晶体管中沟道宽度值W与沟道长度值L的比值W/L，以使与同一条扫描线相连的像素单元同时完成充电。
进一步地，对于所述同一条扫描线相连的像素单元，按照逐渐远离所述栅 极驱动器的顺序，前一个像素单元的薄膜晶体管的W/L小于后一个像素单元的薄膜晶体管的W/L。
进一步地，对于所述同一条扫描线相连的像素单元，按照逐渐远离所述栅极驱动器的顺序，将所述同一条扫描线相连的像素单元分为多组，后一组像素单元的薄膜晶体管的W/L大于前一组像素单元的薄膜晶体管的W/L，并且同一组像素单元的薄膜晶体管的W/L相同。
进一步地，所述前一个像素单元的薄膜晶体管的W/L和所述后一个像素单元的薄膜晶体管的W/L之差的绝对值与所述后一个像素单元的薄膜晶体管的W/L的比值正比于所述前一个像素单元的充电时间和所述后一个像素单元的充电时间之差的绝对值与所述前一个像素单元的充电时间的比值。
进一步地，所述前一组像素单元的薄膜晶体管的W/L和所述后一组像素单元的薄膜晶体管的W/L之差的绝对值与所述后一组像素单元的薄膜晶体管的W/L的比值正比于所述前一组像素单元的充电时间和所述后一组像素单元的充电时间之差的绝对值与所述前一组像素单元的充电时间的比值。
进一步地，与同一条数据线相连的像素单元的薄膜晶体管的W/L均相同。
根据本发明的又一方面，提供了一种显示器，其包括上述的显示面板。
本发明通过使与同一条扫描线相连的像素单元同时完成充电，从而避免邻近栅极驱动器一侧的像素单元出现显示偏白现象。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1示出了根据本发明的实施例的显示面板的架构图；
图2示出了根据本发明的实施例的薄膜晶体管的沟道的长度和宽度的示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域 的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，为了清楚器件，夸大了层和区域的厚度，相同的标号在整个说明书和附图中可用来表示相同的元件。
在本发明的实施例中，将以液晶显示器(LCD)作为示例来进行说明。但是，应当说明的是，本发明的显示面板不仅仅作为LCD中的显示面板，还可以作为有机发光显示器(OLED)或者其他合适类型的显示器中的显示面板。
图1示出了根据本发明的实施例的显示面板的架构图。图2示出了根据本发明的实施例的薄膜晶体管的沟道的长度和宽度的示意图。
参照图1，根据本发明的实施例的显示面板1至少包括：时序控制器(未示出)、源极驱动器2、栅极驱动器3、多条数据线S1至Sn、多条扫描线G1至Gm以及多个像素单元P11、……P1n、……Pmn。应当理解的是，根据本发明的实施例的显示面板1还可包括电压转换器(未示出)等其他合适类型的器件。
时序控制器为源极驱动器2和栅极驱动器3提供时序控制信号，控制源极驱动器2和栅极驱动器3的操作。
源极驱动器2连接到多条数据线S1至Sn，根据时序控制器提供的时序控制信号向所述多条数据线S1至Sn提供数据信号，以驱动所述多条数据线S1至Sn。n为整数。
栅极驱动器3连接到多条扫描线G1至Gm，根据时序控制器提供的时序控制信号向所述多条扫描线G1至Gm提供扫描信号，以驱动所述多条扫描线G1至Gm。m为整数。
多条数据线S1至Sn和多条扫描线G1至Gm彼此垂直交叉布置，形成m×n阵列形式。
像素单元的数量为m×n。每个像素单元Pij可设置在第i条扫描线与第j条数据线之间的节点处(1≤i≤m，1≤j≤n)。像素单元Pij包括薄膜晶体管(TFT)、液晶电容和存储电容。TFT的栅极连接到第i条扫描线，TFT的源极连接到第j条数据线。液晶电容和存储电容的一端连接到TFT的漏极，液晶电容和存储电容的另一端连接到接地端。
作为本发明的一个实施方式，对于每一行像素单元，按照逐渐远离栅极驱动器3的顺序，前一个像素单元的薄膜晶体管的W/L小于后一个像素单元的薄 膜晶体管的W/L，以实现与同一条扫描线相连的所有像素单元(即同一行像素单元)能同时完成充电，其中，如图2所示，W表示薄膜晶体管中沟道的宽度，L表示薄膜晶体管中沟道的长度。此外，在图2中，薄膜晶体管还包括栅极41、源极42和漏极43。
例如，对于第一行像素单元P11、……P1n，按照逐渐远离栅极驱动器3的顺序，前一个像素单元P1j的薄膜晶体管的W/L小于后一个像素单元P1(j+1)的薄膜晶体管的W/L，从而使第一行像素单元P11、……P1n同时完成充电(1≤j≤n)。
进一步地，对于每一行像素单元，按照逐渐远离栅极驱动器3的顺序，前一个像素单元的薄膜晶体管的W/L和后一个像素单元的薄膜晶体管的W/L之差的绝对值与后一个像素单元的薄膜晶体管的W/L的比值正比于前一个像素单元的充电时间和后一个像素单元的充电时间之差的绝对值与前一个像素单元的充电时间的比值。
例如，对于第一行像素单元P11、……P1n，按照逐渐远离栅极驱动器3的顺序，前一个像素单元P1j的薄膜晶体管的(W/L)P1j和后一个像素单元P1(j+1)的薄膜晶体管的(W/L)P1(j+1)之差的绝对值|(W/L)P1j-(W/L)P1(j+1)|与后一个像素单元P1(j+1)的薄膜晶体管的(W/L)P1(j+1)的比值|(W/L)P1j-(W/L)P1(j+1)|/(W/L)P1(j+1)正比于前一个像素单元P1j的充电时间TP1j和后一个像素单元P1(j+1)的充电时间TP1(j+1)之差的绝对值|TP1j-TP1(j+1)|与前一个像素单元P1j的充电时间TP1j的比值|TP1j-TP1(j+1)|/TP1j，即满足式子|(W/L)P1j-(W/L)P1(j+1)|/(W/L)P1(j+1)＝a×|TP1j-TP1(j+1)|/TP1j，其中，a为一比例系数。
对于每一列像素单元(即与同一条数据线相连的所有像素单元)而言，每一列像素单元中的每个像素单元的薄膜晶体管的W/L均相同。例如，对于第一列像素单元P11、……Pm1而言，第一列像素单元P11、……Pm1中的每个像素单元Pi1的薄膜晶体管的W/L均相同。
作为本发明的另一个实施方式，对于每一行像素单元，按照逐渐远离栅极驱动器3的顺序，将每一行像素单元分为多组，后一组像素单元的薄膜晶体管的W/L大于前一组像素单元的薄膜晶体管的W/L，并且同一组像素单元的薄膜晶体管的W/L均相同，以实现与同一条扫描线相连的所有像素单元(即同一行像素单元)能同时完成充电，其中，如图2所示，W表示薄膜晶体管中沟道的宽度，L表示薄膜晶体管中沟道的长度。此外，在图2中，薄膜晶体管还包括栅极41、源极42和漏极43。
例如，对于第一行像素单元P11、……P1n，按照逐渐远离栅极驱动器3的顺序，将第一行像素单元P11、……P1n分为n/q组(q能整除n)，后一组像素单元P1(n-q+1)、……P1n的薄膜晶体管的W/L大于前一组像素单元P1(n-2q+2)、……P1(n-q+1)的薄膜晶体管的W/L，并且同一组像素单元(例如，后一组像素单元P1(n-q+1)、……P1n或者前一组像素单元P1(n-2q+2)、……P1(n-q+1))的薄膜晶体管的W/L均相同，从而使第一行像素单元P11、……P1n同时完成充电(1≤j≤n)。
进一步地，按照逐渐远离栅极驱动器3的顺序，前一组像素单元的薄膜晶体管的W/L和后一组像素单元的薄膜晶体管的W/L之差的绝对值与后一组像素单元的薄膜晶体管的W/L的比值正比于前一组像素单元的充电时间和后一组像素单元的充电时间之差的绝对值与前一组像素单元的充电时间的比值。
例如，第(n/q)-1组像素单元P1(n-2q+2)、……P1(n-q+1))的薄膜晶体管的(W/L)(n/q)-1和第n/q组像素单元P1(n-q+1)、……P1n薄膜晶体管的(W/L)n/q之差的绝对值|(W/L)(n/q)-1-(W/L)n/q|与第n/q组像素单元P1(n-q+1)、……P1n薄膜晶体管的(W/L)n/q的比值|(W/L)(n/q)-1-(W/L)n/q|/(W/L)n/q正比于第(n/q)-1组像素单元P1(n-2q+2)、……P1(n-q+1))的充电时间T(n/q)-1和第n/q组像素单元P1(n-q+1)、……P1n的充电时间T n/q之差的绝对值|T(n/q)-1-Tn/q|与第(n/q)-1组像素单元P1(n-2q+2)、……P1(n-q+1))的充电时间T(n/q)-1的比值|T(n/q)-1-Tn/q|/T(n/q)-1，即|(W/L)(n/q)-1-(W/L)n/q|/(W/L)n/q＝b×|T(n/q)-1-Tn/q|/T(n/q)-1，其中，b为一比例系数。
对于每一列像素单元(即与同一条数据线相连的所有像素单元)而言，每一列像素单元中的每个像素单元的薄膜晶体管的W/L均相同。例如，对于第一列像素单元P11、……Pm1而言，第一列像素单元P11、……Pm1中的每个像素单元Pi1的薄膜晶体管的W/L均相同。
综上所述，根据本发明的实施例，通过使与同一条扫描线相连的像素单元同时完成充电，从而避免邻近栅极驱动器一侧的像素单元出现显示偏白现象。虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (11)

  1. 一种显示面板，包括：
    多个像素单元，所述像素单元至少包括薄膜晶体管，所述薄膜晶体管中沟道的宽度值为W，所述薄膜晶体管中沟道的长度值为L；
    多条扫描线和多条数据线，所述扫描线和所述数据线交叉布置，以用于限定所述像素单元的位置；
    源极驱动器，用于连接所述数据线且向每条所述数据线提供数据信号；
    栅极驱动器，用于连接所述扫描线且向所述扫描线提供扫描信号；
    其中，调整所述薄膜晶体管中沟道宽度值W与沟道长度值L的比值W/L，以使与同一条扫描线相连的像素单元同时完成充电。
  2. 根据权利要求1所述的显示面板，其中，对于所述同一条扫描线相连的像素单元，按照逐渐远离所述栅极驱动器的顺序，前一个像素单元的薄膜晶体管的W/L小于后一个像素单元的薄膜晶体管的W/L。
  3. 根据权利要求1所述的显示面板，其中，对于所述同一条扫描线相连的像素单元，按照逐渐远离所述栅极驱动器的顺序，将所述同一条扫描线相连的像素单元分为多组，后一组像素单元的薄膜晶体管的W/L大于前一组像素单元的薄膜晶体管的W/L，并且同一组像素单元的薄膜晶体管的W/L相同。
  4. 根据权利要求2所述的显示面板，其中，所述前一个像素单元的薄膜晶体管的W/L和所述后一个像素单元的薄膜晶体管的W/L之差的绝对值与所述后一个像素单元的薄膜晶体管的W/L的比值正比于所述前一个像素单元的充电时间和所述后一个像素单元的充电时间之差的绝对值与所述前一个像素单元的充电时间的比值。
  5. 根据权利要求3所述的显示面板，其中，所述前一组像素单元的薄膜晶体管的W/L和所述后一组像素单元的薄膜晶体管的W/L之差的绝对值与所述后一组像素单元的薄膜晶体管的W/L的比值正比于所述前一组像素单元的充电时间和所述后一组像素单元的充电时间之差的绝对值与所述前一组像素单元的充电时间的比值。
  6. 根据权利要求1所述的显示面板，其中，与同一条数据线相连的像素单元的薄膜晶体管的W/L均相同。
  7. 根据权利要求2所述的显示面板，其中，与同一条数据线相连的像素单元的薄膜晶体管的W/L均相同。
  8. 根据权利要求3所述的显示面板，其中，与同一条数据线相连的像素单元的薄膜晶体管的W/L均相同。
  9. 根据权利要求4所述的显示面板，其中，与同一条数据线相连的像素单元的薄膜晶体管的W/L均相同。
  10. 根据权利要求5所述的显示面板，其中，与同一条数据线相连的像素单元的薄膜晶体管的W/L均相同。
  11. 一种显示器，包括显示面板，其中，所述显示面板包括：
    多个像素单元，所述像素单元至少包括薄膜晶体管，所述薄膜晶体管中沟道的宽度值为W，所述薄膜晶体管中沟道的长度值为L；
    多条扫描线和多条数据线，所述扫描线和所述数据线交叉布置，以用于限定所述像素单元的位置；
    源极驱动器，用于连接所述数据线且向每条所述数据线提供数据信号；
    栅极驱动器，用于连接所述扫描线且向所述扫描线提供扫描信号；
    其中，调整所述薄膜晶体管中沟道宽度值W与沟道长度值L的比值W/L，以使与同一条扫描线相连的像素单元同时完成充电。
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CN104751820B (zh) * 2015-04-20 2017-10-24 深圳市华星光电技术有限公司 显示面板及具有该显示面板的显示器
CN107037654A (zh) * 2017-05-15 2017-08-11 深圳市华星光电技术有限公司 一种像素驱动电路及阵列基板、显示面板
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10206823A (ja) * 1997-01-20 1998-08-07 Sony Corp Ｘｙアドレス型表示装置
US20090033817A1 (en) * 2007-06-07 2009-02-05 Jun Ooida Display device
CN104252076A (zh) * 2014-09-24 2014-12-31 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN104465669A (zh) * 2014-12-04 2015-03-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104751820A (zh) * 2015-04-20 2015-07-01 深圳市华星光电技术有限公司 显示面板及具有该显示面板的显示器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204659A (en) * 1987-11-13 1993-04-20 Honeywell Inc. Apparatus and method for providing a gray scale in liquid crystal flat panel displays
JP3276900B2 (ja) * 1997-09-30 2002-04-22 三洋電機株式会社 半導体装置及び表示装置
KR101142785B1 (ko) * 2005-06-28 2012-05-08 엘지디스플레이 주식회사 박막트랜지스터를 포함하는 액정표시장치
JP5052142B2 (ja) * 2007-01-16 2012-10-17 株式会社ジャパンディスプレイイースト 表示装置
CN101414083B (zh) * 2007-10-16 2010-06-30 瀚宇彩晶股份有限公司 液晶显示器面板、像素结构、及开关元件
TWI415100B (zh) * 2010-12-30 2013-11-11 Au Optronics Corp 可補償饋通電壓之液晶顯示面板
CN102269905A (zh) * 2011-07-30 2011-12-07 华映光电股份有限公司 液晶面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10206823A (ja) * 1997-01-20 1998-08-07 Sony Corp Ｘｙアドレス型表示装置
US20090033817A1 (en) * 2007-06-07 2009-02-05 Jun Ooida Display device
CN104252076A (zh) * 2014-09-24 2014-12-31 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN104465669A (zh) * 2014-12-04 2015-03-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104751820A (zh) * 2015-04-20 2015-07-01 深圳市华星光电技术有限公司 显示面板及具有该显示面板的显示器

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