WO2016161694A1 - 基于p型薄膜晶体管的goa电路 - Google Patents

基于p型薄膜晶体管的goa电路 Download PDF

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WO2016161694A1
WO2016161694A1 PCT/CN2015/079377 CN2015079377W WO2016161694A1 WO 2016161694 A1 WO2016161694 A1 WO 2016161694A1 CN 2015079377 W CN2015079377 W CN 2015079377W WO 2016161694 A1 WO2016161694 A1 WO 2016161694A1
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Prior art keywords
thin film
film transistor
type thin
electrically connected
clock signal
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English (en)
French (fr)
Inventor
曹尚操
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/770,824 priority Critical patent/US9786239B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a GOA circuit based on a P-type thin film transistor.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF), and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • each pixel is electrically connected to a thin film transistor (TFT), a gate of a thin film transistor is connected to a horizontal scanning line, and a drain is connected to a vertical data line, and a source (Source) ) is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by an external integrated circuit (IC), and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • the GOA technology Gate Driver on Array
  • the driving circuit of the horizontal scanning line can be fabricated on the substrate around the display area by using the original array process of the liquid crystal display panel, so that it can replace the external IC to complete The drive of the horizontal scan line.
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase production capacity and reduce product cost, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • the GOA circuit includes a GOA circuit based on a P-type thin film transistor, a CMOS-based GOA circuit, and a GOA circuit based on an N-type thin film transistor, wherein a GOA circuit based on a P-type thin film transistor, particularly a low temperature polysilicon (LTPS) material.
  • P-based film The GOA circuit of the transistor has the characteristics of simple process and low leakage, and has a good development prospect.
  • existing P-type thin film transistor-based GOA circuits tend to be less stable and have higher power consumption.
  • the stability of the GOA circuit is not limited to a P-type thin film transistor, which can reduce the deterioration of the thin film transistor in the forward and reverse scan module, reduce the power consumption of the circuit, reduce the number of signal lines, and realize a narrow bezel design and improvement.
  • the present invention provides a GOA circuit based on a P-type thin film transistor, comprising a plurality of cascaded GOA unit circuits, each stage of the GOA unit circuit comprising: a forward and reverse scanning module, an output module, and a pull-down maintenance Module, and pull-down module; let n be a positive integer, the n-th stage GOA unit circuit and its adjacent n+1th-level GOA unit circuit are one cycle;
  • the forward-reverse scan module includes: a first P-type thin film transistor, a gate of the first P-type thin film transistor is electrically connected to the first high-frequency clock signal, and a source is electrically connected to the first-stage n-th a level-transmitting signal of the level-1 GOA unit, the drain is electrically connected to the first node; and the gate of the second P-type thin film transistor is electrically connected to the first reverse high-frequency clock signal, The source is electrically connected to the level-transmitting signal of the n+1th GOA unit of the next stage, and the drain is electrically connected to the first node;
  • the output module includes: a third P-type thin film transistor, a gate of the third P-type thin film transistor is electrically connected to the first node, a source is electrically connected to the second node, and a drain is electrically connected to the constant voltage a gate of the low potential and fourth P-type thin film transistor; a fourth P-type thin film transistor, wherein a gate of the fourth P-type thin film transistor is electrically connected to a constant voltage low potential and a drain of the third P-type thin film transistor, The source is electrically connected to the second node, and the drain is electrically connected to the third node; the fifth P-type thin film transistor, the gate of the fifth P-type thin film transistor is electrically connected to the third node, and the source is electrically Connected to the second high frequency clock signal, the drain is electrically connected to the level transfer signal; the fifteenth P type thin film transistor, the gate of the fifteenth P type thin film transistor is electrically connected to the third node, and the source is electrically Connected to the second high
  • the pull-down maintaining module includes: an eleventh P-type thin film transistor, a gate of the eleventh P-type thin film transistor is electrically connected to the fourth node, a source is electrically connected to the second node, and the drain is electrically connected a constant voltage high potential; a seventh P-type thin film transistor, the gate of the seventh P-type thin film transistor is electrically connected to the fourth node, the source is electrically connected to the level transmission signal, and the drain is electrically connected to the constant voltage High potential; eighth P-type thin film transistor, gate electrical connection of the eighth P-type thin film transistor Connected to the fourth node, the source is electrically connected to the scan signal, and the drain is electrically connected to the constant voltage high potential;
  • the pull-down module includes: a tenth P-type thin film transistor, the gate of the tenth P-type thin film transistor is electrically connected to the first node, and the source is electrically connected to the gate of the thirteenth P-type thin film transistor, and the drain The galvanic connection is connected to the constant voltage high potential; the ninth P-type thin film transistor, the gate of the ninth P-type thin film transistor is electrically connected to the first node, the source is electrically connected to the fourth node, and the drain is electrically Connected to a constant voltage high potential;
  • the nth stage GOA unit circuit further includes: a fourteenth P-type thin film transistor, wherein the gate and the source of the fourteenth P-type thin film transistor are electrically connected to the second high frequency clock signal, and the drain level electrical property Connected to one end of the second capacitor and the gate of the thirteenth P-type thin film transistor; the thirteenth P-type thin film transistor, the gate of the thirteenth P-type thin film transistor is electrically connected to the fourteenth P-type thin film transistor a drain and a source of the tenth P-type thin film transistor, the source is electrically connected to the second reverse high-frequency clock signal, and the drain is electrically connected to the source of the twelfth P-type thin film transistor; the twelfth P a thin film transistor, the gate of the twelfth P-type thin film transistor is electrically connected to the second reverse high frequency clock signal, and the source is electrically connected to the drain of the thirteenth P-type thin film transistor, and the drain is electrically Connected to the fourth node;
  • the gate of the first P-type thin film transistor is electrically connected to the first reverse high frequency clock signal
  • the gate of the second P-type thin film transistor is electrically connected to the first high frequency
  • the clock signal, the sources of the fifth and fifteenth P-type thin film transistors are electrically connected to the second reverse high-frequency clock signal, and the gate and the source of the fourteenth P-type thin film transistor are electrically connected to the second
  • the reverse high frequency clock signal, the source of the thirteenth P-type thin film transistor and the gate of the twelfth thin film transistor are electrically connected to the second high frequency clock signal;
  • the first high frequency clock signal is opposite in phase to the first reverse high frequency clock signal
  • the second high frequency clock signal is opposite in phase to the second reverse high frequency clock signal
  • the P-type thin film transistor-based GOA circuit When the P-type thin film transistor-based GOA circuit performs forward scanning, the timings of the first high-frequency clock signal and the second reverse high-frequency clock signal are identical, and the first reverse high-frequency clock signal and the second high-frequency signal The timing of the clock signal is consistent;
  • the P-type thin film transistor-based GOA circuit When the P-type thin film transistor-based GOA circuit performs reverse scanning, the timings of the first high-frequency clock signal and the second high-frequency clock signal are identical, and the first reverse high-frequency clock signal and the second reverse high-frequency signal The timing of the clock signal is consistent.
  • the source of the first P-type thin film transistor is electrically connected to the start signal.
  • the source of the second P-type thin film transistor is electrically connected to the start signal.
  • the second reverse high-frequency clock signal can be replaced by a first high-frequency clock signal, and the second high-frequency clock signal can be reversed by the first High frequency clock signal replacement;
  • the second high-frequency clock signal can be replaced by a first reverse high-frequency clock signal, and the second reverse high-frequency clock signal can be A reverse high frequency clock signal is replaced.
  • the P-type thin film transistor-based GOA circuit has four high frequency clock signal lines or two high frequency clock signal lines.
  • Each of the stages of the GOA unit circuit further includes: a sixteenth P-type thin film transistor, the gate of the sixteenth P-type thin film transistor is electrically connected to the level transmission signal, and the source is electrically connected to the fourth node, and the drain is electrically connected The pole is electrically connected to a constant voltage high potential.
  • Each of the stages of the GOA unit circuit further includes: a sixteenth P-type thin film transistor, the gate of the sixteenth P-type thin film transistor is electrically connected to the fourth node, and the source is electrically connected to the first node, and the drain The pole is electrically connected to a constant voltage high potential.
  • Each of the stages of the GOA unit circuit further includes: a sixteenth P-type thin film transistor, the gate of the sixteenth P-type thin film transistor is electrically connected to the fourth node, and the source is electrically connected to the first node, and the drain The electrically connected to the constant voltage high potential; the seventeenth P-type thin film transistor, the source of the seventeenth P-type thin film transistor is electrically connected to the drain of the fourth P-type thin film transistor, and the drain is electrically connected a third node, in the nth stage GOA unit circuit, the gate of the seventeenth P-type thin film transistor is electrically connected to the second reverse high frequency clock signal, in the n+1th stage GOA unit circuit, The gate of the seventeenth P-type thin film transistor is electrically connected to the second high-frequency clock signal; the third capacitor has one end electrically connected to the third node and the other end electrically connected to the level-transmitting signal. .
  • the third node is low and the fourth node is high; after the output is finished, the third node is high and the fourth node is low.
  • each P-type thin film transistor is low temperature polysilicon.
  • the invention also provides a GOA circuit based on a P-type thin film transistor, comprising a plurality of cascaded GOA unit circuits, each stage GOA unit circuit comprises: a forward and reverse scanning module, an output module, a pull-down maintenance module, and a pull-down module Let n be a positive integer, the nth stage GOA unit circuit and its adjacent n+1th stage GOA unit circuit be one cycle;
  • the forward-reverse scan module includes: a first P-type thin film transistor, a gate of the first P-type thin film transistor is electrically connected to the first high-frequency clock signal, and a source is electrically connected to the first-stage n-th a level-1 signal of the level 1 GOA unit, the drain is electrically connected to the first node; the second P type thin film transistor, The gate of the second P-type thin film transistor is electrically connected to the first reverse high-frequency clock signal, and the source is electrically connected to the level-transmitting signal of the n+1th GOA unit of the next stage, and the drain is electrically connected.
  • a first P-type thin film transistor a gate of the first P-type thin film transistor is electrically connected to the first high-frequency clock signal, and a source is electrically connected to the first-stage n-th a level-1 signal of the level 1 GOA unit, the drain is electrically connected to the first node;
  • the output module includes: a third P-type thin film transistor, a gate of the third P-type thin film transistor is electrically connected to the first node, a source is electrically connected to the second node, and a drain is electrically connected to the constant voltage a gate of the low potential and fourth P-type thin film transistor; a fourth P-type thin film transistor, wherein a gate of the fourth P-type thin film transistor is electrically connected to a constant voltage low potential and a drain of the third P-type thin film transistor, The source is electrically connected to the second node, and the drain is electrically connected to the third node; the fifth P-type thin film transistor, the gate of the fifth P-type thin film transistor is electrically connected to the third node, and the source is electrically Connected to the second high frequency clock signal, the drain is electrically connected to the level transfer signal; the fifteenth P type thin film transistor, the gate of the fifteenth P type thin film transistor is electrically connected to the third node, and the source is electrically Connected to the second high
  • the pull-down maintaining module includes: an eleventh P-type thin film transistor, a gate of the eleventh P-type thin film transistor is electrically connected to the fourth node, a source is electrically connected to the second node, and the drain is electrically connected a constant voltage high potential; a seventh P-type thin film transistor, the gate of the seventh P-type thin film transistor is electrically connected to the fourth node, the source is electrically connected to the level transmission signal, and the drain is electrically connected to the constant voltage a high potential; an eighth P-type thin film transistor, the gate of the eighth P-type thin film transistor is electrically connected to the fourth node, the source is electrically connected to the scan signal, and the drain is electrically connected to the constant voltage high potential;
  • the pull-down module includes: a tenth P-type thin film transistor, the gate of the tenth P-type thin film transistor is electrically connected to the first node, and the source is electrically connected to the gate of the thirteenth P-type thin film transistor, and the drain The galvanic connection is connected to the constant voltage high potential; the ninth P-type thin film transistor, the gate of the ninth P-type thin film transistor is electrically connected to the first node, the source is electrically connected to the fourth node, and the drain is electrically Connected to a constant voltage high potential;
  • the nth stage GOA unit circuit further includes: a fourteenth P-type thin film transistor, wherein the gate and the source of the fourteenth P-type thin film transistor are electrically connected to the second high frequency clock signal, and the drain level electrical property Connected to one end of the second capacitor and the gate of the thirteenth P-type thin film transistor; the thirteenth P-type thin film transistor, the gate of the thirteenth P-type thin film transistor is electrically connected to the fourteenth P-type thin film transistor a drain and a source of the tenth P-type thin film transistor, the source is electrically connected to the second reverse high-frequency clock signal, and the drain is electrically connected to the source of the twelfth P-type thin film transistor; the twelfth P a thin film transistor, the gate of the twelfth P-type thin film transistor is electrically connected to the second reverse high frequency clock signal, and the source is electrically connected to the drain of the thirteenth P-type thin film transistor, and the drain is electrically Connected to the fourth node;
  • the gate of the first P-type thin film transistor is electrically connected to the first reverse high frequency clock signal
  • the gate of the second P-type thin film transistor is electrically connected to the first high frequency
  • the clock signal, the sources of the fifth and fifteenth P-type thin film transistors are electrically connected to the second reverse high-frequency clock signal, and the gate and the source of the fourteenth P-type thin film transistor are electrically connected to the second
  • the reverse high frequency clock signal, the source of the thirteenth P-type thin film transistor and the gate of the twelfth thin film transistor are electrically connected to the second high frequency clock signal;
  • the first high frequency clock signal is opposite in phase to the first reverse high frequency clock signal
  • the second high frequency clock signal is opposite in phase to the second reverse high frequency clock signal
  • the P-type thin film transistor-based GOA circuit When the P-type thin film transistor-based GOA circuit performs forward scanning, the timings of the first high-frequency clock signal and the second reverse high-frequency clock signal are identical, and the first reverse high-frequency clock signal and the second high-frequency signal The timing of the clock signal is consistent;
  • the P-type thin film transistor-based GOA circuit When the P-type thin film transistor-based GOA circuit performs reverse scanning, the timings of the first high-frequency clock signal and the second high-frequency clock signal are identical, and the first reverse high-frequency clock signal and the second reverse high-frequency signal The timing of the clock signal is consistent;
  • the source of the first P-type thin film transistor is electrically connected to the start signal in the first-stage connection relationship of the P-type thin film transistor-based GOA circuit;
  • the source of the second P-type thin film transistor is electrically connected to the start signal.
  • the present invention provides a P-type thin film transistor-based GOA circuit that uses a first high-frequency clock signal and a first reverse high-frequency clock signal to control forward-backward scanning of a P-type thin film transistor, and a direct current
  • the signal control can reduce the deterioration of the associated thin film transistor in the forward and reverse scan module;
  • the first high frequency clock signal and the first reverse high frequency clock can be used not only as a control signal for controlling forward and reverse scan but also as a scan
  • the signal output signal source reduces the load of the second high frequency clock signal and the second reverse high frequency clock signal, reduces the scanning signal delay, ensures the smooth output of the scanning signal, improves the stability of the GOA circuit, and can reduce the strip of the signal line Number, to achieve a narrow bezel design;
  • the drop-down module uses a two-stage design to reduce the power consumption of the circuit.
  • FIG. 1 is a circuit diagram of a first embodiment of a P-type thin film transistor-based GOA circuit of the present invention
  • FIG. 2 is a circuit diagram of a first stage GOA unit circuit of a first embodiment of a P-type thin film transistor-based GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of a final stage GOA unit circuit of a first embodiment of a P-type thin film transistor-based GOA circuit of the present invention
  • FIG. 4 is a circuit diagram of a second embodiment of a P-type thin film transistor-based GOA circuit of the present invention.
  • FIG. 5 is a circuit diagram of a third embodiment of a P-type thin film transistor-based GOA circuit of the present invention.
  • FIG. 6 is a circuit diagram of a fourth embodiment of a P-type thin film transistor-based GOA circuit of the present invention.
  • FIG. 7 is a circuit diagram of a fifth embodiment of a P-type thin film transistor-based GOA circuit of the present invention.
  • FIG. 8 is a timing diagram of a forward scanning of a GOA circuit based on a P-type thin film transistor of the present invention.
  • FIG. 9 is a timing chart of the reverse scanning of the GOA circuit based on the P-type thin film transistor of the present invention.
  • FIG. 1 is a circuit diagram of a first embodiment of a P-type thin film transistor-based GOA circuit of the present invention.
  • the P-type thin film transistor-based GOA circuit of the present invention includes a plurality of cascaded GOA unit circuits, and each stage of the GOA unit circuit includes: a forward-reverse scanning module 100, an output module 200, and a pull-down maintenance. Module 300, and pull down module 400.
  • n be a positive integer
  • the nth stage GOA unit circuit and its adjacent n+1th stage GOA unit circuit be one cycle.
  • the forward-reverse-scanning module 100 includes a first P-type thin film transistor T1.
  • the gate of the first P-type thin film transistor T1 is electrically connected to the first high-frequency clock signal LCK, and the source is electrically connected to the previous one.
  • the stage pass signal ST(n-1) of the stage n-1th GOA unit, the drain is electrically connected to the first node A(n); the second P type thin film transistor T2, the second P type thin film transistor T2
  • the gate is electrically connected to the first reverse high frequency clock signal XLCK, and the source is electrically connected to the next level n+1
  • the level signal ST(n+1) of the GOA unit is electrically connected to the first node A(n).
  • the output module 200 includes: a third P-type thin film transistor T3, a gate of the third P-type thin film transistor T3 is electrically connected to the first node A(n), and a source is electrically connected to the second node B ( n), the drain is electrically connected to the constant voltage low potential L and the gate of the fourth P-type thin film transistor T4; the fourth P-type thin film transistor T4, the gate of the fourth P-type thin film transistor T4 is electrically connected to a constant voltage low potential L and a drain of the third P-type thin film transistor T3, the source is electrically connected to the second node B(n), and the drain is electrically connected to the third node Q(n); the fifth P-type film The transistor T5, the gate of the fifth P-type thin film transistor T5 is electrically connected to the third node Q(n), the source is electrically connected to the second high-frequency clock signal CK, and the drain is electrically connected to the level-transmitting signal.
  • a fifteenth P-type thin film transistor T15 a fifteenth P-type thin film transistor T15, the gate of the fifteenth P-type thin film transistor T15 is electrically connected to the third node Q(n), and the source is electrically connected to the second high-frequency clock a signal CK, the drain is electrically connected to the scan signal G(n); the first capacitor C1, one end of the first capacitor C1 is electrically connected to the second node B(n), and the other end is electrically connected to a constant height. Electricity Press VGH.
  • the pull-down maintaining module 300 includes: an eleventh P-type thin film transistor T11, the gate of the eleventh P-type thin film transistor T11 is electrically connected to the fourth node P(n), and the source is electrically connected to the second a node B(n), the drain is electrically connected to the constant voltage high potential H; the seventh P-type thin film transistor T7, the gate of the seventh P-type thin film transistor T7 is electrically connected to the fourth node P(n), The source is electrically connected to the step signal ST(n), the drain is electrically connected to the constant voltage high potential H, and the eighth P-type thin film transistor T8 is electrically connected to the gate of the eighth P-type thin film transistor T8.
  • the fourth node P(n) has a source electrically connected to the scan signal G(n) and a drain electrically connected to the constant voltage high potential H.
  • the pull-down module 400 includes a tenth P-type thin film transistor T10, the gate of the tenth P-type thin film transistor T10 is electrically connected to the first node A(n), and the source is electrically connected to the thirteenth P-type The gate of the thin film transistor T13 is electrically connected to the constant voltage high potential H; the ninth P-type thin film transistor T9 is electrically connected to the first node A(n) The source is electrically connected to the fourth node P(n), and the drain is electrically connected to the constant voltage high potential H.
  • the n-th stage GOA unit circuit further includes: a fourteenth P-type thin film transistor T14, wherein the gate and the source of the fourteenth P-type thin film transistor T14 are electrically connected to the second high-frequency clock signal CK, and the drain
  • the gate is electrically connected to one end of the second capacitor C2 and the gate of the thirteenth P-type thin film transistor T13; and the thirteenth P-type thin film transistor T13 is electrically connected to the gate of the thirteenth P-type thin film transistor T13
  • the drain of the fourteenth P-type thin film transistor T14 and the source of the tenth P-type thin film transistor T10 are electrically connected to the second reverse high-frequency clock signal XCK, and the drain is electrically connected to the twelfth P-type a source of the thin film transistor T12; a twelfth P-type thin film transistor T12, a gate of the twelfth P-type thin film transistor T12 is electrically connected to the second reverse high-frequency clock signal XCK
  • the gate of the first P-type thin film transistor T1 is electrically connected to the first reverse high-frequency clock signal XLCK
  • the gate of the second P-type thin film transistor T2 is electrically connected to
  • the sources of the first high frequency clock signal LCK, the fifth and fifteenth P-type thin film transistors T5 and T15 are electrically connected to the second reverse high frequency clock signal XCK and the gate of the fourteenth P-type thin film transistor T14.
  • the source is electrically connected to the second reverse high frequency clock signal XCK
  • the source of the thirteenth P-type thin film transistor T13 and the gate of the twelfth thin film transistor T12 are electrically connected to the second high frequency clock signal.
  • Other than CK other circuit structures and connection relationships are the same as those of the nth stage GOA unit circuit, and the description thereof will not be repeated here.
  • the material of each P-type thin film transistor in the P-type thin film transistor-based GOA circuit is low-temperature polysilicon, and the P-type thin film transistor-based GOA circuit has the characteristics of simple process and low leakage, and can improve GOA. The stability of the circuit.
  • the source of the first P-type thin film transistor T1 is electrically connected to the start signal STV;
  • the source of the second P-type thin film transistor T2 is electrically connected to the start signal STV.
  • the first high frequency clock signal LCK is opposite to the phase of the first reverse high frequency clock signal XLCK, and the second high frequency clock signal CK and the second reverse high frequency clock signal XCK. The opposite phase.
  • the timings of the first high-frequency clock signal LCK and the second reverse high-frequency clock signal XCK are the same, and the first reverse height is high.
  • the timings of the frequency clock signal XLCK and the second high frequency clock signal CK are identical, and the timing and output timing of the level transmission signal ST(n) and the scanning signal G(n) are identical.
  • the specific forward scanning process is divided into first, second, and third stages;
  • the first stage the first high frequency clock signal LCK provides a low potential, the first reverse clock signal XLCK provides a high potential, the first P-type thin film transistor T1 is turned on, and the second P-type thin film transistor T2 is turned off; the n-1th level GOA
  • the stage signal ST(n-1) of the unit circuit provides a low potential, the first node A(n) is low, the third and fourth P-type thin film transistors T3, T4 are both turned on, and the third node Q(n) is Charging to a low potential, the fifth and fifteenth P-type thin film transistors T5, T15 are both turned on, the second high-frequency clock signal CK provides a high potential, and the level-transmitting signal ST(n) and the scanning signal G(n) output a high potential;
  • the ninth and tenth P-type thin film transistors T9 and T10 are turned on by the low potential of the first node A(n), and the fourth node P(n) is raised to a high potential,
  • the second stage the stage signal ST(n+1) of the n+1th stage GOA unit circuit provides a high potential, the first high frequency clock signal LCK provides a high potential, and the first reverse clock signal XLCK provides a low potential, first P-type thin film transistor T1 is turned off, second P-type thin film transistor T2 is turned on, first node A(n) becomes high potential, third P-type thin film transistor T3 is turned off, fourth P-type thin film transistor T4 is turned on, third node Q (n), continued to maintain a low potential due to the influence of the capacitor C1, the fifth and fifteenth P-type thin film transistors T5, T15 are both turned on, the second high-frequency clock signal CK provides a low potential, the level transmission signal ST(n) and the scanning signal G(n) smoothly outputs a low potential to realize progressive scanning, the fourth node P(n) maintains a high potential, and the seventh and eighth P-type thin film transistors are turned off; meanwhile, the fourteenth P-type thin film transistor T14 is
  • the third stage the first high frequency clock signal LCK provides a low potential, the first reverse clock signal XLCK provides a high potential, the first P-type thin film transistor T1 is turned on, the second P-type thin film transistor T2 is turned off, the n-1th stage GOA
  • the stage signal ST(n-1) of the unit circuit provides a high potential, the first node A(n) remains high, the tenth and ninth P-type thin film transistors T10, T9 are both turned off, and the second high-frequency clock signal CK is provided.
  • the fourteenth P-type thin film transistor T14 is turned off, the thirteenth P-type thin film transistor T13 is turned on under the control of the low potential of the second capacitor C2, and the second reverse high-frequency clock signal XCK is supplied with a low potential, the twelfth P
  • the thin film transistor T12 is turned on, the fourth node P(n) becomes a low potential, and remains low for the rest of the frame, and the eleventh, seventh, and eighth P-type thin film transistors T11, T7, and T8 are turned on.
  • the third node Q(n) is raised to a high potential, and the fifth and fifteenth P-type thin film transistors T5 and T15 are turned off, and the level transmission signal ST(n) and the scanning signal G(n) are outputted at a high potential, and are left in one frame. Time keeps this state.
  • the fourteenth P-type thin film transistor T14 and the tenth P-type thin film transistor T10 are not simultaneously turned on, and the fourteenth P-type thin film transistor T14 is alternately opened with the twelfth and thirteenth P-type thin film transistors T12 and T13.
  • a two-stage design reduces power consumption.
  • the P-type thin film transistor-based GOA circuit performs reverse scanning
  • the timings of the first high-frequency clock signal LCK and the second high-frequency clock signal CK are the same, and the first reverse high-frequency clock
  • the timing of the signal XLCK and the second inverted high frequency clock signal XCK are identical.
  • the specific reverse scanning process is the inverse of the above forward scanning.
  • FIG. 4 is a circuit diagram of a second embodiment of the present invention.
  • the timings of the first high frequency clock signal LCK and the second reverse high frequency clock signal XCK are the same, and the timings of the first reverse high frequency clock signal XLCK and the second high frequency clock signal CK are the same. Therefore, when the forward scan is performed, the second reverse high frequency clock signal XCK can be replaced by the first high frequency clock signal LCK, and the second high frequency clock signal CK can be replaced by the first reverse high frequency clock signal XLCK.
  • the first high frequency clock signal LCK and the second high frequency clock The timing of the signal CK is identical, and the timings of the first reverse high frequency clock signal XLCK and the second reverse high frequency clock signal XCK are identical, so that when the reverse scan is performed, the second high frequency clock signal CK can be the first high frequency clock.
  • the signal LCK is replaced, and the second inverted high frequency clock signal XCK can be replaced by the first reverse high frequency clock signal XLCK.
  • 4 illustrates that, in the forward scan, the second high frequency clock signal XCK and the second high frequency clock signal CK are replaced by the first high frequency clock signal LCK and the first reverse high frequency clock signal XLCK.
  • Only two high-frequency clock signal lines can be used, which is beneficial to the narrow bezel design.
  • all four high frequency clock signal lines may also be selected, but the first high frequency clock signal LCK and the first reverse high frequency clock signal XLCK may partially replace the second reverse high frequency clock signal XCK and the second high frequency clock.
  • the signal CK is used to reduce the load of the second high frequency clock signal CK and the second reverse high frequency clock signal XCK, reducing the delay of the scan signal G(n). The rest are the same as in Figure 1, and will not be described here.
  • FIG. 5 is a circuit diagram of a third embodiment of the present invention.
  • FIG. 5 is different from FIG. 1 in that each of the stages of the GOA unit circuit further includes a sixteenth P-type thin film transistor T16, the tenth The gate of the six P-type thin film transistor T16 is electrically connected to the level transfer signal ST(n), the source is electrically connected to the fourth node P(n), and the drain is electrically connected to the constant voltage high potential H.
  • the scan signal G(n) is at a low potential, and the sixteenth P-type thin film transistor T16 is turned on to raise the potential of the fourth node P(n) to ensure that the P point is stabilized at a high potential, and the scanning signal G(n) is increased.
  • the output quality of the sixteenth P-type thin film transistor T16 is turned off after the output is completed. The rest are the same as in Figure 1, and will not be described here.
  • FIG. 6 is a circuit diagram of a fourth embodiment of the present invention.
  • FIG. 6 is different from FIG. 1 in that each stage of the GOA unit circuit further includes a sixteenth P-type thin film transistor T16, the tenth The gate of the six P-type thin film transistor T16 is electrically connected to the fourth node P(n), the source is electrically connected to the first node A(n), and the drain is electrically connected to the constant voltage high potential H.
  • the potential of the first node A(n) is affected by the coupling capacitance generated by the first high frequency clock signal LCK and the first reverse high frequency clock signal XLCK.
  • the coupling capacitances can cancel each other to a considerable extent, but considering the device variability, the sixteenth P-type thin film transistor T16 can be stabilized.
  • FIG. 7 is a circuit diagram of a fifth embodiment of the present invention.
  • FIG. 7 is different from FIG. 1 in that each stage of the GOA unit circuit further includes a sixteenth P-type thin film transistor T16, the tenth The gate of the six P-type thin film transistor T16 is electrically connected to the fourth node P(n), the source is electrically connected to the first node A(n), and the drain is electrically connected to the constant voltage high potential H; a P-type thin film transistor T17, the source of the seventeenth P-type thin film transistor T17 is electrically connected to the fourth P-type film The drain of the transistor T4 is electrically connected to the third node Q(n).
  • the gate of the seventeenth P-type thin film transistor T17 is electrically connected to the second reverse The high frequency clock signal XCK, in the n+1th stage GOA unit circuit, the gate of the seventeenth P-type thin film transistor T17 is electrically connected to the second high frequency clock signal CK; the third capacitor C3, the first One end of the three capacitor C3 is electrically connected to the third node Q(n), and the other end is electrically connected to the level transmission signal ST(n).
  • the sixteenth P-type thin film transistor T16 which is the same as that of FIG.
  • the seventh P-type thin film transistor T17 and the third capacitor C3 are added, which can reduce the coupling capacitance and stabilize the third node Q ( The potential of n); in the output stage of the scanning signal G(n), the seventeenth P-type thin film transistor is turned off, and the third capacitor C3 can raise the gate potential of the fifteenth P-type thin film transistor T15, and reduce the scanning signal G ( The delay of n).
  • the rest are the same as in Figure 1, and will not be described here.
  • the P-type thin film transistor-based GOA circuit of the present invention controls the forward-backward scanning of the P-type thin film transistor by using the first high-frequency clock signal and the first reverse high-frequency clock signal, compared with the DC signal control.
  • the deterioration of the associated thin film transistor in the forward and reverse scan module can be alleviated; the first high frequency clock signal and the first reverse high frequency clock can be used not only as a control signal for controlling forward and reverse scan but also as a signal for outputting a scan signal.
  • the source reduces the load of the second high frequency clock signal and the second reverse high frequency clock signal, reduces the delay of the scanning signal, ensures the smooth output of the scanning signal, improves the stability of the GOA circuit, and can reduce the number of signal lines and achieve narrow
  • the bezel design the pull-down module uses a two-stage design to reduce the power consumption of the circuit.

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Abstract

一种基于P型薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：正反向扫描模块(100)、输出模块(200)、下拉维持模块(300)、及下拉模块(400)；第n级GOA单元电路与其相邻的第n+1级GOA单元电路为一周期；所述正反向扫描模块(100)采用第一高频时钟信号(LCK)与第一反向高频时钟信号(XLCK)控制P型薄膜晶体管的正反向扫描。该基于P型薄膜晶体管的GOA电路，能够减轻正反向扫描模块中的薄膜晶体管的恶化，降低电路功耗，减少信号线的条数，实现窄边框设计，并能够提升GOA电路的稳定性，保证扫描信号(G(n))顺利输出。

Description

基于P型薄膜晶体管的GOA电路 技术领域
本发明涉及液晶显示器技术领域，尤其涉及一种基于P型薄膜晶体管的GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，可以运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
通常GOA电路包括：基于P型薄膜晶体管的GOA电路、基于CMOS的GOA电路、和基于N型薄膜晶体管的GOA电路，其中基于P型薄膜晶体管的GOA电路，尤其是以低温多晶硅(LTPS)为材料的基于P型薄膜 晶体管的GOA电路具有工艺较为简单、漏电较低的特点，发展前景良好。然而，现有的基于P型薄膜晶体管的GOA电路往往稳定性较差，且功耗较高。
发明内容
本发明的目的在于，提供一种基于P型薄膜晶体管的GOA电路，能够减轻正反向扫描模块中的薄膜晶体管的恶化，降低电路功耗，减少信号线的条数，实现窄边框设计，提升GOA电路的稳定性。
为实现上述目的，本发明提供了一种基于P型薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：正反向扫描模块、输出模块、下拉维持模块、及下拉模块；设n为正整数，第n级GOA单元电路与其相邻的第n+1级GOA单元电路为一周期；
除第一级与最后一级GOA单元电路以外，在第n级GOA单元电路中：
所述正反向扫描模块包括：第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于第一高频时钟信号，源极电性连接于上一级第n-1级GOA单元的级传信号，漏极电性连接于第一节点；第二P型薄膜晶体管，所述第二P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号，源极电性连接于下一级第n+1级GOA单元的级传信号，漏极电性连接于第一节点；
所述输出模块包括：第三P型薄膜晶体管，所述第三P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于恒压低电位及第四P型薄膜晶体管的栅极；第四P型薄膜晶体管，所述第四P型薄膜晶体管的栅极电性连接于恒压低电位及第三P型薄膜晶体管的漏极，源极电性连接于第二节点，漏极电性连接于第三节点；第五P型薄膜晶体管，所述第五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于级传信号；第十五P型薄膜晶体管，所述第十五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于扫描信号；第一电容，所述第一电容的一端电性连接于第二节点，另一端电性连接于一恒定高电压；
所述下拉维持模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第二节点，漏极电性连接于恒压高电位；第七P型薄膜晶体管，所述第七P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于级传信号，漏极电性连接于恒压高电位；第八P型薄膜晶体管，所述第八P型薄膜晶体管的栅极电性连 接于第四节点，源极电性连接于扫描信号，漏极电性连接于恒压高电位；
所述下拉模块包括：第十P型薄膜晶体管，所述第十P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第十三P型薄膜晶体管的栅极，漏极电性连接于恒压高电位；第九P型薄膜晶体管，所述第九P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于恒压高电位；
所述第n级GOA单元电路还包括：第十四P型薄膜晶体管，所述第十四P型薄膜晶体管的栅极及源极均电性连接于第二高频时钟信号，漏级电性连接于第二电容的一端及第十三P型薄膜晶体管的栅极；第十三P型薄膜晶体管，所述第十三P型薄膜晶体管的栅极电性连接于第十四P型薄膜晶体管的漏极及第十P型薄膜晶体管的源极，源极电性连接于第二反向高频时钟信号，漏极电性连接于第十二P型薄膜晶体管的源极；第十二P型薄膜晶体管，所述第十二P型薄膜晶体管的栅极电性连接于第二反向高频时钟信号，源极电性连接于第十三P型薄膜晶体管的漏极，漏极电性连接于第四节点；第二电容，所述第二电容的一端电性连接于第十四P型薄膜晶体管的漏极，另一端电性连接于一恒定高电压；
在第n+1级GOA单元电路中，第一P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号、第二P型薄膜晶体管的栅极电性连接于第一高频时钟信号、第五与第十五P型薄膜晶体管的源极均电性连接于第二反向高频时钟信号、第十四P型薄膜晶体管的栅极及源极均电性连接于第二反向高频时钟信号、第十三P型薄膜晶体管的源极与第十二薄膜晶体管的栅极均电性连接于第二高频时钟信号；
所述第一高频时钟信号与第一反向高频时钟信号的相位相反，所述第二高频时钟信号与第二反向高频时钟信号的相位相反；
所述基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第一高频时钟信号和第二反向高频时钟信号的时序一致，第一反向高频时钟信号和第二高频时钟信号的时序一致；
所述基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第一高频时钟信号和第二高频时钟信号的时序一致，第一反向高频时钟信号和第二反向高频时钟信号的时序一致。
所述基于P型薄膜晶体管的GOA电路的第一级连接关系中，所述第一P型薄膜晶体管的源极电性连接于起始信号。
所述基于P型薄膜晶体管的GOA电路的最后一级连接关系中，所述第二P型薄膜晶体管的源极电性连接于起始信号。
所述基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第二反向高频时钟信号能够被第一高频时钟信号替换，所述第二高频时钟信号能够被第一反向高频时钟信号替换；
所述基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第二高频时钟信号能够被第一反向高频时钟信号替换，所述第第二反向高频时钟信号能够被第一反向高频时钟信号替换。
所述基于P型薄膜晶体管的GOA电路具有四条高频时钟信号线或两条高频时钟信号线。
所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管的栅极电性连接于级传信号，源极电性连接于第四节点，漏极电性连接于恒压高电位。
所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第一节点，漏极电性连接于恒压高电位。
所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第一节点，漏极电性连接于恒压高电位；第十七P型薄膜晶体管，所述第十七P型薄膜晶体管的源极电性连接于第四P型薄膜晶体管的漏极，漏极电性连接于第三节点，在第n级GOA单元电路中，所述第十七P型薄膜晶体管的栅极电性连接于第二反向高频时钟信号，在第n+1级GOA单元电路中，所述第十七P型薄膜晶体管的栅极电性连接于第二高频时钟信号；第三电容，所述第三电容的一端电性连接于第三节点，另一端电性连接于级传信号。
所述基于P型薄膜晶体管的GOA电路在输出期间，第三节点为低电位，第四节点为高电位；在输出结束后，第三节点为高电位，第四节点为低电位。
各个P型薄膜晶体管的材料均为低温多晶硅。
本发明还提供一种基于P型薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：正反向扫描模块、输出模块、下拉维持模块、及下拉模块；设n为正整数，第n级GOA单元电路与其相邻的第n+1级GOA单元电路为一周期；
除第一级与最后一级GOA单元电路以外，在第n级GOA单元电路中：
所述正反向扫描模块包括：第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于第一高频时钟信号，源极电性连接于上一级第n-1级GOA单元的级传信号，漏极电性连接于第一节点；第二P型薄膜晶体管， 所述第二P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号，源极电性连接于下一级第n+1级GOA单元的级传信号，漏极电性连接于第一节点；
所述输出模块包括：第三P型薄膜晶体管，所述第三P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于恒压低电位及第四P型薄膜晶体管的栅极；第四P型薄膜晶体管，所述第四P型薄膜晶体管的栅极电性连接于恒压低电位及第三P型薄膜晶体管的漏极，源极电性连接于第二节点，漏极电性连接于第三节点；第五P型薄膜晶体管，所述第五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于级传信号；第十五P型薄膜晶体管，所述第十五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于扫描信号；第一电容，所述第一电容的一端电性连接于第二节点，另一端电性连接于一恒定高电压；
所述下拉维持模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第二节点，漏极电性连接于恒压高电位；第七P型薄膜晶体管，所述第七P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于级传信号，漏极电性连接于恒压高电位；第八P型薄膜晶体管，所述第八P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于扫描信号，漏极电性连接于恒压高电位；
所述下拉模块包括：第十P型薄膜晶体管，所述第十P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第十三P型薄膜晶体管的栅极，漏极电性连接于恒压高电位；第九P型薄膜晶体管，所述第九P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于恒压高电位；
所述第n级GOA单元电路还包括：第十四P型薄膜晶体管，所述第十四P型薄膜晶体管的栅极及源极均电性连接于第二高频时钟信号，漏级电性连接于第二电容的一端及第十三P型薄膜晶体管的栅极；第十三P型薄膜晶体管，所述第十三P型薄膜晶体管的栅极电性连接于第十四P型薄膜晶体管的漏极及第十P型薄膜晶体管的源极，源极电性连接于第二反向高频时钟信号，漏极电性连接于第十二P型薄膜晶体管的源极；第十二P型薄膜晶体管，所述第十二P型薄膜晶体管的栅极电性连接于第二反向高频时钟信号，源极电性连接于第十三P型薄膜晶体管的漏极，漏极电性连接于第四节点；第二电容，所述第二电容的一端电性连接于第十四P型薄膜晶体管的漏极，另一端电性连接于一恒定高电压；
在第n+1级GOA单元电路中，第一P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号、第二P型薄膜晶体管的栅极电性连接于第一高频时钟信号、第五与第十五P型薄膜晶体管的源极均电性连接于第二反向高频时钟信号、第十四P型薄膜晶体管的栅极及源极均电性连接于第二反向高频时钟信号、第十三P型薄膜晶体管的源极与第十二薄膜晶体管的栅极均电性连接于第二高频时钟信号；
所述第一高频时钟信号与第一反向高频时钟信号的相位相反，所述第二高频时钟信号与第二反向高频时钟信号的相位相反；
所述基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第一高频时钟信号和第二反向高频时钟信号的时序一致，第一反向高频时钟信号和第二高频时钟信号的时序一致；
所述基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第一高频时钟信号和第二高频时钟信号的时序一致，第一反向高频时钟信号和第二反向高频时钟信号的时序一致；
其中，该基于P型薄膜晶体管的GOA电路的第一级连接关系中，所述第一P型薄膜晶体管的源极电性连接于起始信号；
其中，该基于P型薄膜晶体管的GOA电路的最后一级连接关系中，所述第二P型薄膜晶体管的源极电性连接于起始信号。
本发明的有益效果：本发明提供的一种基于P型薄膜晶体管的GOA电路，采用第一高频时钟信号与第一反向高频时钟信号控制P型薄膜晶体管的正反向扫描，与直流信号控制相比能够减轻正反向扫描模块中相关薄膜晶体管的恶化；所述第一高频时钟信号和第一反向高频时钟不仅可以作为控制正反向扫描的控制信号，还可以作为扫描信号输出的信号源，降低第二高频时钟信号和第二反向高频时钟信号的负载，减少扫描信号延迟，保证扫描信号顺利输出，提升GOA电路的稳定性，并能够减少信号线的条数，实现窄边框设计；下拉模块采用二段式设计能够降低电路的功耗。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的基于P型薄膜晶体管的GOA电路的第一实施例的电路图；
图2为本发明的基于P型薄膜晶体管的GOA电路的第一实施例的第一级GOA单元电路的电路图；
图3为本发明的基于P型薄膜晶体管的GOA电路的第一实施例的最后一级GOA单元电路的电路图；
图4为本发明的基于P型薄膜晶体管的GOA电路的第二实施例的电路图；
图5为本发明的基于P型薄膜晶体管的GOA电路的第三实施例的电路图；
图6为本发明的基于P型薄膜晶体管的GOA电路的第四实施例的电路图；
图7为本发明的基于P型薄膜晶体管的GOA电路的第五实施例的电路图；
图8为本发明的基于P型薄膜晶体管的GOA电路正向扫描时的时序图；
图9为本发明的基于P型薄膜晶体管的GOA电路反向扫描时的时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，图1为本发明的基于P型薄膜晶体管的GOA电路的第一实施例的电路图。如图1所示，本发明的基于P型薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：正反向扫描模块100、输出模块200、下拉维持模块300、及下拉模块400。设n为正整数，第n级GOA单元电路与其相邻的第n+1级GOA单元电路为一周期。
除第一级与最后一级GOA单元电路以外，在第n级GOA单元电路中：
所述正反向扫描模块100包括：第一P型薄膜晶体管T1，所述第一P型薄膜晶体管T1的栅极电性连接于第一高频时钟信号LCK，源极电性连接于上一级第n-1级GOA单元的级传信号ST(n-1)，漏极电性连接于第一节点A(n)；第二P型薄膜晶体管T2，所述第二P型薄膜晶体管T2的栅极电性连接于第一反向高频时钟信号XLCK，源极电性连接于下一级第n+1级 GOA单元的级传信号ST(n+1)，漏极电性连接于第一节点A(n)。
所述输出模块200包括：第三P型薄膜晶体管T3，所述第三P型薄膜晶体管T3的栅极电性连接于第一节点A(n)，源极电性连接于第二节点B(n)，漏极电性连接于恒压低电位L及第四P型薄膜晶体管T4的栅极；第四P型薄膜晶体管T4，所述第四P型薄膜晶体管T4的栅极电性连接于恒压低电位L及第三P型薄膜晶体管T3的漏极，源极电性连接于第二节点B(n)，漏极电性连接于第三节点Q(n)；第五P型薄膜晶体管T5，所述第五P型薄膜晶体管T5的栅极电性连接于第三节点Q(n)，源极电性连接于第二高频时钟信号CK，漏极电性连接于级传信号ST(n)；第十五P型薄膜晶体管T15，所述第十五P型薄膜晶体管T15的栅极电性连接于第三节点Q(n)，源极电性连接于第二高频时钟信号CK，漏极电性连接于扫描信号G(n)；第一电容C1，所述第一电容C1的一端电性连接于第二节点B(n)，另一端电性连接于一恒定高电压VGH。
所述下拉维持模块300包括：第十一P型薄膜晶体管T11，所述第十一P型薄膜晶体管T11的栅极电性连接于第四节点P(n)，源极电性连接于第二节点B(n)，漏极电性连接于恒压高电位H；第七P型薄膜晶体管T7，所述第七P型薄膜晶体管T7的栅极电性连接于第四节点P(n)，源极电性连接于级传信号ST(n)，漏极电性连接于恒压高电位H；第八P型薄膜晶体管T8，所述第八P型薄膜晶体管T8的栅极电性连接于第四节点P(n)，源极电性连接于扫描信号G(n)，漏极电性连接于恒压高电位H。
所述下拉模块400包括：第十P型薄膜晶体管T10，所述第十P型薄膜晶体管T10的栅极电性连接于第一节点A(n)，源极电性连接于第十三P型薄膜晶体管T13的栅极，漏极电性连接于恒压高电位H；第九P型薄膜晶体管T9，所述第九P型薄膜晶体管T9的栅极电性连接于第一节点A(n)，源极电性连接于第四节点P(n)，漏极电性连接于恒压高电位H。
所述第n级GOA单元电路还包括：第十四P型薄膜晶体管T14，所述第十四P型薄膜晶体管T14的栅极及源极均电性连接于第二高频时钟信号CK，漏级电性连接于第二电容C2的一端及第十三P型薄膜晶体管T13的栅极；第十三P型薄膜晶体管T13，所述第十三P型薄膜晶体管T13的栅极电性连接于第十四P型薄膜晶体管T14的漏极及第十P型薄膜晶体管T10的源极，源极电性连接于第二反向高频时钟信号XCK，漏极电性连接于第十二P型薄膜晶体管T12的源极；第十二P型薄膜晶体管T12，所述第十二P型薄膜晶体管T12的栅极电性连接于第二反向高频时钟信号XCK，源极电性连接于第十三P型薄膜晶体管T13的漏极，漏极电性连接于第四节 点P(n)；第二电容C2，所述第二电容C2的一端电性连接于第十四P型薄膜晶体管T14的漏极，另一端电性连接于一恒定高电压VGH。
在第n+1级GOA单元电路中，除第一P型薄膜晶体管T1的栅极电性连接于第一反向高频时钟信号XLCK、第二P型薄膜晶体管T2的栅极电性连接于第一高频时钟信号LCK、第五与第十五P型薄膜晶体管T5、T15的源极均电性连接于第二反向高频时钟信号XCK、第十四P型薄膜晶体管T14的栅极及源极均电性连接于第二反向高频时钟信号XCK、第十三P型薄膜晶体管T13的源极与第十二薄膜晶体管T12的栅极均电性连接于第二高频时钟信号CK以外，其它电路结构及连接关系均与第n级GOA单元电路相同，此处不再重复描述。
特别的，所述基于P型薄膜晶体管的GOA电路中的各个P型薄膜晶体管的材料均为低温多晶硅，该基于P型薄膜晶体管的GOA电路具有工艺较为简单、漏电较低的特点，能够提升GOA电路的稳定性。
请参阅图2、图3，该基于P型薄膜晶体管的GOA电路的第一级连接关系中，所述第一P型薄膜晶体管T1的源极电性连接于起始信号STV；该基于P型薄膜晶体管的GOA电路的最后一级连接关系中，所述第二P型薄膜晶体管T2的源极电性连接于起始信号STV。
请参阅图8、图9，所述第一高频时钟信号LCK与第一反向高频时钟信号XLCK的相位相反，所述第二高频时钟信号CK与第二反向高频时钟信号XCK的相位相反。
结合图8与图1，该基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第一高频时钟信号LCK和第二反向高频时钟信号XCK的时序一致，第一反向高频时钟信号XLCK和第二高频时钟信号CK的时序一致，级传信号ST(n)与扫描信号G(n)的时序及输出时序均一致。具体的正向扫描过程分为第一、第二、第三阶段；
第一阶段：第一高频时钟信号LCK提供低电位，第一反向时钟信号XLCK提供高电位，第一P型薄膜晶体管T1打开，第二P型薄膜晶体管T2关闭；第n-1级GOA单元电路的级传信号ST(n-1)提供低电位，第一节点A(n)为低电位，第三、第四P型薄膜晶体管T3、T4均打开，第三节点Q(n)被充电至低电位，第五、第十五P型薄膜晶体管T5、T15均打开，第二高频时钟信号CK提供高电位，级传信号ST(n)及扫描信号G(n)输出高电位；同时，第九、第十P型薄膜晶体管T9、T10受第一节点A(n)低电位的控制而打开，第四节点P(n)被抬升到高电位，第七、第八P型薄膜晶体管T7、T8关闭，第十三、第十四P型薄膜晶体管关闭，有利于减小电流和电 路功耗。
第二阶段：第n+1级GOA单元电路的级传信号ST(n+1)提供高电位，第一高频时钟信号LCK提供高电位，第一反向时钟信号XLCK提供低电位，第一P型薄膜晶体管T1关闭，第二P型薄膜晶体管T2打开，第一节点A(n)变为高电位，第三P型薄膜晶体管T3关闭、第四P型薄膜晶体管T4打开，第三节点Q(n)，受电容C1的影响继续保持低电位，第五、十五P型薄膜晶体管T5、T15均打开，第二高频时钟信号CK提供低电位，级传信号ST(n)及扫描信号G(n)顺利输出低电位，实现逐行扫描，第四节点P(n)保持高电位，第七、第八P型薄膜晶体管关闭；同时，第十四P型薄膜晶体管T14打开，第二电容C2充电至低电位。
第三阶段：第一高频时钟信号LCK提供低电位，第一反向时钟信号XLCK提供高电位，第一P型薄膜晶体管T1打开，第二P型薄膜晶体管T2关闭，第n-1级GOA单元电路的级传信号ST(n-1)提供高电位，第一节点A(n)保持高电位，第十、第九P型薄膜晶体管T10、T9均关闭，第二高频时钟信号CK提供高电位，第十四P型薄膜晶体管T14关闭，第十三P型薄膜晶体管T13在第二电容C2低电位的控制下打开，第二反向高频时钟信号XCK提供低电位，第十二P型薄膜晶体管T12打开，第四节点P(n)变为低电位，并在一帧余下的时间一直保持低电位，第十一、第七、第八P型薄膜晶体管T11、T7、T8打开，第三节点Q(n)被抬升到高电位，第五、十五P型薄膜晶体管T5、T15关闭，级传信号ST(n)及扫描信号G(n)输出高电位，并在一帧余下时间保持这种状态。
特别的，第十四P型薄膜晶体管T14和第十P型薄膜晶体管T10非同时打开，第十四P型薄膜晶体管T14与第十二和第十三P型薄膜晶体管T12、T13交替打开，这种二段式的设计可以减小功耗。
结合图9与图1，该基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第一高频时钟信号LCK和第二高频时钟信号CK的时序一致，第一反向高频时钟信号XLCK和第二反向高频时钟信号XCK的时序一致。具体的反向扫描过程为上述正向扫描的逆过程。
请参阅图4，图4为本发明的第二实施例的电路图。由于正向扫描时，所述第一高频时钟信号LCK和第二反向高频时钟信号XCK的时序一致，第一反向高频时钟信号XLCK和第二高频时钟信号CK的时序一致，因此进行正向扫描时，所述第二反向高频时钟信号XCK能够被第一高频时钟信号LCK替换，所述第二高频时钟信号CK能够被第一反向高频时钟信号XLCK替换；而反向扫描时，所述第一高频时钟信号LCK和第二高频时钟 信号CK的时序一致，第一反向高频时钟信号XLCK和第二反向高频时钟信号XCK的时序一致，因此进行反向扫描时，第二高频时钟信号CK能够被第一高频时钟信号LCK替换，所述第二反向高频时钟信号XCK能够被第一反向高频时钟信号XLCK替换。图4示意出了正向扫描时，采用所述第一高频时钟信号LCK和第一反向高频时钟信号XLCK来替换第二反向高频时钟信号XCK和第二高频时钟信号CK，仅采用两条高频时钟信号线即可实现，有利于窄边框设计。当然，也可以选择保留全部四条高频时钟信号线，但第一高频时钟信号LCK和第一反向高频时钟信号XLCK可部分替换第二反向高频时钟信号XCK和第二高频时钟信号CK，以降低第二高频时钟信号CK和第二反向高频时钟信号XCK的负载，减少扫描信号G(n)的延迟。其余部分均与图1相同，此处不再赘述。
请参阅图5，图5为本发明的第三实施例的电路图，图5与图1的区别在于，所述每一级GOA单元电路还包括第十六P型薄膜晶体管T16，所述第十六P型薄膜晶体管T16的栅极电性连接于级传信号ST(n)，源极电性连接于第四节点P(n)，漏极电性连接于恒压高电位H。在输出期间，扫描信号G(n)为低电位，第十六P型薄膜晶体管T16打开，拉高第四节点P(n)的电位，保证P点稳定在高电位，提高扫描信号G(n)的输出质量，输出结束后，第十六P型薄膜晶体管T16关闭。其余部分均与图1相同，此处不再赘述。
请参阅图6，图6为本发明的第四实施例的电路图，图6与图1的区别在于，所述每一级GOA单元电路还包括第十六P型薄膜晶体管T16，所述第十六P型薄膜晶体管T16的栅极电性连接于第四节点P(n)，源极电性连接于第一节点A(n)，漏极电性连接于恒压高电位H。在非作用期间(扫描信号G(n)输出结束后)，第一节点A(n)的电位会受到第一高频时钟信号LCK和第一反向高频时钟信号XLCK产生的耦合电容的影响，虽然第一高频时钟信号LCK和第一反向高频时钟信号XLCK时序相反，耦合电容可以相当大程度相互抵消，但考虑期器件差异性，增加第十六P型薄膜晶体管T16可以稳定非作用期间第一节点A(n)点的电位。其余部分均与图1相同，此处不再赘述。
请参阅图7，图7为本发明的第五实施例的电路图，图7与图1的区别在于，所述每一级GOA单元电路还包括第十六P型薄膜晶体管T16，所述第十六P型薄膜晶体管T16的栅极电性连接于第四节点P(n)，源极电性连接于第一节点A(n)，漏极电性连接于恒压高电位H；第十七P型薄膜晶体管T17，所述第十七P型薄膜晶体管T17的源极电性连接于第四P型薄膜 晶体管T4的漏极，漏极电性连接于第三节点Q(n)，在第n级GOA单元电路中，所述第十七P型薄膜晶体管T17的栅极电性连接于第二反向高频时钟信号XCK，在第n+1级GOA单元电路中，所述第十七P型薄膜晶体管T17的栅极电性连接于第二高频时钟信号CK；第三电容C3，所述第三电容C3的一端电性连接于第三节点Q(n)，另一端电性连接于级传信号ST(n)。图7除了增加了与图6连接相同的第十六P型薄膜晶体管T16外，还增加了第十七P型薄膜晶体管T17及第三电容C3，能够减小耦合电容，稳定第三节点Q(n)的电位；在扫描信号G(n)输出阶段，第十七P型薄膜晶体管关闭，第三电容C3能够抬高第十五P型薄膜晶体管T15的栅极电位，减小扫描信号G(n)的延迟。其余部分均与图1相同，此处不再赘述。
综上所述，本发明的基于P型薄膜晶体管的GOA电路，采用第一高频时钟信号与第一反向高频时钟信号控制P型薄膜晶体管的正反向扫描，与直流信号控制相比能够减轻正反向扫描模块中相关薄膜晶体管的恶化；所述第一高频时钟信号和第一反向高频时钟不仅可以作为控制正反向扫描的控制信号，还可以作为扫描信号输出的信号源，降低第二高频时钟信号和第二反向高频时钟信号的负载，减少扫描信号延迟，保证扫描信号顺利输出，提升GOA电路的稳定性，并能够减少信号线的条数，实现窄边框设计；下拉模块采用二段式设计能够降低电路的功耗。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种基于P型薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：正反向扫描模块、输出模块、下拉维持模块、及下拉模块；设n为正整数，第n级GOA单元电路与其相邻的第n+1级GOA单元电路为一周期；
    除第一级与最后一级GOA单元电路以外，在第n级GOA单元电路中：
    所述正反向扫描模块包括：第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于第一高频时钟信号，源极电性连接于上一级第n-1级GOA单元的级传信号，漏极电性连接于第一节点；第二P型薄膜晶体管，所述第二P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号，源极电性连接于下一级第n+1级GOA单元的级传信号，漏极电性连接于第一节点；
    所述输出模块包括：第三P型薄膜晶体管，所述第三P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于恒压低电位及第四P型薄膜晶体管的栅极；第四P型薄膜晶体管，所述第四P型薄膜晶体管的栅极电性连接于恒压低电位及第三P型薄膜晶体管的漏极，源极电性连接于第二节点，漏极电性连接于第三节点；第五P型薄膜晶体管，所述第五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于级传信号；第十五P型薄膜晶体管，所述第十五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于扫描信号；第一电容，所述第一电容的一端电性连接于第二节点，另一端电性连接于一恒定高电压；
    所述下拉维持模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第二节点，漏极电性连接于恒压高电位；第七P型薄膜晶体管，所述第七P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于级传信号，漏极电性连接于恒压高电位；第八P型薄膜晶体管，所述第八P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于扫描信号，漏极电性连接于恒压高电位；
    所述下拉模块包括：第十P型薄膜晶体管，所述第十P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第十三P型薄膜晶体管的栅极，漏极电性连接于恒压高电位；第九P型薄膜晶体管，所述第九P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电 性连接于恒压高电位；
    所述第n级GOA单元电路还包括：第十四P型薄膜晶体管，所述第十四P型薄膜晶体管的栅极及源极均电性连接于第二高频时钟信号，漏级电性连接于第二电容的一端及第十三P型薄膜晶体管的栅极；第十三P型薄膜晶体管，所述第十三P型薄膜晶体管的栅极电性连接于第十四P型薄膜晶体管的漏极及第十P型薄膜晶体管的源极，源极电性连接于第二反向高频时钟信号，漏极电性连接于第十二P型薄膜晶体管的源极；第十二P型薄膜晶体管，所述第十二P型薄膜晶体管的栅极电性连接于第二反向高频时钟信号，源极电性连接于第十三P型薄膜晶体管的漏极，漏极电性连接于第四节点；第二电容，所述第二电容的一端电性连接于第十四P型薄膜晶体管的漏极，另一端电性连接于一恒定高电压；
    在第n+1级GOA单元电路中，第一P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号、第二P型薄膜晶体管的栅极电性连接于第一高频时钟信号、第五与第十五P型薄膜晶体管的源极均电性连接于第二反向高频时钟信号、第十四P型薄膜晶体管的栅极及源极均电性连接于第二反向高频时钟信号、第十三P型薄膜晶体管的源极与第十二薄膜晶体管的栅极均电性连接于第二高频时钟信号；
    所述第一高频时钟信号与第一反向高频时钟信号的相位相反，所述第二高频时钟信号与第二反向高频时钟信号的相位相反；
    所述基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第一高频时钟信号和第二反向高频时钟信号的时序一致，第一反向高频时钟信号和第二高频时钟信号的时序一致；
    所述基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第一高频时钟信号和第二高频时钟信号的时序一致，第一反向高频时钟信号和第二反向高频时钟信号的时序一致。
  2. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，该基于P型薄膜晶体管的GOA电路的第一级连接关系中，所述第一P型薄膜晶体管的源极电性连接于起始信号。
  3. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，该基于P型薄膜晶体管的GOA电路的最后一级连接关系中，所述第二P型薄膜晶体管的源极电性连接于起始信号。
  4. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，所述基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第二反向高频时钟信号能够被第一高频时钟信号替换，所述第二高频时钟信号能够被第一 反向高频时钟信号替换；
    所述基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第二高频时钟信号能够被第一高频时钟信号替换，所述第二反向高频时钟信号能够被第一反向高频时钟信号替换。
  5. 如权利要求4所述的基于P型薄膜晶体管的GOA电路，其中，所述基于P型薄膜晶体管的GOA电路具有四条高频时钟信号线或两条高频时钟信号线。
  6. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管的栅极电性连接于级传信号，源极电性连接于第四节点，漏极电性连接于恒压高电位。
  7. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第一节点，漏极电性连接于恒压高电位。
  8. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管栅极电性连接于第四节点，源极电性连接于第一节点，漏极电性连接于恒压高电位；第十七P型薄膜晶体管，所述第十七P型薄膜晶体管的源极电性连接于第四P型薄膜晶体管的漏极，漏极电性连接于第三节点，在第n级GOA单元电路中，所述第十七P型薄膜晶体管的栅极电性连接于第二反向高频时钟信号，在第n+1级GOA单元电路中，所述第十七P型薄膜晶体管的栅极电性连接于第二高频时钟信号；第三电容，所述第三电容的一端电性连接于第三节点，另一端电性连接于级传信号。
  9. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，所述基于P型薄膜晶体管的GOA电路在输出期间，第三节点为低电位，第四节点为高电位；在输出结束后，第三节点为高电位，第四节点为低电位。
  10. 如权利要求1所述的基于P型薄膜晶体管的GOA电路，其中，各个P型薄膜晶体管的材料均为低温多晶硅。
  11. 一种基于P型薄膜晶体管的GOA电路，包括级联的多个GOA单元电路，每一级GOA单元电路均包括：正反向扫描模块、输出模块、下拉维持模块、及下拉模块；设n为正整数，第n级GOA单元电路与其相邻的第n+1级GOA单元电路为一周期；
    除第一级与最后一级GOA单元电路以外，在第n级GOA单元电路中：
    所述正反向扫描模块包括：第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极电性连接于第一高频时钟信号，源极电性连接于上一级第n-1级GOA单元的级传信号，漏极电性连接于第一节点；第二P型薄膜晶体管，所述第二P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号，源极电性连接于下一级第n+1级GOA单元的级传信号，漏极电性连接于第一节点；
    所述输出模块包括：第三P型薄膜晶体管，所述第三P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于恒压低电位及第四P型薄膜晶体管的栅极；第四P型薄膜晶体管，所述第四P型薄膜晶体管的栅极电性连接于恒压低电位及第三P型薄膜晶体管的漏极，源极电性连接于第二节点，漏极电性连接于第三节点；第五P型薄膜晶体管，所述第五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于级传信号；第十五P型薄膜晶体管，所述第十五P型薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二高频时钟信号，漏极电性连接于扫描信号；第一电容，所述第一电容的一端电性连接于第二节点，另一端电性连接于一恒定高电压；
    所述下拉维持模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第二节点，漏极电性连接于恒压高电位；第七P型薄膜晶体管，所述第七P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于级传信号，漏极电性连接于恒压高电位；第八P型薄膜晶体管，所述第八P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于扫描信号，漏极电性连接于恒压高电位；
    所述下拉模块包括：第十P型薄膜晶体管，所述第十P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第十三P型薄膜晶体管的栅极，漏极电性连接于恒压高电位；第九P型薄膜晶体管，所述第九P型薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第四节点，漏极电性连接于恒压高电位；
    所述第n级GOA单元电路还包括：第十四P型薄膜晶体管，所述第十四P型薄膜晶体管的栅极及源极均电性连接于第二高频时钟信号，漏级电性连接于第二电容的一端及第十三P型薄膜晶体管的栅极；第十三P型薄膜晶体管，所述第十三P型薄膜晶体管的栅极电性连接于第十四P型薄膜晶体管的漏极及第十P型薄膜晶体管的源极，源极电性连接于第二反向高频时钟信号，漏极电性连接于第十二P型薄膜晶体管的源极；第十二P型薄膜晶体管，所述第十二P型薄膜晶体管的栅极电性连接于第二反向高频 时钟信号，源极电性连接于第十三P型薄膜晶体管的漏极，漏极电性连接于第四节点；第二电容，所述第二电容的一端电性连接于第十四P型薄膜晶体管的漏极，另一端电性连接于一恒定高电压；
    在第n+1级GOA单元电路中，第一P型薄膜晶体管的栅极电性连接于第一反向高频时钟信号、第二P型薄膜晶体管的栅极电性连接于第一高频时钟信号、第五与第十五P型薄膜晶体管的源极均电性连接于第二反向高频时钟信号、第十四P型薄膜晶体管的栅极及源极均电性连接于第二反向高频时钟信号、第十三P型薄膜晶体管的源极与第十二薄膜晶体管的栅极均电性连接于第二高频时钟信号；
    所述第一高频时钟信号与第一反向高频时钟信号的相位相反，所述第二高频时钟信号与第二反向高频时钟信号的相位相反；
    所述基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第一高频时钟信号和第二反向高频时钟信号的时序一致，第一反向高频时钟信号和第二高频时钟信号的时序一致；
    所述基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第一高频时钟信号和第二高频时钟信号的时序一致，第一反向高频时钟信号和第二反向高频时钟信号的时序一致；
    其中，该基于P型薄膜晶体管的GOA电路的第一级连接关系中，所述第一P型薄膜晶体管的源极电性连接于起始信号；
    其中，该基于P型薄膜晶体管的GOA电路的最后一级连接关系中，所述第二P型薄膜晶体管的源极电性连接于起始信号。
  12. 如权利要求11所述的基于P型薄膜晶体管的GOA电路，其中，所述基于P型薄膜晶体管的GOA电路进行正向扫描时，所述第二反向高频时钟信号能够被第一高频时钟信号替换，所述第二高频时钟信号能够被第一反向高频时钟信号替换；
    所述基于P型薄膜晶体管的GOA电路进行反向扫描时，所述第二高频时钟信号能够被第一高频时钟信号替换，所述第二反向高频时钟信号能够被第一反向高频时钟信号替换。
  13. 如权利要求12所述的基于P型薄膜晶体管的GOA电路，其中，所述基于P型薄膜晶体管的GOA电路具有四条高频时钟信号线或两条高频时钟信号线。
  14. 如权利要求11所述的基于P型薄膜晶体管的GOA电路，其中，所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管的栅极电性连接于级传信号，源极电性连接于第四节点，漏 极电性连接于恒压高电位。
  15. 如权利要求11所述的基于P型薄膜晶体管的GOA电路，其中，所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第一节点，漏极电性连接于恒压高电位。
  16. 如权利要求11所述的基于P型薄膜晶体管的GOA电路，其中，所述每一级GOA单元电路还包括：第十六P型薄膜晶体管，所述第十六P型薄膜晶体管栅极电性连接于第四节点，源极电性连接于第一节点，漏极电性连接于恒压高电位；第十七P型薄膜晶体管，所述第十七P型薄膜晶体管的源极电性连接于第四P型薄膜晶体管的漏极，漏极电性连接于第三节点，在第n级GOA单元电路中，所述第十七P型薄膜晶体管的栅极电性连接于第二反向高频时钟信号，在第n+1级GOA单元电路中，所述第十七P型薄膜晶体管的栅极电性连接于第二高频时钟信号；第三电容，所述第三电容的一端电性连接于第三节点，另一端电性连接于级传信号。
  17. 如权利要求11所述的基于P型薄膜晶体管的GOA电路，其中，所述基于P型薄膜晶体管的GOA电路在输出期间，第三节点为低电位，第四节点为高电位；在输出结束后，第三节点为高电位，第四节点为低电位。
  18. 如权利要求11所述的基于P型薄膜晶体管的GOA电路，其中，各个P型薄膜晶体管的材料均为低温多晶硅。
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