WO2016138816A1 - 阵列基板及其制作方法以及相应的数据线合格性测试方法和装置 - Google Patents

阵列基板及其制作方法以及相应的数据线合格性测试方法和装置 Download PDF

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WO2016138816A1
WO2016138816A1 PCT/CN2016/073849 CN2016073849W WO2016138816A1 WO 2016138816 A1 WO2016138816 A1 WO 2016138816A1 CN 2016073849 W CN2016073849 W CN 2016073849W WO 2016138816 A1 WO2016138816 A1 WO 2016138816A1
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pixel
data line
brightness
array substrate
preset
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French (fr)
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张博
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/58—Testing of lines, cables or conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • An exemplary embodiment of the present invention is directed to an array substrate and a method of fabricating the same, and a corresponding data line qualification test method and apparatus.
  • One test method in the prior art is to simultaneously fabricate a metal test line from the data drive circuit and extend through the edge region outside the sealant region of the panel to the data drive when fabricating the array substrate.
  • the voltage drop of the metal test line is determined by measuring the voltage at the end of the metal test line at the opposite end of the data drive circuit, and then the voltage drop of the data line can be simulated, and the line resistance of the data line is judged to be acceptable.
  • annular common electrode pattern Since the annular common electrode pattern is usually disposed under the sealant region, an opening is required at a corner of the annular common electrode pattern away from the data driving circuit so that the metal test line located at the edge region can be introduced at the opposite end of the data driving circuit. Go to the pixel area.
  • FIG. 1 it is a schematic structural view of an array substrate fabricated by the method for fabricating an array substrate in the prior art before forming a sealant at a panel.
  • the array substrate includes a pixel area AA and is surrounded by a ring-shaped common electrode pattern 1 outside the pixel area AA and a metal test line 2 formed outside the common electrode pattern 1, the common electrode pattern 1 is provided with an opening at a corner, and the metal test line 2 is introduced through the opening Pixel area AA.
  • the sealant is required to be laser irradiated for curing.
  • the metal test line has a higher reflectance than the other ones in the open position
  • the area and the cooling rate of the metal test line are different from the sealant, which results in different curing speeds and cooling rates of the sealant at the metal test line and the sealant at the metal test line, thereby making the position of the opening
  • the sealant is cracked, causing the package to fail.
  • the array substrate needs to be cut to obtain individual panels.
  • the metal test line 2 located on the right side of the common electrode pattern 1 is cut, which exposes the metal test line 2 under the extended cutting line.
  • the exposed metal test line will undergo electrochemical corrosion, which will eventually cause the sealant around it to be corroded, which will also lead to package failure.
  • an array substrate and a manufacturing method thereof, and a corresponding data line qualification test method and apparatus can complete the test of the data line qualification of the array substrate without providing a metal test line.
  • the problem of package failure due to the provision of metal test leads can be fundamentally avoided.
  • a method for fabricating an array substrate comprising:
  • a continuous and complete annular common electrode pattern surrounding the pixel area is formed.
  • the forming a continuous and complete annular common electrode pattern surrounding the pixel region includes forming the continuous and complete annular common electrode in the same layer when forming the data line pattern of the array substrate Graphics.
  • forming the continuous and complete annular common electrode pattern by the same layer includes:
  • a patterning process is performed on the metal electrode layer to form a data line pattern and a continuous and complete annular common electrode pattern.
  • the depositing the metal electrode layer includes depositing a metal material by a sputtering process.
  • the array substrate fabrication method further includes coating a photoresist over the metal electrode layer, and exposing and developing the photoresist using a mask.
  • the mask is opaque or not completely transparent at a position corresponding to the data line pattern and the continuous and complete annular common electrode pattern.
  • the performing a patterning process on the metal electrode layer to form a data line pattern and the continuous and complete annular common electrode pattern further includes:
  • the metal electrode layer on the periphery of the continuous and complete annular common electrode pattern is etched away.
  • an array substrate comprising:
  • a continuous and complete annular common electrode pattern surrounding the pixel area is provided.
  • the array substrate further includes:
  • the array substrate further includes:
  • metal electrode layer forms the data line pattern and the continuous and complete annular common electrode pattern by a single patterning process.
  • the array substrate further includes:
  • the photoresist layer being coated on the metal electrode layer.
  • a data line eligibility test method for the above array substrate comprising:
  • the first preset data voltage is equal in magnitude to the second preset data voltage.
  • the preset luminance difference corresponds to the first preset data voltage and the second preset data voltage.
  • the first pixel and the second pixel include the same number of plurality of sub-pixels.
  • a data line eligibility testing apparatus for the above array substrate comprising:
  • a lighting module configured to illuminate a first pixel closest to the data driving circuit according to the first preset data voltage, and illuminate a second pixel farthest from the data driving circuit according to the second preset data voltage;
  • the pixel and the second pixel are connected to the same measured data line;
  • An acquiring module configured to acquire brightness of the first pixel and brightness of the second pixel
  • a determining module configured to determine whether an actual brightness difference between the brightness of the first pixel and the brightness of the second pixel is greater than a preset brightness difference; and determining the measured data when the actual brightness difference is greater than a preset brightness difference The line does not meet the requirements.
  • the first preset voltage is equal in magnitude to the second preset data voltage.
  • the preset luminance difference corresponds to the first preset data voltage and the second preset data voltage.
  • the first pixel and the second pixel include the same number of plurality of sub-pixels.
  • the acquisition module is a photosensitive detection device.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic flow chart of a data line eligibility test method according to an embodiment of the invention.
  • FIG. 3 is a schematic structural view of an array substrate fabricated by using the manufacturing method provided by the embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a data line qualification test apparatus according to an embodiment of the present invention.
  • first, second, and third are used for descriptive purposes only, and are not to be construed as indicating or implying relative importance.
  • plurality refers to two or more, unless specifically defined otherwise.
  • a data line eligibility test method for an array substrate in an embodiment of the present invention is provided. As shown in FIG. 2, the method may include:
  • Step S1 illuminating the first pixel closest to the data driving circuit according to the first preset data voltage, and illuminating the second pixel farthest from the data driving circuit according to the second preset data voltage, wherein the first pixel and The second pixel is connected to the same measured data line;
  • Step S2 acquiring brightness of the first pixel and brightness of the second pixel
  • Step S3 determining the actual brightness of the brightness of the first pixel and the brightness of the second pixel Whether the difference is greater than a preset brightness difference; and when the actual brightness difference is greater than the preset brightness difference, determining that the measured data line does not meet the requirement.
  • the first predetermined data voltage and the second data voltage are respectively used to respectively illuminate two pixels that are closest to and farthest from the data driving circuit and connected to the same measured data line, if such two If the brightness difference of the pixel is greater than the preset value, the line resistance of the data line is too large and does not meet the requirements. In addition, if it is determined that the brightness difference between the two pixels is less than or equal to the preset value, it indicates that the line resistance of the data line can basically meet the requirement of uniform illumination of the display panel, and at this time, it is determined that the measured data line meets the requirements.
  • the qualification test of the data line can be completed without the aid of the metal test line, and the problem of package failure due to the provision of the metal test line can be fundamentally avoided.
  • the first preset data voltage and the second preset data voltage in the above step S1 can be set as needed.
  • the preset brightness difference should correspond to the selected first preset data voltage and the second preset data voltage.
  • the first preset voltage and the second preset voltage may be set to a larger data voltage, so that the first pixel and the second pixel can display a larger brightness for detection. And judgment.
  • the values of the first preset voltage and the second preset voltage may be set equal, which can reduce the complexity of setting the preset luminance difference.
  • first pixel herein may include a plurality of sub-pixels, and the corresponding second pixel may also include the same number of multiple sub-pixels.
  • the brightness of the first pixel and the brightness of the second pixel can be acquired using the photosensitive detecting means.
  • an array substrate manufacturing method is provided.
  • the array substrate fabricated according to the method for fabricating an array substrate provided by the embodiment of the present invention can be applied to the above data line qualification test method.
  • the method for fabricating the array substrate includes:
  • the complete annular common electrode pattern is closed at each corner of the side away from the data driving circuit (no need to provide an opening through which the metal test line passes), and the annular common electrode pattern is formed without forming the annular common electrode pattern
  • the outer periphery forms a metal test line.
  • the structure of the array substrate prepared by the method for fabricating the array substrate according to the embodiment of the present invention may be as shown in FIG. 3, and includes a pixel area AA and a surrounding at a corner away from the side of the data driving circuit. A continuous and complete annular common electrode pattern 1 outside the pixel area.
  • the common electrode pattern 1 does not need to form an opening through which the metal test line passes at a corner away from the side of the data drive circuit. This on the one hand reduces the complexity of the manufacturing process, on the other hand, it can completely avoid the package failure caused by the electrochemical corrosion of the metal test line in the reliability test.
  • the ring common electrode pattern here can be made of metal and can be used to access a common high voltage VGH, or a common low voltage VSS.
  • the forming a continuous and complete annular common electrode pattern surrounding the pixel region may include forming the continuous and complete annular common electrode pattern in the same layer when forming the data line pattern of the array substrate. This can reduce the thickness of the formed array substrate, which is advantageous for lightening and thinning of the product.
  • forming the continuous and complete annular common electrode pattern by the same layer herein may include: depositing a metal electrode layer; performing a patterning process on the metal electrode layer to form a data line pattern and continuous And a complete circular common electrode pattern. In this way, the number of patterning processes used can be reduced, reducing process complexity.
  • a metal material may be deposited as a metal electrode layer by a sputtering process, then a photoresist is coated on the metal electrode layer, and the photoresist is exposed and developed using a mask.
  • the mask is opaque or not completely transparent at locations corresponding to the data line pattern and the continuous and complete annular common electrode pattern.
  • the photoresist corresponding to the data line pattern and the annular common electrode pattern region is not etched, and then the metal electrode layer is etched by using the photoresist as a protective layer to form a data line pattern and a continuous and complete ring common. Electrode pattern.
  • data line graphics can also be formed and continuous and complete
  • the metal electrode layer on the periphery of the ring-shaped common electrode pattern is etched away, thereby forming an array substrate not including the metal test line.
  • a data line eligibility testing device that can be used in the array substrate in the embodiment of the present invention is further provided, and can be used to implement the data line eligibility testing method in the above embodiment.
  • the device may specifically include:
  • the lighting module 401 is configured to illuminate the first pixel closest to the data driving circuit according to the first preset data voltage, and illuminate the second pixel farthest from the data driving circuit according to the second preset data voltage; One pixel and the second pixel are connected to the same measured data line;
  • the obtaining module 402 is configured to acquire the brightness of the first pixel and the brightness of the second pixel;
  • the determining module 403 is configured to determine whether an actual brightness difference between the brightness of the first pixel and the brightness of the second pixel is greater than a preset brightness difference; and when the actual brightness difference is greater than a preset brightness difference, determine the The measured data line does not meet the requirements.
  • the first preset voltage is equal in magnitude to the second preset data voltage.
  • array substrate fabricated according to the array substrate fabrication method provided in the above embodiments and the display device including the above array substrate also fall within the protection scope of the present invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制作方法以及相应的数据线合格性测试方法和装置，其中，阵列基板制作方法包括：形成环绕像素区域的连续且完整的环形公共电极图形（1）；数据线合格性测试方法包括：根据第一预设数据电压点亮距离数据驱动电路最近的第一像素，并根据第二预设数据电压点亮距离数据驱动电路最远的第二像素；第一像素和第二像素对应连接同一条被测数据线；获取第一像素的亮度和第二像素的亮度；判断第一像素的亮度与第二像素的亮度的实际亮度差是否大于预设亮度差；并在实际亮度差大于预设亮度差时，判定被测数据线不符合要求。

Description

阵列基板及其制作方法以及相应的数据线合格性测试方法和装置
本申请要求于2015年3月3日递交的中国专利申请第201510094570.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明的示例性实施例涉及一种阵列基板及其制作方法以及相应的数据线合格性测试方法和装置。
背景技术
在阵列基板的制作过程中，需要测试所形成的数据线的线阻是否合格。现有技术中的一种测试方法是，在制作阵列基板时，同时制作金属测试线，该金属测试线从数据驱动电路处引出并经由面板中封框胶区域之外的边缘区域延伸到数据驱动电路的对端，通过测量在数据驱动电路对端的金属测试线末端的电压而确定金属测试线的压降，进而可以模拟得到数据线的压降，并判断数据线的线阻是否合格。由于环形公共电极图形通常设置在封框胶区域的下方，需要在环形公共电极图形远离数据驱动电路的弯角处设置开口，以便使位于边缘区域的金属测试线能够在数据驱动电路对端处引入到像素区域。
如图1所示，其给出了现有技术中的阵列基板制作方法所制作的阵列基板在形成封框胶之前在其中一个面板处的结构示意图，所述阵列基板包括像素区域A-A、环绕在像素区域A-A之外的环形公共电极图形1以及形成在所述公共电极图形1之外的金属测试线2，所述公共电极图形1一个弯角处设置有开口，金属测试线2经过开口引入到像素区域A-A。
在对图1中的阵列基板使用封框胶过程中，需要对封框胶进行激光照射以便固化。而在开口处，由于金属测试线反射率高于开口位置内的其他 区域，且金属测试线的冷却速率不同于封框胶，从而导致金属测试线处的封框胶与不存在金属测试线处的封框胶的固化速度和冷却速度均不同，进而使得开口位置的封框胶产生裂纹，导致封装失效。
另一方面，在完成封装之后，需要将阵列基板进行切割从而得到各个独立的面板。在进行切割时，位于公共电极图形1右侧的金属测试线2被切割掉，这样会使得延切割线下方的金属测试线2暴露出来。在进行后续的信赖性测试时，暴露出来的金属测试线会发生电化学腐蚀，最终导致位于其周围的封框胶被腐蚀，这样也会导致封装失效。
发明内容
根据本发明示例性实施例提供的一种阵列基板及其制作方法以及相应的数据线合格性测试方法和装置，可以在不设置金属测试线的情况下完成对阵列基板数据线合格性的测试，能够从根本上避免因设置金属测试线而导致的封装失效的问题。
根据本发明的第一方面，提出了一种阵列基板制作方法，包括：
形成环绕像素区域的连续且完整的环形公共电极图形。
根据本发明的示例性实施例，所述形成环绕像素区域的连续且完整的环形公共电极图形包括：在形成所述阵列基板的数据线图形时，同层形成所述连续且完整的环形公共电极图形。
根据本发明的示例性实施例，所述在形成所述阵列基板的数据线图形时，同层形成所述连续且完整的环形公共电极图形包括：
沉积金属电极层；
对所述金属电极层进行一次图案化工艺形成数据线图形和连续且完整的环形公共电极图形。
根据本发明的示例性实施例，所述沉积金属电极层包括通过溅射工艺沉积金属材料。
根据本发明的示例性实施例，所述阵列基板制作方法还包括在金属电极层之上涂覆光刻胶，并使用掩膜板对所述光刻胶进行曝光显影。
根据本发明的示例性实施例，所述掩膜板在对应于数据线图形和连续且完整的环形公共电极图形的位置不透明或者不完全透明。
根据本发明的示例性实施例，所述对所述金属电极层进行一次图案化工艺形成数据线图形和连续且完整的环形公共电极图形还包括：
在同一次图案化工艺中，刻蚀掉所述连续且完整的环形公共电极图形外围的金属电极层。
根据本发明的第二方面，提出了一种阵列基板，包括：
像素区域；以及
环绕像素区域的连续且完整的环形公共电极图形。
根据本发明的示例性实施例，所述阵列基板还包括：
数据线图形，其中所述数据线图形和所述连续且完整的环形公共电极图形同层形成。
根据本发明的示例性实施例，所述阵列基板还包括：
金属电极层，其中所述金属电极层通过一次图案化工艺形成所述数据线图形和所述连续且完整的环形公共电极图形。
根据本发明的示例性实施例，所述阵列基板还包括：
光刻胶层，所述光刻胶层涂覆在所述金属电极层之上。
根据本发明的第三方面，提出了一种用于上述的阵列基板的数据线合格性测试方法，包括：
根据第一预设数据电压点亮距离数据驱动电路最近的第一像素，并根据第二预设数据电压点亮距离数据驱动电路最远的第二像素；所述第一像素和所述第二像素对应连接同一条被测数据线；
获取所述第一像素的亮度和所述第二像素的亮度；
判断所述第一像素的亮度与所述第二像素的亮度的实际亮度差是否大于预设亮度差；并在所述实际亮度差大于预设亮度差时，判定所述被测数据线不符合要求。
根据本发明的示例性实施例，所述第一预设数据电压与所述第二预设数据电压的大小相等。
根据本发明的示例性实施例，所述预设亮度差与所述第一预设数据电压和第二预设数据电压相对应。
根据本发明的示例性实施例，所述第一像素和所述第二像素包括相同数目的多个子像素。
根据本发明的第四方面，提出了一种用于上述的阵列基板的数据线合格性测试装置，包括：
点亮模块，用于根据第一预设数据电压点亮距离数据驱动电路最近的第一像素，并根据第二预设数据电压点亮距离数据驱动电路最远的第二像素；所述第一像素和所述第二像素对应连接同一条被测数据线；
获取模块，用于获取所述第一像素的亮度和所述第二像素的亮度；以及
判断模块，用于判断所述第一像素的亮度与所述第二像素的亮度的实际亮度差是否大于预设亮度差；并在所述实际亮度差大于预设亮度差时，判定被测数据线不符合要求。
根据本发明的示例性实施例，所述第一预设电压与所述第二预设数据电压的大小相等。
根据本发明的示例性实施例，所述预设亮度差与所述第一预设数据电压和第二预设数据电压相对应。
根据本发明的示例性实施例，所述第一像素和所述第二像素包括相同数目的多个子像素。
根据本发明的示例性实施例，所述获取模块为光敏检测装置。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的一种阵列基板的结构示意图；
图2为根据本发明实施例的一种数据线合格性测试方法的流程示意图；
图3为利用本发明实施例提供的制作方法所制作的阵列基板的结构示意图；以及
图4为根据本发明实施例的一种数据线合格性测试装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，在本发明中，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
根据本发明的一示例性实施例，提供了一种可用于本发明实施例中的阵列基板的数据线合格性测试方法，如图2所示，该方法可以包括：
步骤S1，根据第一预设数据电压点亮距离数据驱动电路最近的第一像素，并根据第二预设数据电压点亮距离数据驱动电路最远的第二像素，其中所述第一像素和所述第二像素对应连接同一条被测数据线；
步骤S2，获取所述第一像素的亮度和所述第二像素的亮度；以及
步骤S3，判断所述第一像素的亮度与所述第二像素的亮度的实际亮度 差是否大于预设亮度差；并在所述实际亮度差大于预设亮度差时，判定被测数据线不符合要求。
根据本发明的示例性实施例，分别使用第一预设数据电压和第二数据电压对应地点亮距离数据驱动电路最近和最远且连接同一被测数据线的两个像素，如果这样两个像素的亮度差大于预设值，则说明数据线的线阻过大，不符合要求。另外，如果判断两个像素的亮度差小于或者等于预设值，则说明数据线的线阻基本能够满足显示面板均匀发光的要求，此时判定被测数据线符合要求。
根据本发明示例性实施例的方法，可以不借助于金属测试线即可完成对数据线的合格性测试，能够从根本上避免因设置金属测试线而导致的封装失效的问题。
在一实施例中，上述的步骤S1中的第一预设数据电压和第二预设数据电压可以根据需要设置。相应地，所述预设的亮度差应与所选择的第一预设数据电压和第二预设数据电压相对应。
作为一种可选的方式，可以将第一预设电压和第二预设电压均设置为一个较大的数据电压，这样能够使第一像素和第二像素显示较大的亮度，以便于检测和判断。
在一实施例中，可以设置第一预设电压和第二预设电压的值相等，这样能够降低设置预设亮度差的复杂度。
不难理解的是，这里的第一像素可以包括多个子像素、相应的第二像素也可以包括相同数目的多个子像素。
在上述的步骤S2中，可以使用光敏检测装置采集第一像素的亮度和第二像素的亮度。
根据本发明的另一示例性实施例，提供了一种阵列基板制作方法，根据本发明实施例提供的阵列基板制作方法而制作的阵列基板可适用于上述数据线合格性测试方法。
具体地，所述阵列基板制作方法包括：
形成环绕像素区域的连续且完整的环形公共电极图形，即所述连续且 完整的环形公共电极图形在远离数据驱动电路的一侧的各个弯角处封闭(无需设置供金属测试线穿过的开口)，且形成所述环形公共电极图形时无需在所述环形公共电极图形的外围形成金属测试线。
根据本发明实施例的阵列基板制作方法所制作的阵列基板在形成封框胶之前的结构可以如图3所示，在远离数据驱动电路的一侧的一个弯角处包括：像素区域A-A、环绕在像素区域之外的连续且完整的环形公共电极图形1。在该阵列基板上，公共电极图形1的外侧无需形成金属测试线，且公共电极图形1在远离数据驱动电路的一侧的弯角处也无需形成供金属测试线穿过的开口。这样一方面降低了制作工艺的复杂度，另一方面，能够彻底避免在信赖性测试中由于金属测试线的电化学腐蚀而导致的封装失效。
值得注意的是，这里的环形公共电极图形可以采用金属制作，并且可以用于接入公共高电压VGH、或者公共低电压VSS。
在一实施例中，上述形成环绕像素区域的连续且完整的环形公共电极图形可以包括：在形成所述阵列基板的数据线图形时，同层形成所述连续且完整的环形公共电极图形。这样能够降低所形成的阵列基板的厚度，利于产品的轻薄化。
根据本发明的示例性实施例，这里的同层形成所述连续且完整的环形公共电极图形可以包括：沉积金属电极层；对所述金属电极层进行一次图案化工艺以形成数据线图形和连续且完整的环形公共电极图形。通过这种方式，能够减少所使用的图案化工艺的次数，降低工艺复杂度。
根据本发明的示例性实施例，可以通过溅射工艺沉积一层金属材料作为金属电极层，随后在金属电极层之上涂覆光刻胶，并使用掩膜板对光刻胶进行曝光显影，该掩膜板在对应于数据线图形和连续且完整的环形公共电极图形的位置不透明或者不完全透明。这样，使得数据线图形和环形公共电极图形区域对应的光刻胶不会被刻蚀，之后利用光刻胶作为保护层对金属电极层进行刻蚀，形成数据线图形和连续且完整的环形公共电极图形。
根据本发明的示例性实施例，还可以在形成数据线图形和连续且完整 的环形公共电极图形时对所述金属电极层的图案化工艺中，刻蚀掉环形公共电极图形外围的金属电极层，从而形成不包括金属测试线的阵列基板。
根据本发明的另一示例性实施例，还提供了一种可用于本发明实施例中的阵列基板的数据线合格性测试装置，并可以用于实施上述实施例中的数据线合格性测试方法，如图4所示，该发装置可以具体包括：
点亮模块401，用于根据第一预设数据电压点亮距离数据驱动电路最近的第一像素，并根据第二预设数据电压点亮距离数据驱动电路最远的第二像素；所述第一像素和所述第二像素对应连接同一条被测数据线；
获取模块402，用于获取所述第一像素的亮度和所述第二像素的亮度；以及
判断模块403，用于判断所述第一像素的亮度与所述第二像素的亮度的实际亮度差是否大于预设亮度差；并在所述实际亮度差大于预设亮度差时，判定所述被测数据线不符合要求。采用根据本发明实施例提供的数据线合格性测试装置，可以不借助于金属测试线而完成对数据线的合格性测试，能够从根本上避免因设置金属测试线而导致的封装失效的问题。
根据本发明的示例性实施例，所述第一预设电压与所述第二预设数据电压的大小相等。
值得注意的是，根据上述实施例中提供的阵列基板制作方法制作的阵列基板以及包括上述阵列基板的显示装置也落入本发明的保护范围内。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板制作方法，包括：
    形成环绕像素区域的连续且完整的环形公共电极图形。
  2. 如权利要求1所述的方法，其中，所述形成环绕像素区域的连续且完整的环形公共电极图形包括：在形成所述阵列基板的数据线图形时，同层形成所述连续且完整的环形公共电极图形。
  3. 如权利要求2所述的方法，其中，所述在形成所述阵列基板的数据线图形时，同层形成所述连续且完整的环形公共电极图形包括：
    沉积金属电极层；
    对所述金属电极层进行一次图案化工艺形成数据线图形和连续且完整的环形公共电极图形。
  4. 如权利要求3所述的方法，其中，所述沉积金属电极层包括通过溅射工艺沉积金属材料。
  5. 如权利要求3或者4所述的方法，还包括在金属电极层之上涂覆光刻胶，并使用掩膜板对所述光刻胶进行曝光显影。
  6. 如权利要求5所述的方法，其中，所述掩膜板在对应于数据线图形和连续且完整的环形公共电极图形的位置不透明或者不完全透明。
  7. 如权利要求3-6任一所述的方法，其中，所述对所述金属电极层进行一次图案化工艺形成数据线图形和连续且完整的环形公共电极图形还包括：
    在同一次图案化工艺中，刻蚀掉所述连续且完整的环形公共电极图形外围的金属电极层。
  8. 一种阵列基板，包括：
    像素区域；以及
    环绕像素区域的连续且完整的环形公共电极图形。
  9. 如权利要求8所述的阵列基板，还包括：
    数据线图形，其中所述数据线图形和所述连续且完整的环形公共电极图形同层形成。
  10. 如权利要求9所述的阵列基板，还包括：
    金属电极层，其中所述金属电极层通过一次图案化工艺形成所述数据线图形和所述连续且完整的环形公共电极图形。
  11. 如权利要求10所述的阵列基板，还包括：
    光刻胶层，所述光刻胶层涂覆在所述金属电极层之上。
  12. 一种用于如权利要求8-11任一所述的阵列基板的数据线合格性测试方法，包括：
    根据第一预设数据电压点亮距离数据驱动电路最近的第一像素，并根据第二预设数据电压点亮距离数据驱动电路最远的第二像素；所述第一像素和所述第二像素对应连接同一条被测数据线；
    获取所述第一像素的亮度和所述第二像素的亮度；
    判断所述第一像素的亮度与所述第二像素的亮度的实际亮度差是否大于预设亮度差；并在所述实际亮度差大于预设亮度差时，判定所述被测数据线不符合要求。
  13. 如权利要求12所述的方法，其中，所述第一预设数据电压与所述第二预设数据电压的大小相等。
  14. 如权利要求12或者13所述的方法，其中，所述预设亮度差与所述第一预设数据电压和第二预设数据电压相对应。
  15. 如权利要求12-14任一所述的方法，其中，所述第一像素和所述第二像素包括相同数目的多个子像素。
  16. 一种用于根据权利要求8-11任一所述的阵列基板的数据线合格性测试装置，包括：
    点亮模块，用于根据第一预设数据电压点亮距离数据驱动电路最近的第一像素，并根据第二预设数据电压点亮距离数据驱动电路最远的第二像素；所述第一像素和所述第二像素对应连接同一条被测数据线；
    获取模块，用于获取所述第一像素的亮度和所述第二像素的亮度；以及
    判断模块，用于判断所述第一像素的亮度与所述第二像素的亮度的实 际亮度差是否大于预设亮度差；并在所述实际亮度差大于预设亮度差时，判定被测数据线不符合要求。
  17. 如权利要求16所述的装置，所述第一预设电压与所述第二预设数据电压的大小相等。
  18. 如权利要求16或者17所述的装置，其中，所述预设亮度差与所述第一预设数据电压和第二预设数据电压相对应。
  19. 如权利要求16-18任一所述的装置，其中，所述第一像素和所述第二像素包括相同数目的多个子像素。
  20. 如权利要求16-19任一所述的装置，其中，所述获取模块为光敏检测装置。
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