WO2016137720A1 - Réseau de cellules de mémoire non volatile à cellules à mémoire morte (rom) - Google Patents

Réseau de cellules de mémoire non volatile à cellules à mémoire morte (rom) Download PDF

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Publication number
WO2016137720A1
WO2016137720A1 PCT/US2016/016738 US2016016738W WO2016137720A1 WO 2016137720 A1 WO2016137720 A1 WO 2016137720A1 US 2016016738 W US2016016738 W US 2016016738W WO 2016137720 A1 WO2016137720 A1 WO 2016137720A1
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WO
WIPO (PCT)
Prior art keywords
rom
channel region
cells
insulated
disposed over
Prior art date
Application number
PCT/US2016/016738
Other languages
English (en)
Inventor
Jinho Kim
Vipin TIWARI
Nhan Do
Xian Liu
Xiaozhou QIAN
Ning BAI
Kai Man Yue
Original Assignee
Silicon Storage Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201510089866.9A external-priority patent/CN105990367B/zh
Application filed by Silicon Storage Technology, Inc. filed Critical Silicon Storage Technology, Inc.
Priority to JP2017545283A priority Critical patent/JP6488401B2/ja
Priority to EP16706290.0A priority patent/EP3262683A1/fr
Priority to KR1020177027334A priority patent/KR102003628B1/ko
Priority to TW105105437A priority patent/TWI581371B/zh
Publication of WO2016137720A1 publication Critical patent/WO2016137720A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/34—Source electrode or drain electrode programmed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Definitions

  • the present invention relates to non-volatile memory cell arrays, and more particularly to such arrays that include read-only memory cells.
  • FIG. 1 illustrates an example of such conventional split gate memory cells 10 formed on a semiconductor substrate 12.
  • Source and drain regions 14 and 16 are formed as diffusion regions in silicon substrate 12, and define a channel region 18 therebetween.
  • Each memory cell 10 includes four conductive gates: a floating gate 20 disposed over and insulated from a first portion of the channel region 18 and a portion of the source region 14, a control gate 22 disposed over and insulated from the floating gate 20 by insulation layer 23, an erase gate 24 disposed over and insulated from the source region 14, and a select gate 26 (commonly referred to as the word line gate) disposed over and insulated from a second portion of the channel region 18.
  • a conductive contact 28 electrically connects the drain region 16 to a conductive bit line 30, that electrically connects to all the drain regions in the column of memory cells 10.
  • the memory cells 10 are formed in pairs that share a common source region 14 and erase gate 24.
  • Memory cells 10 are programmed by injecting electrons onto the floating gate 20.
  • the negatively charged floating gate 20 causes a reduced or zero conductivity in the underlying channel region 18, which is read as a "0" state.
  • Memory cells 10 are erased by removing the electrons from the floating gate 20, which allows the underlying channel region to conduct when the corresponding select gate 26 and control gate 22 are raised to their reading voltage potentials. This is read as a "1" state.
  • Memory cells 10 can be repeatedly programmed, erased and re-programmed.
  • ROM read only memory
  • NVM non-volatile memory
  • ROM read only memory
  • ROM includes memory cells that are only programmable once, and thereafter cannot be erased or re-programmed.
  • ROM is formed on the same chip as the NVM array to provide code that cannot be changed.
  • the code needs to be secure (i.e. once programmed, the user or hacker should not be able to change it or hack it).
  • the NVM cells are not appropriate for storing this secure code, because the user could accidentally program code over this secure code, or it could be hacked by those with malicious intentions.
  • One solution has been to provide a dedicated ROM structure that is separate from, but on the same chip as, the NVM array.
  • a memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate, with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells.
  • the conductive line is electrically coupled to the drain regions of a first subgroup of the plurality of ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the plurality of ROM cells.
  • a memory device includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate, with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, and a second gate disposed over and insulated from a second portion of the channel region.
  • the ROM cell For each of a first subgroup of the plurality of ROM cells, the ROM cell includes a higher voltage threshold implant region in the channel region, and for each of a second subgroup of the plurality of ROM cells, the ROM cell lacks any higher voltage threshold implant region in the channel region.
  • Fig. 1 is a side cross sectional view of a conventional non-volatile memory cell.
  • Fig. 2 is a side cross sectional view of ROM cells showing ROM cells programmed with intact bit line contacts.
  • Fig. 3 is a side cross sectional view of ROM cells showing a ROM cell programmed with a missing bit line contact.
  • Figs. 4-9 are side cross sectional views of alternate embodiments of the ROM cells of the present invention.
  • the present invention is a technique that integrates ROM within the non-volatile memory (NVM) array using the same basic structures as the NVM cells, such that the ROM is not easily distinguishable or identifiable from the NVM array by potential hackers.
  • the technique is easily manufactured because it involves easy to implement changes to the existing memory cells within the array.
  • Fig. 2 illustrates ROM cells 40a, 40b, 40c and 40d, which can be embedded anywhere in an array of the above described NVM cells 10.
  • Each ROM cell has the same components as the above described memory cells 10, except that insulation 23 is omitted such that floating gate 20 and control gate 22 are integrally formed as a single control gate 42 (i.e. no floating gate).
  • each ROM cell does not share drain region 16 or contact 28 with the adjacent ROM cell, but rather each ROM cell has its own drain region 16 and contact 28.
  • a dummy gate 44 is formed between the drain regions 16 of adjacent ROM cells.
  • ROM cell 40b when gates 42 and 26 of that cell are raised to their reading voltage potentials, channel region 18b will always be rendered conductive between source 14 and drain 16b, which is read as a "1" state. Therefore, ROM cell 40b will always read as a "1" state by detected current flow from source region 14, through channel region 18b, drain 16b, drain contact 28b and to bit line 30). This "1" state is determined and fixed (i.e. not changeable later) at the time of fabrication. In contrast, if it is desired that ROM cell 40b always reads as a "0" state, then it would be fabricated with the configuration shown in Fig. 3, which is the same configuration as that shown in Fig.
  • drain contact 28b would be omitted during the fabrication process.
  • gates 42 and 26 of ROM cell 40b are raised to their reading voltage potentials, channel region 18b will always be rendered conductive between source 14 and drain 16b, but that conductivity is broken by the lack of any contact between drain 16b and bit line 30.
  • ROM cell 40b with this configuration will always read as a "0" state (i.e. no detected current flow between source region 14 and bit line 30).
  • dummy gate 44 is held at zero volts (or a positive or negative voltage that is less than the subthreshold voltage) to ensure that the silicon underneath gate 44 is not conductive.
  • ROM cell 40b will always read as a "0" state
  • ROM cell 40c which has a bit line contact 28c
  • the programming state of ROM cells 40 is dictated by including, or not including, the corresponding bit line contact 28 during fabrication.
  • the ROM cells can be easily fabricated at the same time as the non-volatile memory cell array (i.e. very similar process flows, only one additional masking step).
  • the masking step used to form the contacts 28 for the ROM and NVM cells dictates which ROM cells will include a contact 28 and which will not.
  • the ROM cells 40 can be formed either adjacent to or even inside the NVM array of memory cells 10. Also, because the ROM cells 40 are so similar to the NVM cells 10, it would be very difficult to distinguish the two types of cells when they are formed in the same array, making hacking difficult.
  • Fig. 4 illustrates an alternate embodiment, where the ROM cells 40 are even closer in design to the NVM cells 10. Specifically, in this embodiment, the insulation layer 23 is maintained such that each ROM cell 40 includes separate floating and control gates 20 and 22. ROM cells 40 are read in this configuration by raising control gate 22 to a high enough voltage such that, through voltage coupling to the floating gate 20, the channel region under the floating gate 20 is conductive. As shown in Fig. 4, ROM cell 40b would read as a "0" state (because of the missing contact 28) and ROM cell 40c would read as a "1" state (because of the existing contact 28c). [0018] Fig. 5 illustrates another alternate embodiment, which is the same as Fig. 4 except that a hole in layer 23 is formed such that a portion of control gate 22 is in electrical contact with the floating gate 20.
  • Fig. 6 illustrates another alternate embodiment, which is the same as Figs. 2 and 3, except that instead of programming ROM cell 40b in the "0" state by omitting drain contact 28b, a layer of insulation 48 can be formed over drain 16b so that contact 28b is not in electrical contact with drain 16b.
  • Insulation 48 can be selective formed by forming it over all the drain regions 16, followed by a mask and etch process that selectively removes the insulation 48 from the drain regions 16 of those ROM cells that are to be in the "1" state.
  • Fig. 7 illustrates still another alternate embodiment, where ROM cells are programmed through selective substrate implantation instead of selective bit line contact formation.
  • ROM cell 40c includes a higher threshold voltage implant region 50 in channel region 18c.
  • the implant region 50 has a higher threshold voltage (Vt) required to make the channel 18c conduct relative to the channel regions without the implant 50.
  • Vt threshold voltage
  • the threshold voltage Vt of implant region 50 is greater than the read voltages applied to select and control gates 26 and 46.
  • Implant region 50 can be disposed under the select gate 26, under the control gate 42, or at least partially under both as shown. Preferably, implant region 50 extends from source region 14 toward drain region 16, but does not extend all the way to drain region 16 to improve the break down voltage and lower the junction capacitance.
  • Fig. 8 illustrates still another alternate embodiment, which is similar to that in Fig. 7, except the insulation layer 23 is maintained such that each ROM cell 40 includes separate floating and control gates 20 and 22. A hole in layer 23 is formed such that a portion of control gate 22 is in electrical contact with the floating gate 20.
  • Fig. 9 illustrates still another alternate embodiment, which is similar to that in Fig. 7, except the insulation layer 23 is maintained such that each ROM cell 40 includes separate floating and control gates 20 and 22 which are insulated from each other.
  • the implant region 50 is formed under just the select gate 26 (and not under floating gate 20).
  • the floating cells 20 remain unprogrammed (i.e. no electrons injected thereon) such that the channel regions under the floating gates 20 are conductive. Therefore, during the read operation of ROM cell 40c, when a read voltage is applied to select gate 26c, channel region 18c will not conduct due to implant region 50, indicating that ROM cell 40c is configured in the "0" state. In contrast, during the read operation of ROM cell 40b, raising select gate 26b to its reading potentials results in current flow through channel region 18b, indicating that ROM cell 40b is configured in the "1" state.
  • references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims.
  • Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Those skilled in the art understand that the source and drain regions are interchangeable. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
  • the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
  • forming an element "over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

La présente invention porte sur un dispositif de mémoire qui comprend une pluralité de cellules à mémoire morte (ROM) comprenant chacune des régions de source et de drain espacées formées dans un substrat comprenant une région de canal entre celles-ci, une première grille disposée au-dessus d'une première partie de la région de canal de et isolée vis-à-vis de celle-ci, une seconde grille disposée au-dessus d'une seconde partie de la région de canal et isolée vis-à-vis de celle-ci , et une film conducteur s'étendant au-dessus de la pluralité de cellules ROM. La ligne conductrice est couplée électriquement aux régions de drain d'un premier sous-groupe des cellules ROM, et n'est pas couplée électriquement aux régions de drain d'un second sous-groupe de cellules ROM. En variante, un premier sous-groupe des cellules ROM comprend, pour chaque cellule, une région d'implantation de seuil de tension supérieur dans la région de canal, tandis qu'un second sous-groupe des cellules ROM ne présente, pour chaque cellule, aucune région d'implantation de seuil de tension supérieur dans la région de canal.
PCT/US2016/016738 2015-02-27 2016-02-05 Réseau de cellules de mémoire non volatile à cellules à mémoire morte (rom) WO2016137720A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2017545283A JP6488401B2 (ja) 2015-02-27 2016-02-05 Ｒｏｍセルを含む不揮発性メモリセルのアレイ
EP16706290.0A EP3262683A1 (fr) 2015-02-27 2016-02-05 Réseau de cellules de mémoire non volatile à cellules à mémoire morte (rom)
KR1020177027334A KR102003628B1 (ko) 2015-02-27 2016-02-05 Rom 셀들을 갖는 비휘발성 메모리 셀들의 어레이
TW105105437A TWI581371B (zh) 2015-02-27 2016-02-24 具有唯讀記憶體（ｒｏｍ）單元之非揮發性記憶體單元陣列

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201510089866.9 2015-02-27
CN201510089866.9A CN105990367B (zh) 2015-02-27 2015-02-27 具有rom单元的非易失性存储器单元阵列
US14/639,063 2015-03-04
US14/639,063 US9601500B2 (en) 2015-02-27 2015-03-04 Array of non-volatile memory cells with ROM cells

Publications (1)

Publication Number Publication Date
WO2016137720A1 true WO2016137720A1 (fr) 2016-09-01

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259132B1 (en) * 1997-07-08 2001-07-10 Stmicroelectronics S.R.L. Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cells
US20070158737A1 (en) * 2006-01-06 2007-07-12 Samsung Electronics Co., Ltd. Semiconductor device with mask read-only memory and method of fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259132B1 (en) * 1997-07-08 2001-07-10 Stmicroelectronics S.R.L. Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cells
US20070158737A1 (en) * 2006-01-06 2007-07-12 Samsung Electronics Co., Ltd. Semiconductor device with mask read-only memory and method of fabricating the same

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