WO2016127853A1 - 一种基于扩展汉明码的二维乘积码编码装置及编码方法 - Google Patents

一种基于扩展汉明码的二维乘积码编码装置及编码方法 Download PDF

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WO2016127853A1
WO2016127853A1 PCT/CN2016/073141 CN2016073141W WO2016127853A1 WO 2016127853 A1 WO2016127853 A1 WO 2016127853A1 CN 2016073141 W CN2016073141 W CN 2016073141W WO 2016127853 A1 WO2016127853 A1 WO 2016127853A1
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encoding
information
bit
circuit module
encoded
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张萌
李保申
李红
郭仲亚
黄成�
田茜
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes

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  • the invention relates to the field of design and implementation of a digital signal processing system and an error correction coding technology in communication data transmission, in particular to a two-dimensional product code coding apparatus and an encoding method based on an extended Hamming code.
  • Wireless communication is to process the message to be sent in some form, and the information to be transmitted is reliably and accurately transmitted to the receiver through the antenna radio frequency technology.
  • the reliability and accuracy of sending information transmission has always been the goal pursued by wireless communication technology.
  • the error correction coding technique is a technique for performing a certain mathematical operation on the original transmission information in order to improve the transmission reliability of the wireless communication system and reduce the interference of channel noise.
  • the error correction coding is also called channel coding.
  • a certain amount of check symbols are added after the original information symbol transmitted according to a certain mathematical algorithm, and the information code is implemented by the receiving end according to the corresponding decoding algorithm by using the check code word. The error detection and correction of the word improves the transmission accuracy of the original information symbol.
  • the codeword to be transmitted is an information codeword
  • the codeword added after being encoded is a check codeword, which is also called redundant information.
  • the purpose of error correction coding is to exchange the highest error correction performance and coding gain with a minimum coding cost to improve the efficiency and reliability of system transmission.
  • the product code is an error correction code with excellent error correction performance.
  • the product code was proposed by Elias in 1954. It is the first error correction code that can achieve error-free transmission at non-zero code rate after Shannon Information Theory proposes. Due to the hardware level at the time, its application was limited.
  • Pyndiah et al. proposed a soft input soft output decoding algorithm for linear block codes based on Chase algorithm and applied it to product code decoding. It has excellent error correction performance and low algorithm complexity, which lays a solid theoretical foundation for the wide application of product codes.
  • the product code has attracted the attention of many researchers at home and abroad with its excellent error correction performance and low coding and decoding complexity.
  • the United States, Japan, and some European countries have applied product code technology to satellite communications. Companies such as AHA, ALTERA, and XINLNX in the United States have developed flexible coded product code encoding and decoding chips. There is no dedicated chip in this field in China.
  • Product code technology is an important technology in current digital communication, which has caused great concern in the communication industry.
  • the product code can be divided into two-dimensional, three-dimensional and multi-dimensional product codes according to the number of sub-codes, and the two-dimensional product code is mainly used in practical applications.
  • the product code encoder requires a buffer dedicated to store the original information and the encoded information, and finally encodes and outputs.
  • the product code can be divided into a plurality of types according to the type of the subcode, such as a subcode of an RS code, an LDPC code, an extended Hamming code, or a combination of two codes.
  • the coding delay of the product code is a major technical problem in hardware design. Therefore, improving coding efficiency and reducing coding delay while reducing hardware consumption are important items to be studied.
  • the product code adopts the method of row and column coding in coding, which means that for the two-dimensional product code composed of different subcodes, the encoding has to go through two processes of row and column, and the encoding delay is large; meanwhile, the hardware design of the traditional encoding circuit
  • the read/write memory RAM is used for data information storage and reading.
  • the RAM is divided into two ports and a single port RAM, and the double port reading and writing can be performed at the same time, but only one address bit information can be read at a time, so A product code encoder using RAM storage has a large delay.
  • the register set can be used in the hardware design to realize the storage and reading of the data. It has great advantages in terms of throughput.
  • the present invention provides a two-dimensional product code encoding apparatus and an encoding method based on an extended Hamming code, which are used for storing and reading data by using a register group.
  • the code word parameter of the product code the size and number of the register are set, and the corresponding timing scheduling algorithm is combined to realize the synchronization of the row and column coding, shortening the coding delay and improving the coding circuit throughput rate.
  • an apparatus for encoding a two-dimensional product code based on an extended Hamming code includes: an information input buffer module, an encoding control circuit module, an encoding information storage circuit module, and a subcode encoding logic circuit module,
  • the information input buffer module is configured to store the encoded original information by using the FIFO memory and output the encoded data stream to the encoded information storage circuit module, and simultaneously output a code enable signal to the encoding control circuit module; the encoding control circuit module, And a method for starting a counter inside the circuit after the code enable signal is valid, and controlling the code information storage circuit module by using a selector control signal and an address control signal in a clock cycle, and finally outputting the coded information and the code output
  • the code information storage circuit module is configured to store the encoded data stream in the clock cycle, and then use the subcode encoding logic circuit according to the selector control signal and the address control signal
  • the module performs subcode encoding and the number of bits of information The stream and check bit
  • the encoding information storage circuit module includes: four selectors, information bits containing k k bits, according to an encoding rule of the extended Hamming code, the size and the number of the register are determined.
  • Register information register register group row check register set of row check register containing k nk bits, column check register set of column check register containing k nk bits, double check with nk nk bits
  • a double check register set of registers the input of each register set being coupled to the output of the corresponding selector, where n is the length of the encoded information subcode and k is the length of the information bit data.
  • the calculation of the time series scheduling is performed according to the length of the coded information and the number of check bits, and the count range of the internal counter of the code control circuit module is 1 to n+2k.
  • the subcode encoding logic circuit module includes:
  • a reconfigurable line code encoding operation circuit configured to perform extended Hamming code encoding on the line information data stream stored by the coded information storage circuit module, and feed back the encoded line check data stream to the coded information storage circuit module
  • a reconfigurable column code encoding operation circuit configured to perform extended Hamming code encoding on the column information data stream stored by the encoded information storage circuit module, and feed back the encoded column check data stream to the encoded information storage circuit module
  • the reconfigurable column code encoding operation circuit and the reconfigurable line code encoding operation circuit adopt the same circuit structure.
  • the present invention also provides a two-dimensional product code encoding method based on an extended Hamming code, the method comprising the following steps:
  • the information input buffer module uses the FIFO memory to store the encoded original information and outputs the encoded data stream to the encoded information storage circuit module, and simultaneously outputs the encoding enable signal to the encoding control circuit module;
  • the encoding control circuit module starts a counter inside the circuit after the encoding enable signal is valid, and controls the subcode encoding logic circuit module by using a selector control signal and an address control signal in a clock cycle;
  • the coded information storage circuit module stores the encoded data stream in the clock cycle, and then performs subcode coding using the subcode encoding logic circuit module according to the selector control signal and the address control signal. And storing the obtained check bit information, and transmitting the information bit data stream and the check bit data stream to the encoding control circuit module.
  • the encoding control circuit module obtains complete encoding information according to the information bit data stream and the parity bit data stream, and outputs the encoded output enable signal.
  • the counting range of the internal counter of the encoding control circuit module is 1 to n+2k, where n is the length of the encoded information, and k is the length of the information bit data.
  • the code information storage circuit module includes: a selector, an information bit register group, a row check register group, a column check register group, and a double check register group, and each register group is respectively connected with a corresponding selector.
  • the subcode encoding logic circuit module includes a reconfigurable row code encoding operation circuit and a reconfigurable column code encoding operation circuit, and the encoding information storage circuit module in step (3) performs data storage and subcode in the clock cycle.
  • the delivery of the code and data stream includes the following steps:
  • Count value is 1 to k: information bit registration in which the encoded data stream is sequentially stored in the coded information storage circuit module In the device group, the information bit register group includes k k-bit information bit registers;
  • the count value is k+1 ⁇ 2*k: the data stored in the information bit register group is sequentially sent to the reconfigurable line code encoding operation circuit as a line information data stream to obtain row check bit data, and the data is obtained.
  • the row check data is sequentially stored in the row check register group, and the row check register group includes k row check registers of the nk bits; at the same time, the bit data of the information bit register group is sequentially changed from the highest bit to the lowest bit.
  • the bit is set to the highest bit, and the same bit of the information bit register k is the lowest bit.
  • the same bit is combined and sent to the reconfigurable column code encoding operation circuit as a column information data stream to be encoded. Detecting bit data, and sequentially storing the column check bit data into a column check register group, wherein the column check register set includes k column check registers of nk bits;
  • the count value is 2*k+1 ⁇ n+k: the highest bit to the lowest bit of the column check register group are sent to the reconstructed line code encoding operation circuit as a row information data stream every time, and the obtained
  • the row information data stream is sequentially stored in a double check register set, and the double check register set includes nk nk bit double check registers;
  • the output of the encoded information is synchronously performed, and the data stored in the information bit register and the data stored in the corresponding row check register are used as the upper bits as the upper bits and merged into one n-bit code.
  • Data is sent to the encoding control circuit module, and the encoding control circuit module outputs encoding information, and the encoding output enable is enabled;
  • the count value is n+k+1 ⁇ n+2*k: in the counting range n+k+1 ⁇ 2*k, the encoding information in the encoded information storage circuit module is continuously output; in the counting range 2*k +1 ⁇ 3*k, the output coded information is the parallel n-bit data formed by the data in the information bit register and the data in the row check register; in the counting range 3*k+1 ⁇ n+2*k
  • the output encoded information is a parallel n-bit data formed by combining the data in the column check register and the double check register.
  • the two-dimensional product code encoding apparatus and encoding method based on extended Hamming code of the present invention use a register set instead of a RAM memory for data storage and reading, thereby avoiding data storage and reading by RAM.
  • the size and number of the register are set, and the corresponding timing scheduling algorithm is combined to realize the synchronization of the row and column coding, shortening the coding delay, and realizing the double
  • the synchronization of the coding and coding outputs further shortens the delay of the entire coding control process and improves the coding circuit throughput.
  • FIG. 1 is a schematic diagram of a frame of a wireless communication system
  • FIG. 2 is a schematic diagram of an encoding matrix of a two-dimensional product code
  • FIG. 3 is a diagram of a two-dimensional product code encoding apparatus based on an extended Hamming code according to the present invention
  • FIG. 4 is a diagram of a two-dimensional product code encoding apparatus based on (8, 4) extended Hamming code in the embodiment;
  • FIG. 5 is a timing chart of a product code storage matrix and a code output of a product code based on a (8, 4) extended Hamming code in the embodiment.
  • the transmitting end of the wireless communication system first performs channel coding on the original signal of the source, performs modulation mapping, and performs digital-to-analog conversion, and finally uses the antenna to transmit the radio frequency signal, and the antenna of the receiving end receives the radio frequency signal, and then performs the modulus.
  • the conversion and demodulation mapping are performed, and finally the channel decoding is performed to finally obtain the transmitted signal information.
  • the channel coding part that is, the product code coding in the figure, is used, and the extended Hamming code is used as the subcode for encoding.
  • the original k bit length is changed to n bit length.
  • the code code word is composed, the k bit original information is placed in front, followed by the (n-k) bit check information. Therefore, for a two-dimensional product code composed of an extended Hamming code whose subcode parameter is (n, k, d), the size of the memory matrix is n*n.
  • the rows of the matrix represent the row codes of the two-dimensional product code
  • the columns represent the column codes.
  • the matrix mainly includes four parts: the information matrix, the row check matrix, the column check matrix and the double check matrix, respectively corresponding to the corresponding Data information.
  • the product code When the product code is encoded, it can be followed by the first row or the first column.
  • the method of synchronous coding of the row and column information bits and then performing the check bit coding can shorten the coding delay of one of the rows and columns, thereby improving the coding efficiency.
  • a two-dimensional product code encoding apparatus based on an extended Hamming code includes: an information input buffer module, an encoding control circuit module, an encoding information storage circuit module, and a subcode encoding logic circuit module, and the subcode encoding logic circuit module mainly includes an internal The line code encoding operation circuit and the reconfigurable column code encoding operation circuit are reconstructed.
  • the encoded original information is first sent to the information input buffer module, and the encoded original information is converted into the encoded data stream and sent to the encoded information storage circuit.
  • the bit width of the encoded original information may be different from the subcode parameter of the product code, so it is necessary to use a buffer to convert it into a bit width data stream that is consistent with the product code subcode parameter, that is, the length of the subcode information bit.
  • the information input buffer consists of a variable bit width FIFO whose size can be determined by the total amount of encoded original information. After all the encoded original information is stored, the information input buffer is divided by k bit width.
  • the encoded data stream is output to the encoded information storage circuit module, and the encoded enable signal is output to the encoding control circuit module.
  • the encoder control circuit module has a counter inside, which is started after the code enable signal is valid.
  • the count range is 1 ⁇ (n+2k), and the count is counted once every (n+2k) clock cycles, counting once per cycle, representing the current code. And the output is done once. After the encoding output is completed, the counter is 0, and the next information input and encoding can be entered.
  • the subcode encoding logic circuit module mainly includes a reconfigurable row code encoding operation circuit and a reconfigurable column code encoding operation circuit. Since the row code column code adopts the same extended Hamming code, the two circuit structures are the same, and all are the same extended Han.
  • a coding operation circuit of a clear code which can perform coding of an arbitrary extended Hamming code having a code length smaller than n.
  • the coded information storage circuit module includes the following parts: (1) four selectors: selector 1, selector 2, selector 3, selector 4; (2) k k-bit information bit registers, ie information bit register set (3) k (nk) bit row check register, that is, row check register group; (4) k (nk) bit column check register, that is, column check register group; (5) (nk) The (nk) bit double check register, that is, the double check register set.
  • the input of each register is connected to the output of the corresponding selector.
  • the encoded data stream is first sent to the selector 1, and the selector 1 stores the encoded data stream in the corresponding information bit register in accordance with the selector 1 control signal and the address control signal of the encoding control circuit.
  • the encoding control circuit takes out the entire codeword from the encoded information storage circuit and outputs the encoded complete information in a row.
  • the timing scheduling process for the entire device is as follows:
  • Step 1 Encoding the original information input bit width conversion FIFO. After the FIFO is stored, the parallel output of the encoded data stream is performed according to the k-bit of the codeword parameter, to the coded information storage circuit module, and the code enable signal is output to the code control circuit module. .
  • Step 2 After the encoding enable signal is valid, the encoding control circuit starts its internal counter, the counting range is 1 ⁇ (n+2*k), and the encoding phase control is performed, and the encoding information storage circuit module is based on the selector of the encoding controller.
  • the control signal and the address control signal store the corresponding data, and output the information after the encoding, and the specific timing scheduling control operation is as follows:
  • the count value is 1 to k: the encoded data stream is sequentially stored in the information bit register 1 to the information bit register k.
  • the count value is k+1 ⁇ 2*k: the start subcode encoding logic circuit module, and the information bit register 1 ⁇ k data is sequentially sent as a line information data stream to the line code encoding operation circuit for encoding, and the line check data is performed.
  • the stream is sequentially stored in the row check register 1 to the row check register k; at the same time, the highest bit (total k bits) and the next highest bit (total k bits) of the information bit registers 1 to k are up to the lowest bit (total k bits)
  • the bit data is fetched, and the bit of the information bit register 1 is the highest bit, and the same bit of the information bit register k is the lowest bit combination, and is sent as a column information data stream to the column code encoding operation circuit for encoding, and the column check data stream is sequentially output. It is sequentially stored in the column check register 1 to the column check register k.
  • Operation 1 The line code encoding operation circuit continues to work, and the column code encoding operation circuit stops working. At the same time, the highest bit (total k bits), the next highest bit (total k bits), and the lowest bit (total k bits) of the column check registers 1 to k are sent to the line code encoding operation circuit as a line information data stream every time counting, The row verification information stream is sequentially stored in the double check register 1 to the double check register nk.
  • Operation 2 In this counting range, the output of the encoding information is synchronously performed, that is, the information bit register 1 and the row check register 1 are used as the upper bits as the upper bits, and the encoded data is merged into an n-bit encoded data to be sent to the encoding control circuit.
  • the coding control circuit inputs the coding information while the code output enable is enabled.
  • the count value is (n+k+1) ⁇ (n+2*k): At this time, the encoded information has been output (nk) group, each group of n bits, and within this counting range, continue to encode information storage. The encoded information is output in the circuit. In the counting range of (2*k+1 ⁇ 3*k), the output information is composed of the data in the information bit register and the contents of the row check register, and the count value is at (3*k+1). When ⁇ n+2*k), the output is parallel n-bit data obtained by combining the data in the column check register and the double check register.
  • the synthesis criterion is as follows: when counting to 3*k+1, the highest bit of the column check registers 1 to k, that is, the kth bit is sequentially taken out, and the kth bit of the column check register 1 is the highest bit.
  • the kth bit of the register k is the lowest bit constituting the k-bit information C1, and C1 is composed of the upper bit and the double check register 1 as n-bit information, and is output to the encoding control circuit, and the encoded information is output therefrom.
  • the next highest bit of the column check registers 1 to k that is, the k-1th bit is sequentially taken out, and the k-1th bit of the column check register 1 is the highest bit, and the column check register k
  • the k-1th bit is the lowest bit constituting the k-bit information C2
  • C2 is composed of the bit information of the upper bit and the double check register 2 to constitute n-bit information, and is output to the encoding control circuit, and the encoded information is output therefrom. And so on, until the least significant bit information of the column check register set and the bit information of the double check register set (n-k) constitute n-bit information output.
  • the encoding apparatus of the present invention requires only (n + 2 * k) clock cycles to complete a full cycle of encoding, and the output of n * n bits of data can be completed within this time.
  • FIG. 4 is a two-dimensional product code of the (8,4) extended Hamming code of the row code and the column code. Device diagram.
  • the encoded data stream is sent to the encoded information storage matrix with a 4-bit width, and the encoding matrix is an 8*8 matrix containing four 4-bit wide information registers and four 4-bit wide rows.
  • the first step the information is transformed into a 4-bit parallel data input value coded information storage circuit by the bit width conversion FIFO for data bit width conversion.
  • the code enable signal is input to the code control circuit.
  • Step 2 The counter inside the encoding control circuit starts counting after receiving the encoding enable signal, and the counting range is 1-16.
  • Each count phase has the following operations:
  • the count value is 1 to 4, and the information bit register sequentially stores the original coded information.
  • the count value is 4 to 8: the line code code is synchronized with the column code code, and the coded check information is stored in the line check registers 1 to 4, and the column check registers 1 to 4.
  • the count value is 9 to 12: the double check code is started, and the 4th bit (the highest bit) of the column check registers 1 to 4 is taken out to form 4-bit data, and encoded, and the coded information after verification is stored. Double check register 1. This is done until all four dual registers are full. At the same time, the information output of the coding matrix of the first to fourth rows is performed.
  • the information bit register is the upper 4 bits, and the row check information register is the lower 4 bits.
  • the count value is 13 to 16: the output of the column check information and the double check information is performed, and the specific output operation is as shown in FIG. 5, and the information in the information matrix in FIG. 5(a) and FIG. 5(b) Starting with I, the row check information starts with R, the column check information starts with C, and the double check information starts with D.
  • the coding matrix each data is stored as shown in the figure, and output is output in rows, and the corresponding output coding information is sequentially information of each row of the matrix.

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Abstract

一种基于扩展汉明码的二维乘积码编码装置及编码方法。该编码装置包括：信息输入缓存模块、编码信息存储电路模块、子码编码逻辑电路模块、编码控制电路模块，子码编码逻辑电路模块包括：可重构行码编码运算电路和可重构列码编码运算电路。该装置通过采用寄存器组进行信息存储，再利用编码运算电路模块进行二维乘积编码，同时通过编码控制电路模块对每个时序进行控制使得行、列编码同步进行以及在编码信息输出的同时进行双重校验位的生成，大大降低了编码延时，提高编码电路的吞吐率。

Description

一种基于扩展汉明码的二维乘积码编码装置及编码方法 技术领域
本发明涉及数字信号处理系统的设计与实现领域以及通信数据传输中的纠错编码技术领域，尤其涉及一种基于扩展汉明码的二维乘积码编码装置及编码方法。
背景技术
无线通信是把要发送的消息以某种形式进行处理，通过天线射频技术将要发送的信息可靠准确的发送给接收方。发送信息传输的可靠性、准确性一直是无线通信技术所追求的目标。纠错编码技术是为了提高无线通信系统传输可靠性、降低信道噪声的干扰而对原始发送信息进行一定数学运算的技术。纠错编码又称信道编码，在发射端根据一定的数学算法在发送的原始信息码元后加入一定量的校验码元，在接收端根据相应的解码算法利用校验码字实现对信息码字的错误发现及纠正，进而提高原始信息码元的传输准确性。在纠错编码技术中，待发送的码字为信息码字，经编码之后添加的码字为校验码字，又称冗余信息。纠错编码的目的为以最少的编码代价换取最高的纠错性能和编码增益以提高系统传输的有效性及可靠性。
乘积码是一种纠错性能优异的纠错编码。乘积码由Elias于1954年提出，它是香农信息理论提出后第一个在非零码率时可以实现无误码传输的纠错编码。由于当时的硬件水平限制了其应用。1998年Pyndiah等人在Chase算法的基础上提出了一种线性分组码的软输入软输出译码算法，并将其应用于乘积码译码中。其纠错性能优异，且算法复杂度低，为乘积码的广泛应用打下了坚实的理论基础。
乘积码以其出色的纠错性能和较低的编译码复杂度目前已在国内外吸引了众多研究学者的眼球。美国、日本以及欧洲一些国家已经将乘积码技术应用在卫星通信上。美国的AHA、ALTERA、XINLNX等公司己经开发了可灵活编程的乘积码编译码芯片，国内还没有这方面的专用芯片。乘积码技术是当前数字通信中的重要技术，引起通信界的极大关注。
乘积码可以根据子码数目分为二维、三维及多维乘积码，在实际应用中以二维乘积码为主。乘积码在编码时，按照行列编码的方式进行。因此，乘积码编码器需要一个缓存专门用来存放原始信息和编码信息，最后再进行编码输出。乘积码根据其子码的种类不同，可以分为多种类型，如子码为RS码、LDPC码及扩展汉明码等，亦或是两种码子的合成。在硬件设计时，乘积码的编码延时是一个主要得技术难题。因此，提高编码效率降低编码延时同时降低硬件消耗是需要着重研究的内容。
乘积码在编码上采用行列编码的方式，这意味着对于不同子码构成的二维乘积码，其编码要经过行列两个过程，其编码延时很大；同时，对于传统编码电路的硬件设计，在信息存储上采用读写存储器RAM进行数据信息的存储于读取，RAM分为双口和单口RAM，双口的读写可以同时进行，但是一次只能读出一个地址位的信息，因此采用RAM存储的乘积码编码器具有很大延时。当存储量较大时，采用寄存器与RAM的硬件消耗是一样的因此可以在硬件设计中采用寄存器组来实现数据的存储与读取。其在吞吐率方面有很大优势。
发明内容
发明目的：为了解决现有技术中编码延时大的问题，本发明提供了一种基于扩展汉明码的二维乘积码编码装置及编码方法，通过采用寄存器组进行数据的存储与读取，同时根据乘积码的码字参数进行寄存器的大小及个数的设定，结合相应的时序调度算法，实现了行列编码同步进行，缩短了编码延时，提高了编码电路吞吐率。
技术方案：为实现上述目的，本发明提供的基于扩展汉明码的二维乘积码编码装置，包括：信息输入缓存模块、编码控制电路模块、编码信息存储电路模块和子码编码逻辑电路模块，所述信息输入缓存模块用于利用FIFO存储器将编码原始信息进行存储并输出编码数据流至所述编码信息存储电路模块，同时输出编码使能信号至所述编码控制电路模块；所述编码控制电路模块，用于在所述编码使能信号有效后启动电路内部的计数器，并在时钟周期内利用选择器控制信号和地址控制信号对所述编码信息存储电路模块进行控制，最终输出编码信息和编码输出使能信号；所述编码信息存储电路模块，用于在所述时钟周期内对所述编码数据流进行存储，然后根据所述选择器控制信号和所述地址控制信号利用所述子码编码逻辑电路模块进行子码编码，并将信息位数据流和校验位数据流输送至所述编码控制电路模块用于输出所述编码信息。
其中，根据扩展汉明码的编码规则，确定了寄存器的大小和个数，所述编码信息存储电路模块包括：所述编码信息存储电路模块包括：四个选择器、含有k个k位的信息位寄存器的信息位寄存器组、含有k个n-k位的行校验寄存器的行校验寄存器组、含有k个n-k位的列校验寄存器的列校验寄存器组、含有n-k个n-k位的双重校验寄存器的双重校验寄存器组，每个寄存器组的输入端都连接相应选择器的输出，其中n为所述编码信息子码长度，k为所述信息位数据的长度。
其中，根据编码信息的长度以及校验位的个数进行时序调度的计算，得出所述编码控制电路模块内部计数器的计数范围为1～n+2k。
其中，所述子码编码逻辑电路模块包括：
可重构行码编码运算电路，用于对所述编码信息存储电路模块存储的行信息数据流进行扩展汉明码编码，并将编码后的行校验数据流反馈给所述编码信息存储电路模块进行存储；
可重构列码编码运算电路，用于对所述编码信息存储电路模块存储的列信息数据流进行扩展汉明码编码，并将编码后的列校验数据流反馈给所述编码信息存储电路模块进行存储；
所述可重构列码编码运算电路和所述可重构行码编码运算电路采用相同的电路结构。
相应地，本发明还提供了一种基于扩展汉明码的二维乘积码编码方法，该方法包括以下步骤：
(1)信息输入缓存模块利用FIFO存储器将编码原始信息进行存储并输出编码数据流至编码信息存储电路模块，同时输出编码使能信号至编码控制电路模块；
(2)所述编码控制电路模块在所述编码使能信号有效后启动电路内部的计数器，并在时钟周期内利用选择器控制信号和地址控制信号对所述子码编码逻辑电路模块进行控制；
(3)所述编码信息存储电路模块在所述时钟周期内对所述编码数据流进行存储，然后根据所述选择器控制信号和所述地址控制信号利用子码编码逻辑电路模块进行子码编码，并将所得到的校验位信息进行存储，以及将信息位数据流和校验位数据流输送至所述编码控制电路模块。
(4)所述编码控制电路模块根据所述信息位数据流和所述校验位数据流得到完整的编码信息并进行输出，同时输出编码输出使能信号。
其中，所述编码控制电路模块内部计数器的计数范围为1～n+2k，其中n为所述编码信息长度，k为所述信息位数据的长度。
其中，所述编码信息存储电路模块包括：选择器、信息位寄存器组、行校验寄存器组、列校验寄存器组、双重校验寄存器组，每个寄存器组分别与对应的选择器连接，所述子码编码逻辑电路模块包括可重构行码编码运算电路和可重构列码编码运算电路，步骤(3)中所述编码信息存储电路模块在所述时钟周期内进行数据存储、子码编码和数据流的输送，包括以下步骤：
计数值为1～k：依次将所述编码数据流存入编码信息存储电路模块中的信息位寄存 器组中，所述信息位寄存器组包含k个k位的信息位寄存器；
计数值为k+1～2*k：将信息位寄存器组中存储的数据作为行信息数据流依次送至所述可重构行码编码运算电路进行编码得到行校验位数据，并将所述行校验数据依次存储至行校验寄存器组中，所述行校验寄存器组包含k个n-k位的行校验寄存器；同时，将信息位寄存器组的比特数据从最高位到最低位依次取出，且信息位寄存器1的比特位为最高位，信息位寄存器k的相同比特位为最低位合并后作为列信息数据流依次送至所述可重构列码编码运算电路进行编码得到列校验位数据，并将所述列校验位数据依次存储至列校验寄存器组，所述列校验寄存器组包含k个n-k位的列校验寄存器；
计数值为2*k+1～n+k：每计数一次将所述列校验寄存器组的最高位至最低位作为行信息数据流送入所述重构行码编码运算电路，并将得到的行信息数据流依次存入双重校验寄存器组，所述双重校验寄存器组包含n-k个n-k位的双重校验寄存器；
同时，在此计数范围内，同步进行编码信息的输出，将信息位寄存器中存储的数据与对应的行校验寄存器中存储的数据，前者作为高位后者作为低位，合并为一个n比特的编码数据送至所述编码控制电路模块，所述编码控制电路模块输出编码信息，同时编码输出使能有效；
计数值为n+k+1～n+2*k：在计数范围n+k+1～2*k内，继续将所述编码信息存储电路模块中的编码信息输出；在计数范围2*k+1～3*k内，输出的编码信息由信息位寄存器中的数据与行校验寄存器中的数据合并而成的并行n比特数据；在计数范围3*k+1～n+2*k内，输出的编码信息由列校验寄存器和双重校验寄存器中的数据合并而成的并行n比特数据。
有益效果：本发明的基于扩展汉明码的二维乘积码编码装置和编码方法，采用寄存器组代替RAM存储器进行数据的存储和读取，避免了因RAM进行数据的存储与读取时所带来的编码延时；同时，根据乘积码的码字参数进行寄存器的大小及个数的设定，并结合相应的时序调度算法，实现了行列编码同步进行，缩短了编码延时，并且实现了双重编码和编码输出的同步，进一步缩短了整个编码控制过程的延时，提高了编码电路吞吐率。
附图说明
图1为无线通信系统的框架示意图；
图2为二维乘积码的编码矩阵示意图；
图3为本发明的基于扩展汉明码的二维乘积码编码装置图；
图4为实施例中基于(8,4)扩展汉明码的二维乘积码编码装置图；
图5为实施例中基于(8,4)扩展汉明码的乘积码编码信息存储矩阵及编码输出时序图。
具体实施方式
下面结合实施例对本发明作更进一步的说明。
图1中，无线通信系统的发射端对信源的原始信号先进行信道编码，再进行调制映射，并通过数模转换，最后利用天线发送射频信号，接收端的天线接收射频信号，随后进行模数转换和解调映射，最后进行相应地信道解码最终得到发射信号信息，本发明中仅涉及信道编码部分，即图中的乘积码编码，采用扩展汉明码作为子码进行编码。
对于子码均为同一扩展汉明码的二维乘积码，在编码时，假设其子码码字参数为(n,k,d)，其中n＝2m，m为正整数，k＝n-1-m，表示信息比特位数，d＝4表示最小码子距离，为固定值，实际应用中m多大于2。由于扩展汉明码也为线性分组码的一种，因此其编码可以由生成矩阵完成，先将待编码的原始信息进行分组，每组k bit，记为S，则S编码之后的信息N＝S*G，G为生成矩阵，N为含有校验位的n比特编码信息。
子码编码完毕后，由原来的k bit长度变为n比特长度，在组成编码码字时，k bit原始信息放在前面，后面是(n-k)bit的校验信息。因此，对于由子码参数为(n,k,d)的扩展汉明码构成的二维乘积码，其存储矩阵的大小为n*n。
图2中，矩阵的行代表二维乘积码的行码，列代表列码，矩阵主要包括四大部分：信息矩阵，行校验矩阵，列校验矩阵和双重校验矩阵，分别对应相应的数据信息。
乘积码在编码时，可以按照先行后列也可以按照先列后行的编码方式。本发明中采用行列信息位同步编码，然后进行校验位编码的方式，可以缩短行列其中之一的编码延时，进而提高编码效率。
图3中，基于扩展汉明码的二维乘积码编码装置，包括：信息输入缓存模块、编码控制电路模块、编码信息存储电路模块和子码编码逻辑电路模块，子码编码逻辑电路模块内部主要包括可重构行码编码运算电路和可重构列码编码运算电路。
在进行编码之前，编码原始信息首先送入信息输入缓存模块，经过此电路将编码原始信息转换为编码数据流送入编码信息存储电路。编码原始信息的位宽可能与乘积码的子码参数不一样，所以需要利用缓存将其转换为与乘积码子码参数，即子码信息位长度相一致的位宽数据流。信息输入缓存由一个可变位宽FIFO构成，其大小可以由编码原始信息的总量而定。在所有的编码原始信息存储完毕之后，信息输入缓存按k bit位宽，输 出编码数据流至编码信息存储电路模块，同时输出编码使能信号至编码控制电路模块。
编码控制电路模块内部有一个计数器，在编码使能信号有效后启动，其计数范围为1～(n+2k)，(n+2k)个时钟周期循环计数一次，每循环计数一次，代表当前编码和输出完成一次。编码输出完毕后，计数器为0，即可进入下一次的信息输入和编码。
子码编码逻辑电路模块内部主要包括可重构行码编码运算电路和可重构列码编码运算电路，由于行码列码采用同一扩展汉明码，因此二者电路结构相同，均为同一扩展汉明码的编码运算电路，该电路可完成码长小于n的任意扩展汉明码的编码。
编码信息存储电路模块包括以下部分：(1)四个选择器：选择器1，选择器2，选择器3，选择器4；(2)k个k位的信息位寄存器，即信息位寄存器组；(3)k个(n-k)位的行校验寄存器，即行校验寄存器组；(4)k个(n-k)位的列校验寄存器，即列校验寄存器组；(5)(n-k)个(n-k)位的双重校验寄存器，即双重校验寄存器组。每个寄存器的输入端都连接相应选择器的输出。编码数据流先送入选择器1，选择器1根据编码控制电路的选择器1控制信号和地址控制信号将编码数据流存入相应信息位寄存器。在所有的信息位数据存储完毕，亦即信息位寄存器组存满之后，开始进行校验位的编码。编码完毕之后，编码控制电路从编码信息存储电路中取出整个码字按行输出编码完整信息。
整个装置的时序调度流程如下：
第1步：编码原始信息输入位宽变换FIFO，FIFO存储完毕之后，按照码字参数k比特进行编码数据流的并行输出，至编码信息存储电路模块，同时输出编码使能信号至编码控制电路模块。
第2步：编码使能信号有效后，编码控制电路启动其内部的计数器，计数范围为1～(n+2*k)，进行编码阶段控制，编码信息存储电路模块根据编码控制器的选择器控制信号和地址控制信号进行相应数据的存储，并输出编码之后的信息，其具体的时序调度控制操作如下：
(1)计数值为1～k：依次将编码数据流存入信息位寄存器1至信息位寄存器k。
(2)计数值为k+1～2*k：启动子码编码逻辑电路模块，将信息位寄存器1～k数据作为行信息数据流依次送至行码编码运算电路进行编码，行校验数据流依次存储至行校验寄存器1～行校验寄存器k；同时，将信息位寄存器1～k的最高位(共k比特)、次高位(共k比特)直至最低位(共k比特)的比特数据取出，且信息位寄存器1的比特位为最高位，信息位寄存器k的相同比特位为最低位合并，作为列信息数据流依次送至列码编码运算电路进行编码，列校验数据流依次存储至列校验寄存器1～列校验寄存器k。
(3)计数值为2*k+1～(n+k)：在此期间有两个操作同时进行。
操作一：行码编码运算电路继续工作，列码编码运算电路停止工作。同时，每计数一次将列校验寄存器1～k的最高位(共k比特)、次高位(共k比特)直至最低位(共k比特)作为行信息数据流送入行码编码运算电路，并将行校验信息流依次存入双重校验寄存器1～双重校验寄存器n-k。
操作二：在此计数范围内，同步进行编码信息的输出，即将信息位寄存器1与行校验寄存器1，前者作为高位后者作为低位，合并为一个n比特的编码数据送至编码控制电路，编码控制电路输编码信息，同时编码输出使能有效。
(4)计数值为(n+k+1)～(n+2*k)：此时，编码信息已输出(n-k)组，每组n比特，在此计数范围内，继续讲编码信息存储电路中的编码信息输出。在计数范围为(2*k+1～3*k)内，输出的信息为由信息位寄存器中的数据与行校验寄存器中的内容组合而成，而计数值在(3*k+1～n+2*k)时，输出的则为由列校验寄存器和双重校验寄存器中的数据合并的而成的并行n比特数据。其合成准则是这样的：计数到3*k+1时，将列校验寄存器1～k的最高位即第k位依次取出，以列校验寄存器1的第k位为最高位，列校验寄存器k的第k位为最低位组成k比特信息C1，C1作为高位与双重校验寄存器1组成n比特信息，输出至编码控制电路，并由其输出编码信息。计数到3*k+2时，将列校验寄存器1～k的次高位即第k-1位依次取出，以列校验寄存器1的第k-1位为最高位，列校验寄存器k的第k-1位为最低位组成k比特信息C2，C2作为高位与双重校验寄存器2的比特信息组成n比特信息，输出至编码控制电路，并由其输出编码信息。依次类推，直至列校验寄存器组的最低位比特信息与双重校验寄存器组(n-k)的比特信息组成n比特信息输出。
以上即为编码装置的工作流程，编码运算电路在计数值为(2*k～n+2*k-1)之间时，编码输出使能有效，其余时间为无效。
由上可以看出，本发明的编码装置完成一整个周期的编码只需要(n+2*k)个时钟周期，在此时间之内即可完成n*n比特的数据的输出。
本实施例中，以编码信息的子码码长n＝8，信息位长度k＝4为例，图4为行码与列码均为(8,4)扩展汉明码的二维乘积码编码装置图。
在此装置中，编码数据流以4比特位宽送入编码信息存储矩阵，编码矩阵为8*8的矩阵，其中包含4个4比特位宽的信息寄存器，4个4比特位宽的行校验寄存器，4个4比特位宽的列校验寄存器，4个4比特位宽的双重校验寄存器，寄存器中存储矩阵元素 信息。
在编码开始时，信息矩阵存放编码信息，耗时k＝4个周期；然后再经过k＝4个周期，行校验矩阵和列校验矩阵中都存满了校验信息；在进行双重校验编码时，同步进行行编码信息的输出，具体为首先输出第一行的信息，即由信息位寄存器1与行校验寄存器1组成一行，进行输出，在n-k＝4个时钟周期之后，输出了4行的编码信息，同时双重校验信息编码完毕；在接下来的k＝4个时钟周期内，继续进行行编码信息的传输。
此编码装置在整个时序调度周期内的具体流程如下：
第一步：将信息经过位宽变换FIFO进行数据比特位宽的变换，转化为4比特并行数据输入值编码信息存储电路。同时向编码控制电路输入编码使能信号。
第二步：编码控制电路内部的计数器在收到编码使能信号之后开始计数，计数范围为1～16。每一个计数阶段有以下操作：
(1)计数值为1～4，信息位寄存器依次存储原始编码信息。
(2)计数值为4～8：行码编码与列码编码同步进行，并将编码之后的校验信息存入至行校验寄存器1～4，列校验寄存器1～4。
(3)计数值为9～12：双重校验编码开始，将列校验寄存器1～4的第4位(最高位)取出组成4比特数据，进行编码，编码之后的校验信息存入至双重校验寄存器1中。如此进行，直至4个双重寄存器全部存满。同时进行第1～4行编码矩阵的信息输出。信息位寄存器为高4位，行校验信息寄存器为低4位输出。
(4)计数值为13～16：进行列校验信息与双重校验信息的输出，具体输出操作如图5所示，图5(a)和图5(b)中，信息矩阵中的信息以I为开头，行校验信息以R为开头，列校验信息以C为开头，双重校验信息以D为开头。在编码矩阵中，各数据存放如该图所示，输出时按行输出，则对应的输出编码信息依次为矩阵每一行的信息。
如此，经过16个时钟周期，编码与编码输出全部完成，共输出64比特信息。

Claims (7)

  1. 一种基于扩展汉明码的二维乘积码编码装置，其特征在于，该装置包括：信息输入缓存模块、编码控制电路模块、编码信息存储电路模块和子码编码逻辑电路模块，所述信息输入缓存模块用于利用FIFO存储器将编码原始信息进行存储并输出编码数据流至所述编码信息存储电路模块，同时输出编码使能信号至所述编码控制电路模块；所述编码控制电路模块，用于在所述编码使能信号有效后启动电路内部的计数器，并在时钟周期内利用选择器控制信号和地址控制信号对所述编码信息存储电路模块进行控制，最终输出编码信息和编码输出使能信号；所述编码信息存储电路模块，用于在所述时钟周期内对所述编码数据流进行存储，然后根据所述选择器控制信号和所述地址控制信号利用所述子码编码逻辑电路模块进行子码编码，并将信息位数据流和校验位数据流输送至所述编码控制电路模块用于输出所述编码信息。
  2. 根据权利要求1所述的基于扩展汉明码的二维乘积码编码装置，其特征在于，所述编码信息存储电路模块包括：四个选择器、含有k个k位的信息位寄存器的信息位寄存器组、含有k个n-k位的行校验寄存器的行校验寄存器组、含有k个n-k位的列校验寄存器的列校验寄存器组、含有n-k个n-k位的双重校验寄存器的双重校验寄存器组，每个寄存器组的输入端都连接相应选择器的输出，其中n为所述编码信息子码长度，k为所述信息位数据的长度。
  3. 根据权利要求2所述的基于扩展汉明码的二维乘积码编码装置，其特征在于，所述编码控制电路模块内部计数器的计数范围为1～n+2k。
  4. 根据权利要求1所述的基于扩展汉明码的二维乘积码编码装置，其特征在于，所述子码编码逻辑电路模块包括：
    可重构行码编码运算电路，用于对所述编码信息存储电路模块存储的行信息数据流进行扩展汉明码编码，并将编码后的行校验数据流反馈给所述编码信息存储电路模块进行存储；
    可重构列码编码运算电路，用于对所述编码信息存储电路模块存储的列信息数据流进行扩展汉明码编码，并将编码后的列校验数据流反馈给所述编码信息存储电路模块进行存储；
    所述可重构列码编码运算电路和所述可重构行码编码运算电路采用相同的电路结构。
  5. 一种基于扩展汉明码的二维乘积码编码方法，其特征在于，该方法包括以下步 骤：
    (1)信息输入缓存模块利用FIFO存储器将编码原始信息进行存储并输出编码数据流至编码信息存储电路模块，同时输出编码使能信号至编码控制电路模块；
    (2)所述编码控制电路模块在所述编码使能信号有效后启动电路内部的计数器，并在时钟周期内利用选择器控制信号和地址控制信号对所述子码编码逻辑电路模块进行控制；
    (3)所述编码信息存储电路模块在所述时钟周期内对所述编码数据流进行存储，然后根据所述选择器控制信号和所述地址控制信号利用子码编码逻辑电路模块进行子码编码，并将所得到的校验位信息进行存储，以及将信息位数据流和校验位数据流输送至所述编码控制电路模块。
    (4)所述编码控制电路模块根据所述信息位数据流和所述校验位数据流得到完整的编码信息并进行输出，同时输出编码输出使能信号。
  6. 根据权利要求5所述的基于扩展汉明码的二维乘积码编码方法，其特征在于，所述编码控制电路模块内部计数器的计数范围为1～n+2k，其中n为所述编码信息子码长度，k为所述信息位数据的长度。
  7. 根据权利要求6所述的基于扩展汉明码的二维乘积码编码方法，其特征在于，所述编码信息存储电路模块包括：选择器、信息位寄存器组、行校验寄存器组、列校验寄存器组、双重校验寄存器组，每个寄存器组分别与对应的选择器连接，所述子码编码逻辑电路模块包括可重构行码编码运算电路和可重构列码编码运算电路，步骤(3)中所述编码信息存储电路模块在所述时钟周期内进行数据存储、子码编码和数据流的输送，包括以下步骤：
    计数值为1～k：依次将所述编码数据流存入编码信息存储电路模块中的信息位寄存器组中，所述信息位寄存器组包含k个k位的信息位寄存器；
    计数值为k+1～2*k：将信息位寄存器组中存储的数据作为行信息数据流依次送至所述可重构行码编码运算电路进行编码得到行校验位数据，并将所述行校验数据依次存储至行校验寄存器组中，所述行校验寄存器组包含k个n-k位的行校验寄存器；同时，将信息位寄存器组的比特数据从最高位到最低位依次取出，且信息位寄存器1的比特位为最高位，信息位寄存器k的相同比特位为最低位合并后作为列信息数据流依次送至所述可重构列码编码运算电路进行编码得到列校验位数据，并将所述列校验位数据依次存储至列校验寄存器组，所述列校验寄存器组包含k个n-k位的列校验寄存器；
    计数值为2*k+1～n+k：每计数一次将所述列校验寄存器组的最高位至最低位作为行信 息数据流送入所述重构行码编码运算电路，并将得到的行信息数据流依次存入双重校验寄存器组，所述双重校验寄存器组包含n-k个n-k位的双重校验寄存器；
    同时，在此计数范围内，同步进行编码信息的输出，将信息位寄存器中存储的数据与对应的行校验寄存器中存储的数据，前者作为高位后者作为低位，合并为一个n比特的编码数据送至所述编码控制电路模块，所述编码控制电路模块输出编码信息，同时编码输出使能有效；
    计数值为n+k+1～n+2*k：在计数范围n+k+1～2*k内，继续将所述编码信息存储电路模块中的编码信息输出；在计数范围2*k+1～3*k内，输出的编码信息由信息位寄存器中的数据与行校验寄存器中的数据合并而成的并行n比特数据；在计数范围3*k+1～n+2*k内，输出的编码信息由列校验寄存器和双重校验寄存器中的数据合并而成的并行n比特数据。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111211793A (zh) * 2020-02-10 2020-05-29 成都烨软科技有限公司 一种基于汉明码并行tpc编码方法及其装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104601180B (zh) * 2015-02-11 2017-05-24 东南大学 一种基于扩展汉明码的二维乘积码编码装置及编码方法
CN107612561B (zh) * 2017-09-30 2021-02-02 武汉虹信科技发展有限责任公司 一种编码、译码方法及装置
CN110213019A (zh) * 2019-05-28 2019-09-06 湖北三江航天险峰电子信息有限公司 一种pcm信号编码系统及方法
CN113055027B (zh) * 2021-03-18 2022-05-13 北京得瑞领新科技有限公司 可变位宽的ldpc编码方法、编码器、ssd及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217284A (zh) * 2008-01-11 2008-07-09 北京大学 一种ldpc级联码的编码方法、译码方法及其译码器
CN101848002A (zh) * 2010-06-18 2010-09-29 上海交通大学 Rs级联网格调制码的迭代译码装置及其译码方法
US20100328528A1 (en) * 2009-06-30 2010-12-30 Nokia Corporation Transmission capacity probing using adaptive redundancy adjustment
CN104601180A (zh) * 2015-02-11 2015-05-06 东南大学 一种基于扩展汉明码的二维乘积码编码装置及编码方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217284A (zh) * 2008-01-11 2008-07-09 北京大学 一种ldpc级联码的编码方法、译码方法及其译码器
US20100328528A1 (en) * 2009-06-30 2010-12-30 Nokia Corporation Transmission capacity probing using adaptive redundancy adjustment
CN101848002A (zh) * 2010-06-18 2010-09-29 上海交通大学 Rs级联网格调制码的迭代译码装置及其译码方法
CN104601180A (zh) * 2015-02-11 2015-05-06 东南大学 一种基于扩展汉明码的二维乘积码编码装置及编码方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111211793A (zh) * 2020-02-10 2020-05-29 成都烨软科技有限公司 一种基于汉明码并行tpc编码方法及其装置
CN111211793B (zh) * 2020-02-10 2023-08-04 成都烨软科技有限公司 一种基于汉明码并行tpc编码方法

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