WO2016123917A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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WO2016123917A1
WO2016123917A1 PCT/CN2015/084429 CN2015084429W WO2016123917A1 WO 2016123917 A1 WO2016123917 A1 WO 2016123917A1 CN 2015084429 W CN2015084429 W CN 2015084429W WO 2016123917 A1 WO2016123917 A1 WO 2016123917A1
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layer
auxiliary electrode
etch barrier
array substrate
barrier layer
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PCT/CN2015/084429
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English (en)
French (fr)
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齐永莲
张锋
王东方
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京东方科技集团股份有限公司
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Priority to US14/906,260 priority Critical patent/US10193100B2/en
Publication of WO2016123917A1 publication Critical patent/WO2016123917A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/818—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/321—Inverted OLED, i.e. having cathode between substrate and anode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a display device, and an array substrate manufacturing method.
  • the transmissive structure and the upper illuminating component of the display panel of the large-sized inverted OLED organic light-emitting diode device
  • light is required to be emitted from the cathode, so that the cathode is made thin, and the work function is not considered, but when the cathode is When thin, there is a problem that the circuit is broken or the metal is easily oxidized, making it difficult for the cathode conductivity to meet the electrical conductivity requirement.
  • the OLED structure is driven by current, when the external circuit is too long or too thin, a large voltage gradient will be formed between the OLED structure and the external circuit, so that the voltage actually applied to the OLED component is lowered, resulting in a decrease in panel illumination intensity. .
  • the electric resistance of the ITO for forming the anode is too large, external power consumption is liable to occur. Therefore, in the prior art, the voltage gradient is reduced by increasing the auxiliary electrode, the light-emitting line is increased, and the driving voltage is reduced.
  • the material of the auxiliary electrode may be Cr, Al, Cr/Al/Cr, Mo/Al/Mo or the like.
  • the technical problem to be solved by the present invention is how to simplify the fabrication of the auxiliary electrode in the inverted OLED device to simplify the fabrication process of the OLED device and reduce the manufacturing cost.
  • the present invention provides an array substrate comprising: a thin film transistor, an auxiliary electrode disposed in the same layer as the active layer of the thin film transistor, and a transparent cathode electrically connected to the auxiliary electrode, wherein
  • the active layer is an oxide semiconductor
  • the auxiliary electrode is an electrical conductor formed by modifying the oxide semiconductor.
  • the array substrate may further include: a substrate; a gate disposed on the substrate; and a gate insulating layer disposed on the gate, wherein the active layer is disposed on the gate insulating layer .
  • the array substrate further includes:
  • a first etch barrier layer disposed on the auxiliary electrode, wherein a via hole is disposed in the first etch barrier layer, and the transparent cathode passes through the first etch barrier layer A hole is electrically connected to the auxiliary electrode.
  • the array substrate further includes:
  • a second etch barrier layer disposed on the active layer, and a source and a drain disposed on the second etch barrier layer, wherein the source and the drain respectively pass through the second A via in the etch stop layer is electrically connected to the active layer.
  • the array substrate further includes:
  • a passivation layer disposed on the gate insulating layer and covering the first etch barrier layer, wherein a pass hole is disposed in the passivation layer, and the transparent cathode is blocked by the first etch A via in the layer and a via in the passivation layer are electrically connected to the auxiliary electrode.
  • the array substrate further includes:
  • a passivation layer disposed on the gate insulating layer and covering the source, the drain, and the first etch barrier layer, wherein the passivation layer is provided with a via hole, and the transparent cathode passes through
  • the via holes in the first etch barrier layer and the via holes in the passivation layer are electrically connected to the auxiliary electrode.
  • the array substrate further includes:
  • a passivation layer disposed on the gate insulating layer and covering the source, the drain, the first etch barrier layer and the second etch barrier layer, wherein the passivation layer is provided with a via hole
  • the transparent cathode is electrically connected to the auxiliary electrode through a via hole in the first etch barrier layer and a via hole in the passivation layer.
  • the auxiliary electrode is an electrical conductor formed by plasma processing or ion implantation of the oxide semiconductor.
  • the array substrate may further include: an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a reflective anode which are sequentially disposed on the transparent cathode.
  • the invention provides a display device comprising any of the array substrates described above.
  • the present invention provides a method for fabricating an array substrate, comprising:
  • a transparent cathode electrically connected to the auxiliary electrode is formed.
  • the method may further include:
  • the oxide semiconductor layer is formed on the gate insulating layer.
  • the method may further include:
  • a first etch barrier layer is formed on the auxiliary electrode pattern.
  • modifying the auxiliary electrode pattern may include modifying the auxiliary electrode pattern via the first etch barrier layer.
  • the auxiliary electrode pattern may be modified after the auxiliary electrode pattern is formed and before the first etch barrier layer is formed.
  • the method may further comprise:
  • a source and a drain are formed on the second etch barrier layer, wherein the source and the drain are electrically connected to the active layer through via holes in the second etch barrier layer, respectively.
  • the method may further comprise:
  • the transparent cathode is electrically connected to the auxiliary electrode through a via hole in the first etch barrier layer and a via hole in the passivation layer when the transparent cathode is formed.
  • the method may further comprise:
  • the transparent cathode is electrically connected to the auxiliary electrode through a via hole in the first etch barrier layer and a via hole in the passivation layer when the transparent cathode is formed.
  • the method may further comprise:
  • the transparent cathode is electrically connected to the auxiliary electrode through a via hole in the first etch barrier layer and a via hole in the passivation layer when the transparent cathode is formed.
  • the method may further include: annealing the auxiliary electrode.
  • the modifying treatment is plasma treatment or ion implantation.
  • the method may further include sequentially forming an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a reflective anode on the transparent cathode.
  • the active layer and the auxiliary electrode in the same layer, the active layer and the auxiliary electrode pattern can be formed by the same etching process, and the process of forming the auxiliary electrode is not separately provided, thereby reducing the overall of the array substrate. Process time saves production costs.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic view showing a method of fabricating an array substrate according to an embodiment of the present invention
  • FIG. 3 illustrates a schematic view of forming a first etch stop layer and a second etch stop layer, in accordance with one embodiment of the present invention
  • FIG. 4 illustrates a schematic view of forming via holes in a first etch barrier layer and a second etch barrier layer, in accordance with one embodiment of the present invention
  • FIG. 5 is a schematic view showing formation of a source and a drain on a second etch barrier layer according to an embodiment of the present invention
  • Figure 6 shows a schematic diagram of forming a passivation layer in accordance with one embodiment of the present invention.
  • an array substrate includes: a thin film transistor (located at the lower left portion of FIG. 1), an auxiliary electrode 5 disposed in the same layer as the active layer 4 of the thin film transistor, and an auxiliary electrode 5
  • the transparent cathode 6 is connected, wherein the active layer 4 is an oxide semiconductor, and the auxiliary electrode 5 is a modified oxide semiconductor.
  • modification process refers to any process capable of converting an oxide semiconductor into an electrical conductor.
  • the modification treatment includes, but is not limited to, plasma treatment, ion implantation, and the like.
  • the array substrate further includes: a substrate 1 , a gate 2 disposed on the substrate 1 , a gate insulating layer 3 disposed on the gate 2 , wherein the active layer 4 is disposed on the gate insulating layer 3 .
  • an oxide semiconductor layer over the gate insulating layer is etched by an etching process to form an active layer and an auxiliary electrode pattern, and then the auxiliary electrode pattern is formed.
  • a modification treatment such as plasma treatment or ion implantation is performed to increase the concentration of carriers in the oxide semiconductor layer so that the auxiliary electrode pattern has conductive characteristics to form an auxiliary electrode.
  • the oxide semiconductor layer can be processed by an etching process to simultaneously form the active layer and the auxiliary electrode without separately setting a process.
  • the formation of the auxiliary electrode simplifies the fabrication process of the array substrate and saves manufacturing costs.
  • the array substrate may further include: a first etch barrier layer 15 disposed on the auxiliary electrode 5, wherein the first etch barrier layer 15 is disposed
  • the hole, transparent cathode 6 is electrically connected to the auxiliary electrode 5 through a via hole in the first etch barrier layer 15. Since the first etch barrier layer is disposed on the auxiliary electrode, the auxiliary electrode pattern needs to be modified to have conductivity through the first etch barrier layer on the auxiliary electrode pattern when the array substrate is fabricated.
  • auxiliary electrode As an auxiliary electrode.
  • the array substrate may further include a second etch barrier layer 13 disposed on the active layer 4, and a source 11 and a drain 12 disposed on the second etch barrier layer 13, wherein the source 11 and The drain electrodes 12 are electrically connected to the active layer 4 through via holes in the second etch barrier layer 13, respectively.
  • the second etch stop layer can prevent the auxiliary electrode from being damaged when forming the source and drain electrodes.
  • the array substrate may further include: a passivation layer 14 disposed on the gate insulating layer 3 and covering the first etch barrier layer 15, wherein the passivation layer 14 is provided with a via hole, and the transparent cathode 6 passes through the The via holes in the etch stop layer 15 and the via holes in the passivation layer 14 are electrically connected to the auxiliary electrode 5.
  • the array substrate further includes: a passivation layer 14 disposed on the gate insulating layer 3 and covering the source electrode 11, the drain electrode 12 and the first etch barrier layer 15, wherein the passivation layer 14 is disposed
  • the via hole, the transparent cathode 6 is electrically connected to the auxiliary electrode 5 through a via hole in the first etch barrier layer 15 and a via hole in the passivation layer 14.
  • the array substrate may further include: a passivation layer 14 disposed on the gate insulating layer 3 and covering the first etch barrier layer 15, the source electrode 11, the drain electrode 12 and the second etch barrier layer 13, wherein A via hole is disposed in the passivation layer 14, and the transparent cathode 6 is electrically connected to the auxiliary electrode 5 through a via hole in the first etch barrier layer 15 and a via hole in the passivation layer 14.
  • the passivation layer 14 can avoid intrusion of external impurities.
  • the array substrate may further include: an electron injection layer, an electron transport layer (not shown), a light-emitting layer 7, a hole transport layer 8, and a hole which are sequentially disposed on the transparent cathode 6.
  • the layer 9 and the reflective anode 10 are injected.
  • the structure in this embodiment is mainly described for the array substrate in the inverted OLED, but the structure of the auxiliary electrode and the active layer in the present invention is also applicable to other array substrates having the auxiliary electrodes.
  • the present invention also provides a display device comprising the array substrate of any of the above.
  • the display device may include, for example, a color filter substrate in addition to the array substrate in the embodiment.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • a method for fabricating an array substrate according to an embodiment of the present invention includes:
  • Step S1 forming an oxide semiconductor layer
  • Step S2 performing a patterning process on the oxide semiconductor layer to form the active layer 4 of the thin film transistor, and forming an auxiliary electrode pattern in a predetermined region;
  • Step S3 modifying the auxiliary electrode pattern to form the auxiliary electrode 5;
  • step S4 a transparent cathode 6 electrically connected to the auxiliary electrode 5 is formed.
  • the active semiconductor layer 4 and the auxiliary electrode 5 can be separately formed by processing the oxide semiconductor layer by an etching process, and the auxiliary electrode 5 is not separately formed by another process, thereby simplifying the fabrication of the array substrate. Process, saving production costs.
  • the method may further include:
  • An oxide semiconductor layer is formed on the gate insulating layer 3.
  • the method may further include:
  • the modification of the electrode pattern may include:
  • the auxiliary electrode pattern is subjected to a modification treatment such as plasma treatment or ion implantation through the first etch barrier layer 15, or the auxiliary electrode pattern is subjected to plasma such as plasma after forming the auxiliary electrode pattern and before forming the first etch barrier layer 15. Modification of body treatment or ion implantation.
  • the order of modifying the auxiliary electrode pattern can be set as needed.
  • the auxiliary electrode pattern may be directly modified after the auxiliary electrode pattern is formed.
  • the auxiliary electrode pattern may be modified by the first etch barrier layer 15 after the first etch barrier layer 15 is formed.
  • the modification treatment may be, for example, a plasma treatment, a plasma implantation process, or the like, thereby reducing the resistance of the auxiliary electrode pattern to become an electrical conductor.
  • the method may further include: forming a second etch barrier layer 13 on the active layer 4 when the first etch barrier layer 15 is formed, that is, the two are formed by the same patterning process. .
  • an etch barrier covering the active layer 4 and the auxiliary electrode 5 may be formed on the gate insulating layer 3, and then the etch barrier other than the active layer 4 and the auxiliary electrode 5 is etched away. Etching the barrier layer, the second etch barrier layer 13 over the active layer 4 and the etch stop layer 15 over the auxiliary electrode 5 can prevent the active layer 4 and the auxiliary when forming the source 11 and the drain 12 The electrode 5 is etched.
  • the method may further include:
  • a via hole is formed in the second etch barrier layer 13, a source electrode 11 and a drain electrode 12 are formed on the second etch barrier layer 13, and the source electrode 11 and the drain electrode 12 are respectively passed through the second etch barrier layer 13.
  • the via is electrically connected to the active layer 4.
  • the method may further include: forming a passivation layer 14 on the gate insulating layer 3, covering the passivation layer 14 with the source first etch barrier layer 15, and forming a via hole in the passivation layer 14.
  • the transparent cathode 5 is formed, the transparent cathode 5 is electrically connected to the auxiliary electrode 5 through the via holes in the first etch barrier layer 15 and the via holes in the passivation layer 14, see FIG.
  • the method may further include: forming a passivation layer 14 on the gate insulating layer 3, so that the passivation layer 14 covers the source electrode 11, the drain electrode 12, and the first etch barrier layer 15, in passivation A via is formed in layer 14.
  • the transparent cathode 5 is formed, the transparent cathode 5 is electrically connected to the auxiliary electrode 5 through the via holes in the first etch barrier layer 15 and the via holes in the passivation layer 14, see FIG.
  • the method may further include: forming a passivation layer 14 on the gate insulating layer 3.
  • the passivation layer 14 covers the source electrode 11, the drain electrode 12, and the second etch barrier layer 13 in addition to the first etch barrier layer 15, thereby preventing intrusion of external impurities.
  • a via is then formed in the passivation layer 14 at a location corresponding to the via in the first etch stop layer 15 such that the transparent cathode can pass through the via in the passivation layer 14 and the first etch stop layer 15
  • the holes are electrically connected to the auxiliary electrode 5.
  • the method further comprises: annealing the auxiliary electrode 5.
  • annealing residual stress can be eliminated, the size can be stabilized, and the tendency of deformation and cracking can be reduced; the grains can be refined, the structure can be adjusted, and the tissue defects can be eliminated.
  • the method further comprises: sequentially forming an electron injection layer, an electron transport layer, a light-emitting layer 7, a hole transport layer 8, a hole injection layer 9, and a reflective anode 10 on the transparent cathode 6, and the formed array structure can be seen in the figure. 1.
  • the fabrication of the auxiliary electrode in the inverted OLED requires a separate process, which increases the number of processes and the manufacturing cost.
  • the active layer and the auxiliary electrode can be simultaneously formed by the same etching process, and the process of separately forming the auxiliary electrode is not required, thereby reducing the overall process time of the array substrate and saving the manufacturing cost.
  • the above array substrate and the manufacturing method thereof are described by taking an OLED array substrate as an example. Therefore, the array substrate of the present invention and the manufacturing method thereof are suitable for implementing the OLED array substrate and the manufacturing method thereof, but the present invention It is not limited to the OLED array substrate, and regardless of the type of the array substrate, an array substrate substantially the same as or similar to the technical solution described in any of the claims of the present invention and a method for fabricating the same are considered to be within the scope of protection of the present invention.

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Abstract

一种阵列基板及其制作方法，该阵列基板包括：薄膜晶体管，与薄膜晶体管的有源层（4）同层设置的辅助电极（5），以及与辅助电极（5）电连接的透明阴极（6），其中所述有源层（4）为氧化物半导体，所述辅助电极（5）为经等离子体处理过的氧化物半导体。根据本发明的技术方案，将有源层（4）和辅助电极（5）设置于同一层，因此可通过同一道刻蚀工艺形成有源层（4）和辅助电极（5），无需增设形成辅助电极的工艺，从而减少阵列基板的整体工艺时间，节约了制作成本。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明涉及显示技术领域，具体而言，涉及一种阵列基板、显示装置和一种阵列基板制作方法。
背景技术
在制备大尺寸倒置型OLED(有机发光二极管器件)显示面板的穿透式结构和上发光组件结构中，需要光从阴极发出，因此将阴极做薄，就可以不用考虑功函数，但是当阴极很薄的时候，会产生断路或者金属容易氧化的问题，使得阴极导电度难以满足导电需求。另外，因为OLED结构为电流驱动，当外部线路过长或者过细时，OLED结构与外部电路之间将会形成较大的电压梯度，使得实际施加在OLED组件上的电压下降，导致面板发光强度降低。同时，因为用于形成阳极的ITO的电阻过大，容易造成外部功率消耗。因此已知技术中通过增加辅助电极的方式来降低电压梯度，增加发光线路，减少驱动电压。具体地，辅助电极的材料可以采用Cr、Al、Cr/Al/Cr、Mo/Al/Mo等。
但是在制备辅助电极时，需要增加一道溅射金属的工艺，同时还需要进行刻蚀，增加了OLED制备的成本。
发明内容
本发明所要解决的技术问题是，如何简化倒置式OLED器件中辅助电极的制作，以简化OLED器件的制作工艺，降低制作成本。
为此目的，本发明的实施例中采用了下述技术方案。
在第一方面，本发明提出了一种阵列基板，包括：薄膜晶体管，与所述薄膜晶体管的有源层同层设置的辅助电极，以及与所述辅助电极电连接的透明阴极，其中所述有源层为氧化物半导体，所述辅助电极为所述氧化物半导体经过改性处理而形成的电导体。
该阵列基板还可以包括：基底；设置于所述基底之上的栅极；以及设置于所述栅极之上的栅极绝缘层，其中所述有源层设置在所述栅极绝缘层上。
优选地，该阵列基板还可以包括：
设置在所述辅助电极上的第一刻蚀阻挡层，其中，所述第一刻蚀阻挡层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过 孔与所述辅助电极电连接。
优选地，该阵列基板还可以包括：
设置在所述有源层上的第二刻蚀阻挡层，以及设置在所述第二刻蚀阻挡层上的源极和漏极，其中，所述源极和漏极分别通过所述第二刻蚀阻挡层中的过孔与所述有源层电连接。
优选地，该阵列基板还可以包括：
设置在所述栅极绝缘层上，且覆盖所述第一刻蚀阻挡层的钝化层，其中，所述钝化层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
优选地，该阵列基板还可以包括：
设置在所述栅极绝缘层上，且覆盖所述源极、漏极和第一刻蚀阻挡层的钝化层，其中，所述钝化层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
优选地，该阵列基板还可以包括：
设置在所述栅极绝缘层上，且覆盖所述源极、漏极、第一刻蚀阻挡层和第二刻蚀阻挡层的钝化层，其中，所述钝化层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
优选地，在该阵列基板中，所述辅助电极为所述氧化物半导体经过等离子体处理或离子注入而形成的电导体。
优选地，该阵列基板还可以包括：在所述透明阴极上依次设置的电子注入层、电子传输层、发光层、空穴传输层、空穴注入层和反射阳极。
在第二方面，本发明提出了一种显示装置，包括任何一种前文所述的阵列基板。
在第三方面，本发明提出了一种阵列基板制作方法，包括：
形成氧化物半导体层；
对氧化物半导体层进行构图工艺，以形成薄膜晶体管的有源层，并在预设区域形成辅助电极图案；
对所述辅助电极图案进行改性处理以形成辅助电极；以及
形成与所述辅助电极电连接的透明阴极。
优选地，在形成氧化物半导体层之前，该方法还可以包括：
在基底上形成栅极；
在所述栅极上形成栅极绝缘层；以及
在所述栅极绝缘层上形成所述氧化物半导体层。
优选地，在对氧化物半导体层进行构图工艺之后，该方法还可以包括：
在所述辅助电极图案上形成第一刻蚀阻挡层。
优选地，在该方法中，对所述辅助电极图案进行改性处理可以包括：隔着所述第一刻蚀阻挡层对所述辅助电极图案进行改性处理。
可选地，在该方法中，可以在形成所述辅助电极图案之后和形成所述第一刻蚀阻挡层之前对所述辅助电极图案进行改性处理。
优选地，该方法还可以包括：
在形成第一刻蚀阻挡层时，在所述有源层上形成第二刻蚀阻挡层；
在形成所述透明阴极之前，在所述第二刻蚀阻挡层中形成过孔；以及
在所述第二刻蚀阻挡层上形成源极和漏极，其中所述源极和漏极分别通过所述第二刻蚀阻挡层中的过孔与所述有源层电连接。
优选地，该方法还可以包括：
在所述栅极绝缘层上形成钝化层，其中所述钝化层覆盖所述第一刻蚀阻挡层：
在所述钝化层中形成过孔；以及
在形成所述透明阴极时，将所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
优选地，该方法还可以包括：
在所述栅极绝缘层上形成钝化层，其中所述钝化层覆盖所述源极、漏极和第一刻蚀阻挡层；
在所述钝化层中形成过孔；以及
在形成所述透明阴极时，将所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
优选地，该方法还可以包括：
在所述栅极绝缘层上形成钝化层，其中所述钝化层覆盖所述源极、漏极、第一刻蚀阻挡层和第二刻蚀阻挡层；
在所述钝化层中形成过孔；以及
在形成所述透明阴极时，将所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
优选地，在形成所述透明阴极之前，该方法还可以包括：对所述辅助电极进行退火处理。
优选地，在该方法中，所述改性处理为等离子体处理或离子注入。
优选地，该方法还可以包括：在所述透明阴极上依次形成电子注入层、电子传输层、发光层、空穴传输层、空穴注入层和反射阳极。
根据上述技术方案，通过将有源层和辅助电极设置于同一层，因此可通过同一道刻蚀工艺形成有源层和辅助电极图案，无需单独设置形成辅助电极的工艺，从而减少阵列基板的整体工艺时间，节约了制作成本。
附图说明
通过参考附图会更加清楚的理解本发明的特征和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1示出了根据本发明一个实施例的阵列基板的结构示意图；
图2示出了根据本发明一个实施例的阵列基板制作方法的示意图；
图3示出了根据本发明一个实施例的形成第一刻蚀阻挡层和第二刻蚀阻挡层的示意图；
图4示出了根据本发明一个实施例的在第一刻蚀阻挡层和第二刻蚀阻挡层中形成过孔的示意图；
图5示出了根据本发明一个实施例的在第二刻蚀阻挡层上形成源极和漏极的示意图；以及
图6示出了根据本发明一个实施例的形成钝化层的示意图。
附图标号说明：
1-基底；2-栅极；3-栅极绝缘层；4-有源层；5-辅助电极；6-透明阴极；7-发光层；8-空穴传输层；9-空穴注入层；10-反射阳极；11-源极；12-漏极；13-第二刻蚀阻挡层；14-钝化层；15-第一刻蚀阻挡层。
具体实施方式
为了能够更清楚地理解本发明的上述目的、特征和优点，下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互 组合。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是，本发明还可以采用其他不同于在此描述的其他方式来实施，因此，本发明的保护范围并不受下面公开的具体实施例的限制。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。在本发明中，术语“多个”指两个或两个以上，除非另有明确的限定。
如图1所示，根据本发明一个实施例的阵列基板包括：薄膜晶体管(位于图1的左下部)，与薄膜晶体管的有源层4同层设置的辅助电极5，以及与辅助电极5电连接的透明阴极6，其中有源层4为氧化物半导体，辅助电极5为经过改性处理的氧化物半导体。此处的术语“改性处理”是指任何能够将氧化物半导体转换成电导体的任何处理。该改性处理包括但不限于等离子体处理、离子注入等。
优选地，阵列基板还包括：基底1，设置于基底1之上的栅极2，设置于栅极2之上的栅极绝缘层3，其中，有源层4设置在栅极绝缘层3上。
具体地，通过一道刻蚀工艺对位于栅极绝缘层之上的一层氧化物半导体层进行刻蚀，形成有源层和辅助电极图案，然后对辅助电极图 案进行诸如等离子体处理或离子注入的改性处理，提高氧化物半导体层载流子的浓度，使得辅助电极图案具有导电特性，从而形成辅助电极。
在上述实施例的阵列基板中，由于有源层和辅助电极同层设置，即可通过一道刻蚀工艺对氧化物半导体层进行加工，从而同时形成有源层和辅助电极，无需单独设置工艺来形成辅助电极，简化了阵列基板的制作工艺，节约了制作成本。
一般地，为了防止辅助电极在形成源漏极时受到损伤，阵列基板还可以包括：设置在辅助电极5上的第一刻蚀阻挡层15，其中，第一刻蚀阻挡层15中设置有过孔，透明阴极6通过第一刻蚀阻挡层15中的过孔与辅助电极5电连接。由于在辅助电极上设置有第一刻蚀阻挡层，那么在制作阵列基板时需要隔着辅助电极图案上的第一刻蚀阻挡层对辅助电极图案进行改性处理，使其具有导电性，以作为辅助电极。
一般地，阵列基板还可以包括设置在有源层4上的第二刻蚀阻挡层13，以及设置在第二刻蚀阻挡层13上的源极11和漏极12，其中，源极11和漏极12分别通过第二刻蚀阻挡层13中的过孔与有源层4电连接。第二刻蚀阻挡层可以防止辅助电极在形成源漏极时受到损伤。
一般地，阵列基板还可以包括：设置在栅极绝缘层3上，且覆盖第一刻蚀阻挡层15的钝化层14，其中，钝化层14中设置有过孔，透明阴极6通过第一刻蚀阻挡层15中的过孔和钝化层14中的过孔与辅助电极5电连接。
优选地，阵列基板还可以包括：设置在栅极绝缘层3上，且覆盖源极11、漏极12和第一刻蚀阻挡层15的钝化层14，其中，钝化层14中设置有过孔，透明阴极6通过第一刻蚀阻挡层15中的过孔和钝化层14中的过孔与辅助电极5电连接。
优选地，阵列基板还可以包括：设置在栅极绝缘层3上，且覆盖第一刻蚀阻挡层15、源极11、漏极12和第二刻蚀阻挡层13的钝化层14，其中，钝化层14中设置有过孔，透明阴极6通过第一刻蚀阻挡层15中的过孔和钝化层14中的过孔与辅助电极5电连接。钝化层14可以避免外界杂质入侵。
一般地，阵列基板还可以包括：在透明阴极6上依次设置的电子注入层、电子传输层(图中未示出)、发光层7、空穴传输层8、空穴 注入层9和反射阳极10。
应该理解，本实施例中的结构主要是针对倒置型OLED中的阵列基板进行描述，但是本发明中辅助电极和有源层的结构也适用于其他具有辅助电极的阵列基板。
本发明还提出了一种显示装置，包括上述任一项的阵列基板。
该显示装置除了包括本实施例中的阵列基板，例如还可包括彩膜基板。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
如图2所示，根据本发明一个实施例的阵列基板制作方法，包括：
步骤S1，形成氧化物半导体层；
步骤S2，对氧化物半导体层进行构图工艺，以形成薄膜晶体管的有源层4，并在预设区域形成辅助电极图案；
步骤S3，对辅助电极图案进行改性处理以形成辅助电极5；以及
步骤S4，形成与辅助电极5电连接的透明阴极6。
本领域技术人员应该理解，各层的形成可以采用各种工艺实现，一般可包括通过沉积材料层和对材料层进行刻蚀形成图案。当然，也可以通过其他的构图工艺实现。只要是与本发明权利要求限定的技术方案一致、类似或等效，无论“形成”通过何种工艺实现，均应认为属于本发明所要求保护的范围。
上述实施例的方法中，通过一道刻蚀工艺对氧化物半导体层进行加工，可以分别形成有源层4和辅助电极5，无需单独通过别的工艺来形成辅助电极5，简化了阵列基板的制作工艺，节约了制作成本。
一般地，在形成氧化物半导体层(步骤S1)之前，该方法还可以包括：
在基底1上形成栅极2；
在栅极2上形成栅极绝缘层3；以及
在栅极绝缘层3上形成氧化物半导体层。
一般地，在对氧化物半导体层进行构图工艺之后，该方法还可以包括：
在预设区域的氧化物半导体层上形成第一刻蚀阻挡层15，对辅助 电极图案进行改性处理可以包括：
隔着第一刻蚀阻挡层15对辅助电极图案进行诸如等离子体处理或离子注入的改性处理，或在形成辅助电极图案之后和形成第一刻蚀阻挡层15之前对辅助电极图案进行诸如等离子体处理或离子注入的改性处理。
对辅助电极图案进行改性处理的顺序可以根据需要进行设置。既可以在形成辅助电极图案之后直接对辅助电极图案进行改性处理。亦可以在形成第一刻蚀阻挡层15之后隔着第一刻蚀阻挡层15对辅助电极图案进行改性处理。具体地，改性处理例如可以采用等离子体处理、等离子注入工艺等，从而使辅助电极图案电阻降低而成为电导体。
一般地，如图3所示，该方法还可以包括：在形成第一刻蚀阻挡层15时，在有源层4上形成第二刻蚀阻挡层13，即两者通过同一道构图工艺形成。具体地，可以先在栅极绝缘层3上形成覆盖有源层4和辅助电极5的刻蚀阻挡层，然后刻蚀掉除了有源层4和辅助电极5之上的刻蚀阻挡层以外的刻蚀阻挡层，在有源层4之上的第二刻蚀阻挡层13和辅助电极5之上的刻蚀阻挡层15可以防止在形成源极11和漏极12时有源层4和辅助电极5被刻蚀。
如图4、5所示，在形成透明阴极6之前，该方法还可以包括：
在第二刻蚀阻挡层13中形成过孔，在第二刻蚀阻挡层13上形成源极11和漏极12，将源极11和漏极12分别通过第二刻蚀阻挡层13中的过孔与有源层4电连接。
如图5所示，一般地，在第二刻蚀阻挡层13中形成过孔时，在第一刻蚀阻挡层15中也形成过孔。
如图6所示，该方法还可以包括：在栅极绝缘层3上形成钝化层14，使钝化层14覆盖源第一刻蚀阻挡层15，在钝化层14中形成过孔。在形成透明阴极5时，将透明阴极5通过第一刻蚀阻挡层15中的过孔和钝化层14中的过孔与辅助电极5电连接，参见图1。
如图6所示，该方法还可以包括：在栅极绝缘层3上形成钝化层14，使钝化层14覆盖源极11、漏极12和第一刻蚀阻挡层15，在钝化层14中形成过孔。在形成透明阴极5时，将透明阴极5通过第一刻蚀阻挡层15中的过孔和钝化层14中的过孔与辅助电极5电连接，参见图1。
如图6所示，该方法还可以包括：在栅极绝缘层3上形成钝化层14。钝化层14除了覆盖第一刻蚀阻挡层15之外，还覆盖源极11、漏极12和第二刻蚀阻挡层13，从而避免外界杂质侵入。然后在钝化层14中与第一刻蚀阻挡层15中的过孔对应的位置形成过孔，使得透明阴极可以通过钝化层14中的过孔和第一刻蚀阻挡层15中的过孔电连接至辅助电极5。
优选地，该方法还包括：对辅助电极5进行退火处理。通过退火处理，可以消除残余应力，稳定尺寸，减少变形与裂纹倾向；细化晶粒，调整组织，消除组织缺陷。
优选地，该方法还包括：在透明阴极6上依次形成电子注入层、电子传输层、发光层7、空穴传输层8、空穴注入层9和反射阳极10，形成的阵列结构可参见图1。
以上结合附图详细说明了本发明的技术方案，考虑到相关技术中，在倒置型OLED中制作辅助电极需要增设单独的工艺，增加了工艺次数和制作成本。根据本发明的技术方案，能够通过同一道刻蚀工艺同时形成有源层和辅助电极，无需单独形成辅助电极的工艺，从而减少阵列基板的整体工艺时间，节约了制作成本。
本领域技术人员应该理解，上述阵列基板及其制作方法均以OLED阵列基板为例进行说明，因此本发明的阵列基板及其制作方法适于以OLED阵列基板及其制作方法实现，但本发明并不限于OLED阵列基板，不论阵列基板的类型，对于与本发明任一权利要求所记载的技术方案实质相同或类似的阵列基板及其制作方法，均应认为属于本发明的保护范围。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (22)

  1. 一种阵列基板，其特征在于，包括：薄膜晶体管，与所述薄膜晶体管的有源层同层设置的辅助电极，以及与所述辅助电极电连接的透明阴极，其中所述有源层为氧化物半导体，所述辅助电极为所述氧化物半导体经过改性处理而形成的电导体。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括：
    基底；设置于所述基底之上的栅极；以及设置于所述栅极之上的栅极绝缘层，其中所述有源层设置在所述栅极绝缘层上。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括：
    设置在所述辅助电极上的第一刻蚀阻挡层，其中，所述第一刻蚀阻挡层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过孔与所述辅助电极电连接。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述阵列基板还包括：
    设置在所述有源层上的第二刻蚀阻挡层，以及设置在所述第二刻蚀阻挡层上的源极和漏极，其中，所述源极和漏极分别通过所述第二刻蚀阻挡层中的过孔与所述有源层电连接。
  5. 根据权利要求3所述的阵列基板，其特征在于，所述阵列基板还包括：
    设置在所述栅极绝缘层上，且覆盖所述第一刻蚀阻挡层的钝化层，其中，所述钝化层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
  6. 根据权利要求4所述的阵列基板，其特征在于，所述阵列基板还包括：
    设置在所述栅极绝缘层上，且覆盖所述源极、漏极和第一刻蚀阻挡层的钝化层，其中，所述钝化层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
  7. 根据权利要求4所述的阵列基板，其特征在于，所述阵列基板 还包括：
    设置在所述栅极绝缘层上，且覆盖所述源极、漏极、第一刻蚀阻挡层和第二刻蚀阻挡层的钝化层，其中，所述钝化层中设置有过孔，所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
  8. 根据权利要求1所述的阵列基板，其特征在于，所述辅助电极为所述氧化物半导体经过等离子体处理或离子注入而形成的电导体。
  9. 根据权利要求1至8中任一项所述的阵列基板，其特征在于，所述阵列基板还包括：在所述透明阴极上依次设置的电子注入层、电子传输层、发光层、空穴传输层、空穴注入层和反射阳极。
  10. 一种显示装置，其特征在于，包括权利要求1至9中任一项所述的阵列基板。
  11. 一种阵列基板制作方法，其特征在于，包括：
    形成氧化物半导体层；
    对氧化物半导体层进行构图工艺，以形成薄膜晶体管的有源层，并在预设区域形成辅助电极图案；
    对所述辅助电极图案进行改性处理以形成辅助电极；以及
    形成与所述辅助电极电连接的透明阴极。
  12. 根据权利要求11所述的方法，其特征在于，在形成氧化物半导体层之前，所述方法还包括：
    在基底上形成栅极；
    在所述栅极上形成栅极绝缘层；以及
    在所述栅极绝缘层上形成所述氧化物半导体层。
  13. 根据权利要求12所述的方法，其特征在于，在对氧化物半导体层进行构图工艺之后，所述方法还包括：
    在所述辅助电极图案上形成第一刻蚀阻挡层。
  14. 根据权利要求13所述的方法，其特征在于，对所述辅助电极图案进行改性处理包括：隔着所述第一刻蚀阻挡层对所述辅助电极图案进行改性处理。
  15. 根据权利要求13所述的方法，其特征在于，在形成所述辅助电极图案之后和形成所述第一刻蚀阻挡层之前对所述辅助电极图案进行改性处理。
  16. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    在形成第一刻蚀阻挡层时，在所述有源层上形成第二刻蚀阻挡层；
    在形成所述透明阴极之前，在所述第二刻蚀阻挡层中形成过孔；以及
    在所述第二刻蚀阻挡层上形成源极和漏极，其中所述源极和漏极分别通过所述第二刻蚀阻挡层中的过孔与所述有源层电连接。
  17. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    在所述栅极绝缘层上形成钝化层，其中所述钝化层覆盖所述第一刻蚀阻挡层；
    在所述钝化层中形成过孔；以及
    在形成所述透明阴极时，将所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
  18. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    在所述栅极绝缘层上形成钝化层，其中所述钝化层覆盖所述源极、漏极和第一刻蚀阻挡层；
    在所述钝化层中形成过孔；以及
    在形成所述透明阴极时，将所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
  19. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    在所述栅极绝缘层上形成钝化层，其中所述钝化层覆盖所述源极、漏极、第一刻蚀阻挡层和第二刻蚀阻挡层；
    在所述钝化层中形成过孔；以及
    在形成所述透明阴极时，将所述透明阴极通过所述第一刻蚀阻挡层中的过孔和所述钝化层中的过孔与所述辅助电极电连接。
  20. 根据权利要求11所述的方法，其特征在于，在形成所述透明阴极之前，所述方法还包括：对所述辅助电极进行退火处理。
  21. 根据权利要求11所述的方法，其特征在于，所述改性处理为等离子体处理或离子注入。
  22. 根据权利要求11至21中任一项所述的方法，其特征在于，所述方法还包括：在所述透明阴极上依次形成电子注入层、电子传输层、发光层、空穴传输层、空穴注入层和反射阳极。
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