WO2016119397A1 - 一种实现信道估计的方法、装置及计算机存储介质 - Google Patents

一种实现信道估计的方法、装置及计算机存储介质 Download PDF

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Publication number
WO2016119397A1
WO2016119397A1 PCT/CN2015/083062 CN2015083062W WO2016119397A1 WO 2016119397 A1 WO2016119397 A1 WO 2016119397A1 CN 2015083062 W CN2015083062 W CN 2015083062W WO 2016119397 A1 WO2016119397 A1 WO 2016119397A1
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antenna port
domain interpolation
time domain
descrambling
result
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PCT/CN2015/083062
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English (en)
French (fr)
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郭震巍
李爱军
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深圳市中兴微电子技术有限公司
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Publication of WO2016119397A1 publication Critical patent/WO2016119397A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes

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  • the present invention relates to the field of wireless communications, and in particular, to a method, an apparatus, and a computer storage medium for implementing channel estimation.
  • channel estimation is generally implemented by second-order interpolation methods such as left prediction, right prediction, or interpolation for different scenarios.
  • second-order interpolation methods such as left prediction, right prediction, or interpolation for different scenarios.
  • traffic continues to increase, the number of ports continues to increase, and the scene becomes more complex. Therefore, if the channel estimation is still implemented according to the foregoing single second-order interpolation method, the entire channel estimation process is very complicated and consumes more resources, thereby increasing the cost and power consumption of the terminal.
  • Embodiments of the present invention provide a method, an apparatus, and a computer storage medium for implementing channel estimation, which can effectively reduce the complexity of the entire channel estimation process, thereby saving resources.
  • An embodiment of the present invention provides a method for implementing channel estimation, where the method includes:
  • Frequency domain interpolation processing is performed on each antenna port according to the time domain interpolation result, and a frequency domain interpolation result corresponding to each antenna port is obtained.
  • the descrambling processing is performed on the extracted reference signal to obtain a descrambling result corresponding to each antenna port, including:
  • the extracted reference signal is descrambled by using a least squares algorithm to obtain a descrambling result corresponding to each antenna port.
  • time domain interpolation processing is performed on each antenna port according to the descrambling result, and time domain interpolation results corresponding to each antenna port are obtained, including:
  • the second-order interpolation algorithm is classified to determine a unified multiplication and interpolation algorithm
  • the adjacent two descrambling results corresponding to each antenna port are subjected to time domain interpolation processing according to the multiplication plus interpolation algorithm to obtain a time domain interpolation result corresponding to each antenna port.
  • frequency domain interpolation processing is performed on each antenna port according to the time domain interpolation result, and frequency domain interpolation results corresponding to each antenna port are obtained, including:
  • a convolution operation is performed on the time domain interpolation result corresponding to each antenna port and the filter coefficient sequence to obtain a convolution result, which is taken as a frequency domain interpolation result corresponding to each antenna port.
  • the sequence of filter coefficients is a sequence of filter coefficients corresponding to a sixteenth order filter.
  • the embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to perform the method for implementing channel estimation according to an embodiment of the present invention.
  • An embodiment of the present invention further provides an apparatus for implementing channel estimation, where the apparatus includes an extraction module, a descrambling processing module, a time domain interpolation processing module, and a frequency domain interpolation processing module;
  • the extracting module is configured to extract a reference signal of each antenna port
  • the descrambling processing module is configured to perform descrambling processing on the extracted reference signal to obtain a descrambling result corresponding to each antenna port;
  • the time domain interpolation processing module is configured to perform time domain interpolation processing on each antenna port according to the descrambling result, to obtain a time domain interpolation result corresponding to each antenna port;
  • the frequency domain interpolation processing module is configured to perform frequency domain interpolation processing on each antenna port according to the time domain interpolation result, to obtain a frequency domain interpolation result corresponding to each antenna port.
  • the descrambling processing module is configured to perform descrambling processing on the extracted reference signal by using a least squares algorithm to obtain a descrambling result corresponding to each antenna port.
  • the time domain interpolation processing module includes a determining unit and a time domain interpolation processing unit; wherein
  • the determining unit is configured to classify the second-order interpolation algorithm to determine a unified multiply-add interpolation algorithm
  • the time domain interpolation processing unit is configured to perform time domain interpolation processing on the adjacent two descrambling results corresponding to each antenna port according to the multiplication and interpolation algorithm to obtain a time domain corresponding to each antenna port. Interpolation results.
  • the frequency domain interpolation processing module is configured to perform a convolution operation on a time domain interpolation result corresponding to each antenna port and a filter coefficient sequence to obtain a convolution result, and use the convolution result as Corresponding to the frequency domain interpolation result of each antenna port.
  • the method and device for implementing channel estimation and the computer storage medium provided by the embodiments of the present invention extract a reference signal of each antenna port, and perform descrambling processing on the extracted reference signal to obtain a descrambling result corresponding to each antenna port.
  • Performing time domain interpolation processing on each antenna port according to the descrambling result obtaining a time domain interpolation result corresponding to each antenna port; performing frequency domain interpolation processing on each antenna port according to the time domain interpolation result, Corresponding to the frequency domain interpolation result of each antenna port.
  • FIG. 1 is a schematic flowchart diagram of a method for implementing channel estimation according to an embodiment of the present invention
  • FIG. 2 is a block diagram of a reference signal distribution according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of performing time domain interpolation processing on each antenna port according to the descrambling result according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a structure of a multiply-add circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a reference signal distribution after descrambling processing according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a model for implementing frequency domain interpolation processing according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a device for implementing channel estimation according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a time domain interpolation processing module according to an embodiment of the present invention.
  • extracting a reference signal of each antenna port performing descrambling processing on the extracted reference signal to obtain a descrambling result corresponding to each antenna port; and each antenna port according to the descrambling result Performing a time domain interpolation process to obtain a time domain interpolation result corresponding to each antenna port; performing frequency domain interpolation processing on each antenna port according to the time domain interpolation result, and obtaining a frequency domain interpolation result corresponding to each antenna port.
  • FIG. 1 is a schematic flowchart of a method for implementing channel estimation according to an embodiment of the present invention. As shown in FIG. 1 , a method for implementing channel estimation according to an embodiment of the present invention includes:
  • Step S101 Extract a reference signal of each antenna port
  • channel estimation is typically performed based on a cell-specific reference signal, which is a signal known from the base station that is known to the terminal.
  • the LTE system includes four antenna ports, and the four antenna ports include a cell-specific reference signal corresponding to each antenna port, which is simply referred to as a reference signal of the antenna port.
  • the reference signal shown in Figure 2 the reference signals corresponding to the four antenna ports are comb-shaped in a two-dimensional space in the time domain and the frequency domain. Specifically, as shown in FIG.
  • each small square is defined as a resource RE according to the protocol
  • R0 represents the RE of the reference signal of the antenna port
  • R1 represents the RE of the reference signal of the antenna port 1
  • R2 represents the reference of the antenna port 2.
  • the signal is located at RE
  • R3 represents the RE of the reference signal of antenna port 3
  • the remaining squares are represented as the RE of the data.
  • channel estimation is implemented by using reference signals of four antenna ports R0 to R3 to estimate channel estimation values of all data portions. Therefore, in the process of implementing channel estimation, the reference signal corresponding to each antenna port is first extracted from the terminal to which the device belongs according to the layout shown in FIG. 2 by the means for channel estimation.
  • Step S102 Perform descrambling processing on the extracted reference signal to obtain a descrambling result corresponding to each antenna port.
  • the apparatus for channel estimation performs descrambling processing on the extracted reference signal by using a Least Square (LS) algorithm to obtain a descrambling result corresponding to each antenna port.
  • LS Least Square
  • the apparatus for channel estimation performs descrambling of a reference signal for each antenna port according to an LS algorithm, and obtains a descrambling result H LS corresponding to each antenna port; wherein, the LS algorithm based H LS Calculated as follows:
  • H LS Y RS /X RS ;
  • the Y RS represents data of a reference signal position corresponding to an antenna port received by a terminal to which the device for channel estimation belongs
  • X RS represents a reference corresponding to the antenna port issued by the base station known by the terminal. signal.
  • the H LS may be stored.
  • Step S103 performing time domain interpolation processing on each antenna port according to the descrambling result, and obtaining a time domain interpolation result corresponding to each antenna port;
  • the apparatus for channel estimation according to FIG. 3 performs time domain interpolation processing on each antenna port according to the descrambling result, and obtains a time domain interpolation result corresponding to each antenna port, including:
  • Step S1031 classifying the second-order interpolation algorithm to determine a unified multiplication and interpolation algorithm
  • the apparatus for channel estimation may classify multiple second-order interpolation algorithms, such as left prediction, right prediction, or interpolation, to determine a unified multiplication and interpolation algorithm, and the multiplication and interpolation algorithm.
  • the implementation can be implemented by a multiply-accumulate circuit as shown in FIG.
  • Step S1032 Perform time domain interpolation processing on the adjacent two descrambling results corresponding to each antenna port according to the multiplication and interpolation algorithm to obtain a time domain interpolation result corresponding to each antenna port.
  • the vertical line box represents the H LS corresponding to the reference signal obtained by the LS algorithm
  • the slanted line frame indicates that the time domain estimation is to be performed.
  • Data RE The means for channel estimation performs time domain interpolation according to the position of the data to be estimated RE, using two H LSs obtained by using adjacent LS algorithms corresponding to an antenna port, according to the multiplication and interpolation algorithm Processing, obtaining a time domain interpolation result corresponding to the antenna port; wherein the multiplication plus interpolation algorithm is implemented by using an expression:
  • H TI represents a time domain interpolation result
  • H LS (0) represents the left H LS in FIG. 5
  • H LS (1) represents the right H LS in FIG. 5 .
  • Step S104 Perform frequency domain interpolation processing on each antenna port according to the time domain interpolation result, to obtain a frequency domain interpolation result corresponding to each antenna port.
  • the apparatus for channel estimation performs a convolution operation on a time domain interpolation result corresponding to each antenna port and a sequence of filter coefficients to obtain a convolution result, and the convolution result is used as corresponding to each antenna.
  • H represents a frequency domain interpolation result, that is, a final result of channel estimation; said Coef(k) represents a filter coefficient; "*" represents a convolution operation.
  • a model structure for implementing frequency domain interpolation processing is as shown in FIG. 6, and H TI is output from a multiply-add circuit as shown in FIG.
  • the input data shift register is filtered to form a pipeline processing structure in which time domain interpolation and frequency domain interpolation can be performed simultaneously, which effectively reduces the processing delay of channel estimation.
  • FIG. 6 a model structure for implementing frequency domain interpolation processing is as shown in FIG. 6, and H TI is output from a multiply-add circuit as shown in FIG.
  • the input data shift register is filtered to form a pipeline processing structure in which time domain interpolation and frequency domain interpolation can be performed simultaneously, which effectively reduces the processing delay of channel estimation.
  • the method for implementing channel estimation according to the first embodiment of the present invention can effectively reduce the complexity of the entire channel estimation process, thereby saving resources, thereby reducing the cost and power consumption of the terminal.
  • the embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to perform the method for implementing channel estimation according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an apparatus for implementing channel estimation according to an embodiment of the present invention.
  • the apparatus according to the embodiment of the present invention includes an extraction module 701, a descrambling processing module 702, a time domain interpolation processing module 703, and a frequency domain. Interpolation processing module 704; wherein
  • the extracting module 701 is configured to extract a reference signal of each antenna port
  • the descrambling processing module 702 is configured to perform descrambling processing on the extracted reference signal, To the descrambling result corresponding to each antenna port;
  • the descrambling processing module 702 performs descrambling processing on the extracted reference signal by using a least squares algorithm to obtain a descrambling result corresponding to each antenna port.
  • the time domain interpolation processing module 703 is configured to perform time domain interpolation processing on each antenna port according to the descrambling result, to obtain a time domain interpolation result corresponding to each antenna port;
  • the frequency domain interpolation processing module 704 is configured to perform frequency domain interpolation processing on each antenna port according to the time domain interpolation result, to obtain a frequency domain interpolation result corresponding to each antenna port.
  • the frequency domain interpolation processing module 704 performs a convolution operation on the time domain interpolation result corresponding to each antenna port and the filter coefficient sequence to obtain a convolution result, and the convolution result is used as corresponding to each antenna.
  • the frequency domain interpolation result of the port is a sequence of filter coefficients corresponding to a sixteenth order filter.
  • the time domain interpolation processing module 703 includes a determining unit 7031 and a time domain interpolation processing unit 7032;
  • the determining unit 7031 is configured to classify the second-order interpolation algorithm to determine a unified multiply-add interpolation algorithm
  • the time domain interpolation processing unit 7032 is configured to perform time domain interpolation processing on the adjacent two descrambling results corresponding to each antenna port according to the multiply-add interpolation algorithm to obtain a time corresponding to each antenna port. Domain interpolation results.
  • each module included in the second embodiment of the present invention and each unit included in the module can pass through a central processing unit (CPU) of the terminal to which the device for implementing channel estimation belongs, and micro processing.
  • CPU central processing unit
  • MPU Micro Processor Unit
  • DSP Digital Signal Processor
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Circuit
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the method for implementing channel estimation extracts a reference signal of each antenna port, and performs descrambling processing on the extracted reference signal to obtain a descrambling result corresponding to each antenna port; according to the descrambling result Performing time domain interpolation processing on each antenna port to obtain a time domain interpolation result corresponding to each antenna port; performing frequency domain interpolation processing on each antenna port according to the time domain interpolation result, and obtaining corresponding to each antenna port Frequency domain interpolation results.
  • the complexity of the entire channel estimation process can be effectively reduced, thereby saving resources, thereby reducing the cost and power consumption of the terminal.

Abstract

本发明实施例提供了一种实现信道估计的方法、装置及计算机存储介质，提取每个天线端口的参考信号；对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。

Description

一种实现信道估计的方法、装置及计算机存储介质 技术领域
本发明涉及无线通信领域，尤其涉及一种实现信道估计的方法、装置及计算机存储介质。
背景技术
近年来，随着长期演进(Long Term Evolution，LTE)系统的广泛应用，信道估计已成为多输入多输出(Multiple Input Multiple Output，MIMO)检测技术的基础。
目前信道估计一般针对不同的场景通过向左预测、向右预测或内插等二阶插值方法来分别实现。然而，随着LTE技术的不断发展，流量的不断提升，端口数不断增加，场景变得越发复杂。所以，如果仍然按照前述单一的二阶插值方法来实现信道估计，将会使得整个信道估计过程非常复杂，且消耗较多资源，从而增加终端的成本和功耗。
发明内容
本发明实施例提供一种实现信道估计的方法、装置及计算机存储介质，能够有效降低整个信道估计过程的复杂度，从而节省资源。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种实现信道估计的方法，该方法包括：
提取每个天线端口的参考信号；
对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；
根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每 个天线端口的时域插值结果；
根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。
在一实施例中，所述对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果，包括：
采用最小二乘算法对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果。
在一实施例中，根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果，包括：
对二阶插值算法进行归类，确定出统一的乘加插值算法；
将对应于每个天线端口的相邻的两个解扰结果，按照所述乘加插值算法进行时域插值处理，得到对应于每个天线端口的时域插值结果。
在一实施例中，根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果，包括：
将对应于每个天线端口的时域插值结果与滤波器系数序列进行卷积操作，得到卷积结果，将所述卷积结果作为对应于每个天线端口的频域插值结果。
在一实施例中，所述滤波器系数序列为对应于十六阶滤波器的滤波器系数序列。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述实现信道估计的方法。
本发明实施例还提供一种实现信道估计的装置，该装置包括提取模块、解扰处理模块、时域插值处理模块和频域插值处理模块；其中，
所述提取模块，配置为提取每个天线端口的参考信号；
所述解扰处理模块，配置为对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；
所述时域插值处理模块，配置为根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；
所述频域插值处理模块，配置为根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。
在一实施例中，所述解扰处理模块，配置为采用最小二乘算法对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果。
在一实施例中，所述时域插值处理模块包括确定单元和时域插值处理单元；其中，
所述确定单元，配置为对二阶插值算法进行归类，确定出统一的乘加插值算法；
所述时域插值处理单元，配置为将对应于每个天线端口的相邻的两个解扰结果，按照所述乘加插值算法进行时域插值处理，得到对应于每个天线端口的时域插值结果。
在一实施例中，所述频域插值处理模块，配置为将对应于每个天线端口的时域插值结果与滤波器系数序列进行卷积操作，得到卷积结果，将所述卷积结果作为对应于每个天线端口的频域插值结果。
本发明实施例所提供的实现信道估计的方法、装置及计算机存储介质，提取每个天线端口的参考信号；对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。如此，能够有效降低整个信道估计过程的复杂度，从而节省资源，进而降低终端的成本和功耗。
附图说明
图1为本发明实施例实现信道估计的方法的流程示意图；
图2为本发明实施例参考信号分布框图；
图3为本发明实施例根据所述解扰结果对每个天线端口进行时域插值处理的流程示意图；
图4为本发明实施例乘加电路的组成结构示意图；
图5为本发明实施例经解扰处理后的参考信号分布图；
图6为本发明实施例实现频域插值处理的模型的组成结构示意图；
图7为本发明实施例实现信道估计的装置的组成结构示意图；
图8为本发明实施例所述时域插值处理模块的组成结构示意图。
具体实施方式
在本发明实施例中，提取每个天线端口的参考信号；对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。
下面结合附图及具体实施例对本发明再作进一步详细的说明。
实施例一
图1为本发明实施例实现信道估计的方法的流程示意图，如图1所示，本发明实施例实现信道估计的方法包括：
步骤S101：提取每个天线端口的参考信号；
这里，在LTE系统中，信道估计通常基于小区专用参考信号进行运算，所述小区专用参考信号是终端所已知的从基站发出的信号。LTE系统中包括四个天线端口，所述四个天线端口共包括分别对应于每个天线端口的小区专用参考信号，简称为天线端口的参考信号。在如图2所示的参考信号 分布框图中，所述对应于四个天线端口的参考信号在时域和频域的二维空间上成梳状分布。具体地，如图2所示，依据协议每一小方格定义为资源RE，R0表示天线端口0的参考信号所在RE，R1表示天线端口1的参考信号所在RE，R2表示天线端口2的参考信号所在RE，R3表示天线端口3的参考信号所在RE，其余方格表示为数据所在RE。而本发明实施例所述实现信道估计正是采用R0～R3这四个天线端口的参考信号来估计出所有数据部分的信道估计值。因此，在实现信道估计的过程中，首先通过用于信道估计的装置从所述装置所隶属的终端中按照附图2所示的布局提取对应于每个天线端口的参考信号。
步骤S102：对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；
具体地，所述用于信道估计的装置采用最小二乘算法(Least Square，LS)对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果。
这里，所述用于信道估计的装置依据LS算法来完成对每个天线端口的参考信号的解扰，得到对应于每个天线端口的解扰结果HLS；其中，基于LS算法的HLS的计算公式如下：
HLS＝YRS/XRS；
其中，所述YRS表示用于信道估计的装置所隶属的终端所接收到的对应于天线端口的参考信号位置的数据，XRS表示所述终端所已知的基站发出的对应于天线端口参考信号。
在实际应用中，在通过上述LS算法得到解扰结果HLS后，可以对所述HLS进行存储。
步骤S103：根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；
具体地，如图3所述用于信道估计的装置根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果，包括：
步骤S1031：对二阶插值算法进行归类，确定出统一的乘加插值算法；
具体地，所述用于信道估计的装置将可能采用向左预测、向右预测或内插等多种二阶插值算法进行归类，确定出统一的乘加插值算法，所述乘加插值算法的实现可以由如图4所示的乘加电路实现。
步骤S1032：将对应于每个天线端口的相邻的两个解扰结果，按照所述乘加插值算法进行时域插值处理，得到对应于每个天线端口的时域插值结果。
举例来说，在如图5所示的经解扰处理后的参考信号分布图中，竖线框表示已采用LS算法得到的对应于参考信号的HLS，斜线框表示待进行时域估计的数据RE。所述用于信道估计的装置根据待估计数据RE所在的位置，利用对应于某一个天线端口的相邻的已采用LS算法得到的两个HLS，按照所述乘加插值算法进行时域插值处理，得到对应于所述天线端口的时域插值结果；其中，所述乘加插值算法采用如下表达式来实现：
Figure PCTCN2015083062-appb-000001
其中，所述HTI表示时域插值结果，HLS(0)表示附图5中所处左边的HLS，而HLS(1)表示附图5中所处右边的HLS。
步骤S104：根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。
具体地，所述用于信道估计的装置将对应于每个天线端口的时域插值结果与滤波器系数序列进行卷积操作，得到卷积结果，将所述卷积结果作为对应于每个天线端口的频域插值结果；其中，所述滤波器系数序列可以为对应于十六阶滤波器的滤波器系数序列。
这里，所述卷积操作采用如下表达式来实现：
H＝HTI*Coef(k)；
其中，所述H表示频域插值结果，即信道估计的最终结果；所述Coef(k)表示滤波器系数；“*”表示卷积操作。
在实际应用中，在所述用于信道估计的装置中，用于实现频域插值处理的模型结构如图6所示，HTI从如图4所示的乘加电路输出至16阶滤波器的输入数据移位寄存器进行滤波，形成时域插值与频域插值可同时进行的流水线处理结构，有效降低信道估计的处理延迟。另外，如图6所示，为了支持四个天线端口的频域插值处理，在滤波器的数据输入(如data[i][1])和滤波器系数输入(如coef[i][1])过程中均采用选择器，同时对每个天线端口的输入数据和滤波器系数进行选择，并采用统一的滤波器结构完成对每个天线端口的频域插值处理，从而得到频域插值结果，即信道估计的最终结果。
如此，通过本发明实施例一所述实现信道估计的方法，能够有效降低整个信道估计过程的复杂度，从而节省资源，进而降低终端的成本和功耗。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述实现信道估计的方法。
实施例二
图7为本发明实施例实现信道估计的装置的组成结构示意图，如图7所示，本发明实施例所述装置包括提取模块701、解扰处理模块702、时域插值处理模块703和频域插值处理模块704；其中，
所述提取模块701，配置为提取每个天线端口的参考信号；
所述解扰处理模块702，配置为对所提取的参考信号进行解扰处理，得 到对应于每个天线端口的解扰结果；
具体地，所述解扰处理模块702采用最小二乘算法对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果。
所述时域插值处理模块703，配置为根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；
所述频域插值处理模块704，配置为根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。
具体地，所述频域插值处理模块704将对应于每个天线端口的时域插值结果与滤波器系数序列进行卷积操作，得到卷积结果，将所述卷积结果作为对应于每个天线端口的频域插值结果。其中，所述滤波器系数序列为对应于十六阶滤波器的滤波器系数序列。
在一实施例中，如图8所示，所述时域插值处理模块703包括确定单元7031和时域插值处理单元7032；其中，
所述确定单元7031，配置为对二阶插值算法进行归类，确定出统一的乘加插值算法；
所述时域插值处理单元7032，配置为将对应于每个天线端口的相邻的两个解扰结果，按照所述乘加插值算法进行时域插值处理，得到对应于每个天线端口的时域插值结果。
在实际应用中，本发明实施例二所提供的各模块及模块所包括的各单元均可以通过用于实现信道估计的装置所隶属的终端的中央处理器(Central Processing Unit，CPU)、微处理器(Micro Processor Unit，MPU)、数字信号处理器(Digital Signal Processor，DSP)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或特定用途集成电路(Application Specific Integrated Circuit，ASIC)实现。
本发明实施例所记载的技术方案之间，在不冲突的情况下，可以任意 组合。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可 轻易想到变化或替换，都应涵盖在本发明的保护范围之内。
工业实用性
本发明实施例所述实现信道估计的方法，提取每个天线端口的参考信号；对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。如此，能够有效降低整个信道估计过程的复杂度，从而节省资源，进而降低终端的成本和功耗。

Claims (11)

  1. 一种实现信道估计的方法，所述方法包括：
    提取每个天线端口的参考信号；
    对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；
    根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；
    根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。
  2. 根据权利要求1所述的方法，其中，所述对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果，包括：
    采用最小二乘算法对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果。
  3. 根据权利要求1所述的方法，其中，根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果，包括：
    对二阶插值算法进行归类，确定出统一的乘加插值算法；
    将对应于每个天线端口的相邻的两个解扰结果，按照所述乘加插值算法进行时域插值处理，得到对应于每个天线端口的时域插值结果。
  4. 根据权利要求1至3任一项所述的方法，其中，根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果，包括：
    将对应于每个天线端口的时域插值结果与滤波器系数序列进行卷积操作，得到卷积结果，将所述卷积结果作为对应于每个天线端口的频域插值结果。
  5. 根据权利要求4所述的方法，其中，所述滤波器系数序列为对应于 十六阶滤波器的滤波器系数序列。
  6. 一种实现信道估计的装置，所述装置包括提取模块、解扰处理模块、时域插值处理模块和频域插值处理模块；
    所述提取模块，配置为提取每个天线端口的参考信号；
    所述解扰处理模块，配置为对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果；
    所述时域插值处理模块，配置为根据所述解扰结果对每个天线端口进行时域插值处理，得到对应于每个天线端口的时域插值结果；
    所述频域插值处理模块，配置为根据所述时域插值结果对每个天线端口进行频域插值处理，得到对应于每个天线端口的频域插值结果。
  7. 根据权利要求6所述的装置，其中，
    所述解扰处理模块，配置为采用最小二乘算法对所提取的参考信号进行解扰处理，得到对应于每个天线端口的解扰结果。
  8. 根据权利要求6所述的装置，其中，所述时域插值处理模块包括确定单元和时域插值处理单元；
    所述确定单元，配置为对二阶插值算法进行归类，确定出统一的乘加插值算法；
    所述时域插值处理单元，配置为将对应于每个天线端口的相邻的两个解扰结果，按照所述乘加插值算法进行时域插值处理，得到对应于每个天线端口的时域插值结果。
  9. 根据权利要求6至8任一项所述的装置，其中，
    所述频域插值处理模块，配置为将对应于每个天线端口的时域插值结果与滤波器系数序列进行卷积操作，得到卷积结果，将所述卷积结果作为对应于每个天线端口的频域插值结果。
  10. 根据权利要求9所述的装置，其中，所述滤波器系数序列为对应 于十六阶滤波器的滤波器系数序列。
  11. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至5任一项所述实现信道估计的方法。
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