WO2016115855A1 - 一种闭环的时钟校准方法、终端及计算机存储介质 - Google Patents

一种闭环的时钟校准方法、终端及计算机存储介质 Download PDF

Info

Publication number
WO2016115855A1
WO2016115855A1 PCT/CN2015/084794 CN2015084794W WO2016115855A1 WO 2016115855 A1 WO2016115855 A1 WO 2016115855A1 CN 2015084794 W CN2015084794 W CN 2015084794W WO 2016115855 A1 WO2016115855 A1 WO 2016115855A1
Authority
WO
WIPO (PCT)
Prior art keywords
calibration
period
factor
nth
clock
Prior art date
Application number
PCT/CN2015/084794
Other languages
English (en)
French (fr)
Inventor
李焱
张骏凌
Original Assignee
深圳市中兴微电子技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市中兴微电子技术有限公司 filed Critical 深圳市中兴微电子技术有限公司
Priority to EP15878526.1A priority Critical patent/EP3249978B1/en
Priority to US15/545,035 priority patent/US10172093B2/en
Publication of WO2016115855A1 publication Critical patent/WO2016115855A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H04W52/029—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment reducing the clock frequency of the controller
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to clock calibration techniques in the field of wireless communications, and more particularly to a closed loop clock calibration method, terminal, and computer storage medium.
  • DRX discontinuous reception period
  • the discontinuous reception period is usually divided into two periods: active ( Active) and Sleep periods, as shown in Figure 1.
  • Active active
  • Sleep periods are usually divided into two periods: active ( Active) and Sleep periods, as shown in Figure 1.
  • the working unit includes a system clock, which may also be called a high-frequency clock.
  • the terminal turns off the high-frequency clock and uses a low-frequency, low-power low frequency.
  • the clock maintains system timing. For example, most terminals in a wireless cellular communication system usually use a low frequency clock with a frequency of 32.768 kHz to maintain system timing.
  • the terminal When the terminal enters the active time period, it first needs to recover the system timing through the low frequency clock of the Sleep period.
  • the low frequency clock is multiplied by a calibration factor to be converted to a high frequency clock to restore system timing. Since the accuracy and stability of the low-frequency clock are relatively low and there is no function of temperature compensation, the low-frequency clock will be affected by factors such as environment and temperature.
  • the system timing may have calibration deviation, and the terminal also needs Synchronize frequency and time before you can initiate or receive a page. It can be seen that the terminal needs to adjust the calibration factor to make the recovered system timing more accurate, thereby improving the execution efficiency of subsequent synchronization operations.
  • the system clock (high-frequency clock) is usually used as the calibration clock to calibrate the low-frequency clock, that is, the high-frequency clock and the low-frequency clock work simultaneously and count separately, and the high-frequency clock and the low-frequency are calculated after a period of time.
  • the ratio of the clock gets the calibration factor; however, the high frequency clock is affected by the clock jitter, so the existing calibration factor adjustment method needs to increase the calibration time.
  • the longer the calibration time the higher the calibration accuracy.
  • the calibration time needs to be more than 100ms. However, if the calibration time is too long, the sleep time of the terminal during the Sleep period will be reduced, which will increase the standby power consumption of the terminal.
  • embodiments of the present invention are expected to provide a closed loop clock calibration method, a terminal, and a computer storage medium.
  • Embodiments of the present invention provide a closed loop clock calibration method, including:
  • the clock calibration is performed according to the calibration factor of the nth calibration period, and the calibration error of the nth calibration period is obtained;
  • the calibration factor of the n+1th calibration period is obtained; where n is a positive integer.
  • the method further includes:
  • the calibration factor for the first calibration period is preset.
  • the preset calibration factor of the first calibration period includes:
  • the calibration factor is obtained according to the theoretical frequency value of the system clock and the theoretical frequency value of the low frequency clock;
  • the resulting calibration factor is preset to the calibration factor of the first calibration period.
  • the preset calibration factor of the first calibration period includes:
  • the system clock and the low frequency clock work simultaneously and are counted separately during a preset time period
  • the ratio of the count value of the system clock cycle to the count value of the low frequency clock cycle is calculated to obtain a calibration factor; the obtained calibration factor is preset as a calibration factor of the first calibration period.
  • the clock calibration is performed according to the calibration factor of the nth calibration period in the nth calibration period, and the calibration error of the nth calibration period is obtained, including:
  • the calibration factor that multiplies the low frequency clock by the nth calibration period is converted to The system clock is restored to the system timing; and the calibration error ⁇ t of the nth calibration period is obtained according to the following formula:
  • T s is the actual system timing and T c is the system timing recovered by the calibration factor of the nth calibration period.
  • the calibration factor of the n+1th calibration period is obtained according to the calibration error and the calibration factor of the nth calibration period, including:
  • the calibration factor f(n+1) of the n+1th calibration period is obtained according to the following formula:
  • f(n) is the calibration factor of the nth calibration period
  • ⁇ t is the calibration error of the nth calibration period
  • Tsleep is the sleep period in the discontinuous reception period.
  • the calibration period is preset to be at least one discontinuous reception period.
  • an embodiment of the present invention further provides a terminal, where the terminal includes: a calibration error extraction unit, and a calibration factor adjustment unit;
  • the calibration error extracting unit is configured to perform clock calibration according to a calibration factor of the nth calibration period during the nth calibration period, and obtain a calibration error of the nth calibration period;
  • the calibration factor adjustment unit is configured to obtain a calibration factor of the n+1th calibration period according to the calibration error and the calibration factor of the nth calibration period; wherein n is a positive integer.
  • the terminal further includes:
  • the initial value preset unit is configured to preset a calibration factor of the first calibration period.
  • the initial value preset unit is configured to obtain a calibration factor according to a theoretical frequency value of the system clock and a theoretical frequency value of the low frequency clock; and the obtained calibration factor is preset as a calibration factor of the first calibration period.
  • the initial value preset unit is configured to: at a preset time period, the system clock and the low frequency clock work simultaneously and count separately; after the preset time period, calculate the system clock cycle The ratio of the count value to the count value of the low frequency clock cycle results in a calibration factor; the resulting calibration factor is preset to the calibration factor of the first calibration period.
  • the calibration period is preset to be at least one discontinuous reception period.
  • Embodiments of the present invention further provide a computer storage medium comprising a set of instructions that, when executed, cause at least one processor to perform the closed loop clock calibration method described above.
  • the closed loop clock calibration method, the terminal and the computer storage medium provided by the embodiments of the present invention perform clock calibration according to the calibration factor of the nth calibration period in the nth calibration period, and obtain a calibration error of the nth calibration period;
  • the calibration error of the calibration period and the calibration factor yield a calibration factor for the n+1th calibration period; where n is a positive integer.
  • the embodiment of the present invention performs closed-loop clock calibration according to the calibration error, which not only improves the accuracy of the clock calibration, but also reduces the standby power consumption of the terminal.
  • FIG. 1 is a schematic structural diagram of a discontinuous reception period in the related art
  • FIG. 2 is a schematic flowchart of implementing a closed loop clock calibration method according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a terminal structure according to an embodiment of the present invention.
  • the clock calibration is performed according to the calibration factor of the nth calibration period, and the calibration error of the nth calibration period is obtained; according to the calibration error and the calibration factor of the nth calibration period, the nth is obtained.
  • the closed loop clock calibration process provided by the embodiment of the present invention includes specific steps:
  • Step S201 During the nth calibration period, according to the calibration factor of the nth calibration period The clock is calibrated and the calibration error of the nth calibration period is obtained; where n is a positive integer.
  • the calibration factor used in the first calibration period is an initial calibration factor
  • the initial calibration factor can be preset in two ways:
  • Method 1 According to the theoretical frequency value of the system clock and the theoretical frequency value of the low frequency clock, and obtain the calibration factor f(1) according to the following formula:
  • F d is the theoretical frequency value of the low frequency clock and F is the theoretical frequency value of the system clock (high frequency clock);
  • the obtained calibration factor f(1) is preset as a calibration factor for the first calibration period.
  • Method 2 Using the system clock to perform clock calibration for a preset period of time to obtain a calibration factor, the specific implementation process is as follows:
  • the system clock and the low frequency clock work simultaneously and count separately in a preset time period
  • the resulting calibration factor is preset to the calibration factor of the first calibration period.
  • the low frequency clock of the Sleep phase is multiplied by the calibration factor of the nth calibration period to be converted into the system clock, thereby restoring the system timing; and the calibration error ⁇ t of the nth calibration period is obtained according to the following formula. :
  • T s is the actual system timing and T c is the system timing recovered by the calibration factor of the nth calibration period.
  • the actual system timing T s can be obtained by restoring the frequency and time synchronization process after the system is timed. How to obtain the actual system timing T s belongs to the prior art, and the repeated description will not be repeated.
  • ⁇ t>0 it indicates that the recovery time by the calibration factor of the nth calibration period is earlier than the actual time, and it is necessary to reduce the calibration factor of the nth calibration period, and use the adjusted calibration factor for the calibration factor. Clock calibration in the next calibration cycle; when ⁇ t ⁇ 0, it means that the recovery time by the calibration factor of the nth calibration period is later than the actual time, at which time the calibration factor of the nth calibration period needs to be increased, and the adjusted The calibration factor is used for clock calibration in the next calibration cycle;
  • Step S202 Obtain a calibration factor of the n+1th calibration period according to the calibration error of the nth calibration period and the calibration factor.
  • the calibration factor f(n+1) of the n+1th calibration period is obtained according to the following formula:
  • f (n) is the n calibration period the calibration factor
  • ⁇ t is the n-th calibration error calibration period
  • T sleep period in a discontinuous reception time of the sleep period.
  • the embodiment of the present invention before the n+1th calibration period, the calibration factor of the nth calibration period is adjusted according to the calibration error of the nth calibration period, thereby obtaining a calibration factor of the n+1th calibration period; 1 calibration period calibration factor is used for clock calibration in the n+1th calibration period, and so on, to achieve closed loop clock calibration; thus, the embodiment of the present invention performs closed loop clock calibration based on calibration error, which can improve clock calibration. Accuracy; and the embodiment of the present invention does not depend on the system clock, thereby solving the problem that the calibration time occurring in the prior art is too long, thereby reducing the standby power consumption of the terminal.
  • the terminal preset calibration period T is a discontinuous reception period T DRX , and the calibration factor of the preset first calibration period is f(1);
  • f(1) is corrected according to the calibration error ⁇ t 1 to obtain the corrected f(2); f(2) is used for clock calibration in the second calibration period;
  • f(2) is corrected according to the calibration error ⁇ t 2 to obtain the corrected f(3); f(3) is used for the clock calibration in the third calibration period;
  • the clock calibration is performed according to the calibration factor corrected in the previous calibration period, and the calibration error of the nth calibration period is obtained; the calibration of the nth calibration period is performed according to the calibration error of the nth calibration period.
  • the factor is corrected to obtain a corrected calibration factor; the corrected calibration factor is used for clock calibration in the next calibration cycle to achieve closed loop clock calibration.
  • the embodiment of the present invention provides a terminal.
  • the principle and method for solving the problem are similar. Therefore, the implementation process and implementation principles of the terminal can be described in the implementation process and implementation principles of the foregoing method. I won't go into details here.
  • the terminal provided by the embodiment of the present invention includes: calibration error extraction Unit 301, calibration factor adjustment unit 302; wherein
  • the calibration error extraction unit 301 is configured to perform clock calibration according to a calibration factor of the nth calibration period during the nth calibration period, and obtain a calibration error of the nth calibration period;
  • the calibration factor adjustment unit 302 is configured to obtain a calibration factor of the n+1th calibration period according to the calibration error and the calibration factor of the nth calibration period; wherein n is a positive integer;
  • the calibration period is preset to at least one discontinuous reception period.
  • the terminal may further include:
  • the initial value preset unit 303 is configured to preset a calibration factor of the first calibration period
  • the initial value preset unit 303 is specifically configured to obtain a calibration factor according to a theoretical frequency value of the system clock and a theoretical frequency value of the low frequency clock; and preset the obtained calibration factor as a calibration factor of the first calibration period. .
  • the initial value preset unit 303 is configured to: at a preset time period, the system clock and the low frequency clock work simultaneously and count separately; after the preset time period, calculate a count value of the high frequency clock cycle and The ratio of the count values of the low frequency clock cycles, the calibration factor is obtained; the obtained calibration factor is preset as the calibration factor of the first calibration period.
  • the calibration error extraction unit 301, the calibration factor adjustment unit 302, and the initial value preset unit 303 may be implemented by a central processing unit (CPU), a microprocessor (MPU), and a digital signal processor (DSP) located at the terminal. Or field programmable gate array (FPGA) implementation.
  • CPU central processing unit
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA field programmable gate array
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • an embodiment of the present invention further provides a computer storage medium, the computer storage medium comprising a set of instructions, when executed, causing at least one processor to perform the closed loop clock calibration method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Power Sources (AREA)

Abstract

本发明公开了一种闭环的时钟校准方法，包括：在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数。本发明还同时公开了一种终端及计算机存储介质。

Description

一种闭环的时钟校准方法、终端及计算机存储介质 技术领域
本发明涉及无线通信领域的时钟校准技术，尤其涉及一种闭环的时钟校准的方法、终端及计算机存储介质。
背景技术
在无线蜂窝通信系统中，该系统中的终端未执行业务或者执行业务较少时，终端通常会进入非连续接收时段(DRX)，所述非连续接收时段通常分为成两个时段：活跃(Active)时段和睡眠(Sleep)时段，如图1所示。终端进入Sleep时段时，会关闭内部大部分的工作单元，该工作单元包括系统时钟，也可称为高频时钟，此时，终端关闭高频时钟而采用频率较低、功耗较小的低频时钟维持系统定时，例如，无线蜂窝通信系统中的大多数终端通常都采用频率为32.768kHz的低频时钟维持系统定时；终端进入Active时段时，首先需要通过Sleep时段的低频时钟来恢复系统定时，将所述低频时钟乘以一个校准因子转换为高频时钟，从而恢复系统定时。由于低频时钟的精度和稳定度相对较低，且不具备温度补偿的功能，因此，低频时钟会受到环境、温度等因素的影响；终端恢复系统定时后，系统定时可能存在校准偏差，终端还需要进行频率和时间的同步，然后才能发起或接收寻呼。由此可见，终端需要调整校准因子，以使恢复的系统定时更精确，从而提高后续同步操作的执行效率。
现有校准因子调整方式中，通常采用系统时钟(高频时钟)作为校准时钟对低频时钟进行校准，即：高频时钟和低频时钟同时工作且分别计数，经过一段时间后计算高频时钟和低频时钟的比值得到校准因子；但高频时钟会受到时钟抖动的影响，因此，现有校准因子调整方式需要增加校准时 间来保证校准精度，校准时间越长校准精度越高，通常，校准时间需要达到100ms以上，但校准时间过长会使终端在Sleep时段的睡眠时间减少，这样会增加终端的待机功耗。
发明内容
有鉴于此，本发明实施例期望提供一种闭环的时钟校准方法、终端及计算机存储介质。
为达到上述目的，本发明的技术方案是这样实现的：
本发明实施例提供了一种闭环的时钟校准方法，包括：
在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；
根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数。
上述方案中，该方法还包括：
预设第一校准周期的校准因子。
上述方案中，所述预设第一校准周期的校准因子，包括：
根据系统时钟的理论频率值与低频时钟的理论频率值，得到校准因子；
将得到的校准因子预设为第一校准周期的校准因子。
上述方案中，所述预设第一校准周期的校准因子，包括：
在预设时段内，系统时钟和所述低频时钟同时工作且分别计数；
在预设时段后，计算系统时钟周期的计数值和低频时钟周期的计数值的比值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
上述方案中，所述在第n校准周期内根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差，包括：
在第n校准周期内，将低频时钟乘以第n校准周期的校准因子转换为 系统时钟恢复系统定时；并按照如下公式得到第n校准周期的校准误差Δt：
Δt＝Ts-Tc
其中，Ts为实际的系统定时，Tc为通过第n校准周期的校准因子恢复的系统定时。
上述方案中，所述根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子，包括：
根据第n校准周期的校准误差及校准因子，并按照如下公式得到第n+1校准周期的校准因子f(n+1)：
Figure PCTCN2015084794-appb-000001
其中，f(n)为第n校准周期的校准因子，Δt为第n校准周期的校准误差，TSleep为非连续接收时段中的睡眠时段。
上述方案中，所述校准周期预设为至少一个非连续接收时段。
根据上述方法，本发明实施例还提供了一种终端，该终端包括：校准误差提取单元、校准因子调整单元；其中，
所述校准误差提取单元，配置为在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；
所述校准因子调整单元，配置为根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数。
上述方案中，该终端还包括：
初始值预设单元，配置为预设第一校准周期的校准因子。
上述方案中，所述初始值预设单元，配置为根据系统时钟的理论频率值与低频时钟的理论频率值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
上述方案中，所述初始值预设单元，配置为在预设时段内，系统时钟和所述低频时钟同时工作且分别计数；在预设时段后，计算系统时钟周期 的计数值和低频时钟周期的计数值的比值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
上述方案中，所述校准周期预设为至少一个非连续接收时段。
本发明实施例又提供了一种计算机存储介质，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行上述的闭环的时钟校准方法。
本发明实施例所提供的闭环时钟校准方法、终端及计算机存储介质，在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数。如此，本发明实施例根据校准误差进行闭环的时钟校准，不仅能提高时钟校准的精度，还能降低终端的待机功耗。
附图说明
图1为相关技术中非连续接收时段的结构示意图；
图2为本发明实施例闭环的时钟校准方法的实现流程示意图；
图3为本发明实施例终端的组成结构示意图。
具体实施方式
本发明实施例中，在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数。
下面结合附图对本发明的具体实施方式进行说明。
如图2所示，本发明实施例提供的闭环的时钟校准流程，具体实现步骤包括：
步骤S201：在第n校准周期内，根据第n校准周期的校准因子进行时 钟校准，并得到第n校准周期的校准误差；其中，n为正整数。
这里，所述校准周期T通常为至少一个非连续接收时段TDRX，TDRX＝TActive+TSleep；其中，TActive为非连续接收时段TDRX中的活跃时段，TSleep为非连续接收时段TDRX中的睡眠时段。
这里，在第一校准周期内使用的校准因子为初始的校准因子，该初始的校准因子可以通过以下两种方式进行预设：
方式一、根据系统时钟的理论频率值与低频时钟的理论频率值，并按照如下公式得到校准因子f(1)：
Figure PCTCN2015084794-appb-000002
其中，Fd为低频时钟的理论频率值，F为系统时钟(高频时钟)的理论频率值；
将得到的校准因子f(1)预设为第一校准周期的校准因子。
方式二、利用系统时钟进行预设时段的时钟校准得到校准因子，具体实现过程如下：
系统时钟和所述低频时钟在预设时段内同时工作且分别计数；
在预设时段后，计算系统时钟周期的计数值和低频时钟周期的计数值的比值，得到校准因子；
将得到的校准因子预设为第一校准周期的校准因子。
下面对在第n校准周期内，如何根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差，进行详细说明：
在第n校准周期内，在进入Active阶段时将Sleep阶段的低频时钟乘以第n校准周期的校准因子转换为系统时钟，从而恢复系统定时；并按照如下公式得到第n校准周期的校准误差Δt：
Δt＝Ts-Tc
其中，Ts为实际的系统定时，Tc为通过第n校准周期的校准因子恢复的系统定时。
这里，实际的系统定时Ts可以通过恢复系统定时后的频率和时间的同步过程获得，具体如何获得实际的系统定时Ts属于现有技术，重复之处不再赘述。
需要说明的是，当Δt>0时，说明通过第n校准周期的校准因子恢复的时间早于实际时间，此时需要减小第n校准周期的校准因子，并将调整后的校准因子用于下一校准周期中的时钟校准；当Δt<0时，说明通过第n校准周期的校准因子恢复的时间晚于实际时间，此时需要增大第n校准周期的校准因子，并将调整后的校准因子用于下一校准周期中的时钟校准；
步骤S202：根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子。
具体地，在第n+1校准周期之前，根据第n校准周期的校准误差及校准因子，并按照如下公式得到第n+1校准周期的校准因子f(n+1)：
Figure PCTCN2015084794-appb-000003
其中，f(n)为第n校准周期的校准因子，Δt为第n校准周期的校准误差，Tsleep为非连续接收时段中睡眠时段的时间。
本发明实施例中，在第n+1校准周期之前，根据第n校准周期的校准误差对第n校准周期的校准因子进行调整，从而得到第n+1校准周期的校准因子；将第n+1校准周期的校准因子用于第n+1校准周期中的时钟校准，依此类推，以实现闭环的时钟校准；如此，本发明实施例根据校准误差进行闭环的时钟校准，能够提高时钟校准的精度；并且，本发明实施例并不依赖于系统时钟，从而解决了现有技术中出现的校准时间过长的问题，进而降低终端的待机功耗。
为了更清楚地对本发明实施例进行说明，下面以具体实施例对本发明 实施例中的数据交换流程进行详细描述。
实施例一
终端预设校准周期T为一个非连续接收时段TDRX，预设第一校准周期的校准因子为f(1)；
在第一校准周期内，在进入Active阶段时将Sleep阶段的低频时钟乘以f(1)转换为系统时钟，从而恢复系统定时；然后根据实际的系统定时Ts1与通过f(1)恢复的系统定时Tc1，计算出使用f(1)进行时钟校准所造成的校准误差Δt1＝Ts1-Tc1；
然后，在第二校准周期之前，根据校准误差Δt1对f(1)进行修正，得到修正后的f(2)；将f(2)用于第二校准周期中的时钟校准；
在第二校准周期内，在进入Active阶段时将Sleep阶段的低频时钟乘以f(2)转换为系统时钟，从而恢复系统定时；然后根据实际的系统定时Ts2及通过f(2)恢复的系统定时Tc2，计算出使用f(2)进行时钟校准所造成的校准误差Δt2＝Ts2-Tc2；
然后，在第三校准周期之前，根据校准误差Δt2对f(2)进行修正，得到修正后的f(3)；将f(3)用于第三校准周期中的时钟校准；
依此类推，在第n校准周期内，根据前一校准周期修正后的校准因子进行时钟校准，并得到第n校准周期的校准误差；根据第n校准周期的校准误差对第n校准周期的校准因子进行修正，得到修正后的校准因子；将修正后的校准因子用于下一校准周期中的时钟校准，以实现闭环的时钟校准。
为实现上述方法，本发明实施例提供了一种终端，由于该终端解决问题的原理与方法相似，因此，终端的实施过程及实施原理均可以参见前述方法的实施过程及实施原理描述，重复之处不再赘述。
如图3所示，本发明实施例提供的终端，该终端包括：校准误差提取 单元301、校准因子调整单元302；其中，
所述校准误差提取单元301，配置为在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；
所述校准因子调整单元302，配置为根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数；
其中，所述校准周期预设为至少一个非连续接收时段。
以上功能单元或模块的划分方式仅为本发明实施例给出的一种优选实现方式，功能单元或模块的划分方式不构成对本发明的限制。
进一步地，所述终端还可以包括：
初始值预设单元303，配置为预设第一校准周期的校准因子；
具体实施中，所述初始值预设单元303，具体配置为根据系统时钟的理论频率值与低频时钟的理论频率值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
具体实施中，所述初始值预设单元303，具体配置为在预设时段内，系统时钟和所述低频时钟同时工作且分别计数；在预设时段后，计算高频时钟周期的计数值和低频时钟周期的计数值的比值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
在实际应用中，所述校准误差提取单元301、校准因子调整单元302、初始值预设单元303可由位于终端的中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)、或现场可编程门阵列(FPGA)实现。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
基于此，本发明实施例还提供了一种计算机存储介质，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行上述的闭环的时钟校准方法。
本发明所述的方法并不限于具体实施方式中所述的实施例，本领域技术人员根据本发明的技术方案得出其它的实施方式，同样属于本发明的技术创新范围。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权 利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (13)

  1. 一种闭环的时钟校准方法，所述方法包括：
    在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；
    根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    预设第一校准周期的校准因子。
  3. 根据权利要求2所述的方法，其中，所述预设第一校准周期的校准因子，包括：
    根据系统时钟的理论频率值与低频时钟的理论频率值，得到校准因子；
    将得到的校准因子预设为第一校准周期的校准因子。
  4. 根据权利要求2所述的方法，其中，所述预设第一校准周期的校准因子，包括：
    在预设时段内，系统时钟和所述低频时钟同时工作且分别计数；
    在预设时段后，计算系统时钟周期的计数值和低频时钟周期的计数值的比值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
  5. 根据权利要求1所述的方法，其中，所述在第n校准周期内根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差，包括：
    在第n校准周期内，将低频时钟乘以第n校准周期的校准因子转换为系统时钟恢复系统定时；并按照如下公式得到第n校准周期的校准误差Δt：
    Δt＝Ts-Tc
    其中，Ts为实际的系统定时，Tc为通过第n校准周期的校准因子恢复的 系统定时。
  6. 根据权利要求1所述的方法，其中，所述根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子，包括：
    根据第n校准周期的校准误差及校准因子，并按照如下公式得到第n+1校准周期的校准因子f(n+1)：
    Figure PCTCN2015084794-appb-100001
    其中，f(n)为第n校准周期的校准因子，Δt为第n校准周期的校准误差，TSleep为非连续接收时段中的睡眠时段。
  7. 根据权利要求1至6任一项所述的方法，其中，所述校准周期预设为至少一个非连续接收时段。
  8. 一种终端，所述终端包括：校准误差提取单元、校准因子调整单元；其中，
    所述校准误差提取单元，配置为在第n校准周期内，根据第n校准周期的校准因子进行时钟校准，并得到第n校准周期的校准误差；
    所述校准因子调整单元，配置为根据第n校准周期的校准误差及校准因子，得到第n+1校准周期的校准因子；其中，n为正整数。
  9. 根据权利要求8所述的终端，其中，所述终端还包括：
    初始值预设单元，配置为预设第一校准周期的校准因子。
  10. 根据权利要求9所述的终端，其中，所述初始值预设单元，配置为根据系统时钟的理论频率值与低频时钟的理论频率值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
  11. 根据权利要求9所述的终端，其中，所述初始值预设单元，配置为在预设时段内，系统时钟和所述低频时钟同时工作且分别计数；在预设时段后，计算系统时钟周期的计数值和低频时钟周期的计数值的比值，得到校准因子；将得到的校准因子预设为第一校准周期的校准因子。
  12. 根据权利要求8至11任一项所述的终端，其中，所述校准周期预设为至少一个非连续接收时段。
  13. 一种计算机存储介质，所述计算机存储介质包括一组指令，当执行所述指令时，引起至少一个处理器执行如权利要求1至7任一项所述的闭环的时钟校准方法。
PCT/CN2015/084794 2015-01-20 2015-07-22 一种闭环的时钟校准方法、终端及计算机存储介质 WO2016115855A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP15878526.1A EP3249978B1 (en) 2015-01-20 2015-07-22 Closed-loop clock calibration method, terminal and computer storage medium
US15/545,035 US10172093B2 (en) 2015-01-20 2015-07-22 Closed-loop clock calibration method, terminal and computer storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510027790.7A CN105873190B (zh) 2015-01-20 2015-01-20 一种闭环的时钟校准方法及终端
CN201510027790.7 2015-01-20

Publications (1)

Publication Number Publication Date
WO2016115855A1 true WO2016115855A1 (zh) 2016-07-28

Family

ID=56416359

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/084794 WO2016115855A1 (zh) 2015-01-20 2015-07-22 一种闭环的时钟校准方法、终端及计算机存储介质

Country Status (4)

Country Link
US (1) US10172093B2 (zh)
EP (1) EP3249978B1 (zh)
CN (1) CN105873190B (zh)
WO (1) WO2016115855A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180331255A1 (en) * 2017-05-12 2018-11-15 X Development Llc Fabrication of ultraviolet light emitting diode with tunnel junction
CN107817869A (zh) * 2017-11-01 2018-03-20 中颖电子股份有限公司 一种蓝牙芯片构架以及基于低功耗蓝牙芯片的时钟控制方法
CN108230660B (zh) * 2018-01-09 2020-08-25 广东美的制冷设备有限公司 控制方法及控制装置、存储介质及遥控器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1874566A (zh) * 2005-11-25 2006-12-06 凯明信息科技股份有限公司 时钟校准方法和设备
CN101090547A (zh) * 2007-07-24 2007-12-19 北京天碁科技有限公司 一种td－scdma终端睡眠时钟校准的方法和装置
US20100029267A1 (en) * 2008-07-31 2010-02-04 Mediatek Inc. Method for clock calibration
CN102405678B (zh) * 2011-04-26 2014-01-01 华为技术有限公司 一种低频时钟校准方法及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7197341B2 (en) * 2003-12-22 2007-03-27 Interdigital Technology Corporation Precise sleep timer using a low-cost and low-accuracy clock
CN101064898B (zh) 2006-04-29 2012-05-23 华为技术有限公司 一种长期演进系统中测量信道的方法和装置
CN101541073B (zh) * 2009-04-28 2011-01-05 安徽省电力科学研究院 无线传感器网络节点晶振频率误差补偿方法
CN101959298B (zh) 2009-07-17 2015-03-25 联芯科技有限公司 一种慢速定时时钟校准方法及装置和一种终端
US8560875B2 (en) * 2009-09-17 2013-10-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode
CN102540868B (zh) * 2010-12-31 2016-05-04 重庆重邮信科通信技术有限公司 一种移动通信终端慢时钟晶体频率补偿方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1874566A (zh) * 2005-11-25 2006-12-06 凯明信息科技股份有限公司 时钟校准方法和设备
CN101090547A (zh) * 2007-07-24 2007-12-19 北京天碁科技有限公司 一种td－scdma终端睡眠时钟校准的方法和装置
US20100029267A1 (en) * 2008-07-31 2010-02-04 Mediatek Inc. Method for clock calibration
CN102405678B (zh) * 2011-04-26 2014-01-01 华为技术有限公司 一种低频时钟校准方法及装置

Also Published As

Publication number Publication date
EP3249978A4 (en) 2018-01-24
EP3249978A1 (en) 2017-11-29
EP3249978B1 (en) 2019-02-27
US10172093B2 (en) 2019-01-01
US20180007635A1 (en) 2018-01-04
CN105873190A (zh) 2016-08-17
CN105873190B (zh) 2019-04-30

Similar Documents

Publication Publication Date Title
WO2016115855A1 (zh) 一种闭环的时钟校准方法、终端及计算机存储介质
TWI504207B (zh) 通訊裝置及頻偏校正方法
TW200720867A (en) System and method for calibrating a tod clock
CN109116187B (zh) 一种应用于暂态录波型故障指示器的录波同步方法
CN101171754A (zh) 用于确定休眠时钟计时的设备和方法
CN102412957B (zh) 一种高精度同步时钟调整方法
US20130003626A1 (en) Oscillator settling time allowance
CA3000011A1 (en) Apparatus and methods for synchronizing a controller and sensors
CN102405678A (zh) 一种低频时钟校准方法及装置
TWI357721B (en) Oscillation tuning circuit and method
WO2021051915A1 (zh) 一种温度补偿方法、装置、存储介质及温控器
CN102791009B (zh) 多模终端及其跨制式切换时的时间同步方法
MX2022005834A (es) Metodo y aparato para modelar una curva de energia fotovoltaica, dispositivo informatico y medio de almacenamiento del mismo.
JP6898903B2 (ja) リアルタイムクロックを備えたトランシーバ装置
CN101083815B (zh) 一种实现移动终端时钟关系跟踪的方法和装置
CN112230711B (zh) 一种校准装置、方法及计算机可读存储介质
CN106612104B (zh) 一种实时时钟误差补偿装置及方法
CN104378818A (zh) 一种时钟同步方法及装置、基站子系统
WO2016183955A1 (zh) 一种语音同步的方法和装置
CN103513698B (zh) 一种时钟信号校准方法、装置及电子设备
CN109799872A (zh) 提高低解析度实时时钟唤醒精度的方法、装置及电子设备
WO2021135303A1 (zh) 一种基于fpga的间隔均分设计方法和装置
WO2016176923A1 (zh) 一种时钟校准方法、装置及计算机存储介质
WO2012154997A3 (en) Method and system for correcting timing errors due to thermal changes within a portable computing device
CN110876178B (zh) 32k时钟的校准方法及装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15878526

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15545035

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

REEP Request for entry into the european phase

Ref document number: 2015878526

Country of ref document: EP